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//-----------------------------------------------------------------------------
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//
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// (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//-----------------------------------------------------------------------------
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// Project : V5-Block Plus for PCI Express
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// File : pcie_gtx_wrapper.v
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//--------------------------------------------------------------------------------
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//--------------------------------------------------------------------------------
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//
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// ____ ____
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// / /\/ /
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// /___/ \ / Vendor : Xilinx
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// \ \ \/ Version : 1.5
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// \ \ Application : Generated by Xilinx PCI Express Wizard
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// / / Filename : pcie_gt_wrapper.v
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// /___/ /\ Module : pcie_gt_wrapper
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// \ \ / \
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// \___\/\___\
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//
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//------------------------------------------------------------------------------
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//
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// Description : Wrapper for Rocket IO GTX Transceivers
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//
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//-----------------------------------------------------------------------------
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`define DLY #1
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module pcie_gtx_wrapper #
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(
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parameter NO_OF_LANES = 4,
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parameter SIM = 0,
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parameter PLL_DIVSEL_FB = 5,
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parameter PLL_DIVSEL_REF = 1,
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parameter CLK25_DIVIDER = 4,
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parameter TXDIFFBOOST = "FALSE",
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parameter GTDEBUGPORTS = 0
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)
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(
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output wire [7:0] gt_rx_elec_idle,
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output wire [23:0] gt_rx_status,
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output wire [63:0] gt_rx_data,
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output wire [7:0] gt_rx_phy_status,
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output wire [7:0] gt_rx_data_k,
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output wire [7:0] gt_rx_valid,
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output wire [7:0] gt_rx_chanisaligned,
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input wire [NO_OF_LANES-1:0] gt_rx_n,
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input wire [NO_OF_LANES-1:0] gt_rx_p,
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output wire [NO_OF_LANES-1:0] gt_tx_n,
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output wire [NO_OF_LANES-1:0] gt_tx_p,
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input wire [63:0] gt_tx_data,
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input wire [7:0] gt_tx_data_k,
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input wire [7:0] gt_tx_elec_idle,
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input wire [7:0] gt_tx_detect_rx_loopback,
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input wire [7:0] gt_tx_compliance,
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input wire [7:0] gt_rx_polarity,
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input wire [15:0] gt_power_down,
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input wire [7:0] gt_deskew_lanes,
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input wire [7:0] gt_pipe_reset,
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input wire [7:0] gt_rx_present,
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input wire gsr,
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input wire gtreset,
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input wire clock_lock,
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input wire trn_lnk_up_n,
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input wire refclk,
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output wire refclkout_bufg,
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output wire gtclk_bufg,
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output wire [7:0] resetdone,
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output wire [3:0] plllkdet_out,
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input wire gt_usrclk,
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input wire gt_usrclk2,
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input wire txsync_clk,
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output wire [7:0] rxbyteisaligned,
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output wire [7:0] rxchanbondseq,
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output wire pcie_reset,
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//Dynamic reconfiguration port (DRP)
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input wire gt_dclk,
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input wire [NO_OF_LANES*7-1:0] gt_daddr,
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input wire [NO_OF_LANES-1:0] gt_den,
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input wire [NO_OF_LANES-1:0] gt_dwen,
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input wire [NO_OF_LANES*16-1:0] gt_di,
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output wire [NO_OF_LANES*16-1:0] gt_do,
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output wire [NO_OF_LANES-1:0] gt_drdy,
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input wire [2:0] gt_txdiffctrl_0,
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input wire [2:0] gt_txdiffctrl_1,
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input wire [2:0] gt_txbuffctrl_0,
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input wire [2:0] gt_txbuffctrl_1,
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input wire [2:0] gt_txpreemphesis_0,
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input wire [2:0] gt_txpreemphesis_1
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);
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/************************** Start of GT instantiation *************************/
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wire [NO_OF_LANES-1:0] gt_clk;
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wire [NO_OF_LANES-1:0] gt_refclk_out;
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wire [7:0] gt_rx_enchansync = 8'h01;
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wire [3:0] gt_rx_chbond_i [8:0];
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wire [3:0] gt_rx_chbond_o [8:0];
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wire [7:0] float_rx_data_k = 8'b0;
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wire [63:0] float_rx_data = 64'b0;
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wire [7:0] GT_TXN,GT_RXN;
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wire [7:0] GT_TXP,GT_RXP;
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wire [7:0] rTXN;
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wire [7:0] rTXP;
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wire [7:0] gt_rx_elec_idle_reset;
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wire [3:0] gt_rx_en_elec_idle_resetb;
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wire [63:0] gt_rx_data_reg;
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wire [7:0] gt_rx_data_k_reg;
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wire [7:0] gt_rx_valid_reg;
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wire [7:0] gt_rx_elec_idle_reg;
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wire [23:0] gt_rx_status_reg;
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wire [7:0] gt_rx_phy_status_reg;
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wire [7:0] gt_rx_chanisaligned_reg;
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wire [7:0] gt_pipe_reset_reg;
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wire [15:0] gt_rx_power_down_reg;
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wire [7:0] gt_rx_polarity_reg;
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wire [63:0] gt_tx_data_reg;
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wire [7:0] gt_tx_data_k_reg;
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wire [7:0] gt_tx_elec_idle_reg;
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wire [7:0] gt_tx_detect_rx_loopback_reg;
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wire [7:0] gt_tx_compliance_reg;
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wire [15:0] gt_tx_power_down_reg;
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reg [7:0] one = 8'hff;
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reg [63:0] zero = 63'h0000000000000000;
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wire rst_init = gt_pipe_reset[0];
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reg rxreset; // connect to RXRESET of the GT inputs
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reg m1_delayed_elec_idle_reset;
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reg m2_delayed_elec_idle_reset;
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reg delayed_elec_idle_reset;
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//////////////////////////////////////////////////////////
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// Flop Locations for GT TX signals
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/////////////////////////////////////////////////////////
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genvar a;
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generate
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for (a=0 ; a < NO_OF_LANES ; a= a+1)
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begin:flop
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FD tx_data0 ( .Q (gt_tx_data_reg[8*a+0]), .D (gt_tx_data[8*a+0]), .C(gt_usrclk2));
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FD tx_data1 ( .Q (gt_tx_data_reg[8*a+1]), .D (gt_tx_data[8*a+1]), .C(gt_usrclk2));
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FD tx_data2 ( .Q (gt_tx_data_reg[8*a+2]), .D (gt_tx_data[8*a+2]), .C(gt_usrclk2));
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FD tx_data3 ( .Q (gt_tx_data_reg[8*a+3]), .D (gt_tx_data[8*a+3]), .C(gt_usrclk2));
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FD tx_data4 ( .Q (gt_tx_data_reg[8*a+4]), .D (gt_tx_data[8*a+4]), .C(gt_usrclk2));
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FD tx_data5 ( .Q (gt_tx_data_reg[8*a+5]), .D (gt_tx_data[8*a+5]), .C(gt_usrclk2));
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FD tx_data6 ( .Q (gt_tx_data_reg[8*a+6]), .D (gt_tx_data[8*a+6]), .C(gt_usrclk2));
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FD tx_data7 ( .Q (gt_tx_data_reg[8*a+7]), .D (gt_tx_data[8*a+7]), .C(gt_usrclk2));
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FD tx_data_k ( .Q (gt_tx_data_k_reg[a]), .D (gt_tx_data_k[a]), .C(gt_usrclk2));
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FDCP #(.INIT(1'b1)) tx_elec_idle ( .Q (gt_tx_elec_idle_reg[a]), .D (gt_tx_elec_idle[a]), .C(gt_usrclk2), .CLR(1'b0), .PRE(~clock_lock));
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FD tx_compliance ( .Q (gt_tx_compliance_reg[a]), .D (gt_tx_compliance[a]), .C(gt_usrclk2));
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FD tx_detect_rx_loopback ( .Q (gt_tx_detect_rx_loopback_reg[a]), .D (gt_tx_detect_rx_loopback[a]), .C(gt_usrclk2));
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FDCP #(.INIT(1'b1)) tx_power_down0 ( .Q (gt_tx_power_down_reg[2*a+0]), .D (gt_power_down[2*a+0]), .C(gt_usrclk2), .CLR(1'b0), .PRE(~clock_lock));
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FDCP #(.INIT(1'b0)) tx_power_down1 ( .Q (gt_tx_power_down_reg[2*a+1]), .D (gt_power_down[2*a+1]), .C(gt_usrclk2), .CLR(~clock_lock), .PRE(1'b0));
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FDCP #(.INIT(1'b1)) rx_power_down0 ( .Q (gt_rx_power_down_reg[2*a+0]), .D (gt_power_down[2*a+0]), .C(gt_usrclk2), .CLR(1'b0), .PRE(~clock_lock));
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FDCP #(.INIT(1'b0)) rx_power_down1 ( .Q (gt_rx_power_down_reg[2*a+1]), .D (gt_power_down[2*a+1]), .C(gt_usrclk2), .CLR(~clock_lock), .PRE(1'b0));
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FD rx_polarity ( .Q (gt_rx_polarity_reg[a]), .D (gt_rx_polarity[a]), .C(gt_usrclk2));
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FDCP #(.INIT(1'b1)) reset ( .Q (gt_pipe_reset_reg[a]), .D (gt_pipe_reset[a]), .C(gt_usrclk2), .CLR(1'b0), .PRE(~clock_lock));
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FD rx_data_0 ( .Q (gt_rx_data[8*a+0]), .D (gt_rx_data_reg[8*a+0]), .C(gt_usrclk2));
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FD rx_data_1 ( .Q (gt_rx_data[8*a+1]), .D (gt_rx_data_reg[8*a+1]), .C(gt_usrclk2));
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FD rx_data_2 ( .Q (gt_rx_data[8*a+2]), .D (gt_rx_data_reg[8*a+2]), .C(gt_usrclk2));
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FD rx_data_3 ( .Q (gt_rx_data[8*a+3]), .D (gt_rx_data_reg[8*a+3]), .C(gt_usrclk2));
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FD rx_data_4 ( .Q (gt_rx_data[8*a+4]), .D (gt_rx_data_reg[8*a+4]), .C(gt_usrclk2));
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FD rx_data_5 ( .Q (gt_rx_data[8*a+5]), .D (gt_rx_data_reg[8*a+5]), .C(gt_usrclk2));
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FD rx_data_6 ( .Q (gt_rx_data[8*a+6]), .D (gt_rx_data_reg[8*a+6]), .C(gt_usrclk2));
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FD rx_data_7 ( .Q (gt_rx_data[8*a+7]), .D (gt_rx_data_reg[8*a+7]), .C(gt_usrclk2));
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FD rx_data_k ( .Q (gt_rx_data_k[a]), .D (gt_rx_data_k_reg[a]), .C(gt_usrclk2));
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FDCP #(.INIT(1'b1)) rx_elec_idle ( .Q (gt_rx_elec_idle[a]), .D (gt_rx_elec_idle_reg[a]), .C(gt_usrclk2), .CLR(1'b0), .PRE(~clock_lock));
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FD rx_valid ( .Q (gt_rx_valid[a]), .D (gt_rx_valid_reg[a]), .C(gt_usrclk2));
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FDCP #(.INIT(1'b1)) rx_phy_status ( .Q (gt_rx_phy_status[a]), .D (gt_rx_phy_status_reg[a]), .C(gt_usrclk2), .CLR(1'b0), .PRE(~clock_lock));
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FD rx_chanisaligned ( .Q (gt_rx_chanisaligned[a]), .D (gt_rx_chanisaligned_reg[a]), .C(gt_usrclk2));
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FD rx_status_0 ( .Q (gt_rx_status[3*a+0]), .D (gt_rx_status_reg[3*a+0]), .C(gt_usrclk2));
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FD rx_status_1 ( .Q (gt_rx_status[3*a+1]), .D (gt_rx_status_reg[3*a+1]), .C(gt_usrclk2));
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FD rx_status_2 ( .Q (gt_rx_status[3*a+2]), .D (gt_rx_status_reg[3*a+2]), .C(gt_usrclk2));
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end
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endgenerate
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genvar b;
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generate
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for (b=NO_OF_LANES; b < 8; b=b+1)
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begin: tied_off
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assign gt_tx_data_reg[8*b+7:8*b+0] = 8'b0;
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assign gt_tx_data_k_reg[b] = 1'b0;
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assign gt_tx_elec_idle_reg[b] = 1'b1;
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assign gt_tx_detect_rx_loopback_reg[b] = 1'b0;
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assign gt_tx_compliance_reg[b] = 1'b0;
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assign gt_tx_power_down_reg[2*b+1:2*b+0] = 2'b0;
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assign gt_rx_power_down_reg[2*b+1:2*b+0] = 2'b0;
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assign gt_pipe_reset_reg[b] = 1'b0;
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assign gt_rx_polarity_reg[b] = 1'b0;
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assign gt_rx_data[8*b+7:8*b+0] = 8'b0;
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assign gt_rx_data_k[b] = 1'b0;
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assign gt_rx_valid[b] = 1'b0;
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273 |
|
|
assign gt_rx_elec_idle[b] = 1'b1;
|
274 |
|
|
assign gt_rx_status[3*b+2:3*b] = 3'b0;
|
275 |
|
|
assign gt_rx_phy_status[b] = 1'b0;
|
276 |
|
|
assign gt_rx_chanisaligned[b] = 1'b0;
|
277 |
|
|
|
278 |
|
|
end
|
279 |
|
|
endgenerate
|
280 |
|
|
|
281 |
|
|
|
282 |
|
|
assign rTXN = GT_TXN;
|
283 |
|
|
assign rTXP = GT_TXP;
|
284 |
|
|
|
285 |
|
|
assign gt_tx_n = rTXN[(NO_OF_LANES-1):0];
|
286 |
|
|
assign gt_tx_p = rTXP[(NO_OF_LANES-1):0];
|
287 |
|
|
|
288 |
|
|
assign GT_RXN[(NO_OF_LANES-1):0] = gt_rx_n;
|
289 |
|
|
assign GT_RXP[(NO_OF_LANES-1):0] = gt_rx_p;
|
290 |
|
|
|
291 |
|
|
BUFG bufg1 (.I(gt_clk[0]), .O(gtclk_bufg));
|
292 |
|
|
BUFG bufg2 (.I(gt_refclk_out[0]), .O(refclkout_bufg));
|
293 |
|
|
|
294 |
|
|
// Channel bonding settings for simulation. These settings should be changed
|
295 |
|
|
// based on how the GTs are daisy chained. For more imformation on channel
|
296 |
|
|
// bonding please refer to the V5 Rocket I/O Transceiver User Guide
|
297 |
|
|
assign gt_rx_chbond_i[0] = 4'b0;
|
298 |
|
|
|
299 |
|
|
genvar c;
|
300 |
|
|
generate
|
301 |
|
|
for (c = 0; c <= NO_OF_LANES-1 ; c=c+1)
|
302 |
|
|
begin:ch_bond
|
303 |
|
|
assign gt_rx_chbond_i[c+1] = (NO_OF_LANES == 1) ? 4'b0 : gt_rx_chbond_o[c];
|
304 |
|
|
end
|
305 |
|
|
endgenerate
|
306 |
|
|
|
307 |
|
|
// *********************************************
|
308 |
|
|
// LOGIC to generate the individual GT register data and
|
309 |
|
|
// control ports
|
310 |
|
|
//
|
311 |
|
|
wire TXENPMAPHASEALIGN;
|
312 |
|
|
wire TXPMASETPHASE;
|
313 |
|
|
|
314 |
|
|
wire resetdone_all;
|
315 |
|
|
wire drp_clk_in;
|
316 |
|
|
wire mgt_txreset;
|
317 |
|
|
|
318 |
|
|
wire tx_sync_reset;
|
319 |
|
|
wire sync_done;
|
320 |
|
|
reg include_reset = 1'b0;
|
321 |
|
|
reg rst_pcie;
|
322 |
|
|
reg rst_txsync;
|
323 |
|
|
|
324 |
|
|
|
325 |
|
|
wire [NO_OF_LANES*7-1:0] muxed_drp_daddr; //i
|
326 |
|
|
wire [NO_OF_LANES-1:0] muxed_drp_den; // i
|
327 |
|
|
wire [NO_OF_LANES-1:0] muxed_drp_dwen; // i
|
328 |
|
|
wire [NO_OF_LANES*16-1:0] muxed_drp_di; // i
|
329 |
|
|
wire [NO_OF_LANES*16-1:0] muxed_drp_do; // o
|
330 |
|
|
wire [NO_OF_LANES-1:0] muxed_drp_drdy; // o
|
331 |
|
|
|
332 |
|
|
|
333 |
|
|
wire [6:0] txsync_drp_daddr; //i
|
334 |
|
|
wire txsync_drp_den; // i
|
335 |
|
|
wire txsync_drp_dwen; // i
|
336 |
|
|
wire [15:0] txsync_drp_di; // i
|
337 |
|
|
|
338 |
|
|
wire [15:0] txsync_drp_do; // o
|
339 |
|
|
wire txsync_drp_drdy; // o
|
340 |
|
|
|
341 |
|
|
|
342 |
|
|
|
343 |
|
|
genvar i;
|
344 |
|
|
generate
|
345 |
|
|
for (i=0; i < NO_OF_LANES; i= i+2)
|
346 |
|
|
begin: GTD
|
347 |
|
|
GTX_DUAL #
|
348 |
|
|
(
|
349 |
|
|
.SIM_RECEIVER_DETECT_PASS_0 ("TRUE" ),
|
350 |
|
|
.SIM_RECEIVER_DETECT_PASS_1 ("TRUE" ),
|
351 |
|
|
.SIM_GTXRESET_SPEEDUP (1 ),
|
352 |
|
|
.SIM_PLL_PERDIV2 (9'h0c8 ),
|
353 |
|
|
.CLKRCV_TRST ("TRUE" ),
|
354 |
|
|
.AC_CAP_DIS_0 ("FALSE" ),
|
355 |
|
|
.AC_CAP_DIS_1 ("FALSE" ),
|
356 |
|
|
.ALIGN_COMMA_WORD_0 (1 ),
|
357 |
|
|
.ALIGN_COMMA_WORD_1 (1 ),
|
358 |
|
|
.CB2_INH_CC_PERIOD_0 (8 ),
|
359 |
|
|
.CB2_INH_CC_PERIOD_1 (8 ),
|
360 |
|
|
.CHAN_BOND_1_MAX_SKEW_0 (7 ),
|
361 |
|
|
.CHAN_BOND_1_MAX_SKEW_1 (7 ),
|
362 |
|
|
.CHAN_BOND_2_MAX_SKEW_0 (7 ),
|
363 |
|
|
.CHAN_BOND_2_MAX_SKEW_1 (7 ),
|
364 |
|
|
.CHAN_BOND_LEVEL_0 (NO_OF_LANES==1?0:NO_OF_LANES-(i+1)),
|
365 |
|
|
.CHAN_BOND_LEVEL_1 (NO_OF_LANES==1?0:NO_OF_LANES-(i+2)),
|
366 |
|
|
.CHAN_BOND_MODE_0 (NO_OF_LANES==1?"OFF":(i==0)?"MASTER":"SLAVE"),
|
367 |
|
|
.CHAN_BOND_MODE_1 (NO_OF_LANES==1?"OFF":"SLAVE"),
|
368 |
|
|
.CHAN_BOND_SEQ_2_USE_0 ("TRUE" ),
|
369 |
|
|
.CHAN_BOND_KEEP_ALIGN_0 ("FALSE" ),
|
370 |
|
|
.CHAN_BOND_KEEP_ALIGN_1 ("FALSE" ),
|
371 |
|
|
.CHAN_BOND_SEQ_2_USE_1 ("TRUE" ),
|
372 |
|
|
.CHAN_BOND_SEQ_LEN_0 (4 ),
|
373 |
|
|
.CHAN_BOND_SEQ_LEN_1 (4 ),
|
374 |
|
|
.CLK25_DIVIDER (CLK25_DIVIDER ),
|
375 |
|
|
.CLKINDC_B ("TRUE" ),
|
376 |
|
|
.CLK_CORRECT_USE_0 ("TRUE" ),
|
377 |
|
|
.CLK_CORRECT_USE_1 ("TRUE" ),
|
378 |
|
|
.CLK_COR_ADJ_LEN_0 (2 ),
|
379 |
|
|
.CLK_COR_ADJ_LEN_1 (2 ),
|
380 |
|
|
.CLK_COR_DET_LEN_0 (2 ),
|
381 |
|
|
.CLK_COR_DET_LEN_1 (2 ),
|
382 |
|
|
.CLK_COR_INSERT_IDLE_FLAG_0 ("FALSE" ),
|
383 |
|
|
.CLK_COR_INSERT_IDLE_FLAG_1 ("FALSE" ),
|
384 |
|
|
.CLK_COR_KEEP_IDLE_0 ("FALSE" ),
|
385 |
|
|
.CLK_COR_KEEP_IDLE_1 ("FALSE" ),
|
386 |
|
|
.CLK_COR_MAX_LAT_0 (30 ),
|
387 |
|
|
.CLK_COR_MAX_LAT_1 (30 ),
|
388 |
|
|
.CLK_COR_MIN_LAT_0 (28 ),
|
389 |
|
|
.CLK_COR_MIN_LAT_1 (28 ),
|
390 |
|
|
.CLK_COR_PRECEDENCE_0 ("TRUE" ),
|
391 |
|
|
.CLK_COR_PRECEDENCE_1 ("TRUE" ),
|
392 |
|
|
.CLK_COR_REPEAT_WAIT_0 (5 ),
|
393 |
|
|
.CLK_COR_REPEAT_WAIT_1 (5 ),
|
394 |
|
|
.CLK_COR_SEQ_2_USE_0 ("FALSE" ),
|
395 |
|
|
.CLK_COR_SEQ_2_USE_1 ("FALSE" ),
|
396 |
|
|
.COMMA_DOUBLE_0 ("FALSE" ),
|
397 |
|
|
.COMMA_DOUBLE_1 ("FALSE" ),
|
398 |
|
|
.DEC_MCOMMA_DETECT_0 ("TRUE" ),
|
399 |
|
|
.DEC_MCOMMA_DETECT_1 ("TRUE" ),
|
400 |
|
|
.DEC_PCOMMA_DETECT_0 ("TRUE" ),
|
401 |
|
|
.DEC_PCOMMA_DETECT_1 ("TRUE" ),
|
402 |
|
|
.DEC_VALID_COMMA_ONLY_0 ("TRUE" ),
|
403 |
|
|
.DEC_VALID_COMMA_ONLY_1 ("TRUE" ),
|
404 |
|
|
.MCOMMA_DETECT_0 ("TRUE" ),
|
405 |
|
|
.MCOMMA_DETECT_1 ("TRUE" ),
|
406 |
|
|
.OOB_CLK_DIVIDER (4 ),
|
407 |
|
|
.OVERSAMPLE_MODE ("FALSE" ),
|
408 |
|
|
.PCI_EXPRESS_MODE_0 ("TRUE" ),
|
409 |
|
|
.PCI_EXPRESS_MODE_1 ("TRUE" ),
|
410 |
|
|
.PCOMMA_DETECT_0 ("TRUE" ),
|
411 |
|
|
.PCOMMA_DETECT_1 ("TRUE" ),
|
412 |
|
|
.PLL_COM_CFG (24'h21680a ),
|
413 |
|
|
.PLL_CP_CFG (8'h00 ),
|
414 |
|
|
.PLL_DIVSEL_FB (PLL_DIVSEL_FB ),
|
415 |
|
|
.PLL_DIVSEL_REF (PLL_DIVSEL_REF ),
|
416 |
|
|
.PLL_FB_DCCEN ("FALSE" ),
|
417 |
|
|
.PLL_LKDET_CFG (3'b101 ),
|
418 |
|
|
.PLL_TDCC_CFG (3'b000 ),
|
419 |
|
|
.PMA_COM_CFG (69'h000000000000000000 ),
|
420 |
|
|
.PLL_RXDIVSEL_OUT_0 (2 ),
|
421 |
|
|
.PLL_RXDIVSEL_OUT_1 (2 ),
|
422 |
|
|
.GEARBOX_ENDEC_0 (3'b000 ),
|
423 |
|
|
.GEARBOX_ENDEC_1 (3'b000 ),
|
424 |
|
|
.TXGEARBOX_USE_0 ("FALSE" ),
|
425 |
|
|
.TXGEARBOX_USE_1 ("FALSE" ),
|
426 |
|
|
.CM_TRIM_0 (2'b10 ),
|
427 |
|
|
.CM_TRIM_1 (2'b10 ),
|
428 |
|
|
.PMA_TX_CFG_0 (20'h80082 ),
|
429 |
|
|
.PMA_TX_CFG_1 (20'h80082 ),
|
430 |
|
|
.TX_DETECT_RX_CFG_0 (14'h1832 ),
|
431 |
|
|
.TX_DETECT_RX_CFG_1 (14'h1832 ),
|
432 |
|
|
.TX_IDLE_DELAY_0 (3'b010 ),
|
433 |
|
|
.TX_IDLE_DELAY_1 (3'b010 ),
|
434 |
|
|
.DFE_CFG_0 (10'b1101111011 ),
|
435 |
|
|
.DFE_CFG_1 (10'b1101111011 ),
|
436 |
|
|
.DFE_CAL_TIME (5'b00110 ),
|
437 |
|
|
.RXGEARBOX_USE_0 ("FALSE" ),
|
438 |
|
|
.RXGEARBOX_USE_1 ("FALSE" ),
|
439 |
|
|
.PMA_RXSYNC_CFG_0 (7'h00 ),
|
440 |
|
|
.PMA_RXSYNC_CFG_1 (7'h00 ),
|
441 |
|
|
.RX_EN_IDLE_HOLD_DFE_0 ("TRUE" ),
|
442 |
|
|
.RX_EN_IDLE_RESET_BUF_0 ("TRUE" ),
|
443 |
|
|
.RX_IDLE_HI_CNT_0 (4'b1000 ),
|
444 |
|
|
.RX_IDLE_LO_CNT_0 (4'b0000 ),
|
445 |
|
|
.RX_EN_IDLE_HOLD_DFE_1 ("TRUE" ),
|
446 |
|
|
.RX_EN_IDLE_RESET_BUF_1 ("TRUE" ),
|
447 |
|
|
.RX_IDLE_HI_CNT_1 (4'b1000 ),
|
448 |
|
|
.RX_IDLE_LO_CNT_1 (4'b0000 ),
|
449 |
|
|
.CDR_PH_ADJ_TIME (5'b01010 ),
|
450 |
|
|
.RX_EN_IDLE_RESET_FR ("TRUE" ),
|
451 |
|
|
.RX_EN_IDLE_HOLD_CDR ("FALSE" ),
|
452 |
|
|
.RX_EN_IDLE_RESET_PH ("TRUE" ),
|
453 |
|
|
.PLL_SATA_0 ("FALSE" ),
|
454 |
|
|
.PLL_SATA_1 ("FALSE" ),
|
455 |
|
|
.PLL_TXDIVSEL_OUT_0 (2 ),
|
456 |
|
|
.PLL_TXDIVSEL_OUT_1 (2 ),
|
457 |
|
|
.RCV_TERM_GND_0 ("TRUE" ),
|
458 |
|
|
.RCV_TERM_GND_1 ("TRUE" ),
|
459 |
|
|
.RCV_TERM_VTTRX_0 ("FALSE" ),
|
460 |
|
|
.RCV_TERM_VTTRX_1 ("FALSE" ),
|
461 |
|
|
.RX_BUFFER_USE_0 ("TRUE" ),
|
462 |
|
|
.RX_BUFFER_USE_1 ("TRUE" ),
|
463 |
|
|
.RX_DECODE_SEQ_MATCH_0 ("TRUE" ),
|
464 |
|
|
.RX_DECODE_SEQ_MATCH_1 ("TRUE" ),
|
465 |
|
|
.RX_LOSS_OF_SYNC_FSM_0 ("FALSE" ),
|
466 |
|
|
.RX_LOSS_OF_SYNC_FSM_1 ("FALSE" ),
|
467 |
|
|
.RX_LOS_INVALID_INCR_0 (8 ),
|
468 |
|
|
.RX_LOS_INVALID_INCR_1 (8 ),
|
469 |
|
|
.RX_LOS_THRESHOLD_0 (128 ),
|
470 |
|
|
.RX_LOS_THRESHOLD_1 (128 ),
|
471 |
|
|
.RX_SLIDE_MODE_0 ("PCS" ),
|
472 |
|
|
.RX_SLIDE_MODE_1 ("PCS" ),
|
473 |
|
|
.RX_STATUS_FMT_0 ("PCIE" ),
|
474 |
|
|
.RX_STATUS_FMT_1 ("PCIE" ),
|
475 |
|
|
.RX_XCLK_SEL_0 ("RXREC" ),
|
476 |
|
|
.RX_XCLK_SEL_1 ("RXREC" ),
|
477 |
|
|
.SATA_MAX_BURST_0 (7 ),
|
478 |
|
|
.SATA_MAX_BURST_1 (7 ),
|
479 |
|
|
.SATA_MAX_INIT_0 (22 ),
|
480 |
|
|
.SATA_MAX_INIT_1 (22 ),
|
481 |
|
|
.SATA_MAX_WAKE_0 (7 ),
|
482 |
|
|
.SATA_MAX_WAKE_1 (7 ),
|
483 |
|
|
.SATA_MIN_BURST_0 (4 ),
|
484 |
|
|
.SATA_MIN_BURST_1 (4 ),
|
485 |
|
|
.SATA_MIN_INIT_0 (12 ),
|
486 |
|
|
.SATA_MIN_INIT_1 (12 ),
|
487 |
|
|
.SATA_MIN_WAKE_0 (4 ),
|
488 |
|
|
.SATA_MIN_WAKE_1 (4 ),
|
489 |
|
|
.TERMINATION_IMP_0 (50 ),
|
490 |
|
|
.TERMINATION_IMP_1 (50 ),
|
491 |
|
|
.TERMINATION_OVRD ("FALSE" ),
|
492 |
|
|
.TX_BUFFER_USE_0 ("TRUE" ),
|
493 |
|
|
.TX_BUFFER_USE_1 ("TRUE" ),
|
494 |
|
|
.TX_XCLK_SEL_0 ("TXOUT" ),
|
495 |
|
|
.TX_XCLK_SEL_1 ("TXOUT" ),
|
496 |
|
|
.CHAN_BOND_SEQ_1_1_0 (10'b0001001010 ),
|
497 |
|
|
.CHAN_BOND_SEQ_1_1_1 (10'b0001001010 ),
|
498 |
|
|
.CHAN_BOND_SEQ_1_2_0 (10'b0001001010 ),
|
499 |
|
|
.CHAN_BOND_SEQ_1_2_1 (10'b0001001010 ),
|
500 |
|
|
.CHAN_BOND_SEQ_1_3_0 (10'b0001001010 ),
|
501 |
|
|
.CHAN_BOND_SEQ_1_3_1 (10'b0001001010 ),
|
502 |
|
|
.CHAN_BOND_SEQ_1_4_0 (10'b0110111100 ),
|
503 |
|
|
.CHAN_BOND_SEQ_1_4_1 (10'b0110111100 ),
|
504 |
|
|
.CHAN_BOND_SEQ_1_ENABLE_0 (4'b1111 ),
|
505 |
|
|
.CHAN_BOND_SEQ_1_ENABLE_1 (4'b1111 ),
|
506 |
|
|
.CHAN_BOND_SEQ_2_1_0 (10'b0100111100 ),
|
507 |
|
|
.CHAN_BOND_SEQ_2_1_1 (10'b0100111100 ),
|
508 |
|
|
.CHAN_BOND_SEQ_2_2_0 (10'b0100111100 ),
|
509 |
|
|
.CHAN_BOND_SEQ_2_2_1 (10'b0100111100 ),
|
510 |
|
|
.CHAN_BOND_SEQ_2_3_0 (10'b0110111100 ),
|
511 |
|
|
.CHAN_BOND_SEQ_2_3_1 (10'b0110111100 ),
|
512 |
|
|
.CHAN_BOND_SEQ_2_4_0 (10'b0100011100 ),
|
513 |
|
|
.CHAN_BOND_SEQ_2_4_1 (10'b0100011100 ),
|
514 |
|
|
.CHAN_BOND_SEQ_2_ENABLE_0 (4'b1111 ),
|
515 |
|
|
.CHAN_BOND_SEQ_2_ENABLE_1 (4'b1111 ),
|
516 |
|
|
.CLK_COR_SEQ_1_1_0 (10'b0100011100 ),
|
517 |
|
|
.CLK_COR_SEQ_1_1_1 (10'b0100011100 ),
|
518 |
|
|
.CLK_COR_SEQ_1_2_0 (10'b0100011100 ),
|
519 |
|
|
.CLK_COR_SEQ_1_2_1 (10'b0100011100 ),
|
520 |
|
|
.CLK_COR_SEQ_1_3_0 (10'b0000000000 ),
|
521 |
|
|
.CLK_COR_SEQ_1_3_1 (10'b0000000000 ),
|
522 |
|
|
.CLK_COR_SEQ_1_4_0 (10'b0000000000 ),
|
523 |
|
|
.CLK_COR_SEQ_1_4_1 (10'b0000000000 ),
|
524 |
|
|
.CLK_COR_SEQ_1_ENABLE_0 (4'b1111 ),
|
525 |
|
|
.CLK_COR_SEQ_1_ENABLE_1 (4'b1111 ),
|
526 |
|
|
.CLK_COR_SEQ_2_1_0 (10'b0000000000 ),
|
527 |
|
|
.CLK_COR_SEQ_2_1_1 (10'b0000000000 ),
|
528 |
|
|
.CLK_COR_SEQ_2_2_0 (10'b0000000000 ),
|
529 |
|
|
.CLK_COR_SEQ_2_2_1 (10'b0000000000 ),
|
530 |
|
|
.CLK_COR_SEQ_2_3_0 (10'b0000000000 ),
|
531 |
|
|
.CLK_COR_SEQ_2_3_1 (10'b0000000000 ),
|
532 |
|
|
.CLK_COR_SEQ_2_4_0 (10'b0000000000 ),
|
533 |
|
|
.CLK_COR_SEQ_2_4_1 (10'b0000000000 ),
|
534 |
|
|
.CLK_COR_SEQ_2_ENABLE_0 (4'b1111 ),
|
535 |
|
|
.CLK_COR_SEQ_2_ENABLE_1 (4'b1111 ),
|
536 |
|
|
.COMMA_10B_ENABLE_0 (10'b1111111111 ),
|
537 |
|
|
.COMMA_10B_ENABLE_1 (10'b1111111111 ),
|
538 |
|
|
.COM_BURST_VAL_0 (4'b1111 ),
|
539 |
|
|
.COM_BURST_VAL_1 (4'b1111 ),
|
540 |
|
|
.MCOMMA_10B_VALUE_0 (10'b1010000011 ),
|
541 |
|
|
.MCOMMA_10B_VALUE_1 (10'b1010000011 ),
|
542 |
|
|
.OOBDETECT_THRESHOLD_0 (3'b110 ),
|
543 |
|
|
.OOBDETECT_THRESHOLD_1 (3'b110 ),
|
544 |
|
|
.PCOMMA_10B_VALUE_0 (10'b0101111100 ),
|
545 |
|
|
.PCOMMA_10B_VALUE_1 (10'b0101111100 ),
|
546 |
|
|
.PMA_CDR_SCAN_0 (27'h6404035 ),
|
547 |
|
|
.PMA_CDR_SCAN_1 (27'h6404035 ),
|
548 |
|
|
.PMA_RX_CFG_0 (25'h0F44089 ),
|
549 |
|
|
.PMA_RX_CFG_1 (25'h0F44089 ),
|
550 |
|
|
.PRBS_ERR_THRESHOLD_0 (32'h00000001 ),
|
551 |
|
|
.PRBS_ERR_THRESHOLD_1 (32'h00000001 ),
|
552 |
|
|
.SATA_BURST_VAL_0 (3'b100 ),
|
553 |
|
|
.SATA_BURST_VAL_1 (3'b100 ),
|
554 |
|
|
.SATA_IDLE_VAL_0 (3'b011 ),
|
555 |
|
|
.SATA_IDLE_VAL_1 (3'b011 ),
|
556 |
|
|
.TERMINATION_CTRL (5'b10100 ),
|
557 |
|
|
.TRANS_TIME_FROM_P2_0 (16'h003C ),
|
558 |
|
|
.TRANS_TIME_FROM_P2_1 (16'h003C ),
|
559 |
|
|
.TRANS_TIME_NON_P2_0 (16'h0019 ),
|
560 |
|
|
.TRANS_TIME_NON_P2_1 (16'h0019 ),
|
561 |
|
|
.TRANS_TIME_TO_P2_0 (16'h0064 ),
|
562 |
|
|
.TRANS_TIME_TO_P2_1 (16'h0064 ),
|
563 |
|
|
.TXRX_INVERT_0 (3'b011 ),
|
564 |
|
|
.TXRX_INVERT_1 (3'b011 )
|
565 |
|
|
|
566 |
|
|
|
567 |
|
|
)
|
568 |
|
|
|
569 |
|
|
GT_i(
|
570 |
|
|
// GT_DUAL outputs
|
571 |
|
|
.DO(muxed_drp_do[16*i+15:16*i]),
|
572 |
|
|
.DRDY(muxed_drp_drdy[i]),
|
573 |
|
|
|
574 |
|
|
.PHYSTATUS0(gt_rx_phy_status_reg[i+0]),
|
575 |
|
|
.PHYSTATUS1(gt_rx_phy_status_reg[i+1]),
|
576 |
|
|
.PLLLKDET(plllkdet_out[i/2]),
|
577 |
|
|
.REFCLKOUT(gt_refclk_out[i]),
|
578 |
|
|
.RESETDONE0(resetdone[i]),
|
579 |
|
|
.RESETDONE1(resetdone[i+1]),
|
580 |
|
|
.RXBUFSTATUS0(),
|
581 |
|
|
.RXBUFSTATUS1(),
|
582 |
|
|
.RXBYTEISALIGNED0(rxbyteisaligned[i]),
|
583 |
|
|
.RXBYTEISALIGNED1(rxbyteisaligned[i+1]),
|
584 |
|
|
.RXBYTEREALIGN0(),
|
585 |
|
|
.RXBYTEREALIGN1(),
|
586 |
|
|
.RXCHANBONDSEQ0(rxchanbondseq[i]),
|
587 |
|
|
.RXCHANBONDSEQ1(rxchanbondseq[i+1]),
|
588 |
|
|
.RXCHANISALIGNED0(gt_rx_chanisaligned_reg[i+0]),
|
589 |
|
|
.RXCHANISALIGNED1(gt_rx_chanisaligned_reg[i+1]),
|
590 |
|
|
.RXCHANREALIGN0(),
|
591 |
|
|
.RXCHANREALIGN1(),
|
592 |
|
|
.RXCHARISCOMMA0(),
|
593 |
|
|
.RXCHARISCOMMA1(),
|
594 |
|
|
.RXCHARISK0({float_rx_data_k[i],float_rx_data_k[i],float_rx_data_k[i],gt_rx_data_k_reg[i]}),
|
595 |
|
|
.RXCHARISK1({float_rx_data_k[i+1],float_rx_data_k[i+1],float_rx_data_k[i+1],gt_rx_data_k_reg[i+1]}),
|
596 |
|
|
.RXCHBONDO0(gt_rx_chbond_o[i]),
|
597 |
|
|
.RXCHBONDO1(gt_rx_chbond_o[i+1]),
|
598 |
|
|
.RXCLKCORCNT0(),
|
599 |
|
|
.RXCLKCORCNT1(),
|
600 |
|
|
.RXCOMMADET0(),
|
601 |
|
|
.RXCOMMADET1(),
|
602 |
|
|
.RXDATA0({float_rx_data[8*i+7:8*i],float_rx_data[8*i+7:8*i],float_rx_data[8*i+7:8*i],gt_rx_data_reg[8*i+7:8*i]}),
|
603 |
|
|
.RXDATA1({float_rx_data[8*i+15:8*i+8],float_rx_data[8*i+15:8*i+8],float_rx_data[8*i+15:8*i+8],gt_rx_data_reg[8*i+15:8*i+8]}),
|
604 |
|
|
.RXDISPERR0(),
|
605 |
|
|
.RXDISPERR1(),
|
606 |
|
|
.RXELECIDLE0(gt_rx_elec_idle_reg[i+0]),
|
607 |
|
|
.RXELECIDLE1(gt_rx_elec_idle_reg[i+1]),
|
608 |
|
|
.RXLOSSOFSYNC0(),
|
609 |
|
|
.RXLOSSOFSYNC1(),
|
610 |
|
|
.RXNOTINTABLE0(),
|
611 |
|
|
.RXNOTINTABLE1(),
|
612 |
|
|
.RXOVERSAMPLEERR0(),
|
613 |
|
|
.RXOVERSAMPLEERR1(),
|
614 |
|
|
.RXPRBSERR0(),
|
615 |
|
|
.RXPRBSERR1(),
|
616 |
|
|
.RXRECCLK0(),
|
617 |
|
|
.RXRECCLK1(),
|
618 |
|
|
.RXRUNDISP0(),
|
619 |
|
|
.RXRUNDISP1(),
|
620 |
|
|
.RXSTATUS0(gt_rx_status_reg[3*i+2:3*i]),
|
621 |
|
|
.RXSTATUS1(gt_rx_status_reg[3*i+5:3*i+3]),
|
622 |
|
|
.RXVALID0(gt_rx_valid_reg[i+0]),
|
623 |
|
|
.RXVALID1(gt_rx_valid_reg[i+1]),
|
624 |
|
|
.TXBUFSTATUS0(),
|
625 |
|
|
.TXBUFSTATUS1(),
|
626 |
|
|
.TXKERR0(),
|
627 |
|
|
.TXKERR1(),
|
628 |
|
|
.TXN0(GT_TXN[i+0]),
|
629 |
|
|
.TXN1(GT_TXN[i+1]),
|
630 |
|
|
.TXOUTCLK0(gt_clk[i]),
|
631 |
|
|
.TXOUTCLK1(),
|
632 |
|
|
.TXP0(GT_TXP[i+0]),
|
633 |
|
|
.TXP1(GT_TXP[i+1]),
|
634 |
|
|
.TXRUNDISP0(),
|
635 |
|
|
.TXRUNDISP1(),
|
636 |
|
|
// GT_DUAL inputs
|
637 |
|
|
.CLKIN(refclk),
|
638 |
|
|
|
639 |
|
|
.DADDR(muxed_drp_daddr[7*i+6:7*i]),
|
640 |
|
|
.DCLK(drp_clk_in),
|
641 |
|
|
.DEN(muxed_drp_den[i]),
|
642 |
|
|
.DI(muxed_drp_di[16*i+15:16*i]),
|
643 |
|
|
.DWE(muxed_drp_dwen[i]),
|
644 |
|
|
|
645 |
|
|
.GTXRESET(gtreset),
|
646 |
|
|
.INTDATAWIDTH(1'b1),
|
647 |
|
|
.LOOPBACK0(3'b000),
|
648 |
|
|
.LOOPBACK1( (NO_OF_LANES == 1) ? 3'b010 : 3'b000),
|
649 |
|
|
.PLLLKDETEN(1'b1),
|
650 |
|
|
.PLLPOWERDOWN(1'b0),
|
651 |
|
|
.PRBSCNTRESET0(1'b0),
|
652 |
|
|
.PRBSCNTRESET1(1'b0),
|
653 |
|
|
.REFCLKPWRDNB(1'b1),
|
654 |
|
|
.RXBUFRESET0(1'b0),
|
655 |
|
|
.RXBUFRESET1(1'b0),
|
656 |
|
|
.RXCDRRESET0(gt_pipe_reset_reg[i+0] & ~rst_pcie),
|
657 |
|
|
.RXCDRRESET1(gt_pipe_reset_reg[i+1] & ~rst_pcie),
|
658 |
|
|
.RXCHBONDI0(gt_rx_chbond_i[i]),
|
659 |
|
|
.RXCHBONDI1(gt_rx_chbond_i[i+1]),
|
660 |
|
|
.RXCOMMADETUSE0(1'b1),
|
661 |
|
|
.RXCOMMADETUSE1(1'b1),
|
662 |
|
|
.RXDATAWIDTH0(2'b00),
|
663 |
|
|
.RXDATAWIDTH1(2'b00),
|
664 |
|
|
.RXDEC8B10BUSE0(1'b1),
|
665 |
|
|
.RXDEC8B10BUSE1(1'b1),
|
666 |
|
|
.RXENCHANSYNC0(gt_rx_enchansync[i+0]),
|
667 |
|
|
.RXENCHANSYNC1(gt_rx_enchansync[i+1]),
|
668 |
|
|
.RXENEQB0(1'b1),
|
669 |
|
|
.RXENEQB1(1'b1),
|
670 |
|
|
.RXENMCOMMAALIGN0(1'b1),
|
671 |
|
|
.RXENMCOMMAALIGN1(1'b1),
|
672 |
|
|
.RXENPCOMMAALIGN0(1'b1),
|
673 |
|
|
.RXENPCOMMAALIGN1(1'b1),
|
674 |
|
|
.RXENPRBSTST0(2'b00),
|
675 |
|
|
.RXENPRBSTST1(2'b00),
|
676 |
|
|
.RXENSAMPLEALIGN0(1'b0),
|
677 |
|
|
.RXENSAMPLEALIGN1(1'b0),
|
678 |
|
|
.RXEQMIX0(2'b00),
|
679 |
|
|
.RXEQMIX1(2'b00),
|
680 |
|
|
.RXEQPOLE0(4'b0000),
|
681 |
|
|
.RXEQPOLE1(4'b0000),
|
682 |
|
|
.RXN0(GT_RXN[i+0]),
|
683 |
|
|
.RXN1(GT_RXN[i+1]),
|
684 |
|
|
.RXP0(GT_RXP[i+0]),
|
685 |
|
|
.RXP1(GT_RXP[i+1]),
|
686 |
|
|
.RXPMASETPHASE0(1'b1),
|
687 |
|
|
.RXPMASETPHASE1(1'b1),
|
688 |
|
|
.RXPOLARITY0(gt_rx_polarity_reg[i+0]),
|
689 |
|
|
.RXPOLARITY1(gt_rx_polarity_reg[i+1]),
|
690 |
|
|
.RXPOWERDOWN0(gt_rx_power_down_reg[2*i+1:2*i]),
|
691 |
|
|
.RXPOWERDOWN1(gt_rx_power_down_reg[2*i+3:2*i+2]),
|
692 |
|
|
.RXRESET0(rxreset & ~rst_pcie),
|
693 |
|
|
.RXRESET1(rxreset & ~rst_pcie),
|
694 |
|
|
.RXSLIDE0(1'b0),
|
695 |
|
|
.RXSLIDE1(1'b0),
|
696 |
|
|
.RXUSRCLK0(gt_usrclk),
|
697 |
|
|
.RXUSRCLK1(gt_usrclk),
|
698 |
|
|
.RXUSRCLK20(gt_usrclk2),
|
699 |
|
|
.RXUSRCLK21(gt_usrclk2),
|
700 |
|
|
.TXBUFDIFFCTRL0(gt_txbuffctrl_0),
|
701 |
|
|
.TXBUFDIFFCTRL1(gt_txbuffctrl_1),
|
702 |
|
|
.TXBYPASS8B10B0(4'b0000),
|
703 |
|
|
.TXBYPASS8B10B1(4'b0000),
|
704 |
|
|
.TXCHARDISPMODE0({3'b0,gt_tx_compliance_reg[i+0]}),
|
705 |
|
|
.TXCHARDISPMODE1({3'b0,gt_tx_compliance_reg[i+1]}),
|
706 |
|
|
.TXCHARDISPVAL0(4'b0000),
|
707 |
|
|
.TXCHARDISPVAL1(4'b0000),
|
708 |
|
|
.TXCHARISK0({3'b0,gt_tx_data_k_reg[i+0]}),
|
709 |
|
|
.TXCHARISK1({3'b0,gt_tx_data_k_reg[i+1]}),
|
710 |
|
|
.TXCOMSTART0(1'b0),
|
711 |
|
|
.TXCOMSTART1(1'b0),
|
712 |
|
|
.TXCOMTYPE0(1'b0),
|
713 |
|
|
.TXCOMTYPE1(1'b0),
|
714 |
|
|
.TXDATA0({24'b0,gt_tx_data_reg[8*i+7:8*i]}),
|
715 |
|
|
.TXDATA1({24'b0,gt_tx_data_reg[8*i+15:8*i+8]}),
|
716 |
|
|
.TXDATAWIDTH0(2'b00),
|
717 |
|
|
.TXDATAWIDTH1(2'b00),
|
718 |
|
|
.TXDETECTRX0(gt_tx_detect_rx_loopback_reg[i+0]),
|
719 |
|
|
.TXDETECTRX1(gt_tx_detect_rx_loopback_reg[i+1]),
|
720 |
|
|
.TXDIFFCTRL0(gt_txdiffctrl_0),
|
721 |
|
|
.TXDIFFCTRL1(gt_txdiffctrl_1),
|
722 |
|
|
.TXELECIDLE0(gt_tx_elec_idle_reg[i+0]),
|
723 |
|
|
.TXELECIDLE1(gt_tx_elec_idle_reg[i+1]),
|
724 |
|
|
.TXENC8B10BUSE0(1'b1),
|
725 |
|
|
.TXENC8B10BUSE1(1'b1),
|
726 |
|
|
.TXENPMAPHASEALIGN0(TXENPMAPHASEALIGN),
|
727 |
|
|
.TXENPMAPHASEALIGN1(TXENPMAPHASEALIGN),
|
728 |
|
|
.TXENPRBSTST0(2'b00),
|
729 |
|
|
.TXENPRBSTST1(2'b00),
|
730 |
|
|
.TXHEADER0(3'b000),
|
731 |
|
|
.TXHEADER1(3'b000),
|
732 |
|
|
.TXINHIBIT0(1'b0),
|
733 |
|
|
.TXINHIBIT1(1'b0),
|
734 |
|
|
.TXPMASETPHASE0(TXPMASETPHASE),
|
735 |
|
|
.TXPMASETPHASE1(TXPMASETPHASE),
|
736 |
|
|
.TXPOLARITY0(1'b0),
|
737 |
|
|
.TXPOLARITY1(1'b0),
|
738 |
|
|
.TXPOWERDOWN0(gt_tx_power_down_reg[2*i+1:2*i]),
|
739 |
|
|
.TXPOWERDOWN1(gt_tx_power_down_reg[2*i+3:2*i+2]),
|
740 |
|
|
.TXPREEMPHASIS0({1'b0, gt_txpreemphesis_0}),
|
741 |
|
|
.TXPREEMPHASIS1({1'b0, gt_txpreemphesis_1}),
|
742 |
|
|
.TXRESET0(mgt_txreset || ~clock_lock),
|
743 |
|
|
.TXRESET1(mgt_txreset || ~clock_lock),
|
744 |
|
|
.TXUSRCLK0(gt_usrclk),
|
745 |
|
|
.TXUSRCLK1(gt_usrclk),
|
746 |
|
|
.TXUSRCLK20(gt_usrclk2),
|
747 |
|
|
.TXUSRCLK21(gt_usrclk2),
|
748 |
|
|
|
749 |
|
|
.GTXTEST(14'b10000000000000),
|
750 |
|
|
.DFECLKDLYADJ0(6'b000000),
|
751 |
|
|
.DFECLKDLYADJ1(6'b000000),
|
752 |
|
|
.DFETAP10(5'b00000),
|
753 |
|
|
.DFETAP11(5'b00000),
|
754 |
|
|
.DFETAP20(5'b00000),
|
755 |
|
|
.DFETAP21(5'b00000),
|
756 |
|
|
.DFETAP30(4'b0000),
|
757 |
|
|
.DFETAP31(4'b0000),
|
758 |
|
|
.DFETAP40(4'b0000),
|
759 |
|
|
.DFETAP41(4'b0000),
|
760 |
|
|
.RXENPMAPHASEALIGN0(1'b0),
|
761 |
|
|
.RXENPMAPHASEALIGN1(1'b0),
|
762 |
|
|
.RXGEARBOXSLIP0(1'b0),
|
763 |
|
|
.RXGEARBOXSLIP1(1'b0),
|
764 |
|
|
.RXHEADER0(),
|
765 |
|
|
.RXHEADER1(),
|
766 |
|
|
.RXHEADERVALID0(),
|
767 |
|
|
.RXHEADERVALID1(),
|
768 |
|
|
|
769 |
|
|
.TXSTARTSEQ0(1'b0),
|
770 |
|
|
.TXSTARTSEQ1(1'b0),
|
771 |
|
|
.TXSEQUENCE0(7'h00),
|
772 |
|
|
.TXSEQUENCE1(7'h00),
|
773 |
|
|
.TXGEARBOXREADY0(),
|
774 |
|
|
.TXGEARBOXREADY1(),
|
775 |
|
|
.RXSTARTOFSEQ0(),
|
776 |
|
|
.RXSTARTOFSEQ1(),
|
777 |
|
|
.RXDATAVALID0(),
|
778 |
|
|
.RXDATAVALID1(),
|
779 |
|
|
.DFETAP1MONITOR0(),
|
780 |
|
|
.DFETAP1MONITOR1(),
|
781 |
|
|
.DFETAP2MONITOR0(),
|
782 |
|
|
.DFETAP2MONITOR1(),
|
783 |
|
|
.DFETAP3MONITOR0(),
|
784 |
|
|
.DFETAP3MONITOR1(),
|
785 |
|
|
.DFETAP4MONITOR0(),
|
786 |
|
|
.DFETAP4MONITOR1(),
|
787 |
|
|
.DFESENSCAL0(),
|
788 |
|
|
.DFESENSCAL1(),
|
789 |
|
|
.DFECLKDLYADJMONITOR0(),
|
790 |
|
|
.DFECLKDLYADJMONITOR1(),
|
791 |
|
|
.DFEEYEDACMONITOR0(),
|
792 |
|
|
.DFEEYEDACMONITOR1()
|
793 |
|
|
);
|
794 |
|
|
|
795 |
|
|
end
|
796 |
|
|
endgenerate
|
797 |
|
|
|
798 |
|
|
|
799 |
|
|
|
800 |
|
|
//---------------------- TXSYNC module for Lane to lane deskew ------------------------
|
801 |
|
|
// The TXSYNC module performs phase synchronization for all the active TX
|
802 |
|
|
// datapaths. It waits for the user clocks to be stable, performs required
|
803 |
|
|
// drp operations and drives the phase align signals on each GTX. When
|
804 |
|
|
// phase synchronization is complete, it asserts SYNC_DONE. Include the
|
805 |
|
|
// TX_SYNC module in your own design to perform phase synchronization if
|
806 |
|
|
// your protocol requires TX lane to lane deskew
|
807 |
|
|
|
808 |
|
|
// tile0_txsync_i is reset when
|
809 |
|
|
// 1. tile0_resetdone0 or tile0_resetdone1 goes low due to GTXRESET
|
810 |
|
|
// 2. txusrclk20/1 is unstable
|
811 |
|
|
|
812 |
|
|
|
813 |
|
|
// this is to reset tx_sync
|
814 |
|
|
always @(posedge txsync_clk or posedge gtreset)
|
815 |
|
|
begin
|
816 |
|
|
if (gtreset == 1'b1)
|
817 |
|
|
rst_txsync <= `DLY 1'b1;
|
818 |
|
|
else if (resetdone_all & rst_txsync)
|
819 |
|
|
rst_txsync <= `DLY 1'b0;
|
820 |
|
|
end
|
821 |
|
|
|
822 |
|
|
|
823 |
|
|
// this assert trn_reset_n until sync_done is done
|
824 |
|
|
always @(posedge txsync_clk or posedge gtreset)
|
825 |
|
|
begin
|
826 |
|
|
if (gtreset == 1'b1)
|
827 |
|
|
rst_pcie <= `DLY 1'b1;
|
828 |
|
|
else if (sync_done === 1'b1)
|
829 |
|
|
rst_pcie <= `DLY 1'b0;
|
830 |
|
|
else
|
831 |
|
|
rst_pcie <= `DLY 1'b1;
|
832 |
|
|
|
833 |
|
|
end
|
834 |
|
|
|
835 |
|
|
|
836 |
|
|
assign tx_sync_reset = (pcie_reset == 1'b1) ? (~clock_lock) : 1'b0;
|
837 |
|
|
assign pcie_reset = rst_pcie;
|
838 |
|
|
|
839 |
|
|
|
840 |
|
|
generate
|
841 |
|
|
|
842 |
|
|
if (NO_OF_LANES == 4)
|
843 |
|
|
assign resetdone_all = &resetdone[3:0];
|
844 |
|
|
else if (NO_OF_LANES == 2)
|
845 |
|
|
assign resetdone_all = &resetdone[1:0];
|
846 |
|
|
else if (NO_OF_LANES == 1)
|
847 |
|
|
assign resetdone_all = &resetdone[0];
|
848 |
|
|
else
|
849 |
|
|
assign resetdone_all = &resetdone;
|
850 |
|
|
|
851 |
|
|
endgenerate
|
852 |
|
|
|
853 |
|
|
|
854 |
|
|
generate
|
855 |
|
|
|
856 |
|
|
if (GTDEBUGPORTS == 1)
|
857 |
|
|
BUFGMUX BUFGMUX_i (.I0(gt_dclk), .I1(txsync_clk), .O(drp_clk_in),
|
858 |
|
|
.S(~sync_done) );
|
859 |
|
|
else
|
860 |
|
|
|
861 |
|
|
// this is output of pll @125
|
862 |
|
|
// txsync counters set to 1 for 125, 2 for 250mhz
|
863 |
|
|
assign drp_clk_in = txsync_clk;
|
864 |
|
|
|
865 |
|
|
|
866 |
|
|
endgenerate
|
867 |
|
|
|
868 |
|
|
|
869 |
|
|
|
870 |
|
|
generate
|
871 |
|
|
|
872 |
|
|
if (NO_OF_LANES == 4)
|
873 |
|
|
begin
|
874 |
|
|
assign muxed_drp_daddr = (~sync_done) ?
|
875 |
|
|
{7'h0,txsync_drp_daddr, 7'h0,txsync_drp_daddr} :
|
876 |
|
|
gt_daddr;
|
877 |
|
|
|
878 |
|
|
assign muxed_drp_den = (~sync_done) ?
|
879 |
|
|
{1'b0,txsync_drp_den, 1'b0,txsync_drp_den} :
|
880 |
|
|
{1'b0,gt_den, 1'b0,gt_den};
|
881 |
|
|
|
882 |
|
|
assign muxed_drp_dwen = (~sync_done) ?
|
883 |
|
|
{1'b0,txsync_drp_dwen, 1'b0,txsync_drp_dwen} :
|
884 |
|
|
{1'b0,gt_dwen, 1'b0,gt_dwen};
|
885 |
|
|
|
886 |
|
|
assign muxed_drp_di = (~sync_done) ?
|
887 |
|
|
{16'h0,txsync_drp_di, 16'h0,txsync_drp_di} :
|
888 |
|
|
gt_di;
|
889 |
|
|
|
890 |
|
|
assign txsync_drp_drdy = muxed_drp_drdy;
|
891 |
|
|
assign txsync_drp_do = muxed_drp_do[15:0];
|
892 |
|
|
|
893 |
|
|
assign gt_drdy = (sync_done) ? muxed_drp_drdy : 0;
|
894 |
|
|
assign gt_do = (sync_done) ? muxed_drp_do : 0;
|
895 |
|
|
|
896 |
|
|
end else if ((NO_OF_LANES == 2) || (NO_OF_LANES == 1))
|
897 |
|
|
begin
|
898 |
|
|
assign muxed_drp_daddr = (~sync_done) ?
|
899 |
|
|
{7'h0,txsync_drp_daddr} : gt_daddr;
|
900 |
|
|
|
901 |
|
|
assign muxed_drp_den = (~sync_done) ?
|
902 |
|
|
{1'b0,txsync_drp_den} : {1'b0,gt_den};
|
903 |
|
|
|
904 |
|
|
assign muxed_drp_dwen = (~sync_done) ?
|
905 |
|
|
{1'b0,txsync_drp_dwen} : {1'b0,gt_dwen};
|
906 |
|
|
|
907 |
|
|
assign muxed_drp_di = (~sync_done) ?
|
908 |
|
|
{16'h0,txsync_drp_di} : gt_di;
|
909 |
|
|
|
910 |
|
|
assign txsync_drp_drdy = muxed_drp_drdy;
|
911 |
|
|
assign txsync_drp_do = muxed_drp_do[15:0];
|
912 |
|
|
|
913 |
|
|
assign gt_drdy = (sync_done) ? muxed_drp_drdy : 0;
|
914 |
|
|
assign gt_do = (sync_done) ? muxed_drp_do : 0;
|
915 |
|
|
|
916 |
|
|
end else begin
|
917 |
|
|
assign muxed_drp_daddr = (~sync_done) ?
|
918 |
|
|
{7'h0,txsync_drp_daddr, 7'h0,txsync_drp_daddr,
|
919 |
|
|
7'h0,txsync_drp_daddr, 7'h0,txsync_drp_daddr} :
|
920 |
|
|
gt_daddr;
|
921 |
|
|
|
922 |
|
|
assign muxed_drp_den = (~sync_done) ?
|
923 |
|
|
{1'b0,txsync_drp_den, 1'b0,txsync_drp_den,
|
924 |
|
|
1'b0,txsync_drp_den, 1'b0,txsync_drp_den} :
|
925 |
|
|
{1'b0,gt_den, 1'b0,gt_den,
|
926 |
|
|
1'b0,gt_den, 1'b0,gt_den};
|
927 |
|
|
|
928 |
|
|
assign muxed_drp_dwen = (~sync_done) ?
|
929 |
|
|
{1'b0,txsync_drp_dwen, 1'b0,txsync_drp_dwen,
|
930 |
|
|
1'b0,txsync_drp_dwen, 1'b0,txsync_drp_dwen} :
|
931 |
|
|
{1'b0,gt_dwen, 1'b0,gt_dwen,
|
932 |
|
|
1'b0,gt_dwen, 1'b0,gt_dwen};
|
933 |
|
|
|
934 |
|
|
assign muxed_drp_di = (~sync_done) ?
|
935 |
|
|
{16'h0,txsync_drp_di, 16'h0,txsync_drp_di,
|
936 |
|
|
16'h0,txsync_drp_di, 16'h0,txsync_drp_di} :
|
937 |
|
|
gt_di;
|
938 |
|
|
|
939 |
|
|
assign txsync_drp_drdy = muxed_drp_drdy;
|
940 |
|
|
assign txsync_drp_do = muxed_drp_do[15:0];
|
941 |
|
|
|
942 |
|
|
assign gt_drdy = (sync_done) ? muxed_drp_drdy : 0;
|
943 |
|
|
assign gt_do = (sync_done) ? muxed_drp_do : 0;
|
944 |
|
|
end
|
945 |
|
|
endgenerate
|
946 |
|
|
|
947 |
|
|
|
948 |
|
|
|
949 |
|
|
|
950 |
|
|
|
951 |
|
|
TX_SYNC #
|
952 |
|
|
(
|
953 |
|
|
.PLL_DIVSEL_OUT (1) // using 125Mhz clk
|
954 |
|
|
)
|
955 |
|
|
tile0_txsync_i
|
956 |
|
|
(
|
957 |
|
|
.TXENPMAPHASEALIGN(TXENPMAPHASEALIGN), // o
|
958 |
|
|
.TXPMASETPHASE(TXPMASETPHASE), // o
|
959 |
|
|
.TXRESET(mgt_txreset), // o
|
960 |
|
|
.USER_DO(), // o
|
961 |
|
|
.USER_DI(16'h0), // i
|
962 |
|
|
.USER_DADDR(7'h0), // i
|
963 |
|
|
.USER_DEN(1'b0), // i
|
964 |
|
|
.USER_DWE(1'b0), // i
|
965 |
|
|
.USER_DRDY(), // o
|
966 |
|
|
.GT_DO(txsync_drp_di), // o
|
967 |
|
|
.GT_DI(txsync_drp_do), // i
|
968 |
|
|
|
969 |
|
|
.GT_DADDR(txsync_drp_daddr), // o
|
970 |
|
|
.GT_DEN(txsync_drp_den), // o
|
971 |
|
|
.GT_DWE(txsync_drp_dwen), // o
|
972 |
|
|
.GT_DRDY(txsync_drp_drdy), // i
|
973 |
|
|
.RESTART_SYNC(1'b0), // i
|
974 |
|
|
.SYNC_DONE(sync_done), // o
|
975 |
|
|
.USER_CLK(txsync_clk), // i
|
976 |
|
|
.DCLK(drp_clk_in), // i
|
977 |
|
|
.RESETDONE(resetdone_all), // i
|
978 |
|
|
.RESET(tx_sync_reset) // i
|
979 |
|
|
);
|
980 |
|
|
|
981 |
|
|
|
982 |
|
|
|
983 |
|
|
|
984 |
|
|
///////////////////////////////////////////////////////////////////////////////////////////
|
985 |
|
|
// Logic for enabling L0s state
|
986 |
|
|
///////////////////////////////////////////////////////////////////////////////////////////
|
987 |
|
|
|
988 |
|
|
|
989 |
|
|
|
990 |
|
|
always @(posedge gt_usrclk2 or posedge rst_init) begin
|
991 |
|
|
if (rst_init) begin
|
992 |
|
|
m1_delayed_elec_idle_reset <= 1'b0;
|
993 |
|
|
m2_delayed_elec_idle_reset <= 1'b0;
|
994 |
|
|
delayed_elec_idle_reset <= 1'b0;
|
995 |
|
|
rxreset <= 1'b0;
|
996 |
|
|
end else begin
|
997 |
|
|
// synchronize elec_idle_reset
|
998 |
|
|
m1_delayed_elec_idle_reset <= gt_rx_elec_idle_reset[0];
|
999 |
|
|
m2_delayed_elec_idle_reset <= m1_delayed_elec_idle_reset;
|
1000 |
|
|
delayed_elec_idle_reset <= m2_delayed_elec_idle_reset;
|
1001 |
|
|
// create a one-cycle pulse on rxreset
|
1002 |
|
|
rxreset <= ~m2_delayed_elec_idle_reset & delayed_elec_idle_reset;
|
1003 |
|
|
end
|
1004 |
|
|
end
|
1005 |
|
|
|
1006 |
|
|
// Latch for CDRRESET for L0s
|
1007 |
|
|
wire [7:0] icdrreset;
|
1008 |
|
|
reg [7:0] cdrreset = 0;
|
1009 |
|
|
|
1010 |
|
|
generate
|
1011 |
|
|
genvar j;
|
1012 |
|
|
for (j=0; j < 8; j= j+1)
|
1013 |
|
|
begin: gen_cdrreset
|
1014 |
|
|
|
1015 |
|
|
if (j < NO_OF_LANES) begin: for_GT
|
1016 |
|
|
assign icdrreset[j] = resetdone[j] & gt_rx_elec_idle_reg[j];
|
1017 |
|
|
|
1018 |
|
|
always @( icdrreset or gt_rx_valid_reg) begin : yes_latch
|
1019 |
|
|
if ( icdrreset[j] & ~ gt_rx_valid_reg[j] ) begin
|
1020 |
|
|
cdrreset[j] <= #50 1'b1;
|
1021 |
|
|
end else if ( ~ icdrreset[j] ) begin
|
1022 |
|
|
cdrreset[j] <= #50 1'b0;
|
1023 |
|
|
end
|
1024 |
|
|
end
|
1025 |
|
|
|
1026 |
|
|
assign gt_rx_elec_idle_reset[j] = cdrreset[j];
|
1027 |
|
|
|
1028 |
|
|
end else begin : for_tieoff
|
1029 |
|
|
assign icdrreset[j] = 1'b0;
|
1030 |
|
|
|
1031 |
|
|
//synthesis translate_off
|
1032 |
|
|
initial cdrreset[j] <= 1'b0;
|
1033 |
|
|
//synthesis translate_on
|
1034 |
|
|
|
1035 |
|
|
assign gt_rx_elec_idle_reset[j] = 1'b0;
|
1036 |
|
|
end
|
1037 |
|
|
end
|
1038 |
|
|
endgenerate
|
1039 |
|
|
|
1040 |
|
|
generate
|
1041 |
|
|
genvar k;
|
1042 |
|
|
for (k=0; k < 8; k= k+2)
|
1043 |
|
|
begin: gen_resetb
|
1044 |
|
|
assign gt_rx_en_elec_idle_resetb[k/2] = ~ ( cdrreset[k] | cdrreset[k+1]);
|
1045 |
|
|
end
|
1046 |
|
|
endgenerate
|
1047 |
|
|
|
1048 |
|
|
///////////////////////////////////////////////////////////////////////////////////////////
|
1049 |
|
|
|
1050 |
|
|
|
1051 |
|
|
generate
|
1052 |
|
|
if (NO_OF_LANES == 1 || NO_OF_LANES == 2) begin : laneslt4
|
1053 |
|
|
assign plllkdet_out[3:1] = 3'b0;
|
1054 |
|
|
end else if (NO_OF_LANES == 4) begin : laneseq4
|
1055 |
|
|
assign plllkdet_out[3:2] = 2'b0;
|
1056 |
|
|
end
|
1057 |
|
|
endgenerate
|
1058 |
|
|
|
1059 |
|
|
endmodule
|