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[/] [pcie_ds_dma/] [trunk/] [core/] [ds_dma64/] [pcie_src/] [pcie_core64_m1/] [source/] [pcie_mim_wrapper.v] - Blame information for rev 2

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//-----------------------------------------------------------------------------
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//
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// (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//-----------------------------------------------------------------------------
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// Project    : V5-Block Plus for PCI Express
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// File       : pcie_mim_wrapper.v
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//--------------------------------------------------------------------------------
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//--------------------------------------------------------------------------------
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module pcie_mim_wrapper #(
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   parameter TL_TX_SIZE = 4096,
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   parameter TXWRITEPIPE = 0,
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   parameter TXREADADDRPIPE = 0,
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   parameter TXREADDATAPIPE = 0,
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   parameter TL_RX_SIZE = 4096,
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   parameter RXWRITEPIPE = 0,
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   parameter RXREADADDRPIPE = 0,
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   parameter RXREADDATAPIPE = 0,
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   parameter TLRAMREADLATENCY = 3,
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   parameter TLRAMWRITELATENCY = 0,
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   parameter RETRYRAMSIZE = 9,
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   parameter RETRYRAMREADLATENCY = 3,
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   parameter RETRYRAMWRITELATENCY = 0,
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   parameter RETRYWRITEPIPE = 0,
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   parameter RETRYREADADDRPIPE = 0,
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   parameter RETRYREADDATAPIPE = 0
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)
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(
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   input    [63:0]   mim_rx_bwdata, // Write data for TL RX buffers,  
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   output   [63:0]   mim_rx_brdata, // Read data for TL RX buffers,  
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   input    [12:0]   mim_rx_bwadd, // Write Address for TL RX Buffers,
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   input    [12:0]   mim_rx_bradd, // Read Address for TL RX Buffers,
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   input             mim_rx_bwen,  // Write Enable for TL RX Buffers,
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   input             mim_rx_bren, // Read enable for TL RX Buffers,
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   input             mim_rx_bwclk,// Write clock for TL RX Buffers,
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   input             mim_rx_brclk,// Read clock for TL RX Buffers,
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   input    [63:0]   mim_tx_bwdata, // Write data for TL TX buffers,  
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   output   [63:0]   mim_tx_brdata, // Read data for TL TX buffers,  
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   input    [12:0]   mim_tx_bwadd, // Write Address for TL TX Buffers,
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   input    [12:0]   mim_tx_bradd, // Read Address for TL TX Buffers,
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   input             mim_tx_bwen,  // Write Enable for TL TX Buffers,
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   input             mim_tx_bren, // Read enable for TL TX Buffers,
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   input             mim_tx_bwclk,// Write clock for TL TX Buffers,
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   input             mim_tx_brclk,// Read clock for TL TX Buffers,
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   input    [63:0]   mim_dll_bwdata, // Write data for DLL Retry buffers,  
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   output   [63:0]   mim_dll_brdata, // Read data for DLL Retry buffers,  
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   input    [11:0]   mim_dll_bwadd, // Write Address for DLL Retry Buffers,
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   input    [11:0]   mim_dll_bradd, // Read Address for DLL Retry Buffers,
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   input             mim_dll_bwen,  // Write Enable for DLL Retry Buffers,
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   input             mim_dll_bren, // Read enable for DLL Retry Buffers,
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   input             mim_dll_bclk // Read/Write Clock for DLL Retry Buffers
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);
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// retry bram quanties are always in powers of 2.
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// the code which is passed from the top level module is based on the following alogrithm
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// log2(size in bytes) -3. we have to reverse the alogrithm.
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// the size in bytes can be expressed as power of 2
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// the exponent for the user entered size can be obtained by adding 3 to the value passed by top level
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   parameter NUM_RETRY_BRAMS = 2**(RETRYRAMSIZE + 3 - 12);
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   parameter BRAM_SIZE = 4096;
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   // the above value is based on the fact that all BRAMs are 32Kb = 4096 bytes in size.
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   // this is the default. If the building block BRAM size changes, this needs to be modified
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   // Note: function will never return a value of 0
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// modified this to remove the function and fix a max limit of 32 BRAMS
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//   parameter NUM_TL_TX_BRAMS = get_num_bram_pwr2(TL_TX_SIZE, BRAM_SIZE);
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//   parameter NUM_TL_RX_BRAMS = get_num_bram_pwr2(TL_RX_SIZE, BRAM_SIZE);
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  parameter NUM_TL_TX_BRAMS = (TL_TX_SIZE > 16*BRAM_SIZE) ? 32 :
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                              (TL_TX_SIZE > 8*BRAM_SIZE) ? 16 :
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                              (TL_TX_SIZE > 4*BRAM_SIZE) ? 8:
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                              (TL_TX_SIZE > 2*BRAM_SIZE) ? 4:
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                              (TL_TX_SIZE > BRAM_SIZE) ? 2:1;
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  parameter NUM_TL_RX_BRAMS = (TL_RX_SIZE > 16*BRAM_SIZE) ? 32 :
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                              (TL_RX_SIZE > 8*BRAM_SIZE) ? 16 :
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                              (TL_RX_SIZE > 4*BRAM_SIZE) ? 8:
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                              (TL_RX_SIZE > 2*BRAM_SIZE) ? 4:
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                              (TL_RX_SIZE > BRAM_SIZE) ? 2:1;
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   wire  [63:0]   bram_retry_dangle_douta;
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   wire  [63:0]   bram_tl_tx_dangle_douta;
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   wire  [63:0]   bram_tl_rx_dangle_douta;
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// bram_common is a common single top level entity which is reused to model the three buffers
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// writes are through port a and reads are through portb
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// RELEASE NOTE: All BRAMs have fixed read latencies of 3 and require the output register
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// to be enabled. Hence the parameter BRAM_OREG is set to 1 in all buffers
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initial begin
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$display("===== Number of BRAMS for RETRYRAM = %d  =====",NUM_RETRY_BRAMS);
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$display("===== Number of BRAMS for TL_TXRAM = %d  =====",NUM_TL_TX_BRAMS);
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$display("===== Number of BRAMS for TL_RXRAM = %d  =====",NUM_TL_RX_BRAMS);
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end
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bram_common #(
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      .NUM_BRAMS(NUM_RETRY_BRAMS),
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      .ADDR_WIDTH(12),
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      .READ_LATENCY(RETRYRAMREADLATENCY),
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      .WRITE_LATENCY(RETRYRAMWRITELATENCY),
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      .WRITE_PIPE(RETRYWRITEPIPE),
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      .READ_ADDR_PIPE(RETRYREADADDRPIPE),
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      .READ_DATA_PIPE(RETRYREADDATAPIPE),
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      .BRAM_OREG(1)
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      )
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      bram_retry(
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      .clka(mim_dll_bclk),
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      .ena(mim_dll_bwen),
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      .wena(mim_dll_bwen),
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      .dina(mim_dll_bwdata),
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      .douta(bram_retry_dangle_douta),
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      .addra(mim_dll_bwadd),
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      .clkb(mim_dll_bclk),
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      .enb(mim_dll_bren),
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      .wenb(!mim_dll_bren),
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      .dinb(64'h00000000),
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      .doutb(mim_dll_brdata),
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      .addrb(mim_dll_bradd)
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      );
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bram_common #(
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      .NUM_BRAMS(NUM_TL_TX_BRAMS),
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      .ADDR_WIDTH(13),
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      .READ_LATENCY(TLRAMREADLATENCY),
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      .WRITE_LATENCY(TLRAMWRITELATENCY),
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      .WRITE_PIPE(TXWRITEPIPE),
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      .READ_ADDR_PIPE(TXREADADDRPIPE),
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      .READ_DATA_PIPE(TXREADDATAPIPE),
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      .BRAM_OREG(1)
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      )
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      bram_tl_tx(
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      .clka(mim_tx_bwclk),
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      .ena(mim_tx_bwen),
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      .wena(mim_tx_bwen),
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      .dina(mim_tx_bwdata),
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      .douta(bram_tl_tx_dangle_douta),
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      .addra(mim_tx_bwadd),
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      .clkb(mim_tx_brclk),
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      .enb(mim_tx_bren),
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      .wenb(!mim_tx_bren),
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      .dinb(64'h00000000),
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      .doutb(mim_tx_brdata),
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      .addrb(mim_tx_bradd)
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      );
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bram_common #(
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      .NUM_BRAMS(NUM_TL_RX_BRAMS),
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      .ADDR_WIDTH(13),
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      .READ_LATENCY(TLRAMREADLATENCY),
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      .WRITE_LATENCY(TLRAMWRITELATENCY),
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      .WRITE_PIPE(RXWRITEPIPE),
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      .READ_ADDR_PIPE(RXREADADDRPIPE),
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      .READ_DATA_PIPE(RXREADDATAPIPE),
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      .BRAM_OREG(1)
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      )
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      bram_tl_rx(
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      .clka(mim_rx_bwclk),
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      .ena(mim_rx_bwen),
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      .wena(mim_rx_bwen),
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      .dina(mim_rx_bwdata),
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      .douta(bram_tl_rx_dangle_douta),
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      .addra(mim_rx_bwadd),
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      .clkb(mim_rx_brclk),
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      .enb(mim_rx_bren),
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      .wenb(!mim_rx_bren),
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      .dinb(64'h00000000),
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      .doutb(mim_rx_brdata),
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      .addrb(mim_rx_bradd)
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      );
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endmodule
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