1 |
2 |
dsmv |
|
2 |
|
|
//-----------------------------------------------------------------------------
|
3 |
|
|
//
|
4 |
|
|
// (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
|
5 |
|
|
//
|
6 |
|
|
// This file contains confidential and proprietary information
|
7 |
|
|
// of Xilinx, Inc. and is protected under U.S. and
|
8 |
|
|
// international copyright and other intellectual property
|
9 |
|
|
// laws.
|
10 |
|
|
//
|
11 |
|
|
// DISCLAIMER
|
12 |
|
|
// This disclaimer is not a license and does not grant any
|
13 |
|
|
// rights to the materials distributed herewith. Except as
|
14 |
|
|
// otherwise provided in a valid license issued to you by
|
15 |
|
|
// Xilinx, and to the maximum extent permitted by applicable
|
16 |
|
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
17 |
|
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
18 |
|
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
19 |
|
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
20 |
|
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
21 |
|
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
22 |
|
|
// including negligence, or under any other theory of
|
23 |
|
|
// liability) for any loss or damage of any kind or nature
|
24 |
|
|
// related to, arising under or in connection with these
|
25 |
|
|
// materials, including for any direct, or any indirect,
|
26 |
|
|
// special, incidental, or consequential loss or damage
|
27 |
|
|
// (including loss of data, profits, goodwill, or any type of
|
28 |
|
|
// loss or damage suffered as a result of any action brought
|
29 |
|
|
// by a third party) even if such damage or loss was
|
30 |
|
|
// reasonably foreseeable or Xilinx had been advised of the
|
31 |
|
|
// possibility of the same.
|
32 |
|
|
//
|
33 |
|
|
// CRITICAL APPLICATIONS
|
34 |
|
|
// Xilinx products are not designed or intended to be fail-
|
35 |
|
|
// safe, or for use in any application requiring fail-safe
|
36 |
|
|
// performance, such as life-support or safety devices or
|
37 |
|
|
// systems, Class III medical devices, nuclear facilities,
|
38 |
|
|
// applications related to the deployment of airbags, or any
|
39 |
|
|
// other applications that could lead to death, personal
|
40 |
|
|
// injury, or severe property or environmental damage
|
41 |
|
|
// (individually and collectively, "Critical
|
42 |
|
|
// Applications"). Customer assumes the sole risk and
|
43 |
|
|
// liability of any use of Xilinx products in Critical
|
44 |
|
|
// Applications, subject only to applicable laws and
|
45 |
|
|
// regulations governing limitations on product liability.
|
46 |
|
|
//
|
47 |
|
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
48 |
|
|
// PART OF THIS FILE AT ALL TIMES.
|
49 |
|
|
//
|
50 |
|
|
//-----------------------------------------------------------------------------
|
51 |
|
|
// Project : V5-Block Plus for PCI Express
|
52 |
|
|
// File : pcie_reset_logic.v
|
53 |
|
|
//--------------------------------------------------------------------------------
|
54 |
|
|
//--------------------------------------------------------------------------------
|
55 |
|
|
//
|
56 |
|
|
// ____ ____
|
57 |
|
|
// / /\/ /
|
58 |
|
|
// /___/ \ / Vendor : Xilinx
|
59 |
|
|
// \ \ \/ Version : 1.1
|
60 |
|
|
// \ \ Application : Generated by Xilinx PCI Express Wizard
|
61 |
|
|
// / / Filename : pcie_reset_logic.v
|
62 |
|
|
// /___/ /\ Module : reset_logic
|
63 |
|
|
// \ \ / \
|
64 |
|
|
// \___\/\___\
|
65 |
|
|
//
|
66 |
|
|
//------------------------------------------------------------------------------
|
67 |
|
|
|
68 |
|
|
module reset_logic
|
69 |
|
|
(
|
70 |
|
|
L0DLUPDOWN,
|
71 |
|
|
GSR,
|
72 |
|
|
CRMCORECLK,
|
73 |
|
|
USERCLK,
|
74 |
|
|
L0LTSSMSTATE,
|
75 |
|
|
L0STATSCFGTRANSMITTED,
|
76 |
|
|
CRMDOHOTRESETN,
|
77 |
|
|
CRMPWRSOFTRESETN,
|
78 |
|
|
CRMMGMTRSTN,
|
79 |
|
|
|
80 |
|
|
CRMNVRSTN,
|
81 |
|
|
CRMMACRSTN,
|
82 |
|
|
CRMLINKRSTN,
|
83 |
|
|
CRMURSTN,
|
84 |
|
|
CRMUSERCFGRSTN,
|
85 |
|
|
|
86 |
|
|
user_master_reset_n,
|
87 |
|
|
clock_ready
|
88 |
|
|
|
89 |
|
|
);
|
90 |
|
|
|
91 |
|
|
input L0DLUPDOWN;
|
92 |
|
|
input GSR;
|
93 |
|
|
input CRMCORECLK;
|
94 |
|
|
input USERCLK;
|
95 |
|
|
input [3:0] L0LTSSMSTATE;
|
96 |
|
|
input L0STATSCFGTRANSMITTED;
|
97 |
|
|
input CRMDOHOTRESETN;
|
98 |
|
|
input CRMPWRSOFTRESETN;
|
99 |
|
|
|
100 |
|
|
output CRMMGMTRSTN;
|
101 |
|
|
output CRMNVRSTN;
|
102 |
|
|
output CRMMACRSTN;
|
103 |
|
|
output CRMLINKRSTN;
|
104 |
|
|
output CRMURSTN;
|
105 |
|
|
output CRMUSERCFGRSTN;
|
106 |
|
|
|
107 |
|
|
input user_master_reset_n;
|
108 |
|
|
input clock_ready;
|
109 |
|
|
|
110 |
|
|
parameter G_RESETMODE = "FALSE";
|
111 |
|
|
parameter G_RESETSUBMODE = 1;
|
112 |
|
|
parameter G_USE_EXTRA_REG = 1;
|
113 |
|
|
|
114 |
|
|
// Common logic for all reset mode
|
115 |
|
|
|
116 |
|
|
wire fpga_logic_reset_n;
|
117 |
|
|
assign fpga_logic_reset_n = ~GSR && user_master_reset_n;
|
118 |
|
|
|
119 |
|
|
// L0DLUPDOWN[0] capture
|
120 |
|
|
reg dl_down_1, dl_down_2;
|
121 |
|
|
reg dl_down_reset_1_n, dl_down_reset_2_n;
|
122 |
|
|
reg dl_down_reset_n;
|
123 |
|
|
reg crm_pwr_soft_reset_n_aftersentcpl;
|
124 |
|
|
reg softreset_wait_for_cpl;
|
125 |
|
|
reg crmpwrsoftresetn_d;
|
126 |
|
|
reg l0statscfgtransmitted_d;
|
127 |
|
|
wire crmpwrsoftresetn_fell;
|
128 |
|
|
|
129 |
|
|
always @ (posedge CRMCORECLK, negedge fpga_logic_reset_n)
|
130 |
|
|
if (!fpga_logic_reset_n) begin
|
131 |
|
|
dl_down_1 <= 1'b1;
|
132 |
|
|
dl_down_2 <= 1'b1;
|
133 |
|
|
end else begin
|
134 |
|
|
dl_down_1 <= L0DLUPDOWN;
|
135 |
|
|
dl_down_2 <= dl_down_1;
|
136 |
|
|
end
|
137 |
|
|
|
138 |
|
|
// Edge detect and pulse stretch to create dl_down_reset_n pulse
|
139 |
|
|
// The pulse can be further stretched for debugging purpose by adding
|
140 |
|
|
// more register stages.
|
141 |
|
|
always @ (posedge CRMCORECLK, negedge fpga_logic_reset_n)
|
142 |
|
|
if (!fpga_logic_reset_n) begin
|
143 |
|
|
dl_down_reset_1_n <= 1'b1;
|
144 |
|
|
dl_down_reset_2_n <= 1'b1;
|
145 |
|
|
dl_down_reset_n <= 1'b1;
|
146 |
|
|
end else begin
|
147 |
|
|
dl_down_reset_1_n <= ~(~dl_down_1 & dl_down_2);
|
148 |
|
|
dl_down_reset_2_n <= dl_down_reset_1_n;
|
149 |
|
|
dl_down_reset_n <= dl_down_reset_1_n && dl_down_reset_2_n;
|
150 |
|
|
end
|
151 |
|
|
|
152 |
|
|
|
153 |
|
|
// This logic ensures that if we get a D3->D0 transition (which triggers
|
154 |
|
|
// soft_reset), then we will not reset until the Cpl is generated
|
155 |
|
|
// Wait for CRMPWRSOFTRESETN to assert to indicate this condition, and pulse
|
156 |
|
|
// CRMUSERCFGRSTN once the Cfg Cpl exits (L0STATSCFGTRANSMITTED). It is
|
157 |
|
|
// possible for L0STATSCFGTRANSMITTED to occur simultaneously or one cycle
|
158 |
|
|
// before CRMPWRSOFTRESETN asserts.
|
159 |
|
|
always @ (posedge USERCLK, negedge fpga_logic_reset_n)
|
160 |
|
|
if (!fpga_logic_reset_n)
|
161 |
|
|
softreset_wait_for_cpl <= 1'b0;
|
162 |
|
|
else if (crmpwrsoftresetn_fell && !L0STATSCFGTRANSMITTED && !l0statscfgtransmitted_d)
|
163 |
|
|
softreset_wait_for_cpl <= 1'b1;
|
164 |
|
|
else if (L0STATSCFGTRANSMITTED)
|
165 |
|
|
softreset_wait_for_cpl <= 1'b0;
|
166 |
|
|
|
167 |
|
|
always @ (posedge USERCLK, negedge fpga_logic_reset_n)
|
168 |
|
|
if (!fpga_logic_reset_n) begin
|
169 |
|
|
crm_pwr_soft_reset_n_aftersentcpl <= 1'b1;
|
170 |
|
|
crmpwrsoftresetn_d <= 1'b1;
|
171 |
|
|
l0statscfgtransmitted_d <= 1'b0;
|
172 |
|
|
end else begin
|
173 |
|
|
crm_pwr_soft_reset_n_aftersentcpl <= !((softreset_wait_for_cpl && L0STATSCFGTRANSMITTED) ||
|
174 |
|
|
(!CRMPWRSOFTRESETN && L0STATSCFGTRANSMITTED) ||
|
175 |
|
|
(!CRMPWRSOFTRESETN && l0statscfgtransmitted_d));
|
176 |
|
|
crmpwrsoftresetn_d <= CRMPWRSOFTRESETN;
|
177 |
|
|
l0statscfgtransmitted_d <= L0STATSCFGTRANSMITTED;
|
178 |
|
|
end
|
179 |
|
|
|
180 |
|
|
assign crmpwrsoftresetn_fell = !CRMPWRSOFTRESETN && crmpwrsoftresetn_d;
|
181 |
|
|
|
182 |
|
|
|
183 |
|
|
// End common logic section
|
184 |
|
|
|
185 |
|
|
generate
|
186 |
|
|
if (G_RESETMODE == "TRUE") begin : resetmode_true
|
187 |
|
|
// 6-domain reset mode (RESETMODE=TRUE)
|
188 |
|
|
|
189 |
|
|
if (G_RESETSUBMODE == 0) begin : sub_0_mode_true
|
190 |
|
|
// a. user_master_reset_n is used to drive CRMMGMTRSTN
|
191 |
|
|
assign CRMMGMTRSTN = clock_ready && user_master_reset_n;
|
192 |
|
|
assign CRMNVRSTN = 1'b1;
|
193 |
|
|
assign CRMMACRSTN = 1'b1;
|
194 |
|
|
assign CRMLINKRSTN = dl_down_reset_n && CRMDOHOTRESETN;
|
195 |
|
|
assign CRMURSTN = dl_down_reset_n && CRMDOHOTRESETN;
|
196 |
|
|
assign CRMUSERCFGRSTN = dl_down_reset_n && CRMDOHOTRESETN && crm_pwr_soft_reset_n_aftersentcpl;
|
197 |
|
|
end
|
198 |
|
|
|
199 |
|
|
else begin : sub_1_mode_true
|
200 |
|
|
//b. user_master_reset_n is used but does not drive CRMMGMTRSTN
|
201 |
|
|
assign CRMMGMTRSTN = clock_ready;
|
202 |
|
|
assign CRMNVRSTN = user_master_reset_n;
|
203 |
|
|
assign CRMMACRSTN = user_master_reset_n;
|
204 |
|
|
assign CRMLINKRSTN = user_master_reset_n && dl_down_reset_n && CRMDOHOTRESETN;
|
205 |
|
|
assign CRMURSTN = user_master_reset_n && dl_down_reset_n && CRMDOHOTRESETN;
|
206 |
|
|
assign CRMUSERCFGRSTN = user_master_reset_n && dl_down_reset_n && CRMDOHOTRESETN && crm_pwr_soft_reset_n_aftersentcpl;
|
207 |
|
|
end
|
208 |
|
|
|
209 |
|
|
// End 6-domain reset mode logic
|
210 |
|
|
end
|
211 |
|
|
endgenerate
|
212 |
|
|
|
213 |
|
|
|
214 |
|
|
generate
|
215 |
|
|
if (G_RESETMODE == "FALSE") begin : resetmode_false
|
216 |
|
|
// 4-domain hierarchical reset mode (RESETMODE=FALSE)
|
217 |
|
|
// This mode requires decoding the L0LTSSMSTATE outputs
|
218 |
|
|
// from the PCIe block to detect LTSSM transition from Disabled
|
219 |
|
|
// (1011), Loopback (1001) or Hot Reset (1010) to Detect (0001).
|
220 |
|
|
wire ltssm_linkdown_hot_reset_n;
|
221 |
|
|
reg ltssm_dl_down_last_state;
|
222 |
|
|
reg [3:0] ltssm_capture;
|
223 |
|
|
reg crmpwrsoftresetn_capture;
|
224 |
|
|
reg ltssm_linkdown_hot_reset_reg_n;
|
225 |
|
|
|
226 |
|
|
// Use with G_USE_EXTRA_REG == 1 for better timing
|
227 |
|
|
always @ (posedge CRMCORECLK) begin
|
228 |
|
|
ltssm_capture <= L0LTSSMSTATE;
|
229 |
|
|
//crmpwrsoftresetn_capture <= CRMPWRSOFTRESETN;
|
230 |
|
|
crmpwrsoftresetn_capture <= crm_pwr_soft_reset_n_aftersentcpl;
|
231 |
|
|
ltssm_linkdown_hot_reset_reg_n <= ltssm_linkdown_hot_reset_n;
|
232 |
|
|
end
|
233 |
|
|
|
234 |
|
|
always @ (posedge CRMCORECLK, negedge fpga_logic_reset_n) begin
|
235 |
|
|
if (G_USE_EXTRA_REG == 1) begin
|
236 |
|
|
if (!fpga_logic_reset_n) begin
|
237 |
|
|
ltssm_dl_down_last_state <= 1'b0;
|
238 |
|
|
end else if ((ltssm_capture == 4'b1010) || (ltssm_capture == 4'b1001) || (ltssm_capture == 4'b1011) ||
|
239 |
|
|
(ltssm_capture == 4'b1100) || (ltssm_capture == 4'b0011)) begin
|
240 |
|
|
ltssm_dl_down_last_state <= 1'b1;
|
241 |
|
|
end else begin
|
242 |
|
|
ltssm_dl_down_last_state <= 1'b0;
|
243 |
|
|
end
|
244 |
|
|
end else begin
|
245 |
|
|
if (!fpga_logic_reset_n) begin
|
246 |
|
|
ltssm_dl_down_last_state <= 1'b0;
|
247 |
|
|
end else if ((L0LTSSMSTATE == 4'b1010) || (L0LTSSMSTATE == 4'b1001) || (L0LTSSMSTATE == 4'b1011) ||
|
248 |
|
|
(L0LTSSMSTATE == 4'b1100) || (L0LTSSMSTATE == 4'b0011)) begin
|
249 |
|
|
ltssm_dl_down_last_state <= 1'b1;
|
250 |
|
|
end else begin
|
251 |
|
|
ltssm_dl_down_last_state <= 1'b0;
|
252 |
|
|
end
|
253 |
|
|
end
|
254 |
|
|
end
|
255 |
|
|
|
256 |
|
|
assign ltssm_linkdown_hot_reset_n = (G_USE_EXTRA_REG == 1) ?
|
257 |
|
|
~(ltssm_dl_down_last_state && (ltssm_capture[3:1] == 3'b000)) :
|
258 |
|
|
~(ltssm_dl_down_last_state && (L0LTSSMSTATE[3:1] == 3'b000));
|
259 |
|
|
|
260 |
|
|
if (G_RESETSUBMODE == 0) begin : sub_0_mode_false
|
261 |
|
|
// a. user_master_reset_n is used to drive CRMMGMTRSTN
|
262 |
|
|
assign CRMMGMTRSTN = clock_ready && user_master_reset_n;
|
263 |
|
|
assign CRMNVRSTN = 1'b1;
|
264 |
|
|
assign CRMURSTN = (G_USE_EXTRA_REG == 1) ? ltssm_linkdown_hot_reset_reg_n : ltssm_linkdown_hot_reset_n;
|
265 |
|
|
assign CRMUSERCFGRSTN = (G_USE_EXTRA_REG == 1) ? crmpwrsoftresetn_capture : crm_pwr_soft_reset_n_aftersentcpl;
|
266 |
|
|
assign CRMMACRSTN = 1'b1; // not used, just avoiding 'z' in simulation
|
267 |
|
|
assign CRMLINKRSTN = 1'b1; // not used, just avoiding 'z' in simulation
|
268 |
|
|
end
|
269 |
|
|
|
270 |
|
|
else begin : sub_1_mode_false
|
271 |
|
|
// b. user_master_reset_n is used but does not drive CRMMGMTRSTN
|
272 |
|
|
assign CRMMGMTRSTN = clock_ready;
|
273 |
|
|
assign CRMNVRSTN = user_master_reset_n;
|
274 |
|
|
assign CRMURSTN = (G_USE_EXTRA_REG == 1) ? ltssm_linkdown_hot_reset_reg_n : ltssm_linkdown_hot_reset_n;
|
275 |
|
|
assign CRMUSERCFGRSTN = (G_USE_EXTRA_REG == 1) ? crmpwrsoftresetn_capture : crm_pwr_soft_reset_n_aftersentcpl;
|
276 |
|
|
assign CRMMACRSTN = 1'b1; // not used, just avoiding 'z' in simulation
|
277 |
|
|
assign CRMLINKRSTN = 1'b1; // not used, just avoiding 'z' in simulation
|
278 |
|
|
end
|
279 |
|
|
|
280 |
|
|
// End 4-domain hierarchical reset mode logic
|
281 |
|
|
end
|
282 |
|
|
endgenerate
|
283 |
|
|
|
284 |
|
|
endmodule
|