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//-----------------------------------------------------------------------------
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//
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// (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//-----------------------------------------------------------------------------
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// Project : V5-Block Plus for PCI Express
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// File : pcie_soft_int.v
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//--------------------------------------------------------------------------------
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//--------------------------------------------------------------------------------
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//--
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//-- Description: PCIe Interrupt Module Wrapper for Softcore CMM32 Interrupt
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//-- module
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//--
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//--
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//--
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//------------------------------------------------------------------------------
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`timescale 1ns/1ns
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`ifndef Tcq
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`define Tcq 1
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`endif
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module pcie_soft_cf_int
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(
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// Clock and reset
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input wire clk,
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input wire rst_n,
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input wire cs_is_intr,
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input wire grant,
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input wire [31:0] cfg_msguaddr,
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// PCIe Block Interrupt Ports
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input wire msi_enable,
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output [3:0] msi_request,
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output wire legacy_int_request,
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// LocalLink Interrupt Ports
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input wire cfg_interrupt_n,
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output wire cfg_interrupt_rdy_n,
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// NEWINTERRUPT signals
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input wire msi_8bit_en,
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input wire cfg_interrupt_assert_n,
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input wire [7:0] cfg_interrupt_di,
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output [2:0] cfg_interrupt_mmenable,
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output [7:0] cfg_interrupt_do,
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output cfg_interrupt_msienable,
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input wire [31:0] msi_laddr,
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input wire [31:0] msi_haddr,
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input wire [15:0] cfg_command,
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input wire [15:0] cfg_msgctrl,
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input wire [15:0] cfg_msgdata,
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// To Arb
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output wire signaledint,
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output wire intr_req_valid,
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output wire [1:0] intr_req_type,
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output wire [7:0] intr_vector
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);
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wire intr_rdy;
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assign cfg_interrupt_rdy_n = ~intr_rdy;
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assign cfg_interrupt_msienable = cfg_msgctrl[0]; // adr 0x48
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assign legacy_int_request = 0; // tied low to disable in block
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// legacy will be generated manually
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assign msi_request = 4'd0; // tied low per ug197
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assign cfg_interrupt_mmenable = cfg_msgctrl[6:4]; // MSI Cap Structure
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assign cfg_interrupt_do = cfg_msgdata[7:0]; // MSI Message Data
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// Interrupt controller from softcore
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cmm_intr u_cmm_intr (
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.clk (clk)
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,.rst (~rst_n)
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,.signaledint (signaledint) // O
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,.intr_req_valid (intr_req_valid) // O
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,.intr_req_type (intr_req_type) // O [1:0]
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,.intr_rdy (intr_rdy) // O
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,.cfg_interrupt_n (cfg_interrupt_n) // I [7:0]
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,.cfg_interrupt_assert_n (cfg_interrupt_assert_n) // I
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,.cfg_interrupt_di (cfg_interrupt_di) // I [7:0]
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,.cfg_interrupt_mmenable (cfg_interrupt_mmenable) // I [2:0]
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//,.cfg_interrupt_mmenable (3'b0) // I [2:0]
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,.msi_data (cfg_msgdata) // I[15:0]
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,.intr_vector (intr_vector) // O [7:0]
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,.cfg ( {556'd0, msi_8bit_en ,467'd0} ) // I[1023:0]
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,.command (cfg_command) // I [15:0]
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,.msi_control (cfg_msgctrl) // I [15:0]
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,.msi_laddr (msi_laddr) // I [31:0]
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,.msi_haddr (msi_haddr) // I [31:0]
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//,.intr_grant (grant) // I
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,.intr_grant (grant & cs_is_intr) // I
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);
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endmodule
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