1 |
2 |
dsmv |
|
2 |
|
|
//-----------------------------------------------------------------------------
|
3 |
|
|
//
|
4 |
|
|
// (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
|
5 |
|
|
//
|
6 |
|
|
// This file contains confidential and proprietary information
|
7 |
|
|
// of Xilinx, Inc. and is protected under U.S. and
|
8 |
|
|
// international copyright and other intellectual property
|
9 |
|
|
// laws.
|
10 |
|
|
//
|
11 |
|
|
// DISCLAIMER
|
12 |
|
|
// This disclaimer is not a license and does not grant any
|
13 |
|
|
// rights to the materials distributed herewith. Except as
|
14 |
|
|
// otherwise provided in a valid license issued to you by
|
15 |
|
|
// Xilinx, and to the maximum extent permitted by applicable
|
16 |
|
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
17 |
|
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
18 |
|
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
19 |
|
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
20 |
|
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
21 |
|
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
22 |
|
|
// including negligence, or under any other theory of
|
23 |
|
|
// liability) for any loss or damage of any kind or nature
|
24 |
|
|
// related to, arising under or in connection with these
|
25 |
|
|
// materials, including for any direct, or any indirect,
|
26 |
|
|
// special, incidental, or consequential loss or damage
|
27 |
|
|
// (including loss of data, profits, goodwill, or any type of
|
28 |
|
|
// loss or damage suffered as a result of any action brought
|
29 |
|
|
// by a third party) even if such damage or loss was
|
30 |
|
|
// reasonably foreseeable or Xilinx had been advised of the
|
31 |
|
|
// possibility of the same.
|
32 |
|
|
//
|
33 |
|
|
// CRITICAL APPLICATIONS
|
34 |
|
|
// Xilinx products are not designed or intended to be fail-
|
35 |
|
|
// safe, or for use in any application requiring fail-safe
|
36 |
|
|
// performance, such as life-support or safety devices or
|
37 |
|
|
// systems, Class III medical devices, nuclear facilities,
|
38 |
|
|
// applications related to the deployment of airbags, or any
|
39 |
|
|
// other applications that could lead to death, personal
|
40 |
|
|
// injury, or severe property or environmental damage
|
41 |
|
|
// (individually and collectively, "Critical
|
42 |
|
|
// Applications"). Customer assumes the sole risk and
|
43 |
|
|
// liability of any use of Xilinx products in Critical
|
44 |
|
|
// Applications, subject only to applicable laws and
|
45 |
|
|
// regulations governing limitations on product liability.
|
46 |
|
|
//
|
47 |
|
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
48 |
|
|
// PART OF THIS FILE AT ALL TIMES.
|
49 |
|
|
//
|
50 |
|
|
//-----------------------------------------------------------------------------
|
51 |
|
|
// Project : V5-Block Plus for PCI Express
|
52 |
|
|
// File : pcie_top.v
|
53 |
|
|
//--------------------------------------------------------------------------------
|
54 |
|
|
//--------------------------------------------------------------------------------
|
55 |
|
|
//
|
56 |
|
|
// ____ ____
|
57 |
|
|
// / /\/ /
|
58 |
|
|
// /___/ \ / Vendor : Xilinx
|
59 |
|
|
// \ \ \/ Version : 1.1
|
60 |
|
|
// \ \ Application : Generated by Xilinx PCI Express Wizard
|
61 |
|
|
// / / Filename : pcie_top.v
|
62 |
|
|
// /___/ /\ Module : pcie_top_wrapper
|
63 |
|
|
// \ \ / \
|
64 |
|
|
// \___\/\___\
|
65 |
|
|
//
|
66 |
|
|
//------------------------------------------------------------------------------
|
67 |
|
|
`define PRODFIX 1
|
68 |
|
|
|
69 |
|
|
`define MINF(A,B) (A)>(B)?(B):(A)
|
70 |
|
|
`define MAXF(A,B) (A)>(B)?(A):(B)
|
71 |
|
|
|
72 |
|
|
module pcie_top_wrapper #
|
73 |
|
|
(
|
74 |
|
|
parameter G_SIM = 1,
|
75 |
|
|
parameter G_USER_RESETS = 0,
|
76 |
|
|
|
77 |
|
|
// integer: 0 for 100MHz, 1 for 250 MHz
|
78 |
|
|
// ------------------------------------------------------
|
79 |
|
|
parameter REF_CLK_FREQ = 1,
|
80 |
|
|
|
81 |
|
|
|
82 |
|
|
// integer: 0 for PCI Express Endpoint, 1 for Legacy PCI Express Endpoint
|
83 |
|
|
// ------------------------------------------------------
|
84 |
|
|
parameter COMPONENTTYPE = 0,
|
85 |
|
|
|
86 |
|
|
// integer: 1 for x1 lane, 2 for x2 lanes, 4 for x4 lanes, 8 for x8 lanes
|
87 |
|
|
// ------------------------------------------------------
|
88 |
|
|
parameter NO_OF_LANES = 1,
|
89 |
|
|
|
90 |
|
|
// integer: 1 for 1/1 ratio, 2 for 1/2 ratio, 4 for 1/4 ratio
|
91 |
|
|
// ------------------------------------------------------
|
92 |
|
|
parameter CLKRATIO = 1, // 1: USERCLK = 250 MHz; 2: USERCLK = 125 MHz; 4: USERCLK = 62.5 MHz
|
93 |
|
|
|
94 |
|
|
// (CLKRATIO > 1) ? "TRUE" : "FALSE";
|
95 |
|
|
// ------------------------------------------------------
|
96 |
|
|
parameter CLKDIVIDED = "FALSE",
|
97 |
|
|
|
98 |
|
|
// V5FXT Product
|
99 |
|
|
parameter USE_V5FXT = 0,
|
100 |
|
|
|
101 |
|
|
// 16 bit hex: 10EE for xilinx
|
102 |
|
|
// ------------------------------------------------------
|
103 |
|
|
parameter VENDORID = 16'h10EE,
|
104 |
|
|
|
105 |
|
|
// 16 bit hex:
|
106 |
|
|
// ------------------------------------------------------
|
107 |
|
|
parameter DEVICEID = 16'h5050,
|
108 |
|
|
|
109 |
|
|
// 8 bit hex:
|
110 |
|
|
// ------------------------------------------------------
|
111 |
|
|
parameter REVISIONID = 8'h00,
|
112 |
|
|
|
113 |
|
|
// 16 bit hex:
|
114 |
|
|
// ------------------------------------------------------
|
115 |
|
|
parameter SUBSYSTEMVENDORID = 16'h10EE,
|
116 |
|
|
|
117 |
|
|
// 16 bit hex:
|
118 |
|
|
// ------------------------------------------------------
|
119 |
|
|
parameter SUBSYSTEMID = 16'h5050,
|
120 |
|
|
|
121 |
|
|
// 24 bit hex:
|
122 |
|
|
// ------------------------------------------------------
|
123 |
|
|
parameter CLASSCODE = 24'h058000,
|
124 |
|
|
|
125 |
|
|
// 32 bit hex:
|
126 |
|
|
// ------------------------------------------------------
|
127 |
|
|
parameter CARDBUSCISPOINTER = 32'h00000000,
|
128 |
|
|
|
129 |
|
|
// integer: 0 for NONE, 1 for INTA, 2 for INTB, 3 for INTC, 4 for INTD
|
130 |
|
|
// ------------------------------------------------------
|
131 |
|
|
parameter [7:0] INTERRUPTPIN = 0,
|
132 |
|
|
|
133 |
|
|
// integer: 0 for false, 1 for true
|
134 |
|
|
// ------------------------------------------------------
|
135 |
|
|
parameter BAR0EXIST = "TRUE",
|
136 |
|
|
|
137 |
|
|
// integer: 0 for MEMORY, 1 for I/O
|
138 |
|
|
// ------------------------------------------------------
|
139 |
|
|
parameter BAR0IOMEMN = 0,
|
140 |
|
|
|
141 |
|
|
// integer: 0 for false, 1 for true
|
142 |
|
|
// ------------------------------------------------------
|
143 |
|
|
parameter BAR064 = 0,
|
144 |
|
|
|
145 |
|
|
// integer: 0 for false, 1 for true
|
146 |
|
|
// ------------------------------------------------------
|
147 |
|
|
parameter BAR0PREFETCHABLE = "FALSE",
|
148 |
|
|
|
149 |
|
|
// integer:
|
150 |
|
|
// ------------------------------------------------------
|
151 |
|
|
parameter [5:0] BAR0MASKWIDTH = 20,
|
152 |
|
|
|
153 |
|
|
// integer: 0 for false, 1 for true
|
154 |
|
|
// ------------------------------------------------------
|
155 |
|
|
parameter BAR1EXIST = "FALSE",
|
156 |
|
|
|
157 |
|
|
// integer: 0 for MEMORY, 1 for I/O
|
158 |
|
|
// ------------------------------------------------------
|
159 |
|
|
parameter BAR1IOMEMN = 0,
|
160 |
|
|
|
161 |
|
|
// integer: 0 for false, 1 for true
|
162 |
|
|
// ------------------------------------------------------
|
163 |
|
|
parameter BAR1PREFETCHABLE = "FALSE",
|
164 |
|
|
|
165 |
|
|
// integer:
|
166 |
|
|
// ------------------------------------------------------
|
167 |
|
|
parameter [5:0] BAR1MASKWIDTH = 0,
|
168 |
|
|
|
169 |
|
|
// integer: 0 for false, 1 for true
|
170 |
|
|
// ------------------------------------------------------
|
171 |
|
|
parameter BAR2EXIST = "FALSE",
|
172 |
|
|
|
173 |
|
|
// integer: 0 for MEMORY, 1 for I/O
|
174 |
|
|
// ------------------------------------------------------
|
175 |
|
|
parameter BAR2IOMEMN = 0,
|
176 |
|
|
|
177 |
|
|
// integer: 0 for false, 1 for true
|
178 |
|
|
// ------------------------------------------------------
|
179 |
|
|
parameter BAR264 = 0,
|
180 |
|
|
|
181 |
|
|
// integer: 0 for false, 1 for true
|
182 |
|
|
// ------------------------------------------------------
|
183 |
|
|
parameter BAR2PREFETCHABLE = "FALSE",
|
184 |
|
|
|
185 |
|
|
// integer:
|
186 |
|
|
// ------------------------------------------------------
|
187 |
|
|
parameter [5:0] BAR2MASKWIDTH = 0,
|
188 |
|
|
|
189 |
|
|
// integer: 0 for false, 1 for true
|
190 |
|
|
// ------------------------------------------------------
|
191 |
|
|
parameter BAR3EXIST = "FALSE",
|
192 |
|
|
|
193 |
|
|
// integer: 0 for MEMORY, 1 for I/O
|
194 |
|
|
// ------------------------------------------------------
|
195 |
|
|
parameter BAR3IOMEMN = 0,
|
196 |
|
|
|
197 |
|
|
// integer: 0 for false, 1 for true
|
198 |
|
|
// ------------------------------------------------------
|
199 |
|
|
parameter BAR3PREFETCHABLE = "FALSE",
|
200 |
|
|
|
201 |
|
|
// integer:
|
202 |
|
|
// ------------------------------------------------------
|
203 |
|
|
parameter [5:0] BAR3MASKWIDTH = 0,
|
204 |
|
|
|
205 |
|
|
// integer: 0 for false, 1 for true
|
206 |
|
|
// ------------------------------------------------------
|
207 |
|
|
parameter BAR4EXIST = "FALSE",
|
208 |
|
|
|
209 |
|
|
// integer: 0 for MEMORY, 1 for I/O
|
210 |
|
|
// ------------------------------------------------------
|
211 |
|
|
parameter BAR4IOMEMN = 0,
|
212 |
|
|
|
213 |
|
|
// integer: 0 for false, 1 for true
|
214 |
|
|
// ------------------------------------------------------
|
215 |
|
|
parameter BAR464 = 0,
|
216 |
|
|
|
217 |
|
|
// integer: 0 for false, 1 for true
|
218 |
|
|
// ------------------------------------------------------
|
219 |
|
|
parameter BAR4PREFETCHABLE = "FALSE",
|
220 |
|
|
|
221 |
|
|
// integer:
|
222 |
|
|
// ------------------------------------------------------
|
223 |
|
|
parameter [5:0] BAR4MASKWIDTH = 0,
|
224 |
|
|
|
225 |
|
|
// integer: 0 for false, 1 for true
|
226 |
|
|
// ------------------------------------------------------
|
227 |
|
|
parameter BAR5EXIST = "FALSE",
|
228 |
|
|
|
229 |
|
|
// integer: 0 for MEMORY, 1 for I/O
|
230 |
|
|
// ------------------------------------------------------
|
231 |
|
|
parameter BAR5IOMEMN = 0,
|
232 |
|
|
|
233 |
|
|
// integer: 0 for false, 1 for true
|
234 |
|
|
// ------------------------------------------------------
|
235 |
|
|
parameter BAR5PREFETCHABLE = "FALSE",
|
236 |
|
|
|
237 |
|
|
// integer:
|
238 |
|
|
// ------------------------------------------------------
|
239 |
|
|
parameter [5:0] BAR5MASKWIDTH = 0,
|
240 |
|
|
|
241 |
|
|
// integer: 0:128, 1:256, 2:512, 3:1024, 4:2048, 5:4096
|
242 |
|
|
// ------------------------------------------------------
|
243 |
|
|
parameter MAXPAYLOADSIZE = 0,
|
244 |
|
|
|
245 |
|
|
// integer: 0 for max of 64ns, 1 for max of 128ns, 2 for max of 256ns, 3 for max of 512ns,
|
246 |
|
|
// 4 for max of 1us, 5 for max of 2us, 6 for max of 4us, 7 for no limit
|
247 |
|
|
// ------------------------------------------------------
|
248 |
|
|
parameter [2:0] DEVICECAPABILITYENDPOINTL0SLATENCY = 0,
|
249 |
|
|
|
250 |
|
|
// integer: 0 for max of 1us, 1 for max of 2us, 2 for max of 4us, 3 for max of 8us,
|
251 |
|
|
// 4 for max of 16us, 5 for max of 32us, 6 for max of 64us, 7 for no limit
|
252 |
|
|
// ------------------------------------------------------
|
253 |
|
|
parameter [2:0] DEVICECAPABILITYENDPOINTL1LATENCY = 0,
|
254 |
|
|
|
255 |
|
|
// integer: 0 for false, 1 for true
|
256 |
|
|
// ------------------------------------------------------
|
257 |
|
|
parameter LINKCAPABILITYASPMSUPPORTEN = 0,
|
258 |
|
|
|
259 |
|
|
// integer: 0 for less than 64ns, 1 for 64ns to 128ns, 2 for 128ns to 256ns, 3 for 256ns to 512ns,
|
260 |
|
|
// 4 for 512ns to 1us, 5 for 1us to 2us, 6 for 2us to 4us, 7 for more than 4us
|
261 |
|
|
// ------------------------------------------------------
|
262 |
|
|
parameter L0SEXITLATENCY = 7,
|
263 |
|
|
|
264 |
|
|
// integer: 0 for less than 64ns, 1 for 64ns to 128ns, 2 for 128ns to 256ns, 3 for 256ns to 512ns,
|
265 |
|
|
// 4 for 512ns to 1us, 5 for 1us to 2us, 6 for 2us to 4us, 7 for more than 4us
|
266 |
|
|
// ------------------------------------------------------
|
267 |
|
|
parameter L0SEXITLATENCYCOMCLK = 7,
|
268 |
|
|
|
269 |
|
|
// integer: 0 for less than 1us, 1 for 1us to 2us, 2 for 2us to 4us, 3 for 4us to 8us,
|
270 |
|
|
// 4 for 8us to 16us, 5 for 16us to 32us, 6 for 32us to 64us, 7 for more than 64us
|
271 |
|
|
// ------------------------------------------------------
|
272 |
|
|
parameter L1EXITLATENCY = 7,
|
273 |
|
|
|
274 |
|
|
// integer: 0 for less than 1us, 1 for 1us to 2us, 2 for 2us to 4us, 3 for 4us to 8us,
|
275 |
|
|
// 4 for 8us to 16us, 5 for 16us to 32us, 6 for 32us to 64us, 7 for more than 64us
|
276 |
|
|
// ------------------------------------------------------
|
277 |
|
|
parameter L1EXITLATENCYCOMCLK = 7,
|
278 |
|
|
|
279 |
|
|
// integer: 0 for false, 1 for true
|
280 |
|
|
// ------------------------------------------------------
|
281 |
|
|
parameter MSIENABLE = 0,
|
282 |
|
|
|
283 |
|
|
// integer: 0 for false, 1 for true
|
284 |
|
|
// ------------------------------------------------------
|
285 |
|
|
parameter DSNENABLE = 0,
|
286 |
|
|
|
287 |
|
|
// integer: 0 for false, 1 for true
|
288 |
|
|
// ------------------------------------------------------
|
289 |
|
|
parameter VCENABLE = 0,
|
290 |
|
|
|
291 |
|
|
// integer: 0 for 1 message, 1 for 2 messages, 2 for 4 messages
|
292 |
|
|
// ------------------------------------------------------
|
293 |
|
|
parameter [2:0] MSICAPABILITYMULTIMSGCAP = 0,
|
294 |
|
|
|
295 |
|
|
//boolean
|
296 |
|
|
// ------------------------------------------------------
|
297 |
|
|
parameter PMCAPABILITYDSI = "TRUE",
|
298 |
|
|
|
299 |
|
|
// PME Support
|
300 |
|
|
// 5bit: {D3cold, D3hot, D2, D1, D0}
|
301 |
|
|
// ------------------------------------------------------
|
302 |
|
|
parameter PMCAPABILITYPMESUPPORT = 5'b00000,
|
303 |
|
|
|
304 |
|
|
// integer: 0, 1
|
305 |
|
|
// ------------------------------------------------------
|
306 |
|
|
parameter [2:0] PORTVCCAPABILITYEXTENDEDVCCOUNT = 0,
|
307 |
|
|
|
308 |
|
|
// integer: 0 for none, 1 for round robin, 2 for weighted round robin
|
309 |
|
|
// ------------------------------------------------------
|
310 |
|
|
parameter [7:0] PORTVCCAPABILITYVCARBCAP = 0,
|
311 |
|
|
|
312 |
|
|
// integer: 0, 1
|
313 |
|
|
// ------------------------------------------------------
|
314 |
|
|
parameter LOWPRIORITYVCCOUNT = 0,
|
315 |
|
|
|
316 |
|
|
// 64 bit hex:
|
317 |
|
|
// ------------------------------------------------------
|
318 |
|
|
parameter DEVICESERIALNUMBER = 64'hE000000001000A35,
|
319 |
|
|
|
320 |
|
|
// integer: 0 for false, 1 for true
|
321 |
|
|
// ------------------------------------------------------
|
322 |
|
|
parameter FORCENOSCRAMBLING = 1'b0,
|
323 |
|
|
|
324 |
|
|
// boolean
|
325 |
|
|
// ------------------------------------------------------
|
326 |
|
|
parameter INFINITECOMPLETIONS = "TRUE",
|
327 |
|
|
|
328 |
|
|
// integer: 0 - 255
|
329 |
|
|
// ------------------------------------------------------
|
330 |
|
|
parameter VC0_CREDITS_PH = 8,
|
331 |
|
|
parameter VC0_CREDITS_NPH = 8,
|
332 |
|
|
|
333 |
|
|
// integer: 0 for false, 1 for true
|
334 |
|
|
// ------------------------------------------------------
|
335 |
|
|
parameter LINKSTATUSSLOTCLOCKCONFIG = "FALSE",
|
336 |
|
|
|
337 |
|
|
// integer: 0..255
|
338 |
|
|
// ------------------------------------------------------
|
339 |
|
|
parameter TXTSNFTS = 255,
|
340 |
|
|
|
341 |
|
|
// integer: 0..255
|
342 |
|
|
// ------------------------------------------------------
|
343 |
|
|
parameter TXTSNFTSCOMCLK = 255,
|
344 |
|
|
|
345 |
|
|
// boolean
|
346 |
|
|
// ------------------------------------------------------
|
347 |
|
|
parameter RESETMODE = "TRUE",
|
348 |
|
|
|
349 |
|
|
// integer: 4096, 8192, 16384, 32768
|
350 |
|
|
// GUI encoding: 4096bytes: 9, 8192: 10, 16384: 11, 32768: 12
|
351 |
|
|
// ------------------------------------------------------
|
352 |
|
|
parameter RETRYRAMSIZE = 9,
|
353 |
|
|
|
354 |
|
|
// integer:
|
355 |
|
|
// ------------------------------------------------------
|
356 |
|
|
parameter VC0RXFIFOSIZEP = 1024,
|
357 |
|
|
|
358 |
|
|
// integer:
|
359 |
|
|
// ------------------------------------------------------
|
360 |
|
|
parameter VC0RXFIFOSIZENP = 192,
|
361 |
|
|
|
362 |
|
|
// integer:
|
363 |
|
|
// ------------------------------------------------------
|
364 |
|
|
parameter VC0RXFIFOSIZEC = 1024,
|
365 |
|
|
|
366 |
|
|
// integer:
|
367 |
|
|
// ------------------------------------------------------
|
368 |
|
|
parameter VC1RXFIFOSIZEP = 0,
|
369 |
|
|
|
370 |
|
|
// integer:
|
371 |
|
|
// ------------------------------------------------------
|
372 |
|
|
parameter VC1RXFIFOSIZENP = 0,
|
373 |
|
|
|
374 |
|
|
// integer:
|
375 |
|
|
// ------------------------------------------------------
|
376 |
|
|
parameter VC1RXFIFOSIZEC = 0,
|
377 |
|
|
|
378 |
|
|
// integer:
|
379 |
|
|
// ------------------------------------------------------
|
380 |
|
|
parameter VC0TXFIFOSIZEP = 1024,
|
381 |
|
|
|
382 |
|
|
// integer:
|
383 |
|
|
// ------------------------------------------------------
|
384 |
|
|
parameter VC0TXFIFOSIZENP = 192,
|
385 |
|
|
|
386 |
|
|
// integer:
|
387 |
|
|
// ------------------------------------------------------
|
388 |
|
|
parameter VC0TXFIFOSIZEC = 1024,
|
389 |
|
|
|
390 |
|
|
// integer:
|
391 |
|
|
// ------------------------------------------------------
|
392 |
|
|
parameter VC1TXFIFOSIZEP = 0,
|
393 |
|
|
|
394 |
|
|
// integer:
|
395 |
|
|
// ------------------------------------------------------
|
396 |
|
|
parameter VC1TXFIFOSIZENP = 0,
|
397 |
|
|
|
398 |
|
|
// integer:
|
399 |
|
|
// ------------------------------------------------------
|
400 |
|
|
parameter VC1TXFIFOSIZEC = 0,
|
401 |
|
|
|
402 |
|
|
// integer:
|
403 |
|
|
// ------------------------------------------------------
|
404 |
|
|
parameter TXDIFFBOOST = "FALSE",
|
405 |
|
|
|
406 |
|
|
// integer:
|
407 |
|
|
// ------------------------------------------------------
|
408 |
|
|
parameter GTDEBUGPORTS = 0
|
409 |
|
|
|
410 |
|
|
|
411 |
|
|
|
412 |
|
|
)
|
413 |
|
|
|
414 |
|
|
(
|
415 |
|
|
|
416 |
|
|
input wire user_reset_n,
|
417 |
|
|
|
418 |
|
|
output wire core_clk,
|
419 |
|
|
output wire user_clk,
|
420 |
|
|
output wire clock_lock,
|
421 |
|
|
|
422 |
|
|
input wire gsr,
|
423 |
|
|
|
424 |
|
|
input wire crm_urst_n,
|
425 |
|
|
input wire crm_nvrst_n,
|
426 |
|
|
input wire crm_mgmt_rst_n,
|
427 |
|
|
input wire crm_user_cfg_rst_n,
|
428 |
|
|
input wire crm_mac_rst_n,
|
429 |
|
|
input wire crm_link_rst_n,
|
430 |
|
|
|
431 |
|
|
input wire compliance_avoid,
|
432 |
|
|
input wire l0_cfg_loopback_master,
|
433 |
|
|
input wire l0_transactions_pending,
|
434 |
|
|
|
435 |
|
|
|
436 |
|
|
input wire l0_set_completer_abort_error,
|
437 |
|
|
input wire l0_set_detected_corr_error,
|
438 |
|
|
input wire l0_set_detected_fatal_error,
|
439 |
|
|
input wire l0_set_detected_nonfatal_error,
|
440 |
|
|
input wire l0_set_user_detected_parity_error,
|
441 |
|
|
input wire l0_set_user_master_data_parity,
|
442 |
|
|
input wire l0_set_user_received_master_abort,
|
443 |
|
|
input wire l0_set_user_received_target_abort,
|
444 |
|
|
input wire l0_set_user_system_error,
|
445 |
|
|
input wire l0_set_user_signalled_target_abort,
|
446 |
|
|
input wire l0_set_completion_timeout_uncorr_error,
|
447 |
|
|
input wire l0_set_completion_timeout_corr_error,
|
448 |
|
|
input wire l0_set_unexpected_completion_uncorr_error,
|
449 |
|
|
input wire l0_set_unexpected_completion_corr_error,
|
450 |
|
|
input wire l0_set_unsupported_request_nonposted_error,
|
451 |
|
|
input wire l0_set_unsupported_request_other_error,
|
452 |
|
|
input wire l0_legacy_int_funct0,
|
453 |
|
|
input wire [3:0] l0_msi_request0,
|
454 |
|
|
|
455 |
|
|
input wire [31:0] mgmt_wdata,
|
456 |
|
|
input wire [3:0] mgmt_bwren,
|
457 |
|
|
input wire mgmt_wren,
|
458 |
|
|
input wire [10:0] mgmt_addr,
|
459 |
|
|
input wire mgmt_rden,
|
460 |
|
|
|
461 |
|
|
input wire [6:0] mgmt_stats_credit_sel,
|
462 |
|
|
|
463 |
|
|
|
464 |
|
|
output crm_do_hot_reset_n,
|
465 |
|
|
output crm_pwr_soft_reset_n,
|
466 |
|
|
|
467 |
|
|
output [31:0] mgmt_rdata,
|
468 |
|
|
output [16:0] mgmt_pso,
|
469 |
|
|
output [11:0] mgmt_stats_credit,
|
470 |
|
|
output l0_first_cfg_write_occurred,
|
471 |
|
|
output l0_cfg_loopback_ack,
|
472 |
|
|
output [1:0] l0_rx_mac_link_error,
|
473 |
|
|
output l0_mac_link_up,
|
474 |
|
|
output wire [3:0] l0_mac_negotiated_link_width,
|
475 |
|
|
output l0_mac_link_training,
|
476 |
|
|
output [3:0] l0_ltssm_state,
|
477 |
|
|
|
478 |
|
|
output l0_mac_new_state_ack,
|
479 |
|
|
output l0_mac_rx_l0s_state,
|
480 |
|
|
output l0_mac_entered_l0,
|
481 |
|
|
|
482 |
|
|
output [7:0] l0_dl_up_down,
|
483 |
|
|
output [6:0] l0_dll_error_vector,
|
484 |
|
|
|
485 |
|
|
output [12:0] l0_completer_id,
|
486 |
|
|
|
487 |
|
|
output l0_msi_enable0,
|
488 |
|
|
output [2:0] l0_multi_msg_en0,
|
489 |
|
|
output l0_stats_dllp_received,
|
490 |
|
|
output l0_stats_dllp_transmitted,
|
491 |
|
|
output l0_stats_os_received,
|
492 |
|
|
output l0_stats_os_transmitted,
|
493 |
|
|
output l0_stats_tlp_received,
|
494 |
|
|
output l0_stats_tlp_transmitted,
|
495 |
|
|
output l0_stats_cfg_received,
|
496 |
|
|
output l0_stats_cfg_transmitted,
|
497 |
|
|
output l0_stats_cfg_other_received,
|
498 |
|
|
output l0_stats_cfg_other_transmitted,
|
499 |
|
|
|
500 |
|
|
output [1:0] l0_pwr_state0,
|
501 |
|
|
output l0_pwr_l23_ready_state,
|
502 |
|
|
output l0_pwr_tx_l0s_state,
|
503 |
|
|
output l0_pwr_turn_off_req,
|
504 |
|
|
input l0_pme_req_in, //JBG
|
505 |
|
|
output l0_pme_ack, //JBG
|
506 |
|
|
|
507 |
|
|
|
508 |
|
|
output io_space_enable,
|
509 |
|
|
output mem_space_enable,
|
510 |
|
|
output bus_master_enable,
|
511 |
|
|
output parity_error_response,
|
512 |
|
|
output serr_enable,
|
513 |
|
|
output interrupt_disable,
|
514 |
|
|
output ur_reporting_enable,
|
515 |
|
|
|
516 |
|
|
//Local Link Interface ports
|
517 |
|
|
// TX ports
|
518 |
|
|
input wire [63:0] llk_tx_data,
|
519 |
|
|
input wire llk_tx_src_rdy_n,
|
520 |
|
|
input wire llk_tx_sof_n,
|
521 |
|
|
input wire llk_tx_eof_n,
|
522 |
|
|
input wire llk_tx_sop_n,
|
523 |
|
|
input wire llk_tx_eop_n,
|
524 |
|
|
input wire [1:0] llk_tx_enable_n,
|
525 |
|
|
input wire [2:0] llk_tx_ch_tc,
|
526 |
|
|
input wire [1:0] llk_tx_ch_fifo,
|
527 |
|
|
input wire llk_tx_src_dsc_n,
|
528 |
|
|
output llk_tx_dst_rdy_n,
|
529 |
|
|
output [9:0] llk_tx_chan_space,
|
530 |
|
|
output [7:0] llk_tx_ch_posted_ready_n,
|
531 |
|
|
output [7:0] llk_tx_ch_non_posted_ready_n,
|
532 |
|
|
output [7:0] llk_tx_ch_completion_ready_n,
|
533 |
|
|
// RX Ports
|
534 |
|
|
input wire llk_rx_dst_req_n,
|
535 |
|
|
input wire llk_rx_dst_cont_req_n,
|
536 |
|
|
input wire [2:0] llk_rx_ch_tc,
|
537 |
|
|
input wire [1:0] llk_rx_ch_fifo,
|
538 |
|
|
output [7:0] llk_tc_status,
|
539 |
|
|
output [63:0] llk_rx_data,
|
540 |
|
|
output llk_rx_src_rdy_n,
|
541 |
|
|
output llk_rx_src_last_req_n,
|
542 |
|
|
output llk_rx_sof_n,
|
543 |
|
|
output llk_rx_eof_n,
|
544 |
|
|
output llk_rx_sop_n,
|
545 |
|
|
output llk_rx_eop_n,
|
546 |
|
|
output [1:0] llk_rx_valid_n,
|
547 |
|
|
output [7:0] llk_rx_ch_posted_available_n,
|
548 |
|
|
output [7:0] llk_rx_ch_non_posted_available_n,
|
549 |
|
|
output [7:0] llk_rx_ch_completion_available_n,
|
550 |
|
|
output [15:0] llk_rx_preferred_type,
|
551 |
|
|
|
552 |
|
|
input wire [NO_OF_LANES - 1: 0] RXN,
|
553 |
|
|
input wire [NO_OF_LANES - 1: 0] RXP,
|
554 |
|
|
output wire [NO_OF_LANES - 1: 0] TXN,
|
555 |
|
|
output wire [NO_OF_LANES - 1: 0] TXP,
|
556 |
|
|
output wire GTPCLK_bufg,
|
557 |
|
|
output wire REFCLKOUT_bufg,
|
558 |
|
|
output wire [3: 0] PLLLKDET_OUT,
|
559 |
|
|
output wire [7: 0] RESETDONE,
|
560 |
|
|
output wire [338:0] DEBUG,
|
561 |
|
|
input wire GTPRESET,
|
562 |
|
|
input wire REFCLK,
|
563 |
|
|
|
564 |
|
|
input wire [7:0] gt_rx_present,
|
565 |
|
|
|
566 |
|
|
input gt_dclk,
|
567 |
|
|
input wire [NO_OF_LANES*7-1:0] gt_daddr,
|
568 |
|
|
input wire [NO_OF_LANES-1:0] gt_den,
|
569 |
|
|
input wire [NO_OF_LANES-1:0] gt_dwen,
|
570 |
|
|
input wire [NO_OF_LANES*16-1:0] gt_di,
|
571 |
|
|
output wire [NO_OF_LANES*16-1:0] gt_do,
|
572 |
|
|
output wire [NO_OF_LANES-1:0] gt_drdy,
|
573 |
|
|
|
574 |
|
|
input wire [2:0] gt_txdiffctrl_0,
|
575 |
|
|
input wire [2:0] gt_txdiffctrl_1,
|
576 |
|
|
input wire [2:0] gt_txbuffctrl_0,
|
577 |
|
|
input wire [2:0] gt_txbuffctrl_1,
|
578 |
|
|
input wire [2:0] gt_txpreemphesis_0,
|
579 |
|
|
input wire [2:0] gt_txpreemphesis_1,
|
580 |
|
|
|
581 |
|
|
input trn_lnk_up_n,
|
582 |
|
|
|
583 |
|
|
output wire [2:0] max_payload_size,
|
584 |
|
|
output wire [2:0] max_read_request_size,
|
585 |
|
|
`ifdef MANAGEMENT_WRITE
|
586 |
|
|
input wire mgmt_reset_delay_n,
|
587 |
|
|
output wire mgmt_rdy,
|
588 |
|
|
`endif
|
589 |
|
|
input fast_train_simulation_only
|
590 |
|
|
|
591 |
|
|
);
|
592 |
|
|
|
593 |
|
|
|
594 |
|
|
//////////////////////////////////
|
595 |
|
|
|
596 |
|
|
// PARAMETER DECLARATIONS WHICH MATCH GUI SOFTWARE ATTRIBUTES
|
597 |
|
|
// COREGEN WILL INSTANTIATE THE TOP LEVEL MODULE AND MAP THE PARAMETERS
|
598 |
|
|
// BASED ON GUI ENTRIES
|
599 |
|
|
//
|
600 |
|
|
// generic parameter definitions
|
601 |
|
|
parameter DUALROLECFGCNTRLROOTEPN = 1'b0;
|
602 |
|
|
parameter ISSWITCH = "FALSE";
|
603 |
|
|
parameter UPSTREAMFACING = "TRUE";
|
604 |
|
|
parameter HEADERTYPE = 8'h00;
|
605 |
|
|
|
606 |
|
|
parameter XPDEVICEPORTTYPE = (COMPONENTTYPE==0)? 4'b0000:4'b0001;
|
607 |
|
|
|
608 |
|
|
// NO_OF_LANES is defined at the module port list level as it is used to decide
|
609 |
|
|
// the width of the cumulative serial rx and tx ports
|
610 |
|
|
parameter [7:0] ACTIVELANESIN = 2**(NO_OF_LANES) - 1;
|
611 |
|
|
|
612 |
|
|
//SCREEN 2 // GUI Note
|
613 |
|
|
|
614 |
|
|
//SCREEN 3 :BASE ADDRESS REGISTERS // GUI Note
|
615 |
|
|
|
616 |
|
|
// override settings if IO, else pass through after converting boolean to binary
|
617 |
|
|
localparam [0:0] BAR0ADDRWIDTH_CALC = (BAR0IOMEMN == 0) ? BAR064 :0;
|
618 |
|
|
//localparam BAR0PREFETCHABLE_CALC = (BAR0IOMEMN == 0) ? BAR0PREFETCHABLE :"FALSE";
|
619 |
|
|
`define BAR0PREFETCHABLE_CALC ((BAR0IOMEMN == 0) ? (BAR0PREFETCHABLE) :("FALSE"))
|
620 |
|
|
|
621 |
|
|
// override settings if IO, else pass through after converting boolean to binary
|
622 |
|
|
// Note that BAR1 cannot have 64 bit checked. BAR364 will always be FALSE
|
623 |
|
|
localparam [0:0] BAR1ADDRWIDTH_CALC = 0;
|
624 |
|
|
//localparam BAR1PREFETCHABLE_CALC = (BAR1IOMEMN == 0) ? BAR1PREFETCHABLE:"FALSE";
|
625 |
|
|
`define BAR1PREFETCHABLE_CALC ((BAR1IOMEMN == 0) ? (BAR1PREFETCHABLE):("FALSE"))
|
626 |
|
|
|
627 |
|
|
localparam [0:0] BAR2ADDRWIDTH_CALC = (BAR2IOMEMN == 0) ? BAR264:0;
|
628 |
|
|
//localparam BAR2PREFETCHABLE_CALC = (BAR2IOMEMN == 0) ? BAR2PREFETCHABLE:"FALSE";
|
629 |
|
|
`define BAR2PREFETCHABLE_CALC ((BAR2IOMEMN == 0) ? (BAR2PREFETCHABLE):("FALSE"))
|
630 |
|
|
|
631 |
|
|
// override settings if IO, else pass through after converting boolean to binary
|
632 |
|
|
// Note that BAR3 cannot have 64 bit checked. BAR364 will always be FALSE
|
633 |
|
|
localparam [0:0] BAR3ADDRWIDTH_CALC = 0;
|
634 |
|
|
//localparam BAR3PREFETCHABLE_CALC = (BAR3IOMEMN == 0) ? BAR3PREFETCHABLE:"FALSE";
|
635 |
|
|
`define BAR3PREFETCHABLE_CALC ((BAR3IOMEMN == 0) ? (BAR3PREFETCHABLE):("FALSE"))
|
636 |
|
|
|
637 |
|
|
localparam [0:0] BAR4ADDRWIDTH_CALC = (BAR4IOMEMN == 0) ? BAR464:0;
|
638 |
|
|
//localparam BAR4PREFETCHABLE_CALC = (BAR4IOMEMN == 0) ? BAR4PREFETCHABLE :"FALSE";
|
639 |
|
|
`define BAR4PREFETCHABLE_CALC ((BAR4IOMEMN == 0) ? (BAR4PREFETCHABLE):("FALSE"))
|
640 |
|
|
|
641 |
|
|
// override settings if IO, else pass through after converting boolean to binary
|
642 |
|
|
// Note that BAR5 cannot have 64 bit checked. BAR564 will always be FALSE
|
643 |
|
|
//localparam [0:0] BAR5ADDRWIDTH_CALC = 0;
|
644 |
|
|
//localparam BAR5PREFETCHABLE_CALC = (BAR5IOMEMN == 0) ? BAR5PREFETCHABLE :"FALSE";
|
645 |
|
|
`define BAR5PREFETCHABLE_CALC ((BAR5IOMEMN == 0) ? (BAR5PREFETCHABLE):("FALSE"))
|
646 |
|
|
|
647 |
|
|
|
648 |
|
|
//SCREEN 4 :CONFIGURATION REGISTERS // GUI Note
|
649 |
|
|
// DEVICE CAPABILITY REGISTER VALUES // GUI Note
|
650 |
|
|
// NOTE THAT THIS IS BROKEN DOWN INTO INDIVIDUAL ATTRIBUTES // GUI Note
|
651 |
|
|
localparam XPMAXPAYLOAD = MAXPAYLOADSIZE;//encoded value is passed by GUI
|
652 |
|
|
localparam MAXPAYLOADBYTES = 2**(MAXPAYLOADSIZE+7);//encoded value is passed by GUI
|
653 |
|
|
|
654 |
|
|
// LINK CAPABILITY REGISTER VALUES // GUI Note
|
655 |
|
|
// NOTE THAT THIS IS BROKEN DOWN INTO INDIVIDUAL ATTRIBUTES // GUI Note
|
656 |
|
|
// NOTE_X: Maximum link speed has no corresponding attribute // GUI Note
|
657 |
|
|
parameter [5:0] LINKCAPABILITYMAXLINKWIDTH = NO_OF_LANES;
|
658 |
|
|
localparam [1:0] LINKCAPABILITYASPMSUPPORT_CALC = LINKCAPABILITYASPMSUPPORTEN ? 2'b11:2'b01;
|
659 |
|
|
|
660 |
|
|
|
661 |
|
|
// EXTENDED CAPABILITIES REGISTERS // GUI Note
|
662 |
|
|
// REPRESENTED AS A LINK LIST // GUI Note
|
663 |
|
|
parameter PMENABLE = 1; //GUI parameter: Power management capability checked = 1, unchecked = 0
|
664 |
|
|
parameter XPENABLE = 1; // GUI parameter : PCI Express checked = 1, unchecked = 0
|
665 |
|
|
localparam [11:0] PMBASEPTR = 64;// 40h
|
666 |
|
|
localparam [11:0] MSIBASEPTR = 72;//48h
|
667 |
|
|
localparam [7:0] XPBASEPTR = 96;//60h
|
668 |
|
|
|
669 |
|
|
parameter [7:0] CAPABILITIESPTR_CALC = (PMENABLE==1) ? 64 : (MSIENABLE==1) ? 72: (XPENABLE==1) ? 96:0;
|
670 |
|
|
parameter [7:0] PMCAPABILITYNEXTPTR_CALC = (PMENABLE==1)? (MSIENABLE==1)?72:(XPENABLE==1)?96:0 : 72;
|
671 |
|
|
parameter [7:0] MSICAPABILITYNEXTPTR_CALC = (MSIENABLE==1)?(XPENABLE==1)?96:0 :96;
|
672 |
|
|
parameter [7:0] PCIECAPABILITYNEXTPTR_CALC = 0;
|
673 |
|
|
|
674 |
|
|
// SECOND LINK LIST // GUI Note
|
675 |
|
|
// Only 4 possibilities can alter the base pointer values // GUI Note
|
676 |
|
|
parameter AERENABLE = 0; // GUI parameter : Advanced Error Reporting checked = 1, unchecked = 0
|
677 |
|
|
parameter PBENABLE = 0; // GUI parameter : Power Budgeting checked = 1, unchecked = 0
|
678 |
|
|
localparam FIRSTENABLEDPTR = 256;//100h
|
679 |
|
|
localparam AERREGSIZE = 56;
|
680 |
|
|
localparam PBREGSIZE = 16;
|
681 |
|
|
localparam DSNREGSIZE = 12;
|
682 |
|
|
localparam VCREGSIZE = 48;
|
683 |
|
|
|
684 |
|
|
parameter [11:0] AERBASEPTR = AERENABLE ? 256 : //100h
|
685 |
|
|
PBENABLE ? 272 : //110h
|
686 |
|
|
DSNENABLE ? 268 : //10Ch
|
687 |
|
|
VCENABLE ? 300 : 272; //12Ch : 110h
|
688 |
|
|
parameter [11:0] PBBASEPTR = AERENABLE ? 312 : //138h
|
689 |
|
|
PBENABLE ? 256 : //100h
|
690 |
|
|
DSNENABLE ? 324 : //144h
|
691 |
|
|
VCENABLE ? 356 : 312;//164h : 138h
|
692 |
|
|
parameter [11:0] DSNBASEPTR = AERENABLE ? 328 : //148h
|
693 |
|
|
PBENABLE ? 328 : //148h
|
694 |
|
|
DSNENABLE ? 256 : // 100h
|
695 |
|
|
VCENABLE ? 372 : 328; //174h : 148h
|
696 |
|
|
parameter [11:0] VCBASEPTR = AERENABLE ? 340 : //154h
|
697 |
|
|
PBENABLE ? 340 : // 154h
|
698 |
|
|
DSNENABLE ? 340 : //154h
|
699 |
|
|
VCENABLE ? 256 : 340; //100h : 154h
|
700 |
|
|
//
|
701 |
|
|
parameter [11:0] AERCAPABILITYNEXTPTR = AERENABLE ? PBENABLE ? PBBASEPTR:(DSNENABLE ? DSNBASEPTR : VCENABLE ? VCBASEPTR : 0):PBBASEPTR;
|
702 |
|
|
parameter [11:0] PBCAPABILITYNEXTPTR = PBENABLE ? (DSNENABLE ? DSNBASEPTR : VCENABLE ? VCBASEPTR : 0 ):DSNBASEPTR ;
|
703 |
|
|
parameter [11:0] DSNCAPABILITYNEXTPTR = DSNENABLE ? (VCENABLE ? VCBASEPTR : 0):VCBASEPTR;
|
704 |
|
|
parameter [11:0] VCCAPABILITYNEXTPTR = 0;
|
705 |
|
|
|
706 |
|
|
|
707 |
|
|
//PCIe Extended Capabilities Register Components // GUI Note
|
708 |
|
|
parameter PCIECAPABILITYSLOTIMPL = "FALSE"; // GUI parameter : checked = 1, unchecked = 0
|
709 |
|
|
parameter PCIECAPABILITYINTMSGNUM = 5'b00000; // GUI parameter : integer
|
710 |
|
|
|
711 |
|
|
// POWER Management extended capabilities register components // GUI Note
|
712 |
|
|
parameter PMCAPABILITYAUXCURRENT = 3'b000; // GUI parameter: integer
|
713 |
|
|
parameter PMCAPABILITYD1SUPPORT = "FALSE"; // GUI parameter: checked = 1, unchecked = 0
|
714 |
|
|
parameter PMCAPABILITYD2SUPPORT = "FALSE"; // GUI parameter: checked = 1, unchecked = 0
|
715 |
|
|
// parameter PMCAPABILITYPMESUPPORT = 5'b00000; // GUI parameter: 5 bit binary value based on checked boxes
|
716 |
|
|
parameter PMDATA0 = 8'h00;
|
717 |
|
|
parameter PMDATA1 = 8'h00;
|
718 |
|
|
parameter PMDATA2 = 8'h00;
|
719 |
|
|
parameter PMDATA3 = 8'h00;
|
720 |
|
|
parameter PMDATA4 = 8'h00;
|
721 |
|
|
parameter PMDATA5 = 8'h00;
|
722 |
|
|
parameter PMDATA6 = 8'h00;
|
723 |
|
|
parameter PMDATA7 = 8'h00;
|
724 |
|
|
parameter PMDATA8 = 8'h00;
|
725 |
|
|
|
726 |
|
|
parameter PMDATASCALE0 = 2'h0;
|
727 |
|
|
parameter PMDATASCALE1 = 2'h0;
|
728 |
|
|
parameter PMDATASCALE2 = 2'h0;
|
729 |
|
|
parameter PMDATASCALE3 = 2'h0;
|
730 |
|
|
parameter PMDATASCALE4 = 2'h0;
|
731 |
|
|
parameter PMDATASCALE5 = 2'h0;
|
732 |
|
|
parameter PMDATASCALE6 = 2'h0;
|
733 |
|
|
parameter PMDATASCALE7 = 2'h0;
|
734 |
|
|
parameter PMDATASCALE8 = 2'h0;
|
735 |
|
|
|
736 |
|
|
//AER Register Components // GUI Note
|
737 |
|
|
parameter AERCAPABILITYECRCGENCAPABLE = "FALSE"; // GUI Parameter : checked = 1, unchecked = 0
|
738 |
|
|
parameter AERCAPABILITYECRCCHECKCAPABLE = "FALSE"; // GUI Parameter: checked = 1, unchecked = 0
|
739 |
|
|
// VC Register Components // GUI Note
|
740 |
|
|
localparam L0VC0PREVIEWEXPAND = 1'b0;
|
741 |
|
|
localparam [7:0] PORTVCCAPABILITYVCARBTABLEOFFSET_CALC = (LOWPRIORITYVCCOUNT==1) ? 8: 0 ;
|
742 |
|
|
|
743 |
|
|
// Power capabilities
|
744 |
|
|
parameter [7:0] PBCAPABILITYDW0BASEPOWER = 0;
|
745 |
|
|
parameter [1:0] PBCAPABILITYDW0DATASCALE = 0;
|
746 |
|
|
parameter [2:0] PBCAPABILITYDW0PMSUBSTATE = 0;
|
747 |
|
|
parameter [1:0] PBCAPABILITYDW0PMSTATE = 0;
|
748 |
|
|
parameter [2:0] PBCAPABILITYDW0TYPE = 0;
|
749 |
|
|
parameter [2:0] PBCAPABILITYDW0POWERRAIL = 0;
|
750 |
|
|
parameter [7:0] PBCAPABILITYDW1BASEPOWER = 0;
|
751 |
|
|
parameter [1:0] PBCAPABILITYDW1DATASCALE = 0;
|
752 |
|
|
parameter [2:0] PBCAPABILITYDW1PMSUBSTATE = 0;
|
753 |
|
|
parameter [1:0] PBCAPABILITYDW1PMSTATE = 0;
|
754 |
|
|
parameter [2:0] PBCAPABILITYDW1TYPE = 0;
|
755 |
|
|
parameter [2:0] PBCAPABILITYDW1POWERRAIL = 0;
|
756 |
|
|
parameter [7:0] PBCAPABILITYDW2BASEPOWER = 0;
|
757 |
|
|
parameter [1:0] PBCAPABILITYDW2DATASCALE = 0;
|
758 |
|
|
parameter [2:0] PBCAPABILITYDW2PMSUBSTATE = 0;
|
759 |
|
|
parameter [1:0] PBCAPABILITYDW2PMSTATE = 0;
|
760 |
|
|
parameter [2:0] PBCAPABILITYDW2TYPE = 0;
|
761 |
|
|
parameter [2:0] PBCAPABILITYDW2POWERRAIL = 0;
|
762 |
|
|
parameter [7:0] PBCAPABILITYDW3BASEPOWER = 0;
|
763 |
|
|
parameter [1:0] PBCAPABILITYDW3DATASCALE = 0;
|
764 |
|
|
parameter [2:0] PBCAPABILITYDW3PMSUBSTATE = 0;
|
765 |
|
|
parameter [1:0] PBCAPABILITYDW3PMSTATE = 0;
|
766 |
|
|
parameter [2:0] PBCAPABILITYDW3TYPE = 0;
|
767 |
|
|
parameter [2:0] PBCAPABILITYDW3POWERRAIL = 0;
|
768 |
|
|
parameter PBCAPABILITYSYSTEMALLOCATED = "FALSE";
|
769 |
|
|
|
770 |
|
|
parameter AUXPOWER = 1'b0;
|
771 |
|
|
parameter MAINPOWER = 1'b1;
|
772 |
|
|
|
773 |
|
|
//SCREEN 5 : BUFFERING
|
774 |
|
|
|
775 |
|
|
//calculate rety ram size based on payload size
|
776 |
|
|
localparam [11:0] RETRYRAMSIZE_CALC = (MAXPAYLOADBYTES == 2048) ? `MAXF(10,RETRYRAMSIZE) :
|
777 |
|
|
(MAXPAYLOADBYTES == 4096) ? `MAXF(11,RETRYRAMSIZE) :
|
778 |
|
|
RETRYRAMSIZE;
|
779 |
|
|
|
780 |
|
|
parameter RETRYRAMWIDTH = 1'b0;
|
781 |
|
|
|
782 |
|
|
parameter [2:0] RETRYRAMREADLATENCY = 3;//GUI parameter
|
783 |
|
|
parameter [2:0] RETRYRAMWRITELATENCY = 1;//GUI parameter
|
784 |
|
|
|
785 |
|
|
// calculate minimum values of RX Posted FIFO Sizes
|
786 |
|
|
localparam VC0RXFIFOSIZEP_MIN = 192 + MAXPAYLOADBYTES;
|
787 |
|
|
localparam VC0RXFIFOSIZEP_MAX = `MINF(192 + (8*MAXPAYLOADBYTES), 32768);
|
788 |
|
|
localparam VC1RXFIFOSIZEP_MIN = (PORTVCCAPABILITYEXTENDEDVCCOUNT == 0) ?
|
789 |
|
|
|
790 |
|
|
localparam VC1RXFIFOSIZEP_MAX = (PORTVCCAPABILITYEXTENDEDVCCOUNT == 0) ?
|
791 |
|
|
|
792 |
|
|
|
793 |
|
|
localparam VC0RXFIFOSIZENP_CALC = 192;
|
794 |
|
|
localparam VC1RXFIFOSIZENP_CALC = (PORTVCCAPABILITYEXTENDEDVCCOUNT==0) ?
|
795 |
|
|
|
796 |
|
|
|
797 |
|
|
// calculate minimum/max values of RX Posted Completion FIFO Sizes
|
798 |
|
|
localparam VC0RXFIFOSIZEC_MIN = 128 + MAXPAYLOADBYTES;
|
799 |
|
|
localparam VC0RXFIFOSIZEC_MAX = `MINF(128 + (8*MAXPAYLOADBYTES), 32768);
|
800 |
|
|
localparam VC1RXFIFOSIZEC_MIN = (PORTVCCAPABILITYEXTENDEDVCCOUNT == 0) ?
|
801 |
|
|
|
802 |
|
|
localparam VC1RXFIFOSIZEC_MAX = (PORTVCCAPABILITYEXTENDEDVCCOUNT == 0) ?
|
803 |
|
|
|
804 |
|
|
|
805 |
|
|
// calculate minimum/max values of TX Posted FIFO Sizes
|
806 |
|
|
localparam VC0TXFIFOSIZEP_MIN = 192 + MAXPAYLOADBYTES;
|
807 |
|
|
localparam VC0TXFIFOSIZEP_MAX = `MINF(192 + (8*MAXPAYLOADBYTES), 32768);
|
808 |
|
|
localparam VC1TXFIFOSIZEP_MIN = (PORTVCCAPABILITYEXTENDEDVCCOUNT == 0) ?
|
809 |
|
|
|
810 |
|
|
localparam VC1TXFIFOSIZEP_MAX = (PORTVCCAPABILITYEXTENDEDVCCOUNT == 0) ?
|
811 |
|
|
|
812 |
|
|
|
813 |
|
|
localparam VC0TXFIFOSIZENP_CALC = 192;
|
814 |
|
|
localparam VC1TXFIFOSIZENP_CALC = (PORTVCCAPABILITYEXTENDEDVCCOUNT==0) ?
|
815 |
|
|
|
816 |
|
|
|
817 |
|
|
localparam VC0TXFIFOSIZEC_MIN = 128 + MAXPAYLOADBYTES;
|
818 |
|
|
localparam VC0TXFIFOSIZEC_MAX = `MINF(128 + (8*MAXPAYLOADBYTES), 32768);
|
819 |
|
|
localparam VC1TXFIFOSIZEC_MIN = (PORTVCCAPABILITYEXTENDEDVCCOUNT == 0) ?
|
820 |
|
|
|
821 |
|
|
localparam VC1TXFIFOSIZEC_MAX = (PORTVCCAPABILITYEXTENDEDVCCOUNT == 0) ?
|
822 |
|
|
|
823 |
|
|
|
824 |
|
|
// calculate base and limit values for the FIFOs
|
825 |
|
|
// The calculated min,max values for fifos based on XPMAXPAYLOAD will override // GUI NOTE
|
826 |
|
|
// user entries in case the value goes out of band // GUI NOTE
|
827 |
|
|
// algorithm: final size = min(max(lowerlimit,userinput),upperlimit) // GUI NOTE
|
828 |
|
|
localparam VC0RXFIFOSIZEP_CALC = `MINF(`MAXF(VC0RXFIFOSIZEP_MIN,VC0RXFIFOSIZEP),VC0RXFIFOSIZEP_MAX);
|
829 |
|
|
localparam VC0RXFIFOSIZEC_CALC = 5752+8; //`MINF(`MAXF(VC0RXFIFOSIZEC_MIN,VC0RXFIFOSIZEC),VC0RXFIFOSIZEC_MAX);
|
830 |
|
|
localparam VC0TXFIFOSIZEP_CALC = `MINF(`MAXF(VC0TXFIFOSIZEP_MIN,VC0TXFIFOSIZEP),VC0TXFIFOSIZEP_MAX);
|
831 |
|
|
localparam VC0TXFIFOSIZEC_CALC = `MINF(`MAXF(VC0TXFIFOSIZEC_MIN,VC0TXFIFOSIZEC),VC0TXFIFOSIZEC_MAX);
|
832 |
|
|
|
833 |
|
|
localparam VC1RXFIFOSIZEP_CALC = `MINF(`MAXF(VC1RXFIFOSIZEP_MIN,VC1RXFIFOSIZEP),VC1RXFIFOSIZEP_MAX);
|
834 |
|
|
localparam VC1RXFIFOSIZEC_CALC = `MINF(`MAXF(VC1RXFIFOSIZEC_MIN,VC1RXFIFOSIZEC),VC1RXFIFOSIZEC_MAX);
|
835 |
|
|
localparam VC1TXFIFOSIZEP_CALC = `MINF(`MAXF(VC1TXFIFOSIZEP_MIN,VC1TXFIFOSIZEP),VC1TXFIFOSIZEP_MAX);
|
836 |
|
|
localparam VC1TXFIFOSIZEC_CALC = `MINF(`MAXF(VC1TXFIFOSIZEC_MIN,VC1TXFIFOSIZEC),VC1TXFIFOSIZEC_MAX);
|
837 |
|
|
|
838 |
|
|
// calculate base pointers and limits for FIFOs
|
839 |
|
|
localparam [12:0] VC0RXFIFOBASEP_CALC = 0;
|
840 |
|
|
localparam [12:0] VC0RXFIFOLIMITP_CALC = VC0RXFIFOBASEP_CALC + VC0RXFIFOSIZEP_CALC/8 - 1;
|
841 |
|
|
localparam [12:0] VC0RXFIFOBASENP_CALC = VC0RXFIFOLIMITP_CALC + 1;
|
842 |
|
|
localparam [12:0] VC0RXFIFOLIMITNP_CALC = VC0RXFIFOBASENP_CALC + VC0RXFIFOSIZENP_CALC/8 - 1;
|
843 |
|
|
localparam [12:0] VC0RXFIFOBASEC_CALC = VC0RXFIFOLIMITNP_CALC + 1;
|
844 |
|
|
localparam [12:0] VC0RXFIFOLIMITC_CALC = VC0RXFIFOBASEC_CALC + VC0RXFIFOSIZEC_CALC/8 - 1;
|
845 |
|
|
localparam [12:0] VC1RXFIFOBASEP_CALC = VC0RXFIFOLIMITC_CALC + 1;
|
846 |
|
|
localparam [12:0] VC1RXFIFOLIMITP_CALC = VC1RXFIFOBASEP_CALC + VC1RXFIFOSIZEP_CALC/8 - 1;
|
847 |
|
|
localparam [12:0] VC1RXFIFOBASENP_CALC = VC1RXFIFOLIMITP_CALC + 1;
|
848 |
|
|
localparam [12:0] VC1RXFIFOLIMITNP_CALC = VC1RXFIFOBASENP_CALC + VC1RXFIFOSIZENP_CALC/8 - 1;
|
849 |
|
|
localparam [12:0] VC1RXFIFOBASEC_CALC = VC1RXFIFOLIMITNP_CALC + 1;
|
850 |
|
|
localparam [12:0] VC1RXFIFOLIMITC_CALC = VC1RXFIFOBASEC_CALC + VC1RXFIFOSIZEC_CALC/8 - 1;
|
851 |
|
|
localparam [12:0] VC0TXFIFOBASEP_CALC = 0;
|
852 |
|
|
localparam [12:0] VC0TXFIFOLIMITP_CALC = VC0TXFIFOBASEP_CALC + VC0TXFIFOSIZEP_CALC/8 - 1;
|
853 |
|
|
localparam [12:0] VC0TXFIFOBASENP_CALC = VC0TXFIFOLIMITP_CALC + 1;
|
854 |
|
|
localparam [12:0] VC0TXFIFOLIMITNP_CALC = VC0TXFIFOBASENP_CALC + VC0TXFIFOSIZENP_CALC/8 - 1;
|
855 |
|
|
localparam [12:0] VC0TXFIFOBASEC_CALC = VC0TXFIFOLIMITNP_CALC + 1;
|
856 |
|
|
localparam [12:0] VC0TXFIFOLIMITC_CALC = VC0TXFIFOBASEC_CALC + VC0TXFIFOSIZEC_CALC/8 - 1;
|
857 |
|
|
localparam [12:0] VC1TXFIFOBASEP_CALC = VC0TXFIFOLIMITC_CALC + 1;
|
858 |
|
|
localparam [12:0] VC1TXFIFOLIMITP_CALC = VC1TXFIFOBASEP_CALC + VC1TXFIFOSIZEP_CALC/8 - 1;
|
859 |
|
|
localparam [12:0] VC1TXFIFOBASENP_CALC = VC1TXFIFOLIMITP_CALC + 1;
|
860 |
|
|
localparam [12:0] VC1TXFIFOLIMITNP_CALC = VC1TXFIFOBASENP_CALC + VC1TXFIFOSIZENP_CALC/8 - 1;
|
861 |
|
|
localparam [12:0] VC1TXFIFOBASEC_CALC = VC1TXFIFOLIMITNP_CALC + 1;
|
862 |
|
|
localparam [12:0] VC1TXFIFOLIMITC_CALC = VC1TXFIFOBASEC_CALC + VC1TXFIFOSIZEC_CALC/8 - 1;
|
863 |
|
|
//////////////////////////////////////////////////////
|
864 |
|
|
// calculations for total BRAM size for each of the buffers TL_TX, TL_RX, DLL_RETRY
|
865 |
|
|
localparam TL_TX_SIZE = VC0TXFIFOSIZEP_CALC + VC0TXFIFOSIZENP_CALC + VC0TXFIFOSIZEC_CALC + VC1TXFIFOSIZEP_CALC + VC1TXFIFOSIZENP_CALC + VC1TXFIFOSIZEC_CALC;
|
866 |
|
|
localparam TL_RX_SIZE = VC0RXFIFOSIZEP_CALC + VC0RXFIFOSIZENP_CALC + VC0RXFIFOSIZEC_CALC + VC1RXFIFOSIZEP_CALC + VC1RXFIFOSIZENP_CALC + VC1RXFIFOSIZEC_CALC;
|
867 |
|
|
|
868 |
|
|
// RAM Latencies
|
869 |
|
|
parameter [2:0] TLRAMREADLATENCY = 3; //GUI parameter
|
870 |
|
|
parameter [2:0] TLRAMWRITELATENCY = 1; //GUI parameter
|
871 |
|
|
parameter TLRAMWIDTH = 1'b0; //GUI parameter
|
872 |
|
|
parameter RAMSHARETXRX = "FALSE"; //GUI parameter. GUI should convert Boolean to Binary
|
873 |
|
|
|
874 |
|
|
// FIFO CREDIT VAlUES
|
875 |
|
|
localparam [6:0] VC0TOTALCREDITSPH = (PORTVCCAPABILITYEXTENDEDVCCOUNT == 0) ? VC0_CREDITS_PH : VC0_CREDITS_PH;
|
876 |
|
|
localparam [6:0] VC0TOTALCREDITSNPH = (PORTVCCAPABILITYEXTENDEDVCCOUNT == 0) ? VC0_CREDITS_NPH : VC0_CREDITS_NPH;
|
877 |
|
|
|
878 |
|
|
localparam [6:0] VC0TOTALCREDITSCH = (PORTVCCAPABILITYEXTENDEDVCCOUNT == 0) ? (INFINITECOMPLETIONS ? 0 : 8) : (INFINITECOMPLETIONS ? 0 : 8); // gui
|
879 |
|
|
|
880 |
|
|
//localparam [6:0] VC0TOTALCREDITSCH = (PORTVCCAPABILITYEXTENDEDVCCOUNT == 0) ? 0 : 0 ;
|
881 |
|
|
localparam [10:0] VC0TOTALCREDITSPD = (PORTVCCAPABILITYEXTENDEDVCCOUNT == 0) ? ((VC0RXFIFOSIZEP_CALC - 192)/16) : ((VC0RXFIFOSIZEP_CALC - 192)/16);
|
882 |
|
|
|
883 |
|
|
localparam [10:0] VC0TOTALCREDITSCD = (PORTVCCAPABILITYEXTENDEDVCCOUNT == 0) ? (INFINITECOMPLETIONS ? 0 : 11'h080) : (INFINITECOMPLETIONS ? 0 : 11'h080); // gui
|
884 |
|
|
|
885 |
|
|
//localparam [10:0] VC0TOTALCREDITSCD = (PORTVCCAPABILITYEXTENDEDVCCOUNT == 0) ? 0 : 0 ;
|
886 |
|
|
localparam [6:0] VC1TOTALCREDITSPH = (PORTVCCAPABILITYEXTENDEDVCCOUNT == 0) ? 0 : 8 ;
|
887 |
|
|
localparam [6:0] VC1TOTALCREDITSNPH = (PORTVCCAPABILITYEXTENDEDVCCOUNT == 0) ? 0 : 8 ;
|
888 |
|
|
localparam [6:0] VC1TOTALCREDITSCH = (PORTVCCAPABILITYEXTENDEDVCCOUNT == 0) ? 0 : 0 ;
|
889 |
|
|
localparam [10:0] VC1TOTALCREDITSPD = (PORTVCCAPABILITYEXTENDEDVCCOUNT == 0) ? 0 : ((VC1RXFIFOSIZEP_CALC - 192)/16);
|
890 |
|
|
localparam [10:0] VC1TOTALCREDITSCD = (PORTVCCAPABILITYEXTENDEDVCCOUNT == 0) ? 0 : 0 ;
|
891 |
|
|
|
892 |
|
|
//localparam INFINITECOMPLETIONS = "TRUE"; // Set to True
|
893 |
|
|
|
894 |
|
|
// ADDITIONAL ATTRIBUTES
|
895 |
|
|
// EITHER NOT SUPPORTED IN RELEASE OR TEST FEATURES
|
896 |
|
|
localparam SELECTDLLIF = "FALSE";
|
897 |
|
|
localparam SELECTASMODE = "FALSE";
|
898 |
|
|
localparam LLKBYPASS = "FALSE";
|
899 |
|
|
localparam XPRCBCONTROL = 1'b0;
|
900 |
|
|
localparam CONFIGROUTING = 3'h1;
|
901 |
|
|
localparam EXTCFGCAPPTR = 8'b0;
|
902 |
|
|
localparam EXTCFGXPCAPPTR = 12'b0;
|
903 |
|
|
localparam XLINKSUPPORTED = "FALSE";
|
904 |
|
|
|
905 |
|
|
localparam PCIEREVISION = 1'b1;
|
906 |
|
|
localparam RETRYWRITEPIPE = "FALSE";
|
907 |
|
|
localparam RETRYREADADDRPIPE = "FALSE";
|
908 |
|
|
localparam RETRYREADDATAPIPE = "FALSE";
|
909 |
|
|
localparam DUALCORESLAVE = "FALSE";
|
910 |
|
|
localparam DUALCOREENABLE = "FALSE";
|
911 |
|
|
localparam RXWRITEPIPE = "FALSE";
|
912 |
|
|
localparam RXREADADDRPIPE = "FALSE";
|
913 |
|
|
localparam RXREADDATAPIPE = "FALSE";
|
914 |
|
|
localparam TXWRITEPIPE = "FALSE";
|
915 |
|
|
localparam TXREADADDRPIPE = "FALSE";
|
916 |
|
|
localparam TXREADDATAPIPE = "FALSE";
|
917 |
|
|
localparam SLOTIMPLEMENTED = "FALSE";
|
918 |
|
|
localparam PMSTATUSCONTROLDATASCALE = 2'b00;
|
919 |
|
|
|
920 |
|
|
//////////////////////////////////////////////////////
|
921 |
|
|
// Tie off declarations:
|
922 |
|
|
localparam TIEOFFTOHIGH1 = 1'b1;//1 bit
|
923 |
|
|
localparam TIEOFFTOLOW1 = 1'b0;//1 bit
|
924 |
|
|
localparam TIEOFFTOHIGH2 = 2'b11;//2 bit
|
925 |
|
|
localparam TIEOFFTOLOW2 = 2'b00;//2 bit
|
926 |
|
|
|
927 |
|
|
localparam TIEOFFTOLOW3 = 3'b000;//2 bit
|
928 |
|
|
|
929 |
|
|
//////////////////////////////////////////////
|
930 |
|
|
|
931 |
|
|
//Parameters
|
932 |
|
|
|
933 |
|
|
parameter L0_TL_LINK_RETRAIN = 1'b0;
|
934 |
|
|
parameter [5:0] CFG_NEGOTIATED_LINK_WIDTH = 6'b000000;
|
935 |
|
|
parameter CROSSLINKSEED = 1'b1;
|
936 |
|
|
|
937 |
|
|
parameter [23:0] L0_CFG_VC_ID = 24'h000000;
|
938 |
|
|
|
939 |
|
|
parameter [11:0] L0_REPLAY_TIMER_ADJUSTMENT = 12'h000;
|
940 |
|
|
parameter L0_ACKNAK_TIMER_ADJUSTMENT = 12'h000;
|
941 |
|
|
parameter L0_DLL_HOLD_LINK_UP = 1'b0;
|
942 |
|
|
parameter [3:0] L0_CFG_AS_STATE_CHANGE_CMD = 4'h0;
|
943 |
|
|
parameter L0_CFG_AS_SPAN_TREE_OWNED_STATE = 1'b0;
|
944 |
|
|
parameter L0_AS_E = 1'b0;
|
945 |
|
|
parameter [2:0] L0_AS_TURN_POOL_BITS_CONSUMED = 3'b0;
|
946 |
|
|
parameter [7:0] L0_AS_PORT_COUNT = 8'h00;
|
947 |
|
|
parameter [7:0] L0_CFG_VC_ENABLE = 8'h00;
|
948 |
|
|
parameter [2:0] L0_CFG_NEGOTIATED_MAXP = 3'h0;
|
949 |
|
|
|
950 |
|
|
parameter L0_CFG_EXTENDED_SYNC = 1'b0;
|
951 |
|
|
parameter L0_CFG_LINK_DISABLE = 1'b0;
|
952 |
|
|
|
953 |
|
|
parameter L0_ALL_DOWN_PORTS_IN_L1 = 1'b0;
|
954 |
|
|
|
955 |
|
|
parameter L0_ATTENTION_BUTTON_PRESSED = 1'b0;
|
956 |
|
|
parameter L0_TX_BEACON = 1'b0;
|
957 |
|
|
parameter L0_WAKE_N = 1'b1;
|
958 |
|
|
//parameter L0_PME_REQ_IN = 1'b0; //JBG
|
959 |
|
|
parameter L0_ROOT_TURN_OFF_REQ = 1'b0;
|
960 |
|
|
parameter L0_TX_CFG_PM = 1'b0;
|
961 |
|
|
parameter [2:0] L0_TX_CFG_PM_TYPE = 3'b000;
|
962 |
|
|
parameter L0_PWR_NEW_STATE_REQ = 1'b0;
|
963 |
|
|
parameter [1:0] L0_PWR_NEXT_LINK_STATE = 2'b00;
|
964 |
|
|
parameter L0_CFG_L0S_ENTRY_SUP = 1'b0;
|
965 |
|
|
parameter L0_CFG_L0S_ENTRY_ENABLE = 1'b0;
|
966 |
|
|
parameter [2:0] L0_CFG_L0S_EXIT_LAT = 3'b000;
|
967 |
|
|
//check gui spec
|
968 |
|
|
parameter [63:0] L0_TX_TL_TLP_DATA = 64'h0000_0000_0000_0000;
|
969 |
|
|
parameter [1:0] L0_TX_TL_TLP_END = 2'b00;
|
970 |
|
|
parameter [1:0] L0_TX_TL_TLP_ENABLE = 2'b00;
|
971 |
|
|
parameter L0_TX_TL_TLP_EDB = 1'b0;
|
972 |
|
|
parameter L0_TX_TL_TLP_REQ = 1'b0;
|
973 |
|
|
parameter L0_TX_TL_TLP_REQ_END = 1'b0;
|
974 |
|
|
parameter L0_TX_TL_TLP_WIDTH = 1'b0;
|
975 |
|
|
parameter [3:0] L0_TX_TL_TLP_LATENCY = 4'h0;
|
976 |
|
|
parameter L0_TL_AS_FC_CRED_STARVATION = 1'b0;
|
977 |
|
|
parameter [18:0] L0_TX_TL_SBFC_DATA = 19'h0;
|
978 |
|
|
parameter L0_TX_TL_SBFC_UPDATE = 1'b0;
|
979 |
|
|
parameter [191:0] L0_TX_TL_FC_NPOST_BYP_CRED = 192'h0;
|
980 |
|
|
parameter [15:0] L0_TX_TL_FC_NPOST_BYP_UPDATE = 16'h0000;
|
981 |
|
|
parameter [159:0] L0_TX_TL_FC_POST_ORD_CRED = 160'h0;
|
982 |
|
|
parameter [15:0] L0_TX_TL_FC_POST_ORD_UPDATE = 16'h0000;
|
983 |
|
|
parameter [159:0] L0_TX_TL_FC_CMPL_MC_CRED = 160'h0;
|
984 |
|
|
parameter [15:0] L0_TX_TL_FC_CMPL_MC_UPDATE = 16'h0000;
|
985 |
|
|
parameter [7:0] L0_RX_TL_TLP_NON_INITIALIZED_VC = 8'h00;
|
986 |
|
|
|
987 |
|
|
parameter SLOTCAPABILITYATTBUTTONPRESENT = "FALSE";
|
988 |
|
|
parameter SLOTCAPABILITYPOWERCONTROLLERPRESENT = "FALSE";
|
989 |
|
|
parameter SLOTCAPABILITYMSLSENSORPRESENT = "FALSE";
|
990 |
|
|
parameter SLOTCAPABILITYATTINDICATORPRESENT = "FALSE";
|
991 |
|
|
parameter SLOTCAPABILITYPOWERINDICATORPRESENT = "FALSE";
|
992 |
|
|
parameter SLOTCAPABILITYHOTPLUGSURPRISE = "FALSE";
|
993 |
|
|
parameter SLOTCAPABILITYHOTPLUGCAPABLE = "FALSE";
|
994 |
|
|
|
995 |
|
|
parameter SLOTCAPABILITYSLOTPOWERLIMITVALUE = 8'h00;
|
996 |
|
|
parameter SLOTCAPABILITYSLOTPOWERLIMITSCALE = 2'b00;
|
997 |
|
|
parameter SLOTCAPABILITYPHYSICALSLOTNUM = 13'h0000;
|
998 |
|
|
|
999 |
|
|
|
1000 |
|
|
|
1001 |
|
|
//signals for module pcie_mim
|
1002 |
|
|
|
1003 |
|
|
wire mim_rx_bwclk;
|
1004 |
|
|
wire mim_rx_brclk;
|
1005 |
|
|
wire mim_tx_bwclk;
|
1006 |
|
|
wire mim_tx_brclk;
|
1007 |
|
|
wire mim_dll_bclk;
|
1008 |
|
|
|
1009 |
|
|
wire [63:0] mim_rx_brdata;
|
1010 |
|
|
wire [12:0] mim_rx_bradd;
|
1011 |
|
|
wire mim_rx_bren;
|
1012 |
|
|
wire [63:0] mim_rx_bwdata;
|
1013 |
|
|
wire [12:0] mim_rx_bwadd;
|
1014 |
|
|
wire mim_rx_bwen;
|
1015 |
|
|
wire [63:0] mim_tx_brdata;
|
1016 |
|
|
wire [12:0] mim_tx_bradd;
|
1017 |
|
|
wire mim_tx_bren;
|
1018 |
|
|
wire [63:0] mim_tx_bwdata;
|
1019 |
|
|
wire [12:0] mim_tx_bwadd;
|
1020 |
|
|
wire mim_tx_bwen;
|
1021 |
|
|
wire [63:0] mim_dll_brdata;
|
1022 |
|
|
wire [11:0] mim_dll_bradd;
|
1023 |
|
|
wire mim_dll_bren;
|
1024 |
|
|
wire [63:0] mim_dll_bwdata;
|
1025 |
|
|
wire [11:0] mim_dll_bwadd;
|
1026 |
|
|
wire mim_dll_bwen;
|
1027 |
|
|
|
1028 |
|
|
wire [63:0] mim_rx_brdata_out;
|
1029 |
|
|
|
1030 |
|
|
wire pipe_rx_elec_idle_l0;
|
1031 |
|
|
wire [2:0] pipe_rx_status_l0;
|
1032 |
|
|
wire [7:0] pipe_rx_data_l0;
|
1033 |
|
|
wire pipe_rx_phy_status_l0;
|
1034 |
|
|
wire pipe_rx_data_k_l0;
|
1035 |
|
|
wire pipe_rx_valid_l0;
|
1036 |
|
|
wire pipe_rxchanisaligned_l0;
|
1037 |
|
|
|
1038 |
|
|
wire [7:0] pipe_tx_data_l0;
|
1039 |
|
|
wire pipe_tx_data_k_l0;
|
1040 |
|
|
wire pipe_tx_elec_idle_l0;
|
1041 |
|
|
wire pipe_tx_detect_rx_loopback_l0;
|
1042 |
|
|
wire pipe_tx_compliance_l0;
|
1043 |
|
|
wire pipe_rx_polarity_l0;
|
1044 |
|
|
wire [1:0] pipe_power_down_l0;
|
1045 |
|
|
wire pipe_deskew_lanes_l0;
|
1046 |
|
|
wire pipe_reset_l0;
|
1047 |
|
|
|
1048 |
|
|
wire pipe_rx_elec_idle_l1;
|
1049 |
|
|
wire [2:0] pipe_rx_status_l1;
|
1050 |
|
|
wire [7:0] pipe_rx_data_l1;
|
1051 |
|
|
wire pipe_rx_phy_status_l1;
|
1052 |
|
|
wire pipe_rx_data_k_l1;
|
1053 |
|
|
wire pipe_rx_valid_l1;
|
1054 |
|
|
wire pipe_rxchanisaligned_l1;
|
1055 |
|
|
|
1056 |
|
|
wire [7:0] pipe_tx_data_l1;
|
1057 |
|
|
wire pipe_tx_data_k_l1;
|
1058 |
|
|
wire pipe_tx_elec_idle_l1;
|
1059 |
|
|
wire pipe_tx_detect_rx_loopback_l1;
|
1060 |
|
|
wire pipe_tx_compliance_l1;
|
1061 |
|
|
wire pipe_rx_polarity_l1;
|
1062 |
|
|
wire [1:0] pipe_power_down_l1;
|
1063 |
|
|
wire pipe_deskew_lanes_l1;
|
1064 |
|
|
wire pipe_reset_l1;
|
1065 |
|
|
|
1066 |
|
|
wire pipe_rx_elec_idle_l2;
|
1067 |
|
|
wire [2:0] pipe_rx_status_l2;
|
1068 |
|
|
wire [7:0] pipe_rx_data_l2;
|
1069 |
|
|
wire pipe_rx_phy_status_l2;
|
1070 |
|
|
wire pipe_rx_data_k_l2;
|
1071 |
|
|
wire pipe_rx_valid_l2;
|
1072 |
|
|
wire pipe_rxchanisaligned_l2;
|
1073 |
|
|
|
1074 |
|
|
wire [7:0] pipe_tx_data_l2;
|
1075 |
|
|
wire pipe_tx_data_k_l2;
|
1076 |
|
|
wire pipe_tx_elec_idle_l2;
|
1077 |
|
|
wire pipe_tx_detect_rx_loopback_l2;
|
1078 |
|
|
wire pipe_tx_compliance_l2;
|
1079 |
|
|
wire pipe_rx_polarity_l2;
|
1080 |
|
|
wire [1:0] pipe_power_down_l2;
|
1081 |
|
|
wire pipe_deskew_lanes_l2;
|
1082 |
|
|
wire pipe_reset_l2;
|
1083 |
|
|
|
1084 |
|
|
wire pipe_rx_elec_idle_l3;
|
1085 |
|
|
wire [2:0] pipe_rx_status_l3;
|
1086 |
|
|
wire [7:0] pipe_rx_data_l3;
|
1087 |
|
|
wire pipe_rx_phy_status_l3;
|
1088 |
|
|
wire pipe_rx_data_k_l3;
|
1089 |
|
|
wire pipe_rx_valid_l3;
|
1090 |
|
|
wire pipe_rxchanisaligned_l3;
|
1091 |
|
|
|
1092 |
|
|
wire [7:0] pipe_tx_data_l3;
|
1093 |
|
|
wire pipe_tx_data_k_l3;
|
1094 |
|
|
wire pipe_tx_elec_idle_l3;
|
1095 |
|
|
wire pipe_tx_detect_rx_loopback_l3;
|
1096 |
|
|
wire pipe_tx_compliance_l3;
|
1097 |
|
|
wire pipe_rx_polarity_l3;
|
1098 |
|
|
wire [1:0] pipe_power_down_l3;
|
1099 |
|
|
wire pipe_deskew_lanes_l3;
|
1100 |
|
|
wire pipe_reset_l3;
|
1101 |
|
|
|
1102 |
|
|
wire pipe_rx_elec_idle_l4;
|
1103 |
|
|
wire [2:0] pipe_rx_status_l4;
|
1104 |
|
|
wire [7:0] pipe_rx_data_l4;
|
1105 |
|
|
wire pipe_rx_phy_status_l4;
|
1106 |
|
|
wire pipe_rx_data_k_l4;
|
1107 |
|
|
wire pipe_rx_valid_l4;
|
1108 |
|
|
wire pipe_rxchanisaligned_l4;
|
1109 |
|
|
|
1110 |
|
|
wire [7:0] pipe_tx_data_l4;
|
1111 |
|
|
wire pipe_tx_data_k_l4;
|
1112 |
|
|
wire pipe_tx_elec_idle_l4;
|
1113 |
|
|
wire pipe_tx_detect_rx_loopback_l4;
|
1114 |
|
|
wire pipe_tx_compliance_l4;
|
1115 |
|
|
wire pipe_rx_polarity_l4;
|
1116 |
|
|
wire [1:0] pipe_power_down_l4;
|
1117 |
|
|
wire pipe_deskew_lanes_l4;
|
1118 |
|
|
wire pipe_reset_l4;
|
1119 |
|
|
|
1120 |
|
|
wire pipe_rx_elec_idle_l5;
|
1121 |
|
|
wire [2:0] pipe_rx_status_l5;
|
1122 |
|
|
wire [7:0] pipe_rx_data_l5;
|
1123 |
|
|
wire pipe_rx_phy_status_l5;
|
1124 |
|
|
wire pipe_rx_data_k_l5;
|
1125 |
|
|
wire pipe_rx_valid_l5;
|
1126 |
|
|
wire pipe_rxchanisaligned_l5;
|
1127 |
|
|
|
1128 |
|
|
wire [7:0] pipe_tx_data_l5;
|
1129 |
|
|
wire pipe_tx_data_k_l5;
|
1130 |
|
|
wire pipe_tx_elec_idle_l5;
|
1131 |
|
|
wire pipe_tx_detect_rx_loopback_l5;
|
1132 |
|
|
wire pipe_tx_compliance_l5;
|
1133 |
|
|
wire pipe_rx_polarity_l5;
|
1134 |
|
|
wire [1:0] pipe_power_down_l5;
|
1135 |
|
|
wire pipe_deskew_lanes_l5;
|
1136 |
|
|
wire pipe_reset_l5;
|
1137 |
|
|
|
1138 |
|
|
wire pipe_rx_elec_idle_l6;
|
1139 |
|
|
wire [2:0] pipe_rx_status_l6;
|
1140 |
|
|
wire [7:0] pipe_rx_data_l6;
|
1141 |
|
|
wire pipe_rx_phy_status_l6;
|
1142 |
|
|
wire pipe_rx_data_k_l6;
|
1143 |
|
|
wire pipe_rx_valid_l6;
|
1144 |
|
|
wire pipe_rxchanisaligned_l6;
|
1145 |
|
|
|
1146 |
|
|
wire [7:0] pipe_tx_data_l6;
|
1147 |
|
|
wire pipe_tx_data_k_l6;
|
1148 |
|
|
wire pipe_tx_elec_idle_l6;
|
1149 |
|
|
wire pipe_tx_detect_rx_loopback_l6;
|
1150 |
|
|
wire pipe_tx_compliance_l6;
|
1151 |
|
|
wire pipe_rx_polarity_l6;
|
1152 |
|
|
wire [1:0] pipe_power_down_l6;
|
1153 |
|
|
wire pipe_deskew_lanes_l6;
|
1154 |
|
|
wire pipe_reset_l6;
|
1155 |
|
|
|
1156 |
|
|
wire pipe_rx_elec_idle_l7;
|
1157 |
|
|
wire [2:0] pipe_rx_status_l7;
|
1158 |
|
|
wire [7:0] pipe_rx_data_l7;
|
1159 |
|
|
wire pipe_rx_phy_status_l7;
|
1160 |
|
|
wire pipe_rx_data_k_l7;
|
1161 |
|
|
wire pipe_rx_valid_l7;
|
1162 |
|
|
wire pipe_rxchanisaligned_l7;
|
1163 |
|
|
|
1164 |
|
|
wire [7:0] pipe_tx_data_l7;
|
1165 |
|
|
wire pipe_tx_data_k_l7;
|
1166 |
|
|
wire pipe_tx_elec_idle_l7;
|
1167 |
|
|
wire pipe_tx_detect_rx_loopback_l7;
|
1168 |
|
|
wire pipe_tx_compliance_l7;
|
1169 |
|
|
wire pipe_rx_polarity_l7;
|
1170 |
|
|
wire [1:0] pipe_power_down_l7;
|
1171 |
|
|
wire pipe_deskew_lanes_l7;
|
1172 |
|
|
wire pipe_reset_l7;
|
1173 |
|
|
|
1174 |
|
|
wire [63:0] pipe_rx_data;
|
1175 |
|
|
wire [7:0] pipe_rx_data_k;
|
1176 |
|
|
wire [7:0] pipe_rx_valid;
|
1177 |
|
|
wire [7:0] pipe_rx_elec_idle;
|
1178 |
|
|
wire [23:0] pipe_rx_status;
|
1179 |
|
|
wire [7:0] pipe_rx_phy_status;
|
1180 |
|
|
wire [7:0] pipe_rxchanisaligned;
|
1181 |
|
|
|
1182 |
|
|
wire [7:0] pipe_rx_polarity;
|
1183 |
|
|
wire [63:0] pipe_tx_data;
|
1184 |
|
|
wire [7:0] pipe_tx_data_k;
|
1185 |
|
|
wire [7:0] pipe_tx_elec_idle;
|
1186 |
|
|
wire [7:0] pipe_tx_compliance;
|
1187 |
|
|
wire [15:0] pipe_power_down;
|
1188 |
|
|
wire [7:0] pipe_tx_detect_rx_loopback;
|
1189 |
|
|
wire [7:0] pipe_deskew_lanes;
|
1190 |
|
|
wire [7:0] pipe_reset;
|
1191 |
|
|
|
1192 |
|
|
wire [2:0] maxpayloadsize_i;
|
1193 |
|
|
wire [2:0] maxreadrequestsize_i;
|
1194 |
|
|
|
1195 |
|
|
wire [3:0] negotiated_link_width;
|
1196 |
|
|
|
1197 |
|
|
/*
|
1198 |
|
|
wire gt_dclk = 0;
|
1199 |
|
|
wire [NO_OF_LANES*7-1:0] gt_daddr = 0;
|
1200 |
|
|
wire [NO_OF_LANES-1:0] gt_den = 0;
|
1201 |
|
|
wire [NO_OF_LANES-1:0] gt_dwen = 0;
|
1202 |
|
|
wire [NO_OF_LANES*16-1:0] gt_di = 0;
|
1203 |
|
|
wire [NO_OF_LANES*16-1:0] gt_do = 0;
|
1204 |
|
|
wire [NO_OF_LANES-1:0] gt_drdy = 0;
|
1205 |
|
|
*/
|
1206 |
|
|
|
1207 |
|
|
wire [7:0] RXBYTEISALIGNED;
|
1208 |
|
|
wire [7:0] RXCHANBONDSEQ;
|
1209 |
|
|
|
1210 |
|
|
wire gt_usrclk;
|
1211 |
|
|
wire core_clkb;
|
1212 |
|
|
|
1213 |
|
|
wire mem_user_clk;
|
1214 |
|
|
|
1215 |
|
|
// Selecting which resets to use
|
1216 |
|
|
wire mux_crm_urst_n;
|
1217 |
|
|
wire mux_crm_nvrst_n;
|
1218 |
|
|
wire mux_crm_mgmt_rst_n;
|
1219 |
|
|
wire mux_crm_user_cfg_rst_n;
|
1220 |
|
|
wire mux_crm_mac_rst_n;
|
1221 |
|
|
wire mux_crm_link_rst_n;
|
1222 |
|
|
|
1223 |
|
|
wire rb_crm_urst_n;
|
1224 |
|
|
wire rb_crm_nvrst_n;
|
1225 |
|
|
wire rb_crm_mgmt_rst_n;
|
1226 |
|
|
wire rb_crm_user_cfg_rst_n;
|
1227 |
|
|
wire rb_crm_mac_rst_n;
|
1228 |
|
|
wire rb_crm_link_rst_n;
|
1229 |
|
|
|
1230 |
|
|
wire usrclk;
|
1231 |
|
|
|
1232 |
|
|
wire crm_core_clk_rx_o;
|
1233 |
|
|
wire crm_user_clk_rx_o;
|
1234 |
|
|
wire crm_core_clk_tx_o;
|
1235 |
|
|
wire crm_user_clk_tx_o;
|
1236 |
|
|
wire crm_core_clk_dl_o;
|
1237 |
|
|
wire crm_core_clk;
|
1238 |
|
|
wire crm_core_clkb;
|
1239 |
|
|
wire crm_user_clk;
|
1240 |
|
|
|
1241 |
|
|
reg reg_enable_ltssm_reset;
|
1242 |
|
|
wire enable_ltssm_reset;
|
1243 |
|
|
reg [3:0] reg_ltssm_reset;
|
1244 |
|
|
wire [3:0] ltssm_reset;
|
1245 |
|
|
reg [3:0] reg_l0_ltssm_state_internal;
|
1246 |
|
|
wire [3:0] l0_ltssm_state_internal;
|
1247 |
|
|
|
1248 |
|
|
`ifdef PRODFIX
|
1249 |
|
|
wire trn_reset_n;
|
1250 |
|
|
wire upcfgcap_cycle;
|
1251 |
|
|
wire masking_ack;
|
1252 |
|
|
wire [7:0] pipe_rx_data_l0_out;
|
1253 |
|
|
wire [7:0] pipe_rx_data_l1_out;
|
1254 |
|
|
wire [7:0] pipe_rx_data_l2_out;
|
1255 |
|
|
wire [7:0] pipe_rx_data_l3_out;
|
1256 |
|
|
wire [7:0] pipe_rx_data_l4_out;
|
1257 |
|
|
wire [7:0] pipe_rx_data_l5_out;
|
1258 |
|
|
wire [7:0] pipe_rx_data_l6_out;
|
1259 |
|
|
wire [7:0] pipe_rx_data_l7_out;
|
1260 |
|
|
reg [7:0] pipe_lane_present_aligned;
|
1261 |
|
|
wire [7:0] pipe_rx_data_k_out;
|
1262 |
|
|
wire [7:0] pipe_rx_valid_out;
|
1263 |
|
|
|
1264 |
|
|
wire chan_bond_done;
|
1265 |
|
|
`endif
|
1266 |
|
|
|
1267 |
|
|
reg [4:0] cmt_rst_cnt = 5'b0;
|
1268 |
|
|
reg cmt_rst;
|
1269 |
|
|
|
1270 |
|
|
// New Delayed User Reset, per Email from Sweatha 11/17/07 part of fix for Matrox training issue
|
1271 |
|
|
wire pcie_reset; // from gt wrapper
|
1272 |
|
|
wire d_user_reset_n = user_reset_n & (~pcie_reset);
|
1273 |
|
|
|
1274 |
|
|
// register ltssm state for timing purposes
|
1275 |
|
|
always @(posedge crm_core_clk or negedge d_user_reset_n)
|
1276 |
|
|
begin
|
1277 |
|
|
if (!d_user_reset_n)
|
1278 |
|
|
reg_l0_ltssm_state_internal <= 4'h0;
|
1279 |
|
|
else
|
1280 |
|
|
reg_l0_ltssm_state_internal <= l0_ltssm_state;
|
1281 |
|
|
end
|
1282 |
|
|
|
1283 |
|
|
assign l0_ltssm_state_internal = reg_l0_ltssm_state_internal;
|
1284 |
|
|
|
1285 |
|
|
// enable ltssm reset only under the condition elec idle is broken
|
1286 |
|
|
// after ltssm is in polling. Disable it after reset is done.
|
1287 |
|
|
always @(posedge crm_core_clk or negedge d_user_reset_n)
|
1288 |
|
|
begin
|
1289 |
|
|
if (!d_user_reset_n)
|
1290 |
|
|
reg_enable_ltssm_reset <= 0;
|
1291 |
|
|
else if (ltssm_reset[3])
|
1292 |
|
|
reg_enable_ltssm_reset <= 0;
|
1293 |
|
|
else if (pipe_rx_elec_idle_l0 & (l0_ltssm_state_internal == 4'b0010))
|
1294 |
|
|
reg_enable_ltssm_reset <= 1;
|
1295 |
|
|
end
|
1296 |
|
|
|
1297 |
|
|
assign enable_ltssm_reset = reg_enable_ltssm_reset;
|
1298 |
|
|
|
1299 |
|
|
// count up to 8 clock cycles when enable is asserted and elec idle is broken.
|
1300 |
|
|
// Stop counting after 8 clock cycles.
|
1301 |
|
|
always @(posedge crm_core_clk or negedge d_user_reset_n)
|
1302 |
|
|
begin
|
1303 |
|
|
if (!d_user_reset_n)
|
1304 |
|
|
reg_ltssm_reset <= 4'h0;
|
1305 |
|
|
else if (enable_ltssm_reset & !ltssm_reset[3] & !pipe_rx_elec_idle_l0)
|
1306 |
|
|
reg_ltssm_reset <= reg_ltssm_reset + 4'h1;
|
1307 |
|
|
end
|
1308 |
|
|
|
1309 |
|
|
assign ltssm_reset = reg_ltssm_reset;
|
1310 |
|
|
|
1311 |
|
|
// assert and hold ltssm reset for 8 clock cycles when enable_ltssm_reset is asserted and elec idle is broken
|
1312 |
|
|
wire user_reset_workaround_n = d_user_reset_n & !(enable_ltssm_reset & !pipe_rx_elec_idle_l0 & !ltssm_reset[3]);
|
1313 |
|
|
//wire ignore_this_rst = (enable_ltssm_reset & !pipe_rx_elec_idle_l0 & !ltssm_reset[3]);
|
1314 |
|
|
|
1315 |
|
|
generate
|
1316 |
|
|
if (G_USER_RESETS == 1) begin : no_reset_logic
|
1317 |
|
|
assign rb_crm_urst_n = 1'b1;
|
1318 |
|
|
assign rb_crm_nvrst_n = 1'b1;
|
1319 |
|
|
assign rb_crm_mgmt_rst_n = 1'b1;
|
1320 |
|
|
assign rb_crm_user_cfg_rst_n = 1'b1;
|
1321 |
|
|
assign rb_crm_mac_rst_n = 1'b1;
|
1322 |
|
|
assign rb_crm_link_rst_n = 1'b1;
|
1323 |
|
|
|
1324 |
|
|
end else begin : use_reset_logic
|
1325 |
|
|
|
1326 |
|
|
reset_logic
|
1327 |
|
|
#(
|
1328 |
|
|
.G_RESETMODE (RESETMODE),
|
1329 |
|
|
.G_RESETSUBMODE (0)
|
1330 |
|
|
)
|
1331 |
|
|
reset_i
|
1332 |
|
|
(
|
1333 |
|
|
.L0DLUPDOWN (l0_dl_up_down[0]),
|
1334 |
|
|
.GSR (gsr),
|
1335 |
|
|
.CRMCORECLK (crm_core_clk),
|
1336 |
|
|
.USERCLK (user_clk),
|
1337 |
|
|
.L0LTSSMSTATE (l0_ltssm_state),
|
1338 |
|
|
.CRMDOHOTRESETN (crm_do_hot_reset_n),
|
1339 |
|
|
.CRMPWRSOFTRESETN (crm_pwr_soft_reset_n),
|
1340 |
|
|
.L0STATSCFGTRANSMITTED (l0_stats_cfg_transmitted),
|
1341 |
|
|
|
1342 |
|
|
.CRMMGMTRSTN (rb_crm_mgmt_rst_n),
|
1343 |
|
|
.CRMNVRSTN (rb_crm_nvrst_n),
|
1344 |
|
|
.CRMMACRSTN (rb_crm_mac_rst_n),
|
1345 |
|
|
.CRMLINKRSTN (rb_crm_link_rst_n),
|
1346 |
|
|
.CRMURSTN (rb_crm_urst_n),
|
1347 |
|
|
.CRMUSERCFGRSTN (rb_crm_user_cfg_rst_n),
|
1348 |
|
|
|
1349 |
|
|
.user_master_reset_n (user_reset_workaround_n),
|
1350 |
|
|
.clock_ready (clock_lock)
|
1351 |
|
|
|
1352 |
|
|
);
|
1353 |
|
|
end
|
1354 |
|
|
endgenerate
|
1355 |
|
|
|
1356 |
|
|
assign mux_crm_mgmt_rst_n = (G_USER_RESETS == 1) ? crm_mgmt_rst_n : rb_crm_mgmt_rst_n;
|
1357 |
|
|
|
1358 |
|
|
`ifdef MANAGEMENT_WRITE
|
1359 |
|
|
assign mux_crm_nvrst_n = (G_USER_RESETS == 1) ? crm_nvrst_n : (rb_crm_nvrst_n && mgmt_reset_delay_n);
|
1360 |
|
|
assign mux_crm_mac_rst_n = (G_USER_RESETS == 1) ? crm_mac_rst_n : (rb_crm_mac_rst_n && mgmt_reset_delay_n);
|
1361 |
|
|
assign mux_crm_link_rst_n = (G_USER_RESETS == 1) ? crm_link_rst_n : (rb_crm_link_rst_n && mgmt_reset_delay_n);
|
1362 |
|
|
assign mux_crm_urst_n = (G_USER_RESETS == 1) ? crm_urst_n : (rb_crm_urst_n && mgmt_reset_delay_n);
|
1363 |
|
|
assign mux_crm_user_cfg_rst_n = (G_USER_RESETS == 1) ? crm_user_cfg_rst_n : (rb_crm_user_cfg_rst_n && mgmt_reset_delay_n);
|
1364 |
|
|
assign mgmt_rdy = rb_crm_mgmt_rst_n;
|
1365 |
|
|
`else
|
1366 |
|
|
assign mux_crm_nvrst_n = (G_USER_RESETS == 1) ? crm_nvrst_n : rb_crm_nvrst_n;
|
1367 |
|
|
assign mux_crm_mac_rst_n = (G_USER_RESETS == 1) ? crm_mac_rst_n : rb_crm_mac_rst_n;
|
1368 |
|
|
assign mux_crm_link_rst_n = (G_USER_RESETS == 1) ? crm_link_rst_n : rb_crm_link_rst_n;
|
1369 |
|
|
assign mux_crm_urst_n = (G_USER_RESETS == 1) ? crm_urst_n : rb_crm_urst_n;
|
1370 |
|
|
assign mux_crm_user_cfg_rst_n = (G_USER_RESETS == 1) ? crm_user_cfg_rst_n : rb_crm_user_cfg_rst_n;
|
1371 |
|
|
`endif
|
1372 |
|
|
|
1373 |
|
|
always @(posedge REFCLKOUT_bufg)
|
1374 |
|
|
begin
|
1375 |
|
|
if (user_reset_n == 1'b1) begin
|
1376 |
|
|
cmt_rst_cnt <= 0;
|
1377 |
|
|
end else if (cmt_rst_cnt == 16) begin
|
1378 |
|
|
cmt_rst_cnt <= 16;
|
1379 |
|
|
end else if (user_reset_n == 1'b0) begin
|
1380 |
|
|
cmt_rst_cnt <= cmt_rst_cnt + 1'b1;
|
1381 |
|
|
end
|
1382 |
|
|
|
1383 |
|
|
|
1384 |
|
|
if (cmt_rst_cnt > 0 && cmt_rst_cnt < 16) begin
|
1385 |
|
|
cmt_rst <= 1'b1;
|
1386 |
|
|
end else begin
|
1387 |
|
|
cmt_rst <= 1'b0;
|
1388 |
|
|
end
|
1389 |
|
|
end
|
1390 |
|
|
|
1391 |
|
|
|
1392 |
|
|
pcie_clocking
|
1393 |
|
|
#(
|
1394 |
|
|
.G_DIVIDE_VAL (CLKRATIO), // use 1 for 250MHz use 2 for 125MHz and 4 for 62.5MHz
|
1395 |
|
|
.REF_CLK_FREQ (REF_CLK_FREQ) // use 0 for 100 MHz, 1 for 250 MHz
|
1396 |
|
|
)
|
1397 |
|
|
clocking_i
|
1398 |
|
|
(
|
1399 |
|
|
.clkin_pll (REFCLKOUT_bufg),
|
1400 |
|
|
.clkin_dcm (GTPCLK_bufg),
|
1401 |
|
|
//.rst (cmt_rst),
|
1402 |
|
|
.rst (~PLLLKDET_OUT[0]),
|
1403 |
|
|
|
1404 |
|
|
.coreclk (core_clk),
|
1405 |
|
|
.userclk (user_clk),
|
1406 |
|
|
.gtx_usrclk (gt_usrclk),
|
1407 |
|
|
.txsync_clk (txsync_clk),
|
1408 |
|
|
.locked (clock_lock),
|
1409 |
|
|
.fast_train_simulation_only(fast_train_simulation_only)
|
1410 |
|
|
);
|
1411 |
|
|
|
1412 |
|
|
|
1413 |
|
|
assign usrclk = (CLKDIVIDED == "FALSE") ? 1'b1 : user_clk;
|
1414 |
|
|
|
1415 |
|
|
assign crm_core_clk_rx_o = core_clk;
|
1416 |
|
|
assign crm_user_clk_rx_o = usrclk;
|
1417 |
|
|
assign crm_core_clk_tx_o = core_clk;
|
1418 |
|
|
assign crm_user_clk_tx_o = usrclk;
|
1419 |
|
|
assign crm_core_clk_dl_o = core_clk;
|
1420 |
|
|
assign crm_core_clk = core_clk;
|
1421 |
|
|
assign crm_core_clkb = core_clkb;
|
1422 |
|
|
assign crm_user_clk = usrclk;
|
1423 |
|
|
|
1424 |
|
|
//synthesis translate_off
|
1425 |
|
|
`ifdef PCIEBLKRTL
|
1426 |
|
|
|
1427 |
|
|
initial begin
|
1428 |
|
|
force pcie_ep.pcie_internal_1_1_1.pcie_internal_1_1_swift_1.ipcie.cfg_reset = glbl.GSR;
|
1429 |
|
|
force pcie_ep.pcie_internal_1_1_1.pcie_internal_1_1_swift_1.ipcie.grestore = glbl.GSR;
|
1430 |
|
|
force pcie_ep.pcie_internal_1_1_1.pcie_internal_1_1_swift_1.ipcie.gwe = 1'b1;
|
1431 |
|
|
force pcie_ep.pcie_internal_1_1_1.pcie_internal_1_1_swift_1.ipcie.ghigh_b = 1'b1;
|
1432 |
|
|
force pcie_ep.pcie_internal_1_1_1.pcie_internal_1_1_swift_1.ipcie.scanenable_n = 1'b1;
|
1433 |
|
|
force pcie_ep.pcie_internal_1_1_1.pcie_internal_1_1_swift_1.ipcie.scanmode_n = 1'b1;
|
1434 |
|
|
force pcie_ep.pcie_internal_1_1_1.pcie_internal_1_1_swift_1.ipcie.scanin = 8'b0;
|
1435 |
|
|
force pcie_ep.pcie_internal_1_1_1.pcie_internal_1_1_swift_1.ipcie.mc_core_clk_dl_o_inv = 1'b0;
|
1436 |
|
|
force pcie_ep.pcie_internal_1_1_1.pcie_internal_1_1_swift_1.ipcie.mc_core_clk_rx_o_inv = 1'b0;
|
1437 |
|
|
force pcie_ep.pcie_internal_1_1_1.pcie_internal_1_1_swift_1.ipcie.mc_user_clk_rx_o_inv = 1'b0;
|
1438 |
|
|
force pcie_ep.pcie_internal_1_1_1.pcie_internal_1_1_swift_1.ipcie.mc_core_clk_tx_o_inv = 1'b0;
|
1439 |
|
|
force pcie_ep.pcie_internal_1_1_1.pcie_internal_1_1_swift_1.ipcie.mc_user_clk_tx_o_inv = 1'b0;
|
1440 |
|
|
force pcie_ep.pcie_internal_1_1_1.pcie_internal_1_1_swift_1.ipcie.mc_core_clk_inv = 1'b0;
|
1441 |
|
|
force pcie_ep.pcie_internal_1_1_1.pcie_internal_1_1_swift_1.ipcie.mc_user_clk_inv = 1'b0;
|
1442 |
|
|
end
|
1443 |
|
|
|
1444 |
|
|
defparam pcie_ep.pcie_internal_1_1_1.pcie_internal_1_1_swift_1.G_TEST_MODE = 1;
|
1445 |
|
|
//`else
|
1446 |
|
|
//defparam pcie_ep.pcie_internal_1_1_1.pcie_internal_1_1_swift_1.TEST_MODE = "1";
|
1447 |
|
|
`endif
|
1448 |
|
|
//synthesis translate_on
|
1449 |
|
|
|
1450 |
|
|
PCIE_EP # (
|
1451 |
|
|
.CLKDIVIDED (CLKDIVIDED ),
|
1452 |
|
|
.RESETMODE (RESETMODE ),
|
1453 |
|
|
.VENDORID (VENDORID ),
|
1454 |
|
|
.DEVICEID (DEVICEID ),
|
1455 |
|
|
.REVISIONID (REVISIONID ),
|
1456 |
|
|
.CLASSCODE (CLASSCODE ),
|
1457 |
|
|
.CARDBUSCISPOINTER (CARDBUSCISPOINTER ),
|
1458 |
|
|
.SUBSYSTEMVENDORID (SUBSYSTEMVENDORID ),
|
1459 |
|
|
.SUBSYSTEMID (SUBSYSTEMID ),
|
1460 |
|
|
.CAPABILITIESPOINTER (CAPABILITIESPTR_CALC ),
|
1461 |
|
|
.INTERRUPTPIN (INTERRUPTPIN ),
|
1462 |
|
|
.AERBASEPTR (AERBASEPTR ),
|
1463 |
|
|
.DSNBASEPTR (DSNBASEPTR ),
|
1464 |
|
|
.MSIBASEPTR (MSIBASEPTR ),
|
1465 |
|
|
.PBBASEPTR (PBBASEPTR ),
|
1466 |
|
|
.PMBASEPTR (PMBASEPTR ),
|
1467 |
|
|
.VCBASEPTR (VCBASEPTR ),
|
1468 |
|
|
.XPBASEPTR (XPBASEPTR ),
|
1469 |
|
|
.PMDATASCALE0 (PMDATASCALE0 ),
|
1470 |
|
|
.PMDATASCALE1 (PMDATASCALE1 ),
|
1471 |
|
|
.PMDATASCALE2 (PMDATASCALE2 ),
|
1472 |
|
|
.PMDATASCALE3 (PMDATASCALE3 ),
|
1473 |
|
|
.PMDATASCALE4 (PMDATASCALE4 ),
|
1474 |
|
|
.PMDATASCALE5 (PMDATASCALE5 ),
|
1475 |
|
|
.PMDATASCALE6 (PMDATASCALE6 ),
|
1476 |
|
|
.PMDATASCALE7 (PMDATASCALE7 ),
|
1477 |
|
|
.PMCAPABILITYNEXTPTR (PMCAPABILITYNEXTPTR_CALC ),
|
1478 |
|
|
.PMCAPABILITYDSI (PMCAPABILITYDSI ),
|
1479 |
|
|
.PMCAPABILITYAUXCURRENT (PMCAPABILITYAUXCURRENT ),
|
1480 |
|
|
.PMCAPABILITYD1SUPPORT (PMCAPABILITYD1SUPPORT ),
|
1481 |
|
|
.PMCAPABILITYD2SUPPORT (PMCAPABILITYD2SUPPORT ),
|
1482 |
|
|
.PMCAPABILITYPMESUPPORT (PMCAPABILITYPMESUPPORT ),
|
1483 |
|
|
.PMDATA0 (PMDATA0 ),
|
1484 |
|
|
.PMDATA1 (PMDATA1 ),
|
1485 |
|
|
.PMDATA2 (PMDATA2 ),
|
1486 |
|
|
.PMDATA3 (PMDATA3 ),
|
1487 |
|
|
.PMDATA4 (PMDATA4 ),
|
1488 |
|
|
.PMDATA5 (PMDATA5 ),
|
1489 |
|
|
.PMDATA6 (PMDATA6 ),
|
1490 |
|
|
.PMDATA7 (PMDATA7 ),
|
1491 |
|
|
.MSICAPABILITYNEXTPTR (MSICAPABILITYNEXTPTR_CALC ),
|
1492 |
|
|
.MSICAPABILITYMULTIMSGCAP (MSICAPABILITYMULTIMSGCAP ),
|
1493 |
|
|
.PCIECAPABILITYNEXTPTR (PCIECAPABILITYNEXTPTR_CALC ),
|
1494 |
|
|
.DEVICECAPABILITYENDPOINTL0SLATENCY (DEVICECAPABILITYENDPOINTL0SLATENCY ),
|
1495 |
|
|
.DEVICECAPABILITYENDPOINTL1LATENCY (DEVICECAPABILITYENDPOINTL1LATENCY ),
|
1496 |
|
|
.LINKCAPABILITYMAXLINKWIDTH (LINKCAPABILITYMAXLINKWIDTH ),
|
1497 |
|
|
.LINKCAPABILITYASPMSUPPORT (LINKCAPABILITYASPMSUPPORT_CALC ),
|
1498 |
|
|
.LINKSTATUSSLOTCLOCKCONFIG (LINKSTATUSSLOTCLOCKCONFIG ),
|
1499 |
|
|
.AERCAPABILITYNEXTPTR (AERCAPABILITYNEXTPTR ),
|
1500 |
|
|
.VCCAPABILITYNEXTPTR (VCCAPABILITYNEXTPTR ),
|
1501 |
|
|
.PORTVCCAPABILITYEXTENDEDVCCOUNT (PORTVCCAPABILITYEXTENDEDVCCOUNT ),
|
1502 |
|
|
.PORTVCCAPABILITYVCARBCAP (PORTVCCAPABILITYVCARBCAP ),
|
1503 |
|
|
.PORTVCCAPABILITYVCARBTABLEOFFSET (PORTVCCAPABILITYVCARBTABLEOFFSET_CALC),
|
1504 |
|
|
.DSNCAPABILITYNEXTPTR (DSNCAPABILITYNEXTPTR ),
|
1505 |
|
|
.DEVICESERIALNUMBER (DEVICESERIALNUMBER ),
|
1506 |
|
|
.PBCAPABILITYNEXTPTR (PBCAPABILITYNEXTPTR ),
|
1507 |
|
|
.PBCAPABILITYDW0BASEPOWER (PBCAPABILITYDW0BASEPOWER ),
|
1508 |
|
|
.PBCAPABILITYDW0DATASCALE (PBCAPABILITYDW0DATASCALE ),
|
1509 |
|
|
.PBCAPABILITYDW0PMSUBSTATE (PBCAPABILITYDW0PMSUBSTATE ),
|
1510 |
|
|
.PBCAPABILITYDW0PMSTATE (PBCAPABILITYDW0PMSTATE ),
|
1511 |
|
|
.PBCAPABILITYDW0TYPE (PBCAPABILITYDW0TYPE ),
|
1512 |
|
|
.PBCAPABILITYDW0POWERRAIL (PBCAPABILITYDW0POWERRAIL ),
|
1513 |
|
|
.PBCAPABILITYDW1BASEPOWER (PBCAPABILITYDW1BASEPOWER ),
|
1514 |
|
|
.PBCAPABILITYDW1DATASCALE (PBCAPABILITYDW1DATASCALE ),
|
1515 |
|
|
.PBCAPABILITYDW1PMSUBSTATE (PBCAPABILITYDW1PMSUBSTATE ),
|
1516 |
|
|
.PBCAPABILITYDW1PMSTATE (PBCAPABILITYDW1PMSTATE ),
|
1517 |
|
|
.PBCAPABILITYDW1TYPE (PBCAPABILITYDW1TYPE ),
|
1518 |
|
|
.PBCAPABILITYDW1POWERRAIL (PBCAPABILITYDW1POWERRAIL ),
|
1519 |
|
|
.PBCAPABILITYDW2BASEPOWER (PBCAPABILITYDW2BASEPOWER ),
|
1520 |
|
|
.PBCAPABILITYDW2DATASCALE (PBCAPABILITYDW2DATASCALE ),
|
1521 |
|
|
.PBCAPABILITYDW2PMSUBSTATE (PBCAPABILITYDW2PMSUBSTATE ),
|
1522 |
|
|
.PBCAPABILITYDW2PMSTATE (PBCAPABILITYDW2PMSTATE ),
|
1523 |
|
|
.PBCAPABILITYDW2TYPE (PBCAPABILITYDW2TYPE ),
|
1524 |
|
|
.PBCAPABILITYDW2POWERRAIL (PBCAPABILITYDW2POWERRAIL ),
|
1525 |
|
|
.PBCAPABILITYDW3BASEPOWER (PBCAPABILITYDW3BASEPOWER ),
|
1526 |
|
|
.PBCAPABILITYDW3DATASCALE (PBCAPABILITYDW3DATASCALE ),
|
1527 |
|
|
.PBCAPABILITYDW3PMSUBSTATE (PBCAPABILITYDW3PMSUBSTATE ),
|
1528 |
|
|
.PBCAPABILITYDW3PMSTATE (PBCAPABILITYDW3PMSTATE ),
|
1529 |
|
|
.PBCAPABILITYDW3TYPE (PBCAPABILITYDW3TYPE ),
|
1530 |
|
|
.PBCAPABILITYDW3POWERRAIL (PBCAPABILITYDW3POWERRAIL ),
|
1531 |
|
|
.PBCAPABILITYSYSTEMALLOCATED (PBCAPABILITYSYSTEMALLOCATED ),
|
1532 |
|
|
.VC0TXFIFOBASEP (VC0TXFIFOBASEP_CALC ),
|
1533 |
|
|
.VC0TXFIFOBASENP (VC0TXFIFOBASENP_CALC ),
|
1534 |
|
|
.VC0TXFIFOBASEC (VC0TXFIFOBASEC_CALC ),
|
1535 |
|
|
.VC0TXFIFOLIMITP (VC0TXFIFOLIMITP_CALC ),
|
1536 |
|
|
.VC0TXFIFOLIMITNP (VC0TXFIFOLIMITNP_CALC ),
|
1537 |
|
|
.VC0TXFIFOLIMITC (VC0TXFIFOLIMITC_CALC ),
|
1538 |
|
|
.VC0TOTALCREDITSPH (VC0TOTALCREDITSPH ),
|
1539 |
|
|
.VC0TOTALCREDITSNPH (VC0TOTALCREDITSNPH ),
|
1540 |
|
|
.VC0TOTALCREDITSCH (VC0TOTALCREDITSCH ),
|
1541 |
|
|
.VC0TOTALCREDITSPD (VC0TOTALCREDITSPD ),
|
1542 |
|
|
.VC0TOTALCREDITSCD (VC0TOTALCREDITSCD ),
|
1543 |
|
|
.VC0RXFIFOBASEP (VC0RXFIFOBASEP_CALC ),
|
1544 |
|
|
.VC0RXFIFOBASENP (VC0RXFIFOBASENP_CALC ),
|
1545 |
|
|
.VC0RXFIFOBASEC (VC0RXFIFOBASEC_CALC ),
|
1546 |
|
|
.VC0RXFIFOLIMITP (VC0RXFIFOLIMITP_CALC ),
|
1547 |
|
|
.VC0RXFIFOLIMITNP (VC0RXFIFOLIMITNP_CALC ),
|
1548 |
|
|
.VC0RXFIFOLIMITC (VC0RXFIFOLIMITC_CALC ),
|
1549 |
|
|
.VC1TXFIFOBASEP (VC1TXFIFOBASEP_CALC ),
|
1550 |
|
|
.VC1TXFIFOBASENP (VC1TXFIFOBASENP_CALC ),
|
1551 |
|
|
.VC1TXFIFOBASEC (VC1TXFIFOBASEC_CALC ),
|
1552 |
|
|
.VC1TXFIFOLIMITP (VC1TXFIFOLIMITP_CALC ),
|
1553 |
|
|
.VC1TXFIFOLIMITNP (VC1TXFIFOLIMITNP_CALC ),
|
1554 |
|
|
.VC1TXFIFOLIMITC (VC1TXFIFOLIMITC_CALC ),
|
1555 |
|
|
.VC1TOTALCREDITSPH (VC1TOTALCREDITSPH ),
|
1556 |
|
|
.VC1TOTALCREDITSNPH (VC1TOTALCREDITSNPH ),
|
1557 |
|
|
.VC1TOTALCREDITSCH (VC1TOTALCREDITSCH ),
|
1558 |
|
|
.VC1TOTALCREDITSPD (VC1TOTALCREDITSPD ),
|
1559 |
|
|
.VC1TOTALCREDITSCD (VC1TOTALCREDITSCD ),
|
1560 |
|
|
.VC1RXFIFOBASEP (VC1RXFIFOBASEP_CALC ),
|
1561 |
|
|
.VC1RXFIFOBASENP (VC1RXFIFOBASENP_CALC ),
|
1562 |
|
|
.VC1RXFIFOBASEC (VC1RXFIFOBASEC_CALC ),
|
1563 |
|
|
.VC1RXFIFOLIMITP (VC1RXFIFOLIMITP_CALC ),
|
1564 |
|
|
.VC1RXFIFOLIMITNP (VC1RXFIFOLIMITNP_CALC ),
|
1565 |
|
|
.VC1RXFIFOLIMITC (VC1RXFIFOLIMITC_CALC ),
|
1566 |
|
|
.BAR0EXIST (BAR0EXIST ),
|
1567 |
|
|
.BAR1EXIST (BAR1EXIST ),
|
1568 |
|
|
.BAR2EXIST (BAR2EXIST ),
|
1569 |
|
|
.BAR3EXIST (BAR3EXIST ),
|
1570 |
|
|
.BAR4EXIST (BAR4EXIST ),
|
1571 |
|
|
.BAR5EXIST (BAR5EXIST ),
|
1572 |
|
|
.BAR0ADDRWIDTH (BAR0ADDRWIDTH_CALC ),
|
1573 |
|
|
.BAR1ADDRWIDTH (BAR1ADDRWIDTH_CALC ),
|
1574 |
|
|
.BAR2ADDRWIDTH (BAR2ADDRWIDTH_CALC ),
|
1575 |
|
|
.BAR3ADDRWIDTH (BAR3ADDRWIDTH_CALC ),
|
1576 |
|
|
.BAR4ADDRWIDTH (BAR4ADDRWIDTH_CALC ),
|
1577 |
|
|
.BAR0PREFETCHABLE (`BAR0PREFETCHABLE_CALC ),
|
1578 |
|
|
.BAR1PREFETCHABLE (`BAR1PREFETCHABLE_CALC ),
|
1579 |
|
|
.BAR2PREFETCHABLE (`BAR2PREFETCHABLE_CALC ),
|
1580 |
|
|
.BAR3PREFETCHABLE (`BAR3PREFETCHABLE_CALC ),
|
1581 |
|
|
.BAR4PREFETCHABLE (`BAR4PREFETCHABLE_CALC ),
|
1582 |
|
|
.BAR5PREFETCHABLE (`BAR5PREFETCHABLE_CALC ),
|
1583 |
|
|
.BAR0IOMEMN (BAR0IOMEMN ),
|
1584 |
|
|
.BAR1IOMEMN (BAR1IOMEMN ),
|
1585 |
|
|
.BAR2IOMEMN (BAR2IOMEMN ),
|
1586 |
|
|
.BAR3IOMEMN (BAR3IOMEMN ),
|
1587 |
|
|
.BAR4IOMEMN (BAR4IOMEMN ),
|
1588 |
|
|
.BAR5IOMEMN (BAR5IOMEMN ),
|
1589 |
|
|
.BAR0MASKWIDTH (BAR0MASKWIDTH ),
|
1590 |
|
|
.BAR1MASKWIDTH (BAR1MASKWIDTH ),
|
1591 |
|
|
.BAR2MASKWIDTH (BAR2MASKWIDTH ),
|
1592 |
|
|
.BAR3MASKWIDTH (BAR3MASKWIDTH ),
|
1593 |
|
|
.BAR4MASKWIDTH (BAR4MASKWIDTH ),
|
1594 |
|
|
.BAR5MASKWIDTH (BAR5MASKWIDTH ),
|
1595 |
|
|
.XPDEVICEPORTTYPE (XPDEVICEPORTTYPE ),
|
1596 |
|
|
.XPMAXPAYLOAD (XPMAXPAYLOAD ),
|
1597 |
|
|
.INFINITECOMPLETIONS (INFINITECOMPLETIONS ),
|
1598 |
|
|
.ACTIVELANESIN (ACTIVELANESIN ),
|
1599 |
|
|
.LOWPRIORITYVCCOUNT (LOWPRIORITYVCCOUNT ),
|
1600 |
|
|
.L0SEXITLATENCY (L0SEXITLATENCY ),
|
1601 |
|
|
.L0SEXITLATENCYCOMCLK (L0SEXITLATENCYCOMCLK ),
|
1602 |
|
|
.L1EXITLATENCY (L1EXITLATENCY ),
|
1603 |
|
|
.L1EXITLATENCYCOMCLK (L1EXITLATENCYCOMCLK ),
|
1604 |
|
|
.TXTSNFTS (TXTSNFTS ),
|
1605 |
|
|
.TXTSNFTSCOMCLK (TXTSNFTSCOMCLK ),
|
1606 |
|
|
.TLRAMREADLATENCY (TLRAMREADLATENCY ),
|
1607 |
|
|
.TLRAMWRITELATENCY (TLRAMWRITELATENCY ),
|
1608 |
|
|
.RETRYRAMSIZE (RETRYRAMSIZE_CALC ),
|
1609 |
|
|
.RETRYRAMREADLATENCY (RETRYRAMREADLATENCY ),
|
1610 |
|
|
.RETRYRAMWRITELATENCY (RETRYRAMWRITELATENCY )
|
1611 |
|
|
|
1612 |
|
|
|
1613 |
|
|
) pcie_ep (
|
1614 |
|
|
|
1615 |
|
|
.PIPERXELECIDLEL0 ( pipe_rx_elec_idle_l0 ),
|
1616 |
|
|
.PIPERXSTATUSL0 ( pipe_rx_status_l0 ),
|
1617 |
|
|
`ifdef PRODFIX
|
1618 |
|
|
.PIPERXDATAL0 ( pipe_rx_data_l0_out ),
|
1619 |
|
|
`else
|
1620 |
|
|
.PIPERXDATAL0 ( pipe_rx_data_l0 ),
|
1621 |
|
|
`endif
|
1622 |
|
|
.PIPEPHYSTATUSL0 ( pipe_rx_phy_status_l0 ),
|
1623 |
|
|
`ifdef PRODFIX
|
1624 |
|
|
.PIPERXDATAKL0 ( pipe_rx_data_k_l0 ),
|
1625 |
|
|
.PIPERXVALIDL0 ( pipe_rx_valid_l0 ),
|
1626 |
|
|
`else
|
1627 |
|
|
.PIPERXDATAKL0 ( pipe_rx_data_k[0] ),
|
1628 |
|
|
.PIPERXVALIDL0 ( pipe_rx_valid[0] ),
|
1629 |
|
|
`endif
|
1630 |
|
|
.PIPERXCHANISALIGNEDL0 ( pipe_rxchanisaligned_l0 ),
|
1631 |
|
|
.PIPERXELECIDLEL1 ( pipe_rx_elec_idle_l1 ),
|
1632 |
|
|
.PIPERXSTATUSL1 ( pipe_rx_status_l1 ),
|
1633 |
|
|
`ifdef PRODFIX
|
1634 |
|
|
.PIPERXDATAL1 ( pipe_rx_data_l1_out ),
|
1635 |
|
|
`else
|
1636 |
|
|
.PIPERXDATAL1 ( pipe_rx_data_l1 ),
|
1637 |
|
|
`endif
|
1638 |
|
|
.PIPEPHYSTATUSL1 ( pipe_rx_phy_status_l1 ),
|
1639 |
|
|
`ifdef PRODFIX
|
1640 |
|
|
.PIPERXDATAKL1 ( pipe_rx_data_k_l1 ),
|
1641 |
|
|
.PIPERXVALIDL1 ( pipe_rx_valid_l1 ),
|
1642 |
|
|
`else
|
1643 |
|
|
.PIPERXDATAKL1 ( pipe_rx_data_k[1] ),
|
1644 |
|
|
.PIPERXVALIDL1 ( pipe_rx_valid[1] ),
|
1645 |
|
|
`endif
|
1646 |
|
|
.PIPERXCHANISALIGNEDL1 ( pipe_rxchanisaligned_l1 ),
|
1647 |
|
|
.PIPERXELECIDLEL2 ( pipe_rx_elec_idle_l2 ),
|
1648 |
|
|
.PIPERXSTATUSL2 ( pipe_rx_status_l2 ),
|
1649 |
|
|
`ifdef PRODFIX
|
1650 |
|
|
.PIPERXDATAL2 ( pipe_rx_data_l2_out ),
|
1651 |
|
|
`else
|
1652 |
|
|
.PIPERXDATAL2 ( pipe_rx_data_l2 ),
|
1653 |
|
|
`endif
|
1654 |
|
|
.PIPEPHYSTATUSL2 ( pipe_rx_phy_status_l2 ),
|
1655 |
|
|
`ifdef PRODFIX
|
1656 |
|
|
.PIPERXDATAKL2 ( pipe_rx_data_k_l2 ),
|
1657 |
|
|
.PIPERXVALIDL2 ( pipe_rx_valid_l2 ),
|
1658 |
|
|
`else
|
1659 |
|
|
.PIPERXDATAKL2 ( pipe_rx_data_k[2] ),
|
1660 |
|
|
.PIPERXVALIDL2 ( pipe_rx_valid[2] ),
|
1661 |
|
|
`endif
|
1662 |
|
|
.PIPERXCHANISALIGNEDL2 ( pipe_rxchanisaligned_l2 ),
|
1663 |
|
|
.PIPERXELECIDLEL3 ( pipe_rx_elec_idle_l3 ),
|
1664 |
|
|
.PIPERXSTATUSL3 ( pipe_rx_status_l3 ),
|
1665 |
|
|
`ifdef PRODFIX
|
1666 |
|
|
.PIPERXDATAL3 ( pipe_rx_data_l3_out ),
|
1667 |
|
|
`else
|
1668 |
|
|
.PIPERXDATAL3 ( pipe_rx_data_l3 ),
|
1669 |
|
|
`endif
|
1670 |
|
|
.PIPEPHYSTATUSL3 ( pipe_rx_phy_status_l3 ),
|
1671 |
|
|
`ifdef PRODFIX
|
1672 |
|
|
.PIPERXDATAKL3 ( pipe_rx_data_k_l3 ),
|
1673 |
|
|
.PIPERXVALIDL3 ( pipe_rx_valid_l3 ),
|
1674 |
|
|
`else
|
1675 |
|
|
.PIPERXDATAKL3 ( pipe_rx_data_k[3] ),
|
1676 |
|
|
.PIPERXVALIDL3 ( pipe_rx_valid[3] ),
|
1677 |
|
|
`endif
|
1678 |
|
|
.PIPERXCHANISALIGNEDL3 ( pipe_rxchanisaligned_l3 ),
|
1679 |
|
|
.PIPERXELECIDLEL4 ( pipe_rx_elec_idle_l4 ),
|
1680 |
|
|
.PIPERXSTATUSL4 ( pipe_rx_status_l4 ),
|
1681 |
|
|
`ifdef PRODFIX
|
1682 |
|
|
.PIPERXDATAL4 ( pipe_rx_data_l4_out ),
|
1683 |
|
|
`else
|
1684 |
|
|
.PIPERXDATAL4 ( pipe_rx_data_l4 ),
|
1685 |
|
|
`endif
|
1686 |
|
|
.PIPEPHYSTATUSL4 ( pipe_rx_phy_status_l4 ),
|
1687 |
|
|
`ifdef PRODFIX
|
1688 |
|
|
.PIPERXDATAKL4 ( pipe_rx_data_k_l4 ),
|
1689 |
|
|
.PIPERXVALIDL4 ( pipe_rx_valid_l4 ),
|
1690 |
|
|
`else
|
1691 |
|
|
.PIPERXDATAKL4 ( pipe_rx_data_k[4] ),
|
1692 |
|
|
.PIPERXVALIDL4 ( pipe_rx_valid[4] ),
|
1693 |
|
|
`endif
|
1694 |
|
|
.PIPERXCHANISALIGNEDL4 ( pipe_rxchanisaligned_l4 ),
|
1695 |
|
|
.PIPERXELECIDLEL5 ( pipe_rx_elec_idle_l5 ),
|
1696 |
|
|
.PIPERXSTATUSL5 ( pipe_rx_status_l5 ),
|
1697 |
|
|
`ifdef PRODFIX
|
1698 |
|
|
.PIPERXDATAL5 ( pipe_rx_data_l5_out ),
|
1699 |
|
|
`else
|
1700 |
|
|
.PIPERXDATAL5 ( pipe_rx_data_l5 ),
|
1701 |
|
|
`endif
|
1702 |
|
|
.PIPEPHYSTATUSL5 ( pipe_rx_phy_status_l5 ),
|
1703 |
|
|
`ifdef PRODFIX
|
1704 |
|
|
.PIPERXDATAKL5 ( pipe_rx_data_k_l5 ),
|
1705 |
|
|
.PIPERXVALIDL5 ( pipe_rx_valid_l5 ),
|
1706 |
|
|
`else
|
1707 |
|
|
.PIPERXDATAKL5 ( pipe_rx_data_k[5] ),
|
1708 |
|
|
.PIPERXVALIDL5 ( pipe_rx_valid[5] ),
|
1709 |
|
|
`endif
|
1710 |
|
|
.PIPERXCHANISALIGNEDL5 ( pipe_rxchanisaligned_l5 ),
|
1711 |
|
|
.PIPERXELECIDLEL6 ( pipe_rx_elec_idle_l6 ),
|
1712 |
|
|
.PIPERXSTATUSL6 ( pipe_rx_status_l6 ),
|
1713 |
|
|
`ifdef PRODFIX
|
1714 |
|
|
.PIPERXDATAL6 ( pipe_rx_data_l6_out ),
|
1715 |
|
|
`else
|
1716 |
|
|
.PIPERXDATAL6 ( pipe_rx_data_l6 ),
|
1717 |
|
|
`endif
|
1718 |
|
|
.PIPEPHYSTATUSL6 ( pipe_rx_phy_status_l6 ),
|
1719 |
|
|
`ifdef PRODFIX
|
1720 |
|
|
.PIPERXDATAKL6 ( pipe_rx_data_k_l6 ),
|
1721 |
|
|
.PIPERXVALIDL6 ( pipe_rx_valid_l6 ),
|
1722 |
|
|
`else
|
1723 |
|
|
.PIPERXDATAKL6 ( pipe_rx_data_k[6] ),
|
1724 |
|
|
.PIPERXVALIDL6 ( pipe_rx_valid[6] ),
|
1725 |
|
|
`endif
|
1726 |
|
|
.PIPERXCHANISALIGNEDL6 ( pipe_rxchanisaligned_l6 ),
|
1727 |
|
|
.PIPERXELECIDLEL7 ( pipe_rx_elec_idle_l7 ),
|
1728 |
|
|
.PIPERXSTATUSL7 ( pipe_rx_status_l7 ),
|
1729 |
|
|
`ifdef PRODFIX
|
1730 |
|
|
.PIPERXDATAL7 ( pipe_rx_data_l7_out ),
|
1731 |
|
|
`else
|
1732 |
|
|
.PIPERXDATAL7 ( pipe_rx_data_l7 ),
|
1733 |
|
|
`endif
|
1734 |
|
|
.PIPEPHYSTATUSL7 ( pipe_rx_phy_status_l7 ),
|
1735 |
|
|
`ifdef PRODFIX
|
1736 |
|
|
.PIPERXDATAKL7 ( pipe_rx_data_k_l7 ),
|
1737 |
|
|
.PIPERXVALIDL7 ( pipe_rx_valid_l7 ),
|
1738 |
|
|
`else
|
1739 |
|
|
.PIPERXDATAKL7 ( pipe_rx_data_k[7] ),
|
1740 |
|
|
.PIPERXVALIDL7 ( pipe_rx_valid[7] ),
|
1741 |
|
|
`endif
|
1742 |
|
|
.PIPERXCHANISALIGNEDL7 ( pipe_rxchanisaligned_l7 ),
|
1743 |
|
|
.MIMRXBRDATA ( mim_rx_brdata ),
|
1744 |
|
|
.CRMCORECLKRXO ( crm_core_clk_rx_o ),
|
1745 |
|
|
.CRMUSERCLKRXO ( crm_user_clk_rx_o ),
|
1746 |
|
|
.MIMTXBRDATA ( mim_tx_brdata ),
|
1747 |
|
|
.CRMCORECLKTXO ( crm_core_clk_tx_o ),
|
1748 |
|
|
.CRMUSERCLKTXO ( crm_user_clk_tx_o ),
|
1749 |
|
|
.MIMDLLBRDATA ( mim_dll_brdata ),
|
1750 |
|
|
.CRMCORECLKDLO ( crm_core_clk_dl_o ),
|
1751 |
|
|
.CRMCORECLK ( crm_core_clk ),
|
1752 |
|
|
.CRMUSERCLK ( crm_user_clk ),
|
1753 |
|
|
|
1754 |
|
|
.CRMURSTN (mux_crm_urst_n ),
|
1755 |
|
|
.CRMNVRSTN (mux_crm_nvrst_n ),
|
1756 |
|
|
.CRMMGMTRSTN (mux_crm_mgmt_rst_n ),
|
1757 |
|
|
|
1758 |
|
|
.CRMLINKRSTN (mux_crm_link_rst_n ),
|
1759 |
|
|
.CRMMACRSTN (mux_crm_mac_rst_n ),
|
1760 |
|
|
|
1761 |
|
|
.CRMUSERCFGRSTN (mux_crm_user_cfg_rst_n ),
|
1762 |
|
|
.LLKTXDATA (llk_tx_data ),
|
1763 |
|
|
.LLKTXSRCRDYN (llk_tx_src_rdy_n ),
|
1764 |
|
|
|
1765 |
|
|
.LLKTXSRCDSCN (llk_tx_src_dsc_n ),
|
1766 |
|
|
.LLKTXSOFN (llk_tx_sof_n ),
|
1767 |
|
|
.LLKTXEOFN (llk_tx_eof_n ),
|
1768 |
|
|
.LLKTXSOPN (llk_tx_sop_n ),
|
1769 |
|
|
.LLKTXEOPN (llk_tx_eop_n ),
|
1770 |
|
|
.LLKTXENABLEN (llk_tx_enable_n ),
|
1771 |
|
|
.LLKTXCHTC (llk_tx_ch_tc ),
|
1772 |
|
|
.LLKTXCHFIFO (llk_tx_ch_fifo ),
|
1773 |
|
|
|
1774 |
|
|
.LLKRXDSTREQN (llk_rx_dst_req_n ),
|
1775 |
|
|
.LLKRXDSTCONTREQN (llk_rx_dst_cont_req_n ),
|
1776 |
|
|
.LLKRXCHTC (llk_rx_ch_tc ),
|
1777 |
|
|
.LLKRXCHFIFO (llk_rx_ch_fifo ),
|
1778 |
|
|
|
1779 |
|
|
.MGMTWDATA (mgmt_wdata ),
|
1780 |
|
|
.MGMTBWREN (mgmt_bwren ),
|
1781 |
|
|
.MGMTWREN (mgmt_wren ),
|
1782 |
|
|
.MGMTADDR (mgmt_addr ),
|
1783 |
|
|
.MGMTRDEN (mgmt_rden ),
|
1784 |
|
|
|
1785 |
|
|
.MGMTSTATSCREDITSEL (mgmt_stats_credit_sel ),
|
1786 |
|
|
|
1787 |
|
|
.AUXPOWER (AUXPOWER ),
|
1788 |
|
|
|
1789 |
|
|
.COMPLIANCEAVOID (compliance_avoid ),
|
1790 |
|
|
|
1791 |
|
|
.L0CFGLOOPBACKMASTER (l0_cfg_loopback_master ),
|
1792 |
|
|
|
1793 |
|
|
.L0CFGDISABLESCRAMBLE (FORCENOSCRAMBLING ),
|
1794 |
|
|
|
1795 |
|
|
.L0TRANSACTIONSPENDING (l0_transactions_pending ),
|
1796 |
|
|
|
1797 |
|
|
.L0SETCOMPLETERABORTERROR (l0_set_completer_abort_error ),
|
1798 |
|
|
.L0SETDETECTEDCORRERROR (l0_set_detected_corr_error ),
|
1799 |
|
|
.L0SETDETECTEDFATALERROR (l0_set_detected_fatal_error ),
|
1800 |
|
|
.L0SETDETECTEDNONFATALERROR (l0_set_detected_nonfatal_error ),
|
1801 |
|
|
.L0SETUSERDETECTEDPARITYERROR (l0_set_user_detected_parity_error),
|
1802 |
|
|
.L0SETUSERMASTERDATAPARITY (l0_set_user_master_data_parity ),
|
1803 |
|
|
.L0SETUSERRECEIVEDMASTERABORT (l0_set_user_received_master_abort),
|
1804 |
|
|
.L0SETUSERRECEIVEDTARGETABORT (l0_set_user_received_target_abort),
|
1805 |
|
|
.L0SETUSERSYSTEMERROR (l0_set_user_system_error ),
|
1806 |
|
|
.L0SETUSERSIGNALLEDTARGETABORT (l0_set_user_signalled_target_abort),
|
1807 |
|
|
|
1808 |
|
|
.L0SETCOMPLETIONTIMEOUTUNCORRERROR(l0_set_completion_timeout_uncorr_error),
|
1809 |
|
|
.L0SETCOMPLETIONTIMEOUTCORRERROR (l0_set_completion_timeout_corr_error),
|
1810 |
|
|
.L0SETUNEXPECTEDCOMPLETIONUNCORRERROR(l0_set_unexpected_completion_uncorr_error),
|
1811 |
|
|
.L0SETUNEXPECTEDCOMPLETIONCORRERROR(l0_set_unexpected_completion_corr_error),
|
1812 |
|
|
.L0SETUNSUPPORTEDREQUESTNONPOSTEDERROR(l0_set_unsupported_request_nonposted_error),
|
1813 |
|
|
.L0SETUNSUPPORTEDREQUESTOTHERERROR(l0_set_unsupported_request_other_error),
|
1814 |
|
|
.L0PACKETHEADERFROMUSER (128'h00000000000000000000000000000000),
|
1815 |
|
|
.L0LEGACYINTFUNCT0 (l0_legacy_int_funct0 ),
|
1816 |
|
|
|
1817 |
|
|
|
1818 |
|
|
.L0MSIREQUEST0 (l0_msi_request0 ),
|
1819 |
|
|
|
1820 |
|
|
.L0PMEREQIN (l0_pme_req_in ),
|
1821 |
|
|
|
1822 |
|
|
.PIPETXDATAL0 (pipe_tx_data_l0 ),
|
1823 |
|
|
.PIPETXDATAKL0 (pipe_tx_data_k_l0 ),
|
1824 |
|
|
.PIPETXELECIDLEL0 (pipe_tx_elec_idle_l0 ),
|
1825 |
|
|
.PIPETXDETECTRXLOOPBACKL0 (pipe_tx_detect_rx_loopback_l0 ),
|
1826 |
|
|
.PIPETXCOMPLIANCEL0 (pipe_tx_compliance_l0 ),
|
1827 |
|
|
.PIPERXPOLARITYL0 (pipe_rx_polarity_l0 ),
|
1828 |
|
|
.PIPEPOWERDOWNL0 (pipe_power_down_l0 ),
|
1829 |
|
|
.PIPEDESKEWLANESL0 (pipe_deskew_lanes_l0 ),
|
1830 |
|
|
.PIPERESETL0 (pipe_reset_l0 ),
|
1831 |
|
|
.PIPETXDATAL1 (pipe_tx_data_l1 ),
|
1832 |
|
|
.PIPETXDATAKL1 (pipe_tx_data_k_l1 ),
|
1833 |
|
|
.PIPETXELECIDLEL1 (pipe_tx_elec_idle_l1 ),
|
1834 |
|
|
.PIPETXDETECTRXLOOPBACKL1 (pipe_tx_detect_rx_loopback_l1 ),
|
1835 |
|
|
.PIPETXCOMPLIANCEL1 (pipe_tx_compliance_l1 ),
|
1836 |
|
|
.PIPERXPOLARITYL1 (pipe_rx_polarity_l1 ),
|
1837 |
|
|
.PIPEPOWERDOWNL1 (pipe_power_down_l1 ),
|
1838 |
|
|
.PIPEDESKEWLANESL1 (pipe_deskew_lanes_l1 ),
|
1839 |
|
|
.PIPERESETL1 (pipe_reset_l1 ),
|
1840 |
|
|
.PIPETXDATAL2 (pipe_tx_data_l2 ),
|
1841 |
|
|
.PIPETXDATAKL2 (pipe_tx_data_k_l2 ),
|
1842 |
|
|
.PIPETXELECIDLEL2 (pipe_tx_elec_idle_l2 ),
|
1843 |
|
|
.PIPETXDETECTRXLOOPBACKL2 (pipe_tx_detect_rx_loopback_l2 ),
|
1844 |
|
|
.PIPETXCOMPLIANCEL2 (pipe_tx_compliance_l2 ),
|
1845 |
|
|
.PIPERXPOLARITYL2 (pipe_rx_polarity_l2 ),
|
1846 |
|
|
.PIPEPOWERDOWNL2 (pipe_power_down_l2 ),
|
1847 |
|
|
.PIPEDESKEWLANESL2 (pipe_deskew_lanes_l2 ),
|
1848 |
|
|
.PIPERESETL2 (pipe_reset_l2 ),
|
1849 |
|
|
.PIPETXDATAL3 (pipe_tx_data_l3 ),
|
1850 |
|
|
.PIPETXDATAKL3 (pipe_tx_data_k_l3 ),
|
1851 |
|
|
.PIPETXELECIDLEL3 (pipe_tx_elec_idle_l3 ),
|
1852 |
|
|
.PIPETXDETECTRXLOOPBACKL3 (pipe_tx_detect_rx_loopback_l3 ),
|
1853 |
|
|
.PIPETXCOMPLIANCEL3 (pipe_tx_compliance_l3 ),
|
1854 |
|
|
.PIPERXPOLARITYL3 (pipe_rx_polarity_l3 ),
|
1855 |
|
|
.PIPEPOWERDOWNL3 (pipe_power_down_l3 ),
|
1856 |
|
|
.PIPEDESKEWLANESL3 (pipe_deskew_lanes_l3 ),
|
1857 |
|
|
.PIPERESETL3 (pipe_reset_l3 ),
|
1858 |
|
|
.PIPETXDATAL4 (pipe_tx_data_l4 ),
|
1859 |
|
|
.PIPETXDATAKL4 (pipe_tx_data_k_l4 ),
|
1860 |
|
|
.PIPETXELECIDLEL4 (pipe_tx_elec_idle_l4 ),
|
1861 |
|
|
.PIPETXDETECTRXLOOPBACKL4 (pipe_tx_detect_rx_loopback_l4 ),
|
1862 |
|
|
.PIPETXCOMPLIANCEL4 (pipe_tx_compliance_l4 ),
|
1863 |
|
|
.PIPERXPOLARITYL4 (pipe_rx_polarity_l4 ),
|
1864 |
|
|
.PIPEPOWERDOWNL4 (pipe_power_down_l4 ),
|
1865 |
|
|
.PIPEDESKEWLANESL4 (pipe_deskew_lanes_l4 ),
|
1866 |
|
|
.PIPERESETL4 (pipe_reset_l4 ),
|
1867 |
|
|
.PIPETXDATAL5 (pipe_tx_data_l5 ),
|
1868 |
|
|
.PIPETXDATAKL5 (pipe_tx_data_k_l5 ),
|
1869 |
|
|
.PIPETXELECIDLEL5 (pipe_tx_elec_idle_l5 ),
|
1870 |
|
|
.PIPETXDETECTRXLOOPBACKL5 (pipe_tx_detect_rx_loopback_l5 ),
|
1871 |
|
|
.PIPETXCOMPLIANCEL5 (pipe_tx_compliance_l5 ),
|
1872 |
|
|
.PIPERXPOLARITYL5 (pipe_rx_polarity_l5 ),
|
1873 |
|
|
.PIPEPOWERDOWNL5 (pipe_power_down_l5 ),
|
1874 |
|
|
.PIPEDESKEWLANESL5 (pipe_deskew_lanes_l5 ),
|
1875 |
|
|
.PIPERESETL5 (pipe_reset_l5 ),
|
1876 |
|
|
.PIPETXDATAL6 (pipe_tx_data_l6 ),
|
1877 |
|
|
.PIPETXDATAKL6 (pipe_tx_data_k_l6 ),
|
1878 |
|
|
.PIPETXELECIDLEL6 (pipe_tx_elec_idle_l6 ),
|
1879 |
|
|
.PIPETXDETECTRXLOOPBACKL6 (pipe_tx_detect_rx_loopback_l6 ),
|
1880 |
|
|
.PIPETXCOMPLIANCEL6 (pipe_tx_compliance_l6 ),
|
1881 |
|
|
.PIPERXPOLARITYL6 (pipe_rx_polarity_l6 ),
|
1882 |
|
|
.PIPEPOWERDOWNL6 (pipe_power_down_l6 ),
|
1883 |
|
|
.PIPEDESKEWLANESL6 (pipe_deskew_lanes_l6 ),
|
1884 |
|
|
.PIPERESETL6 (pipe_reset_l6 ),
|
1885 |
|
|
.PIPETXDATAL7 (pipe_tx_data_l7 ),
|
1886 |
|
|
.PIPETXDATAKL7 (pipe_tx_data_k_l7 ),
|
1887 |
|
|
.PIPETXELECIDLEL7 (pipe_tx_elec_idle_l7 ),
|
1888 |
|
|
.PIPETXDETECTRXLOOPBACKL7 (pipe_tx_detect_rx_loopback_l7 ),
|
1889 |
|
|
.PIPETXCOMPLIANCEL7 (pipe_tx_compliance_l7 ),
|
1890 |
|
|
.PIPERXPOLARITYL7 (pipe_rx_polarity_l7 ),
|
1891 |
|
|
.PIPEPOWERDOWNL7 (pipe_power_down_l7 ),
|
1892 |
|
|
.PIPEDESKEWLANESL7 (pipe_deskew_lanes_l7 ),
|
1893 |
|
|
.PIPERESETL7 (pipe_reset_l7 ),
|
1894 |
|
|
|
1895 |
|
|
.MIMRXBWDATA (mim_rx_bwdata ),
|
1896 |
|
|
.MIMRXBWADD (mim_rx_bwadd ),
|
1897 |
|
|
.MIMRXBRADD (mim_rx_bradd ),
|
1898 |
|
|
.MIMRXBWEN (mim_rx_bwen ),
|
1899 |
|
|
.MIMRXBREN (mim_rx_bren ),
|
1900 |
|
|
.MIMTXBWDATA (mim_tx_bwdata ),
|
1901 |
|
|
.MIMTXBWADD (mim_tx_bwadd ),
|
1902 |
|
|
.MIMTXBRADD (mim_tx_bradd ),
|
1903 |
|
|
.MIMTXBWEN (mim_tx_bwen ),
|
1904 |
|
|
.MIMTXBREN (mim_tx_bren ),
|
1905 |
|
|
.MIMDLLBWDATA (mim_dll_bwdata ),
|
1906 |
|
|
.MIMDLLBWADD (mim_dll_bwadd ),
|
1907 |
|
|
.MIMDLLBRADD (mim_dll_bradd ),
|
1908 |
|
|
.MIMDLLBWEN (mim_dll_bwen ),
|
1909 |
|
|
.MIMDLLBREN (mim_dll_bren ),
|
1910 |
|
|
|
1911 |
|
|
.CRMDOHOTRESETN (crm_do_hot_reset_n ),
|
1912 |
|
|
.CRMPWRSOFTRESETN (crm_pwr_soft_reset_n ),
|
1913 |
|
|
|
1914 |
|
|
.LLKTCSTATUS (llk_tc_status ),
|
1915 |
|
|
.LLKTXDSTRDYN (llk_tx_dst_rdy_n ),
|
1916 |
|
|
.LLKTXCHANSPACE (llk_tx_chan_space ),
|
1917 |
|
|
.LLKTXCHPOSTEDREADYN (llk_tx_ch_posted_ready_n ),
|
1918 |
|
|
.LLKTXCHNONPOSTEDREADYN (llk_tx_ch_non_posted_ready_n ),
|
1919 |
|
|
.LLKTXCHCOMPLETIONREADYN (llk_tx_ch_completion_ready_n ),
|
1920 |
|
|
|
1921 |
|
|
.LLKRXDATA (llk_rx_data ),
|
1922 |
|
|
.LLKRXSRCRDYN (llk_rx_src_rdy_n ),
|
1923 |
|
|
.LLKRXSRCLASTREQN (llk_rx_src_last_req_n ),
|
1924 |
|
|
|
1925 |
|
|
.LLKRXSOFN (llk_rx_sof_n ),
|
1926 |
|
|
.LLKRXEOFN (llk_rx_eof_n ),
|
1927 |
|
|
.LLKRXSOPN (llk_rx_sop_n ),
|
1928 |
|
|
.LLKRXEOPN (llk_rx_eop_n ),
|
1929 |
|
|
.LLKRXVALIDN (llk_rx_valid_n ),
|
1930 |
|
|
.LLKRXPREFERREDTYPE (llk_rx_preferred_type ),
|
1931 |
|
|
.LLKRXCHPOSTEDAVAILABLEN (llk_rx_ch_posted_available_n ),
|
1932 |
|
|
.LLKRXCHNONPOSTEDAVAILABLEN (llk_rx_ch_non_posted_available_n),
|
1933 |
|
|
.LLKRXCHCOMPLETIONAVAILABLEN (llk_rx_ch_completion_available_n),
|
1934 |
|
|
|
1935 |
|
|
.MGMTRDATA (mgmt_rdata ),
|
1936 |
|
|
.MGMTPSO (mgmt_pso ),
|
1937 |
|
|
.MGMTSTATSCREDIT (mgmt_stats_credit ),
|
1938 |
|
|
|
1939 |
|
|
.DLLTXPMDLLPOUTSTANDING (),
|
1940 |
|
|
.L0FIRSTCFGWRITEOCCURRED (l0_first_cfg_write_occurred ),
|
1941 |
|
|
.L0CFGLOOPBACKACK (l0_cfg_loopback_ack ),
|
1942 |
|
|
.L0RXMACLINKERROR (l0_rx_mac_link_error ),
|
1943 |
|
|
.L0MACLINKUP (l0_mac_link_up ),
|
1944 |
|
|
.L0MACNEGOTIATEDLINKWIDTH (negotiated_link_width ),
|
1945 |
|
|
.L0MACLINKTRAINING (l0_mac_link_training ),
|
1946 |
|
|
.L0LTSSMSTATE (l0_ltssm_state ),
|
1947 |
|
|
.L0DLLVCSTATUS (),
|
1948 |
|
|
.L0DLUPDOWN (l0_dl_up_down ),
|
1949 |
|
|
.L0DLLERRORVECTOR (l0_dll_error_vector ),
|
1950 |
|
|
|
1951 |
|
|
.L0COMPLETERID (l0_completer_id ),
|
1952 |
|
|
.L0UNLOCKRECEIVED (),
|
1953 |
|
|
|
1954 |
|
|
.L0MSIENABLE0 (l0_msi_enable0 ),
|
1955 |
|
|
.L0MULTIMSGEN0 (l0_multi_msg_en0 ),
|
1956 |
|
|
.L0STATSDLLPRECEIVED (l0_stats_dllp_received ),
|
1957 |
|
|
.L0STATSDLLPTRANSMITTED (l0_stats_dllp_transmitted ),
|
1958 |
|
|
.L0STATSOSRECEIVED (l0_stats_os_received ),
|
1959 |
|
|
.L0STATSOSTRANSMITTED (l0_stats_os_transmitted ),
|
1960 |
|
|
.L0STATSTLPRECEIVED (l0_stats_tlp_received ),
|
1961 |
|
|
.L0STATSTLPTRANSMITTED (l0_stats_tlp_transmitted ),
|
1962 |
|
|
.L0STATSCFGRECEIVED (l0_stats_cfg_received ),
|
1963 |
|
|
.L0STATSCFGTRANSMITTED (l0_stats_cfg_transmitted ),
|
1964 |
|
|
.L0STATSCFGOTHERRECEIVED (l0_stats_cfg_other_received ),
|
1965 |
|
|
.L0STATSCFGOTHERTRANSMITTED (l0_stats_cfg_other_transmitted ),
|
1966 |
|
|
|
1967 |
|
|
.MAXPAYLOADSIZE (maxpayloadsize_i ),
|
1968 |
|
|
.MAXREADREQUESTSIZE (maxreadrequestsize_i ),
|
1969 |
|
|
.IOSPACEENABLE (io_space_enable ),
|
1970 |
|
|
.MEMSPACEENABLE (mem_space_enable ),
|
1971 |
|
|
|
1972 |
|
|
|
1973 |
|
|
.L0PWRSTATE0 (l0_pwr_state0 ),
|
1974 |
|
|
.L0PMEACK (l0_pme_ack ), //JBG
|
1975 |
|
|
.L0PMEREQOUT (),
|
1976 |
|
|
.L0PMEEN (),
|
1977 |
|
|
|
1978 |
|
|
.L0PWRL1STATE (),
|
1979 |
|
|
|
1980 |
|
|
.L0PWRL23READYSTATE (l0_pwr_l23_ready_state ),
|
1981 |
|
|
.L0PWRTXL0SSTATE (l0_pwr_tx_l0s_state ),
|
1982 |
|
|
.L0PWRTURNOFFREQ (l0_pwr_turn_off_req),
|
1983 |
|
|
.L0RXDLLPM (),
|
1984 |
|
|
.L0RXDLLPMTYPE (),
|
1985 |
|
|
|
1986 |
|
|
.L0MACNEWSTATEACK (l0_mac_new_state_ack ),
|
1987 |
|
|
.L0MACRXL0SSTATE (l0_mac_rx_l0s_state ),
|
1988 |
|
|
.L0MACENTEREDL0 (l0_mac_entered_l0 ),
|
1989 |
|
|
.L0DLLRXACKOUTSTANDING (),
|
1990 |
|
|
.L0DLLTXOUTSTANDING (),
|
1991 |
|
|
.L0DLLTXNONFCOUTSTANDING (),
|
1992 |
|
|
|
1993 |
|
|
.BUSMASTERENABLE (bus_master_enable ),
|
1994 |
|
|
.PARITYERRORRESPONSE (parity_error_response ),
|
1995 |
|
|
.SERRENABLE (serr_enable ),
|
1996 |
|
|
.INTERRUPTDISABLE (interrupt_disable ),
|
1997 |
|
|
.URREPORTINGENABLE (ur_reporting_enable )
|
1998 |
|
|
);
|
1999 |
|
|
|
2000 |
|
|
|
2001 |
|
|
assign l0_mac_negotiated_link_width = negotiated_link_width;
|
2002 |
|
|
|
2003 |
|
|
`ifdef PRODFIX
|
2004 |
|
|
|
2005 |
|
|
assign trn_reset_n = PLLLKDET_OUT[0] && clock_lock && user_reset_workaround_n; //d_user_reset_n;
|
2006 |
|
|
assign chan_bond_done = &pipe_lane_present_aligned[7:0] && pipe_rxchanisaligned[0];
|
2007 |
|
|
|
2008 |
|
|
always@(posedge core_clk) begin
|
2009 |
|
|
pipe_lane_present_aligned[0] <= pipe_rxchanisaligned[0] ^ pipe_rx_elec_idle[0];
|
2010 |
|
|
pipe_lane_present_aligned[1] <= pipe_rxchanisaligned[1] ^ pipe_rx_elec_idle[1];
|
2011 |
|
|
pipe_lane_present_aligned[2] <= pipe_rxchanisaligned[2] ^ pipe_rx_elec_idle[2];
|
2012 |
|
|
pipe_lane_present_aligned[3] <= pipe_rxchanisaligned[3] ^ pipe_rx_elec_idle[3];
|
2013 |
|
|
pipe_lane_present_aligned[4] <= pipe_rxchanisaligned[4] ^ pipe_rx_elec_idle[4];
|
2014 |
|
|
pipe_lane_present_aligned[5] <= pipe_rxchanisaligned[5] ^ pipe_rx_elec_idle[5];
|
2015 |
|
|
pipe_lane_present_aligned[6] <= pipe_rxchanisaligned[6] ^ pipe_rx_elec_idle[6];
|
2016 |
|
|
pipe_lane_present_aligned[7] <= pipe_rxchanisaligned[7] ^ pipe_rx_elec_idle[7];
|
2017 |
|
|
end
|
2018 |
|
|
|
2019 |
|
|
prod_fixes prod_fixes_I
|
2020 |
|
|
(
|
2021 |
|
|
.clk(core_clk),
|
2022 |
|
|
.bit_reset_n(trn_reset_n),
|
2023 |
|
|
.l0_ltssm_state(l0_ltssm_state),
|
2024 |
|
|
//.char_is_k_l0(pipe_rx_data_k_l0),
|
2025 |
|
|
.pipe_rx_data_k(pipe_rx_data_k),
|
2026 |
|
|
.pipe_rx_valid(pipe_rx_valid),
|
2027 |
|
|
//.l0_stats_os_received(l0_stats_os_received),
|
2028 |
|
|
.negotiated_link_width(negotiated_link_width),
|
2029 |
|
|
.trn_lnk_up_n(trn_lnk_up_n),
|
2030 |
|
|
.chan_bond_done(chan_bond_done),
|
2031 |
|
|
.pipe_rx_data_l0(pipe_rx_data_l0),
|
2032 |
|
|
.pipe_rx_data_l1(pipe_rx_data_l1),
|
2033 |
|
|
.pipe_rx_data_l2(pipe_rx_data_l2),
|
2034 |
|
|
.pipe_rx_data_l3(pipe_rx_data_l3),
|
2035 |
|
|
.pipe_rx_data_l4(pipe_rx_data_l4),
|
2036 |
|
|
.pipe_rx_data_l5(pipe_rx_data_l5),
|
2037 |
|
|
.pipe_rx_data_l6(pipe_rx_data_l6),
|
2038 |
|
|
.pipe_rx_data_l7(pipe_rx_data_l7),
|
2039 |
|
|
.pipe_rx_data_l0_out(pipe_rx_data_l0_out),
|
2040 |
|
|
.pipe_rx_data_l1_out(pipe_rx_data_l1_out),
|
2041 |
|
|
.pipe_rx_data_l2_out(pipe_rx_data_l2_out),
|
2042 |
|
|
.pipe_rx_data_l3_out(pipe_rx_data_l3_out),
|
2043 |
|
|
.pipe_rx_data_l4_out(pipe_rx_data_l4_out),
|
2044 |
|
|
.pipe_rx_data_l5_out(pipe_rx_data_l5_out),
|
2045 |
|
|
.pipe_rx_data_l6_out(pipe_rx_data_l6_out),
|
2046 |
|
|
.pipe_rx_data_l7_out(pipe_rx_data_l7_out),
|
2047 |
|
|
.upcfgcap_cycle(upcfgcap_cycle),
|
2048 |
|
|
.masking_ack(masking_ack),
|
2049 |
|
|
.pipe_rx_data_k_out(pipe_rx_data_k_out),
|
2050 |
|
|
.pipe_rx_valid_out(pipe_rx_valid_out)
|
2051 |
|
|
);
|
2052 |
|
|
`endif
|
2053 |
|
|
|
2054 |
|
|
|
2055 |
|
|
|
2056 |
|
|
|
2057 |
|
|
assign mem_user_clk = (CLKDIVIDED == "FALSE") ? crm_core_clk : crm_user_clk;
|
2058 |
|
|
assign max_payload_size = maxpayloadsize_i;
|
2059 |
|
|
assign max_read_request_size = maxreadrequestsize_i;
|
2060 |
|
|
|
2061 |
|
|
|
2062 |
|
|
pcie_mim_wrapper #
|
2063 |
|
|
(
|
2064 |
|
|
.RETRYRAMWRITELATENCY (RETRYRAMWRITELATENCY ),
|
2065 |
|
|
.RETRYRAMREADLATENCY (RETRYRAMREADLATENCY ),
|
2066 |
|
|
.RETRYRAMSIZE (RETRYRAMSIZE_CALC),
|
2067 |
|
|
.RETRYREADDATAPIPE (0 ),
|
2068 |
|
|
|
2069 |
|
|
.TLRAMWRITELATENCY (TLRAMWRITELATENCY ),
|
2070 |
|
|
.TLRAMREADLATENCY (TLRAMREADLATENCY ),
|
2071 |
|
|
.TL_TX_SIZE (TL_TX_SIZE),
|
2072 |
|
|
.TXREADDATAPIPE (0 ),
|
2073 |
|
|
|
2074 |
|
|
.RXREADDATAPIPE (0 ),
|
2075 |
|
|
.TL_RX_SIZE (TL_RX_SIZE)
|
2076 |
|
|
)
|
2077 |
|
|
|
2078 |
|
|
pcie_mim_wrapper_i
|
2079 |
|
|
(
|
2080 |
|
|
.mim_dll_bwadd (mim_dll_bwadd),
|
2081 |
|
|
.mim_dll_bwen (mim_dll_bwen),
|
2082 |
|
|
.mim_dll_bren (mim_dll_bren),
|
2083 |
|
|
.mim_dll_bwdata (mim_dll_bwdata),
|
2084 |
|
|
.mim_dll_bradd (mim_dll_bradd),
|
2085 |
|
|
.mim_dll_brdata (mim_dll_brdata),
|
2086 |
|
|
.mim_dll_bclk (crm_core_clk),
|
2087 |
|
|
|
2088 |
|
|
.mim_tx_bwadd (mim_tx_bwadd),
|
2089 |
|
|
.mim_tx_bwen (mim_tx_bwen),
|
2090 |
|
|
.mim_tx_bren (mim_tx_bren),
|
2091 |
|
|
.mim_tx_bwdata (mim_tx_bwdata),
|
2092 |
|
|
.mim_tx_bradd (mim_tx_bradd),
|
2093 |
|
|
.mim_tx_brdata (mim_tx_brdata),
|
2094 |
|
|
.mim_tx_brclk (crm_core_clk),
|
2095 |
|
|
.mim_tx_bwclk (mem_user_clk),
|
2096 |
|
|
|
2097 |
|
|
.mim_rx_bwadd (mim_rx_bwadd),
|
2098 |
|
|
.mim_rx_bwen (mim_rx_bwen),
|
2099 |
|
|
.mim_rx_bren (mim_rx_bren),
|
2100 |
|
|
.mim_rx_bwdata (mim_rx_bwdata),
|
2101 |
|
|
.mim_rx_bradd (mim_rx_bradd),
|
2102 |
|
|
.mim_rx_brdata (mim_rx_brdata),
|
2103 |
|
|
.mim_rx_bwclk (crm_core_clk),
|
2104 |
|
|
.mim_rx_brclk (mem_user_clk)
|
2105 |
|
|
|
2106 |
|
|
);
|
2107 |
|
|
|
2108 |
|
|
assign {pipe_rx_elec_idle_l7, pipe_rx_elec_idle_l6,
|
2109 |
|
|
pipe_rx_elec_idle_l5, pipe_rx_elec_idle_l4,
|
2110 |
|
|
pipe_rx_elec_idle_l3, pipe_rx_elec_idle_l2,
|
2111 |
|
|
pipe_rx_elec_idle_l1, pipe_rx_elec_idle_l0} = pipe_rx_elec_idle;
|
2112 |
|
|
|
2113 |
|
|
assign {pipe_rx_status_l7, pipe_rx_status_l6,
|
2114 |
|
|
pipe_rx_status_l5, pipe_rx_status_l4,
|
2115 |
|
|
pipe_rx_status_l3, pipe_rx_status_l2,
|
2116 |
|
|
pipe_rx_status_l1, pipe_rx_status_l0} = pipe_rx_status;
|
2117 |
|
|
|
2118 |
|
|
assign {pipe_rx_data_k_l7, pipe_rx_data_k_l6,
|
2119 |
|
|
pipe_rx_data_k_l5, pipe_rx_data_k_l4,
|
2120 |
|
|
pipe_rx_data_k_l3, pipe_rx_data_k_l2,
|
2121 |
|
|
pipe_rx_data_k_l1, pipe_rx_data_k_l0} = pipe_rx_data_k_out;
|
2122 |
|
|
|
2123 |
|
|
assign {pipe_rx_phy_status_l7, pipe_rx_phy_status_l6,
|
2124 |
|
|
pipe_rx_phy_status_l5, pipe_rx_phy_status_l4,
|
2125 |
|
|
pipe_rx_phy_status_l3, pipe_rx_phy_status_l2,
|
2126 |
|
|
pipe_rx_phy_status_l1, pipe_rx_phy_status_l0} = pipe_rx_phy_status;
|
2127 |
|
|
|
2128 |
|
|
assign {pipe_rx_data_l7, pipe_rx_data_l6,
|
2129 |
|
|
pipe_rx_data_l5, pipe_rx_data_l4,
|
2130 |
|
|
pipe_rx_data_l3, pipe_rx_data_l2,
|
2131 |
|
|
pipe_rx_data_l1, pipe_rx_data_l0} = pipe_rx_data;
|
2132 |
|
|
|
2133 |
|
|
assign {pipe_rx_valid_l7, pipe_rx_valid_l6,
|
2134 |
|
|
pipe_rx_valid_l5, pipe_rx_valid_l4,
|
2135 |
|
|
pipe_rx_valid_l3, pipe_rx_valid_l2,
|
2136 |
|
|
pipe_rx_valid_l1, pipe_rx_valid_l0} = pipe_rx_valid_out;
|
2137 |
|
|
|
2138 |
|
|
assign {pipe_rxchanisaligned_l7, pipe_rxchanisaligned_l6,
|
2139 |
|
|
pipe_rxchanisaligned_l5, pipe_rxchanisaligned_l4,
|
2140 |
|
|
pipe_rxchanisaligned_l3, pipe_rxchanisaligned_l2,
|
2141 |
|
|
pipe_rxchanisaligned_l1, pipe_rxchanisaligned_l0} = pipe_rxchanisaligned;
|
2142 |
|
|
|
2143 |
|
|
|
2144 |
|
|
assign pipe_tx_data = {pipe_tx_data_l7, pipe_tx_data_l6,
|
2145 |
|
|
pipe_tx_data_l5, pipe_tx_data_l4,
|
2146 |
|
|
pipe_tx_data_l3, pipe_tx_data_l2,
|
2147 |
|
|
pipe_tx_data_l1, pipe_tx_data_l0};
|
2148 |
|
|
|
2149 |
|
|
assign pipe_tx_data_k = {pipe_tx_data_k_l7, pipe_tx_data_k_l6,
|
2150 |
|
|
pipe_tx_data_k_l5, pipe_tx_data_k_l4,
|
2151 |
|
|
pipe_tx_data_k_l3, pipe_tx_data_k_l2,
|
2152 |
|
|
pipe_tx_data_k_l1, pipe_tx_data_k_l0};
|
2153 |
|
|
|
2154 |
|
|
assign pipe_tx_elec_idle = {pipe_tx_elec_idle_l7, pipe_tx_elec_idle_l6,
|
2155 |
|
|
pipe_tx_elec_idle_l5, pipe_tx_elec_idle_l4,
|
2156 |
|
|
pipe_tx_elec_idle_l3, pipe_tx_elec_idle_l2,
|
2157 |
|
|
pipe_tx_elec_idle_l1, pipe_tx_elec_idle_l0};
|
2158 |
|
|
|
2159 |
|
|
assign pipe_tx_detect_rx_loopback = {pipe_tx_detect_rx_loopback_l7, pipe_tx_detect_rx_loopback_l6,
|
2160 |
|
|
pipe_tx_detect_rx_loopback_l5, pipe_tx_detect_rx_loopback_l4,
|
2161 |
|
|
pipe_tx_detect_rx_loopback_l3, pipe_tx_detect_rx_loopback_l2,
|
2162 |
|
|
pipe_tx_detect_rx_loopback_l1, pipe_tx_detect_rx_loopback_l0};
|
2163 |
|
|
|
2164 |
|
|
assign pipe_tx_compliance = {pipe_tx_compliance_l7, pipe_tx_compliance_l6,
|
2165 |
|
|
pipe_tx_compliance_l5, pipe_tx_compliance_l4,
|
2166 |
|
|
pipe_tx_compliance_l3, pipe_tx_compliance_l2,
|
2167 |
|
|
pipe_tx_compliance_l1, pipe_tx_compliance_l0};
|
2168 |
|
|
|
2169 |
|
|
assign pipe_rx_polarity = {pipe_rx_polarity_l7, pipe_rx_polarity_l6,
|
2170 |
|
|
pipe_rx_polarity_l5, pipe_rx_polarity_l4,
|
2171 |
|
|
pipe_rx_polarity_l3, pipe_rx_polarity_l2,
|
2172 |
|
|
pipe_rx_polarity_l1, pipe_rx_polarity_l0};
|
2173 |
|
|
|
2174 |
|
|
assign pipe_power_down = {pipe_power_down_l7, pipe_power_down_l6,
|
2175 |
|
|
pipe_power_down_l5, pipe_power_down_l4,
|
2176 |
|
|
pipe_power_down_l3, pipe_power_down_l2,
|
2177 |
|
|
pipe_power_down_l1, pipe_power_down_l0};
|
2178 |
|
|
|
2179 |
|
|
assign pipe_deskew_lanes = {pipe_deskew_lanes_l7, pipe_deskew_lanes_l6,
|
2180 |
|
|
pipe_deskew_lanes_l5, pipe_deskew_lanes_l4,
|
2181 |
|
|
pipe_deskew_lanes_l3, pipe_deskew_lanes_l2,
|
2182 |
|
|
pipe_deskew_lanes_l1, pipe_deskew_lanes_l0};
|
2183 |
|
|
|
2184 |
|
|
|
2185 |
|
|
assign pipe_reset = {pipe_reset_l7, pipe_reset_l6,
|
2186 |
|
|
pipe_reset_l5, pipe_reset_l4,
|
2187 |
|
|
pipe_reset_l3, pipe_reset_l2,
|
2188 |
|
|
pipe_reset_l1, pipe_reset_l0};
|
2189 |
|
|
|
2190 |
|
|
|
2191 |
|
|
pcie_gt_wrapper_top#
|
2192 |
|
|
(
|
2193 |
|
|
.NO_OF_LANES(NO_OF_LANES),
|
2194 |
|
|
.SIM(G_SIM),
|
2195 |
|
|
.USE_V5FXT(USE_V5FXT),
|
2196 |
|
|
.REF_CLK_FREQ (REF_CLK_FREQ), // use 0 for 100 MHz, 1 for 250 MHz
|
2197 |
|
|
.TXDIFFBOOST(TXDIFFBOOST),
|
2198 |
|
|
.GTDEBUGPORTS(GTDEBUGPORTS)
|
2199 |
|
|
)
|
2200 |
|
|
SIO
|
2201 |
|
|
(
|
2202 |
|
|
.gt_rx_elec_idle (pipe_rx_elec_idle),
|
2203 |
|
|
.gt_rx_status (pipe_rx_status),
|
2204 |
|
|
.gt_rx_data (pipe_rx_data),
|
2205 |
|
|
.gt_rx_phy_status (pipe_rx_phy_status),
|
2206 |
|
|
.gt_rx_data_k (pipe_rx_data_k),
|
2207 |
|
|
.gt_rx_valid (pipe_rx_valid),
|
2208 |
|
|
.gt_rx_chanisaligned (pipe_rxchanisaligned),
|
2209 |
|
|
|
2210 |
|
|
.gt_rx_n (RXN),
|
2211 |
|
|
.gt_rx_p (RXP),
|
2212 |
|
|
.gt_tx_n (TXN),
|
2213 |
|
|
.gt_tx_p (TXP),
|
2214 |
|
|
|
2215 |
|
|
.gt_tx_data (pipe_tx_data),
|
2216 |
|
|
.gt_tx_data_k (pipe_tx_data_k),
|
2217 |
|
|
.gt_tx_elec_idle (pipe_tx_elec_idle),
|
2218 |
|
|
.gt_tx_detect_rx_loopback(pipe_tx_detect_rx_loopback),
|
2219 |
|
|
.gt_tx_compliance (pipe_tx_compliance),
|
2220 |
|
|
.gt_rx_polarity (pipe_rx_polarity),
|
2221 |
|
|
.gt_power_down (pipe_power_down),
|
2222 |
|
|
.gt_deskew_lanes (pipe_deskew_lanes),
|
2223 |
|
|
.gt_pipe_reset (pipe_reset),
|
2224 |
|
|
.gt_rx_present (gt_rx_present),
|
2225 |
|
|
|
2226 |
|
|
.gsr (gsr),
|
2227 |
|
|
.gtreset (GTPRESET),
|
2228 |
|
|
.refclk (REFCLK),
|
2229 |
|
|
.refclkout_bufg (REFCLKOUT_bufg),
|
2230 |
|
|
.gtclk_bufg (GTPCLK_bufg),
|
2231 |
|
|
.plllkdet_out (PLLLKDET_OUT),
|
2232 |
|
|
.resetdone (RESETDONE),
|
2233 |
|
|
.gt_usrclk (gt_usrclk),
|
2234 |
|
|
.gt_usrclk2 (crm_core_clk),
|
2235 |
|
|
.txsync_clk (txsync_clk),
|
2236 |
|
|
.rxbyteisaligned (RXBYTEISALIGNED),
|
2237 |
|
|
.rxchanbondseq (RXCHANBONDSEQ),
|
2238 |
|
|
.pcie_reset (pcie_reset),
|
2239 |
|
|
.clock_lock (clock_lock),
|
2240 |
|
|
.trn_lnk_up_n (trn_lnk_up_n),
|
2241 |
|
|
|
2242 |
|
|
// GTP register ports
|
2243 |
|
|
.gt_dclk (gt_dclk),
|
2244 |
|
|
.gt_daddr (gt_daddr),
|
2245 |
|
|
.gt_den (gt_den),
|
2246 |
|
|
.gt_dwen (gt_dwen),
|
2247 |
|
|
.gt_di (gt_di),
|
2248 |
|
|
.gt_do (gt_do),
|
2249 |
|
|
.gt_drdy (gt_drdy),
|
2250 |
|
|
|
2251 |
|
|
.gt_txdiffctrl_0 (gt_txdiffctrl_0),
|
2252 |
|
|
.gt_txdiffctrl_1 (gt_txdiffctrl_1),
|
2253 |
|
|
.gt_txbuffctrl_0 (gt_txbuffctrl_0),
|
2254 |
|
|
.gt_txbuffctrl_1 (gt_txbuffctrl_1),
|
2255 |
|
|
.gt_txpreemphesis_0 (gt_txpreemphesis_0),
|
2256 |
|
|
.gt_txpreemphesis_1 (gt_txpreemphesis_1)
|
2257 |
|
|
);
|
2258 |
|
|
|
2259 |
|
|
assign DEBUG[12:0] = mim_tx_bwadd;
|
2260 |
|
|
assign DEBUG[13] = mim_tx_bwen;
|
2261 |
|
|
assign DEBUG[14] = mim_tx_bren;
|
2262 |
|
|
assign DEBUG[78:15] = mim_tx_bwdata;
|
2263 |
|
|
assign DEBUG[91:79] = mim_tx_bradd;
|
2264 |
|
|
assign DEBUG[104:92]= mim_rx_bwadd;
|
2265 |
|
|
assign DEBUG[105] = mim_rx_bwen;
|
2266 |
|
|
assign DEBUG[106] = mim_rx_bren;
|
2267 |
|
|
assign DEBUG[170:107] = mim_rx_bwdata;
|
2268 |
|
|
assign DEBUG[183:171] = mim_rx_bradd;
|
2269 |
|
|
|
2270 |
|
|
assign DEBUG[247:184] = mim_dll_brdata;
|
2271 |
|
|
assign DEBUG[259:248] = mim_dll_bradd;
|
2272 |
|
|
assign DEBUG[260] = mim_dll_bren;
|
2273 |
|
|
assign DEBUG[324:261] = mim_dll_bwdata;
|
2274 |
|
|
assign DEBUG[336:325] = mim_dll_bwadd;
|
2275 |
|
|
assign DEBUG[337] = mim_dll_bwen;
|
2276 |
|
|
|
2277 |
|
|
// assign DEBUG[338] = masking_ack;
|
2278 |
|
|
|
2279 |
|
|
// assign DEBUG[7:0] = pipe_tx_data[7:0];
|
2280 |
|
|
// assign DEBUG[8] = pipe_tx_detect_rx_loopback[0];
|
2281 |
|
|
// assign DEBUG[10:9] = pipe_power_down[1:0];
|
2282 |
|
|
// assign DEBUG[18:11] = pipe_rx_data[7:0];
|
2283 |
|
|
// assign DEBUG[19] = pipe_tx_elec_idle[0];
|
2284 |
|
|
// assign DEBUG[20] = pipe_rx_elec_idle[0];
|
2285 |
|
|
// assign DEBUG[23:21] = pipe_rx_status[2:0];
|
2286 |
|
|
// assign DEBUG[24] = pipe_rx_phy_status[0];
|
2287 |
|
|
// assign DEBUG[25] = pipe_rxchanisaligned[0];
|
2288 |
|
|
//
|
2289 |
|
|
// assign DEBUG[26] = pipe_tx_elec_idle[1];
|
2290 |
|
|
// assign DEBUG[27] = pipe_rx_elec_idle[1];
|
2291 |
|
|
// assign DEBUG[30:28] = pipe_rx_status[5:3];
|
2292 |
|
|
// assign DEBUG[31] = pipe_rx_phy_status[1];
|
2293 |
|
|
// assign DEBUG[32] = pipe_rxchanisaligned[1];
|
2294 |
|
|
//
|
2295 |
|
|
// assign DEBUG[33] = pipe_tx_elec_idle[2];
|
2296 |
|
|
// assign DEBUG[34] = pipe_rx_elec_idle[2];
|
2297 |
|
|
// assign DEBUG[37:35] = pipe_rx_status[8:6];
|
2298 |
|
|
// assign DEBUG[38] = pipe_rx_phy_status[2];
|
2299 |
|
|
// assign DEBUG[39] = pipe_rxchanisaligned[2];
|
2300 |
|
|
//
|
2301 |
|
|
// assign DEBUG[40] = pipe_tx_elec_idle[3];
|
2302 |
|
|
// assign DEBUG[41] = pipe_rx_elec_idle[3];
|
2303 |
|
|
// assign DEBUG[44:42] = pipe_rx_status[11:9];
|
2304 |
|
|
// assign DEBUG[45] = pipe_rx_phy_status[3];
|
2305 |
|
|
// assign DEBUG[46] = pipe_rxchanisaligned[3];
|
2306 |
|
|
//
|
2307 |
|
|
// assign DEBUG[47] = pipe_tx_elec_idle[4];
|
2308 |
|
|
// assign DEBUG[48] = pipe_rx_elec_idle[4];
|
2309 |
|
|
// assign DEBUG[51:49] = pipe_rx_status[14:12];
|
2310 |
|
|
// assign DEBUG[52] = pipe_rx_phy_status[4];
|
2311 |
|
|
// assign DEBUG[53] = pipe_rxchanisaligned[4];
|
2312 |
|
|
//
|
2313 |
|
|
//
|
2314 |
|
|
// assign DEBUG[54] = pipe_tx_elec_idle[5];
|
2315 |
|
|
// assign DEBUG[55] = pipe_rx_elec_idle[5];
|
2316 |
|
|
// assign DEBUG[58:56] = pipe_rx_status[17:15];
|
2317 |
|
|
// assign DEBUG[59] = pipe_rx_phy_status[5];
|
2318 |
|
|
// assign DEBUG[60] = pipe_rxchanisaligned[5];
|
2319 |
|
|
//
|
2320 |
|
|
// assign DEBUG[61] = pipe_tx_elec_idle[6];
|
2321 |
|
|
// assign DEBUG[62] = pipe_rx_elec_idle[6];
|
2322 |
|
|
// assign DEBUG[65:63] = pipe_rx_status[20:18];
|
2323 |
|
|
// assign DEBUG[66] = pipe_rx_phy_status[6];
|
2324 |
|
|
// assign DEBUG[67] = pipe_rxchanisaligned[6];
|
2325 |
|
|
//
|
2326 |
|
|
// assign DEBUG[68] = pipe_tx_elec_idle[7];
|
2327 |
|
|
// assign DEBUG[69] = pipe_rx_elec_idle[7];
|
2328 |
|
|
// assign DEBUG[72:70] = pipe_rx_status[23:21];
|
2329 |
|
|
// assign DEBUG[73] = pipe_rx_phy_status[7];
|
2330 |
|
|
// assign DEBUG[74] = pipe_rxchanisaligned[7];
|
2331 |
|
|
//
|
2332 |
|
|
// assign DEBUG[82:75] = pipe_rx_data[15:8];
|
2333 |
|
|
// assign DEBUG[90:83] = pipe_rx_data[23:16];
|
2334 |
|
|
// assign DEBUG[98:91] = pipe_rx_data[32:24];
|
2335 |
|
|
//
|
2336 |
|
|
// assign DEBUG[99] = RXCHANBONDSEQ[0];
|
2337 |
|
|
// assign DEBUG[100] = RXCHANBONDSEQ[1];
|
2338 |
|
|
// assign DEBUG[101] = RXCHANBONDSEQ[2];
|
2339 |
|
|
// assign DEBUG[102] = RXCHANBONDSEQ[3];
|
2340 |
|
|
//
|
2341 |
|
|
// assign DEBUG[103] = RXBYTEISALIGNED[0];
|
2342 |
|
|
// assign DEBUG[104] = RXBYTEISALIGNED[1];
|
2343 |
|
|
// assign DEBUG[105] = RXBYTEISALIGNED[2];
|
2344 |
|
|
// assign DEBUG[106] = RXBYTEISALIGNED[3];
|
2345 |
|
|
|
2346 |
|
|
//`define CHIPSCOPE_LLK_TX_HANG_DEBUG 1
|
2347 |
|
|
//`define LTSSM_DEBUG 1
|
2348 |
|
|
//`define LINKTRAIN_DEBUG 1
|
2349 |
|
|
|
2350 |
|
|
`ifdef CHIPSCOPE_LLK_TX_HANG_DEBUG
|
2351 |
|
|
|
2352 |
|
|
reg [1:0] tx_state;
|
2353 |
|
|
reg [4:0] dst_rdy_ctr;
|
2354 |
|
|
reg dst_rdy_trig;
|
2355 |
|
|
wire [35:0] control0;
|
2356 |
|
|
|
2357 |
|
|
always @(posedge user_clk or negedge clock_lock) begin
|
2358 |
|
|
|
2359 |
|
|
if (clock_lock == 0) begin
|
2360 |
|
|
|
2361 |
|
|
tx_state <= 2'b0;
|
2362 |
|
|
dst_rdy_ctr <= 4'b0;
|
2363 |
|
|
dst_rdy_trig <= 0;
|
2364 |
|
|
|
2365 |
|
|
end else begin
|
2366 |
|
|
|
2367 |
|
|
dst_rdy_trig <= 0;
|
2368 |
|
|
|
2369 |
|
|
case (tx_state)
|
2370 |
|
|
|
2371 |
|
|
2'b00: begin
|
2372 |
|
|
|
2373 |
|
|
if ((llk_tx_sof_n == 0) &&
|
2374 |
|
|
(llk_tx_src_rdy_n == 0) &&
|
2375 |
|
|
(llk_tx_dst_rdy_n == 0)) begin
|
2376 |
|
|
|
2377 |
|
|
dst_rdy_ctr <= 4'b0; // reset counter
|
2378 |
|
|
tx_state <= 2'b01;
|
2379 |
|
|
|
2380 |
|
|
end else if ((llk_tx_sof_n == 0) &&
|
2381 |
|
|
(llk_tx_src_rdy_n == 0) &&
|
2382 |
|
|
(llk_tx_dst_rdy_n != 0)) begin
|
2383 |
|
|
|
2384 |
|
|
if (dst_rdy_ctr == 5'b11111) begin
|
2385 |
|
|
|
2386 |
|
|
dst_rdy_trig <= 1'b1;
|
2387 |
|
|
tx_state <= 2'b10;
|
2388 |
|
|
|
2389 |
|
|
end else begin
|
2390 |
|
|
|
2391 |
|
|
dst_rdy_ctr <= dst_rdy_ctr + 1'b1;
|
2392 |
|
|
tx_state <= 2'b00;
|
2393 |
|
|
|
2394 |
|
|
end
|
2395 |
|
|
|
2396 |
|
|
end else if (llk_tx_dst_rdy_n != 0) begin
|
2397 |
|
|
|
2398 |
|
|
if (dst_rdy_ctr == 5'b11111) begin
|
2399 |
|
|
|
2400 |
|
|
dst_rdy_trig <= 1'b1;
|
2401 |
|
|
tx_state <= 2'b10;
|
2402 |
|
|
|
2403 |
|
|
end else begin
|
2404 |
|
|
|
2405 |
|
|
dst_rdy_ctr <= dst_rdy_ctr + 1'b1;
|
2406 |
|
|
tx_state <= 2'b00;
|
2407 |
|
|
|
2408 |
|
|
end
|
2409 |
|
|
|
2410 |
|
|
end else begin
|
2411 |
|
|
|
2412 |
|
|
dst_rdy_ctr <= 4'b0;
|
2413 |
|
|
tx_state <= 2'b00;
|
2414 |
|
|
|
2415 |
|
|
end
|
2416 |
|
|
end
|
2417 |
|
|
|
2418 |
|
|
2'b01: begin
|
2419 |
|
|
|
2420 |
|
|
if ((llk_tx_eof_n == 0) &&
|
2421 |
|
|
(llk_tx_src_rdy_n == 0) &&
|
2422 |
|
|
(llk_tx_dst_rdy_n == 0)) begin
|
2423 |
|
|
|
2424 |
|
|
dst_rdy_ctr <= 4'b0;
|
2425 |
|
|
tx_state <= 2'b00;
|
2426 |
|
|
|
2427 |
|
|
end else if (llk_tx_dst_rdy_n != 0) begin
|
2428 |
|
|
|
2429 |
|
|
if (dst_rdy_ctr == 5'b11111) begin
|
2430 |
|
|
|
2431 |
|
|
dst_rdy_trig <= 1'b1;
|
2432 |
|
|
tx_state <= 2'b10;
|
2433 |
|
|
|
2434 |
|
|
end else begin
|
2435 |
|
|
|
2436 |
|
|
dst_rdy_ctr <= dst_rdy_ctr + 1'b1;
|
2437 |
|
|
tx_state <= 2'b01;
|
2438 |
|
|
|
2439 |
|
|
end
|
2440 |
|
|
|
2441 |
|
|
end
|
2442 |
|
|
|
2443 |
|
|
end
|
2444 |
|
|
|
2445 |
|
|
2'b10: begin
|
2446 |
|
|
|
2447 |
|
|
dst_rdy_trig <= 1'b1;
|
2448 |
|
|
tx_state <= 2'b10;
|
2449 |
|
|
|
2450 |
|
|
end
|
2451 |
|
|
|
2452 |
|
|
endcase
|
2453 |
|
|
|
2454 |
|
|
end
|
2455 |
|
|
|
2456 |
|
|
end
|
2457 |
|
|
|
2458 |
|
|
|
2459 |
|
|
wire [35:0] control0;
|
2460 |
|
|
|
2461 |
|
|
ila i_ila
|
2462 |
|
|
(
|
2463 |
|
|
.control(control0),
|
2464 |
|
|
.clk(user_clk),
|
2465 |
|
|
|
2466 |
|
|
.data({
|
2467 |
|
|
|
2468 |
|
|
`ifdef LTSSM_DEBUG
|
2469 |
|
|
ltssm_reset, // 11 : 8
|
2470 |
|
|
enable_ltssm_reset, // 7 : 7
|
2471 |
|
|
user_reset_workaround_n, // 6 : 6
|
2472 |
|
|
d_user_reset_n, // 5 : 5
|
2473 |
|
|
pipe_rx_elec_idle_l0, // 4 : 4
|
2474 |
|
|
l0_ltssm_state // 3 : 0
|
2475 |
|
|
`else
|
2476 |
|
|
dst_rdy_trig, // 31
|
2477 |
|
|
llk_tx_ch_posted_ready_n[0], // 30
|
2478 |
|
|
llk_tx_ch_non_posted_ready_n[0], // 29
|
2479 |
|
|
llk_tx_ch_completion_ready_n[0], // 28
|
2480 |
|
|
llk_tx_chan_space, // 27 : 18
|
2481 |
|
|
llk_tx_ch_fifo, // 17 : 16
|
2482 |
|
|
llk_tx_ch_tc, // 15 : 13
|
2483 |
|
|
llk_tx_eof_n, // 12
|
2484 |
|
|
llk_tx_sof_n, // 11
|
2485 |
|
|
llk_tx_dst_rdy_n, // 10
|
2486 |
|
|
llk_tx_src_rdy_n, // 09
|
2487 |
|
|
llk_tx_enable_n, // 08 : 07
|
2488 |
|
|
llk_tx_data[62:56] // 06 : 00
|
2489 |
|
|
`endif
|
2490 |
|
|
|
2491 |
|
|
}),
|
2492 |
|
|
|
2493 |
|
|
.trig0({
|
2494 |
|
|
|
2495 |
|
|
`ifdef LTSSM_DEBUG
|
2496 |
|
|
ltssm_reset, // 11 : 8
|
2497 |
|
|
enable_ltssm_reset, // 7 : 7
|
2498 |
|
|
user_reset_workaround_n, // 6 : 6
|
2499 |
|
|
d_user_reset_n, // 5 : 5
|
2500 |
|
|
pipe_rx_elec_idle_l0, // 4 : 4
|
2501 |
|
|
l0_ltssm_state // 3 : 0
|
2502 |
|
|
`else
|
2503 |
|
|
dst_rdy_trig, // 11 : 11
|
2504 |
|
|
llk_tx_data[62:56], // 10 : 4
|
2505 |
|
|
llk_tx_ch_fifo, // 3 : 2
|
2506 |
|
|
llk_tx_src_rdy_n, // 1 : 1
|
2507 |
|
|
llk_tx_sof_n // 0 : 0
|
2508 |
|
|
`endif
|
2509 |
|
|
|
2510 |
|
|
})
|
2511 |
|
|
);
|
2512 |
|
|
|
2513 |
|
|
`endif // CHIPSCOPE_LLK_TX_HANG_DEBUG
|
2514 |
|
|
|
2515 |
|
|
`ifdef LINKTRAIN_DEBUG
|
2516 |
|
|
|
2517 |
|
|
wire [35:0] control0;
|
2518 |
|
|
wire trig_out;
|
2519 |
|
|
wire [148:0] trig0;
|
2520 |
|
|
wire all_chan_aligned;
|
2521 |
|
|
|
2522 |
|
|
|
2523 |
|
|
assign all_chan_aligned = &(pipe_rxchanisaligned);
|
2524 |
|
|
//assign chipscope_trig_out = trig_out; // chipscope can change polarity
|
2525 |
|
|
|
2526 |
|
|
//assign trig0[3:0] = ltssm_reset[3:0];
|
2527 |
|
|
//assign trig0[4] = enable_ltssm_reset;
|
2528 |
|
|
//assign trig0[5] = user_reset_workaround_n;
|
2529 |
|
|
//assign trig0[6] = d_user_reset_n;
|
2530 |
|
|
//assign trig0[7] = pipe_rx_elec_idle_l0;
|
2531 |
|
|
//assign trig0[8] = pipe_tx_elec_idle_l0;
|
2532 |
|
|
//assign trig0[12:9] = l0_ltssm_state[3:0];
|
2533 |
|
|
//assign trig0[16:13] = l0_mac_negotiated_link_width[3:0];
|
2534 |
|
|
//assign trig0[17] = l0_mac_link_training;
|
2535 |
|
|
//assign trig0[19:18] = l0_rx_mac_link_error[1:0];
|
2536 |
|
|
//assign trig0[20] = l0_mac_link_up;
|
2537 |
|
|
//assign trig0[21] = PLLLKDET_OUT[0];
|
2538 |
|
|
//assign trig0[22] = clock_lock;
|
2539 |
|
|
//assign trig0[23] = trn_reset_n;
|
2540 |
|
|
//assign trig0[24] = pipe_power_down_l0;
|
2541 |
|
|
//assign trig0[25] = user_reset_n;
|
2542 |
|
|
//assign trig0[26] = ignore_this_rst;
|
2543 |
|
|
//assign trig0[27] = link_not_x8;
|
2544 |
|
|
//assign trig0[31:28] = 4'b0; // unused
|
2545 |
|
|
|
2546 |
|
|
assign trig0[7:0] = pipe_rx_data_l0[7:0];
|
2547 |
|
|
assign trig0[15:8] = pipe_rx_data_l1[7:0];
|
2548 |
|
|
assign trig0[23:16] = pipe_rx_data_l2[7:0];
|
2549 |
|
|
assign trig0[31:24] = pipe_rx_data_l3[7:0];
|
2550 |
|
|
assign trig0[39:32] = pipe_rx_data_l4[7:0];
|
2551 |
|
|
assign trig0[47:40] = pipe_rx_data_l5[7:0];
|
2552 |
|
|
assign trig0[55:48] = pipe_rx_data_l6[7:0];
|
2553 |
|
|
assign trig0[63:56] = pipe_rx_data_l7[7:0];
|
2554 |
|
|
|
2555 |
|
|
assign trig0[71:64] = pipe_rx_data_l0_out[7:0];
|
2556 |
|
|
assign trig0[79:72] = pipe_rx_data_l1_out[7:0];
|
2557 |
|
|
assign trig0[87:80] = pipe_rx_data_l2_out[7:0];
|
2558 |
|
|
assign trig0[95:88] = pipe_rx_data_l3_out[7:0];
|
2559 |
|
|
assign trig0[103:96] = pipe_rx_data_l4_out[7:0];
|
2560 |
|
|
assign trig0[111:104] = pipe_rx_data_l5_out[7:0];
|
2561 |
|
|
assign trig0[119:112] = pipe_rx_data_l6_out[7:0];
|
2562 |
|
|
assign trig0[127:120] = pipe_rx_data_l7_out[7:0];
|
2563 |
|
|
|
2564 |
|
|
assign trig0[128] = l0_stats_os_received;
|
2565 |
|
|
assign trig0[132:129] = l0_ltssm_state[3:0];
|
2566 |
|
|
assign trig0[133] = upcfgcap_cycle; // from inside prod_fix
|
2567 |
|
|
assign trig0[134] = all_chan_aligned;
|
2568 |
|
|
assign trig0[135] = pipe_rx_data_k[0];
|
2569 |
|
|
assign trig0[136] = l0_mac_link_up;
|
2570 |
|
|
assign trig0[140:137] = l0_mac_negotiated_link_width[3:0];
|
2571 |
|
|
|
2572 |
|
|
assign trig0[148:141] = pipe_rxchanisaligned[7:0];
|
2573 |
|
|
|
2574 |
|
|
//-----------------------------------------------------------------
|
2575 |
|
|
//
|
2576 |
|
|
// ILA core instance
|
2577 |
|
|
//
|
2578 |
|
|
//-----------------------------------------------------------------
|
2579 |
|
|
ila i_ila
|
2580 |
|
|
(
|
2581 |
|
|
.control(control0),
|
2582 |
|
|
.clk(core_clk),
|
2583 |
|
|
.trig_out(trig_out),
|
2584 |
|
|
.trig0(trig0)
|
2585 |
|
|
);
|
2586 |
|
|
|
2587 |
|
|
|
2588 |
|
|
icon i_icon
|
2589 |
|
|
(
|
2590 |
|
|
.control0(control0)
|
2591 |
|
|
);
|
2592 |
|
|
|
2593 |
|
|
`endif //LINKTRAIN_DEBUG
|
2594 |
|
|
|
2595 |
|
|
endmodule
|
2596 |
|
|
|
2597 |
|
|
`ifdef CHIPSCOPE_LLK_TX_HANG_DEBUG
|
2598 |
|
|
|
2599 |
|
|
module ila
|
2600 |
|
|
(
|
2601 |
|
|
control,
|
2602 |
|
|
clk,
|
2603 |
|
|
data,
|
2604 |
|
|
trig0
|
2605 |
|
|
) /* synthesis syn_black_box syn_noprune=1 */;
|
2606 |
|
|
input [35:0] control;
|
2607 |
|
|
input clk;
|
2608 |
|
|
input [31:0] data;
|
2609 |
|
|
input [15:0] trig0;
|
2610 |
|
|
endmodule
|
2611 |
|
|
|
2612 |
|
|
//-------------------------------------------------------------------
|
2613 |
|
|
//
|
2614 |
|
|
// ICON core module declaration
|
2615 |
|
|
//
|
2616 |
|
|
//-------------------------------------------------------------------
|
2617 |
|
|
module icon
|
2618 |
|
|
(
|
2619 |
|
|
control0
|
2620 |
|
|
) /* synthesis syn_black_box syn_noprune=1 */;
|
2621 |
|
|
output [35:0] control0;
|
2622 |
|
|
endmodule
|
2623 |
|
|
|
2624 |
|
|
`endif // CHIPSCOPE_LLK_TX_HANG_DEBUG
|
2625 |
|
|
|
2626 |
|
|
`ifdef LINKTRAIN_DEBUG
|
2627 |
|
|
//-------------------------------------------------------------------
|
2628 |
|
|
//
|
2629 |
|
|
// ILA core module declaration
|
2630 |
|
|
//
|
2631 |
|
|
//-------------------------------------------------------------------
|
2632 |
|
|
module ila
|
2633 |
|
|
(
|
2634 |
|
|
control,
|
2635 |
|
|
clk,
|
2636 |
|
|
trig_out,
|
2637 |
|
|
trig0
|
2638 |
|
|
);
|
2639 |
|
|
input [35:0] control;
|
2640 |
|
|
input clk;
|
2641 |
|
|
output trig_out;
|
2642 |
|
|
input [148:0] trig0;
|
2643 |
|
|
endmodule
|
2644 |
|
|
|
2645 |
|
|
|
2646 |
|
|
//-------------------------------------------------------------------
|
2647 |
|
|
//
|
2648 |
|
|
// ICON core module declaration
|
2649 |
|
|
//
|
2650 |
|
|
//-------------------------------------------------------------------
|
2651 |
|
|
module icon
|
2652 |
|
|
(
|
2653 |
|
|
control0
|
2654 |
|
|
) /* synthesis syn_black_box syn_noprune=1 */;
|
2655 |
|
|
output [35:0] control0;
|
2656 |
|
|
endmodule
|
2657 |
|
|
`endif // LINKTRAIN_DEBUG
|