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//-----------------------------------------------------------------------------
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//
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// (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//-----------------------------------------------------------------------------
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// Project : V5-Block Plus for PCI Express
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// File : tlm_rx_data_snk_bar.v
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//--------------------------------------------------------------------------------
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//--------------------------------------------------------------------------------
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/*****************************************************************************
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* Description : Rx Data Sink bar hit communication
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*
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* Hierarchical :
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*
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* Functional :
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* Contructs the bar check fields, and passes hit information on
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*
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****************************************************************************/
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`timescale 1ns/1ps
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`ifndef TCQ
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`define TCQ 1
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`endif
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`ifndef AS
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module tlm_rx_data_snk_bar #(
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parameter DW = 32, // Data width
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parameter BARW = 7) // BAR-hit width
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(
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input clk_i,
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input reset_i,
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output reg [63:0] check_raddr_o,
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output reg check_rmem32_o,
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output reg check_rmem64_o,
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output reg check_rio_o,
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output reg check_rdev_id_o,
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output reg check_rbus_id_o,
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output reg check_rfun_id_o,
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input [BARW-1:0] check_rhit_bar_i,
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input check_rhit_i,
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output [BARW-1:0] check_rhit_bar_o,
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output check_rhit_o,
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output check_rhit_src_rdy_o,
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output check_rhit_ack_o,
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output check_rhit_lock_o,
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input [31:0] addr_lo_i, // 32b addr high word
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input [31:0] addr_hi_i, // 32b addr high word
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input [8:0] fulltype_oh_i, // Packet data type
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input [2:0] routing_i, // routing
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input mem64_i, // 64b memory access?
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input [15:0] req_id_i, // requester ID
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input [15:0] req_id_cpl_i, // req ID when pkt == cpl
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input eval_check_i, // latch the formatting check
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input rhit_lat3_i, // Is BAR-hit latency 3 clocks?
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input legacy_mode_i
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);
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localparam CHECK_IO_BAR_HIT_EN = 1'b1;
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//---------------------------------------------------------------------------
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// PCI Express constants
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//---------------------------------------------------------------------------
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// Bit taps for one-hot Full Type
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localparam MEM_BIT = 8;
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localparam ADR_BIT = 7;
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localparam MRD_BIT = 6;
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localparam MWR_BIT = 5;
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localparam MLK_BIT = 4;
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localparam IO_BIT = 3;
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localparam CFG_BIT = 2;
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localparam MSG_BIT = 1;
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localparam CPL_BIT = 0;
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// Route
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localparam ROUTE_BY_ID = 3'b010;
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wire [63:0] addr_64b = {addr_hi_i, addr_lo_i};
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reg [63:0] check_raddr_d;
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reg check_rmem32_d;
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reg check_rmem64_d;
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reg check_rmemlock_d;
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reg check_rmemlock_d1a;
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reg check_rio_d;
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reg check_rdev_id_d;
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reg check_rbus_id_d;
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reg check_rfun_id_d;
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reg eval_check_q1, eval_check_q2, eval_check_q3, eval_check_q4;
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reg sent_check_q2, sent_check_q3, sent_check_q4;
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reg lock_check_q2, lock_check_q3, lock_check_q4;
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// Check if endpoint is the correct recipient
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//---------------------------------------------------------------------------
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// On every request received, except implicitly routed messages, check if:
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// 1. the endpoint is the right recipient by passing to the CMM for checking:
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// . for Mem, IO and Cfg: the destination addr (checked with BARs)
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// . for Messages:
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// a. the req_id, if TLP was routed by ID
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// b. the address, if TLP was routed by addr
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// c. if dest is not RC, the endpoint is the implicit recipient
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// . for Completions: the req_id
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// 2. the type is valid
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// 3. for Messages: msg_code and routing are valid
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//
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// Since the invalid type won't trigger the 1. check, it will be detected by
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// the non assertion of check_rhit_i by the CMM
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// => check 2. is redundant with check 1.
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//
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// Note: Future possible enhancement
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// . check 3. may also be merged with 1., but that will affect the timing of
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// the live check_*_o signals provided to the CMM
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// => to be considered if those outputs get registered
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//
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// No need to check:
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// . silently dropped: Unlock
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// . passed on : User messages (Vendor_Defined)
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//---------------------------------------------------------------------------
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// Timing is tight here at 250 MHz -> split the calculations out from the CE
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// and return to 0
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// This also allows for a blocking default assignment, which makes the code
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// easier to follow
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always @* begin
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check_raddr_d = (fulltype_oh_i[MSG_BIT] ? {req_id_i,48'h0} : 0) |
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(fulltype_oh_i[CPL_BIT] ? {req_id_cpl_i,48'h0} : 0) |
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(fulltype_oh_i[ADR_BIT] ? addr_64b : 0);
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check_rbus_id_d = (fulltype_oh_i[MSG_BIT] && (routing_i == ROUTE_BY_ID)) ||
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fulltype_oh_i[CPL_BIT];
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check_rdev_id_d = (fulltype_oh_i[MSG_BIT] && (routing_i == ROUTE_BY_ID)) ||
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fulltype_oh_i[CPL_BIT];
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check_rfun_id_d = (fulltype_oh_i[MSG_BIT] && (routing_i == ROUTE_BY_ID)) ||
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fulltype_oh_i[CPL_BIT];
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check_rmem32_d = fulltype_oh_i[MEM_BIT] && !mem64_i;
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check_rmem64_d = fulltype_oh_i[MEM_BIT] && mem64_i;
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check_rmemlock_d= fulltype_oh_i[MLK_BIT];
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check_rio_d = fulltype_oh_i[IO_BIT] && CHECK_IO_BAR_HIT_EN;
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// No checks on CFG: CMM captures bus and dev ids for that function
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end
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always @(posedge clk_i) begin
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if (eval_check_i) begin
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check_raddr_o <= #`TCQ check_raddr_d;
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end
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end
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always @(posedge clk_i) begin
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if (reset_i) begin
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check_rmem32_o <= #`TCQ 0;
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check_rmem64_o <= #`TCQ 0;
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check_rmemlock_d1a <= #`TCQ 0;
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check_rio_o <= #`TCQ 0;
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check_rbus_id_o <= #`TCQ 0;
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check_rdev_id_o <= #`TCQ 0;
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check_rfun_id_o <= #`TCQ 0;
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// Our calculation from above is ready
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end else if (eval_check_i) begin
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check_rmem32_o <= #`TCQ check_rmem32_d;
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check_rmem64_o <= #`TCQ check_rmem64_d;
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check_rmemlock_d1a <= #`TCQ check_rmemlock_d;
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check_rio_o <= #`TCQ check_rio_d;
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check_rbus_id_o <= #`TCQ check_rbus_id_d;
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check_rdev_id_o <= #`TCQ check_rdev_id_d;
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check_rfun_id_o <= #`TCQ check_rfun_id_d;
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// these signals all imply src_rdy, return to zero
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end else begin
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check_rmem32_o <= #`TCQ 0;
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check_rmem64_o <= #`TCQ 0;
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check_rmemlock_d1a <= #`TCQ 0;
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check_rio_o <= #`TCQ 0;
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check_rbus_id_o <= #`TCQ 0;
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check_rdev_id_o <= #`TCQ 0;
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check_rfun_id_o <= #`TCQ 0;
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end
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end
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// Need a pipe to time the return back from the CMM, since
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// 32 and 64 signal the CMM to start calculating at
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// different times
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// Eval is when the check is occuring
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// Sent is if we actually sent one (and expect a response)
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//---------------------------------------------------------
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always @(posedge clk_i) begin
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eval_check_q1 <= #`TCQ eval_check_i;
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eval_check_q2 <= #`TCQ eval_check_q1;
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eval_check_q3 <= #`TCQ eval_check_q2;
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eval_check_q4 <= #`TCQ eval_check_q3;
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sent_check_q2 <= #`TCQ eval_check_q1 &&
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(check_rmem32_o ||
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check_rmem64_o ||
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check_rio_o ||
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check_rbus_id_o ||
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check_rdev_id_o ||
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check_rfun_id_o);
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sent_check_q3 <= #`TCQ sent_check_q2;
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sent_check_q4 <= #`TCQ sent_check_q3;
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lock_check_q2 <= #`TCQ check_rmemlock_d1a;
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lock_check_q3 <= #`TCQ lock_check_q2;
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lock_check_q4 <= #`TCQ lock_check_q3;
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end
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// Values from the CMM
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assign check_rhit_bar_o = check_rhit_bar_i;
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assign check_rhit_o = check_rhit_i;
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// Result of our internal timing circuit
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assign check_rhit_src_rdy_o = rhit_lat3_i ? eval_check_q4 : eval_check_q3;
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assign check_rhit_ack_o = rhit_lat3_i ? sent_check_q4 : sent_check_q3;
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assign check_rhit_lock_o = rhit_lat3_i ? lock_check_q4 : lock_check_q3;
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endmodule
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`endif
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