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//-----------------------------------------------------------------------------
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//
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// (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//-----------------------------------------------------------------------------
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// Project : V5-Block Plus for PCI Express
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// File : tlm_rx_data_snk_pwr_mgmt.v
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//--------------------------------------------------------------------------------
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//--------------------------------------------------------------------------------
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/*****************************************************************************
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* Description : Rx Data Sink power management packet interpretation
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*
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* Hierarchical :
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*
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* Functional :
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* Removes power management packets from the stream and signals
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* sideband to CMM
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*
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****************************************************************************/
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`timescale 1ns/1ps
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`ifndef TCQ
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`define TCQ 1
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`endif
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`ifndef AS
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module tlm_rx_data_snk_pwr_mgmt
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(
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input clk_i,
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input reset_i,
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// Power management signals for CMM
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output reg pm_as_nak_l1_o, // Pkt detected, implies src_rdy
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output reg pm_turn_off_o, // Pkt detected, implies src_rdy
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output reg pm_set_slot_pwr_o, // Pkt detected, implies src_rdy
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output reg [9:0] pm_set_slot_pwr_data_o, // value of field
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output reg pm_msg_detect_o, // grabbed a pm signal
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input ismsg_i, // Packet data type
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input [7:0] msgcode_i, // message code
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input [9:0] pwr_data_i, // set slot value
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input eval_pwr_mgmt_i, // grab the sideband fields
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input eval_pwr_mgmt_data_i, // get the data, if it exists
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input act_pwr_mgmt_i // transmit the sideband fields
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);
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//-----------------------------------------------------------------------------
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// PCI Express constants
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//-----------------------------------------------------------------------------
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// Message code
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localparam PM_ACTIVE_STATE_NAK = 8'b0001_0100;
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localparam PME_TURN_OFF = 8'b0001_1001;
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localparam SET_SLOT_POWER_LIMIT = 8'b0101_0000;
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reg cur_pm_as_nak_l1;
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reg cur_pm_turn_off;
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reg cur_pm_set_slot_pwr;
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reg eval_pwr_mgmt_q1;
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reg eval_pwr_mgmt_data_q1;
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reg act_pwr_mgmt_q1;
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reg [9:0] pm_set_slot_pwr_data_d1;
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// grab the fields at the beginning of the packet when known
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//----------------------------------------------------------
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always @(posedge clk_i) begin
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if (reset_i) begin
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cur_pm_as_nak_l1 <= #`TCQ 0;
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cur_pm_turn_off <= #`TCQ 0;
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cur_pm_set_slot_pwr <= #`TCQ 0;
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end else if (eval_pwr_mgmt_i) begin
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// ismsg is ANY message - malformed will are another modules
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// problem
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if (ismsg_i) begin
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cur_pm_as_nak_l1 <= #`TCQ (msgcode_i == PM_ACTIVE_STATE_NAK);
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cur_pm_turn_off <= #`TCQ (msgcode_i == PME_TURN_OFF);
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cur_pm_set_slot_pwr <= #`TCQ (msgcode_i == SET_SLOT_POWER_LIMIT);
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// if we aren't a mesg, these can't be true
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end else begin
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cur_pm_as_nak_l1 <= #`TCQ 0;
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cur_pm_turn_off <= #`TCQ 0;
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cur_pm_set_slot_pwr <= #`TCQ 0;
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end
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end
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end
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// We need to know which packets we're dropping because we're
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// already signalling them sideband
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// pipelined due to timing
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//------------------------------------------------------
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always @(posedge clk_i) begin
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if (reset_i) begin
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pm_msg_detect_o <= #`TCQ 0;
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end else if (eval_pwr_mgmt_q1) begin
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pm_msg_detect_o <= #`TCQ cur_pm_as_nak_l1 ||
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cur_pm_turn_off ||
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cur_pm_set_slot_pwr;
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end
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end
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// Data comes two cycles after the header fields, so we can't
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// share the input latching fields
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// Furthermore, it will not go away until after eof_q2, so we
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// can cheat on registers
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// Lastly, it does not imply activation, so we can always grab
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// the field
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//-----------------------------------------------------------
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always @(posedge clk_i) begin
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if (eval_pwr_mgmt_data_i) begin
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pm_set_slot_pwr_data_d1 <= #`TCQ pwr_data_i;
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end
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if (eval_pwr_mgmt_data_q1) begin
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pm_set_slot_pwr_data_o <= #`TCQ pm_set_slot_pwr_data_d1;
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end
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end
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// transmit sidebands when we know they are good for
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// one cycle only
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always @(posedge clk_i) begin
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if (reset_i) begin
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pm_as_nak_l1_o <= #`TCQ 0;
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pm_turn_off_o <= #`TCQ 0;
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pm_set_slot_pwr_o <= #`TCQ 0;
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// at this point, we know the packet is valid
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end else if (act_pwr_mgmt_i) begin
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pm_as_nak_l1_o <= #`TCQ cur_pm_as_nak_l1;
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pm_turn_off_o <= #`TCQ cur_pm_turn_off;
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pm_set_slot_pwr_o <= #`TCQ cur_pm_set_slot_pwr;
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// implies src_rdy, return to zero
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end else if (act_pwr_mgmt_q1) begin
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pm_as_nak_l1_o <= #`TCQ 0;
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pm_turn_off_o <= #`TCQ 0;
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pm_set_slot_pwr_o <= #`TCQ 0;
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end
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end
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// Also need delayed version
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always @(posedge clk_i) begin
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if (reset_i) begin
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eval_pwr_mgmt_q1 <= #`TCQ 0;
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eval_pwr_mgmt_data_q1 <= #`TCQ 0;
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act_pwr_mgmt_q1 <= #`TCQ 0;
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end else begin
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eval_pwr_mgmt_q1 <= #`TCQ eval_pwr_mgmt_i;
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eval_pwr_mgmt_data_q1 <= #`TCQ eval_pwr_mgmt_data_i;
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act_pwr_mgmt_q1 <= #`TCQ act_pwr_mgmt_i;
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end
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end
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endmodule
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`endif
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