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//-----------------------------------------------------------------------------
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//
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// (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//-----------------------------------------------------------------------------
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// Project : V5-Block Plus for PCI Express
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// File : tx_sync_gtp.v
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//--------------------------------------------------------------------------------
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//--------------------------------------------------------------------------------
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//----------------------------------------------------------------------
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// ____ ____
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// / /\/ /
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// /___/ \ / Vendor: Xilinx
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// \ \ \/ Version : 1.4
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// \ \ Application : GTP Wizard
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// / / Filename : tx_sync.v
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// /___/ /\ Timestamp :
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// \ \ / \
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// \___\/\___\
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//
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//
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// Module TX_SYNC
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// Generated by Xilinx GTP Wizard
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`timescale 1ns / 1ps
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`define DLY #1
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module TX_SYNC_GTP
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(
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output TXENPMAPHASEALIGN,
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output TXPMASETPHASE,
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output SYNC_DONE,
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input USER_CLK,
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input RESET
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);
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//*******************************Register Declarations************************
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reg begin_r;
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reg phase_align_r;
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reg ready_r;
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reg [14:0] sync_counter_r;
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reg [9:0] wait_before_sync_r;
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reg wait_stable_r;
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//*******************************Wire Declarations****************************
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wire count_512_complete_r;
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wire next_phase_align_c;
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wire next_ready_c;
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wire next_wait_stable_c;
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wire sync_count_complete_r;
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//*******************************Main Body of Code****************************
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//________________________________ State machine __________________________
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// This state machine manages the phase alingnment procedure of the GTP.
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// The module is held in reset till the usrclk source is stable.In the
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// case of buffer bypass where the refclkout is used to clock the usrclks,
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// the usrclk stable indication is given the pll_locked signal.
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// Once the pll_lock is asserted, state machine goes into the wait_stable_r
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// for 512 cycles to allow some time to ensure the pll is stable. After this,
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// it goes into the phase_align_r state where the phase alignment procedure is
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// executed. This involves asserting the TXENPHASEALIGN and TXPMASETPHASE for
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// the recommended number of clock cycles
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// State registers
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always @(posedge USER_CLK)
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if(RESET)
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{begin_r,wait_stable_r,phase_align_r,ready_r} <= `DLY 4'b1000;
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else
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begin
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begin_r <= `DLY 1'b0;
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wait_stable_r <= `DLY next_wait_stable_c;
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phase_align_r <= `DLY next_phase_align_c;
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ready_r <= `DLY next_ready_c;
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end
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// Next state logic
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assign next_wait_stable_c = begin_r |
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(wait_stable_r & !count_512_complete_r);
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assign next_phase_align_c = (wait_stable_r & count_512_complete_r) |
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(phase_align_r & !sync_count_complete_r);
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assign next_ready_c = (phase_align_r & sync_count_complete_r) |
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ready_r;
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//_________ Counter for to wait for pll to be stable before sync __________
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always @(posedge USER_CLK)
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begin
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if (!wait_stable_r)
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wait_before_sync_r <= `DLY 10'b000000000;
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else
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wait_before_sync_r <= `DLY wait_before_sync_r + 1'b1;
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end
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assign count_512_complete_r = wait_before_sync_r[9];
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//_______________ Counter for holding SYNC for SYNC_CYCLES ________________
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always @(posedge USER_CLK)
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begin
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if (!phase_align_r)
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sync_counter_r <= `DLY 15'b000000000000000;
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else
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sync_counter_r <= `DLY sync_counter_r + 1'b1;
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end
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assign sync_count_complete_r = sync_counter_r[12];
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//_______________ Assign the phase align ports into the GTP _______________
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assign TXENPMAPHASEALIGN = !begin_r;
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assign TXPMASETPHASE = phase_align_r;
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//_______________________ Assign the sync_done port _______________________
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assign SYNC_DONE = ready_r;
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endmodule
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