Subversion Repositories pcie_ds_dma

-------------------------------------------------------------------------------

--

-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.

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-------------------------------------------------------------------------------

-- Project    : Series-7 Integrated Block for PCI Express

-- File       : cl_a7pcie_x4.vhd

-- Version    : 1.10

--

-- Description: Solution wrapper for Virtex7 Hard Block for PCI Express

--

--

--

----------------------------------------------------------------------------------

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_misc.all;

use ieee.std_logic_unsigned.all;

use ieee.numeric_std.all;

entity cl_a7pcie_x4 is

  generic (

    CFG_VEND_ID                                    : std_logic_vector := X"10EE";

    CFG_DEV_ID                                     : std_logic_vector := X"7024";

    CFG_REV_ID                                     : std_logic_vector := X"00";

    CFG_SUBSYS_VEND_ID                             : std_logic_vector := X"10EE";

    CFG_SUBSYS_ID                                  : std_logic_vector := X"0007";

    ALLOW_X8_GEN2                                  : string     := "FALSE";

    PIPE_PIPELINE_STAGES                           : integer    := 1;

    AER_BASE_PTR                                   : bit_vector := X"000";

    AER_CAP_ECRC_CHECK_CAPABLE                     : string     := "FALSE";

    AER_CAP_ECRC_GEN_CAPABLE                       : string     := "FALSE";

    AER_CAP_MULTIHEADER                            : string     := "FALSE";

    AER_CAP_NEXTPTR                                : bit_vector := X"000";

    AER_CAP_OPTIONAL_ERR_SUPPORT                   : bit_vector := X"000000";

    AER_CAP_ON                                     : string     := "FALSE";

    AER_CAP_PERMIT_ROOTERR_UPDATE                  : string     := "FALSE";

    BAR0                                           : bit_vector := X"FFE00000";

    BAR1                                           : bit_vector := X"FFE00000";

    BAR2                                           : bit_vector := X"00000000";

    BAR3                                           : bit_vector := X"00000000";

    BAR4                                           : bit_vector := X"00000000";

    BAR5                                           : bit_vector := X"00000000";

    C_DATA_WIDTH                                   : integer    := 64;

    CARDBUS_CIS_POINTER                            : bit_vector := X"00000000";

    CLASS_CODE                                     : bit_vector := X"058000";

    CMD_INTX_IMPLEMENTED                           : string     := "TRUE";

    CPL_TIMEOUT_DISABLE_SUPPORTED                  : string     := "FALSE";

    CPL_TIMEOUT_RANGES_SUPPORTED                   : bit_vector := X"2";

    DEV_CAP_ENDPOINT_L0S_LATENCY                   : integer    := 0;

    DEV_CAP_ENDPOINT_L1_LATENCY                    : integer    := 7;

    DEV_CAP_EXT_TAG_SUPPORTED                      : string     := "FALSE";

    DEV_CAP_MAX_PAYLOAD_SUPPORTED                  : integer    := 1;

    DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT              : integer    := 0;

    DEV_CAP2_ARI_FORWARDING_SUPPORTED              : string     := "FALSE";

    DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED        : string     := "FALSE";

    DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED        : string     := "FALSE";

    DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED            : string     := "FALSE";

    DEV_CAP2_CAS128_COMPLETER_SUPPORTED            : string     := "FALSE";

    DEV_CAP2_TPH_COMPLETER_SUPPORTED               : bit_vector := X"00";

    DEV_CONTROL_EXT_TAG_DEFAULT                    : string     := "FALSE";

    DISABLE_LANE_REVERSAL                          : string     := "TRUE";

    DISABLE_RX_POISONED_RESP                       : string     := "FALSE";

    DISABLE_SCRAMBLING                             : string     := "FALSE";

    DSN_BASE_PTR                                   : bit_vector := X"100";

    DSN_CAP_NEXTPTR                                : bit_vector := X"000";

    DSN_CAP_ON                                     : string     := "TRUE";

    ENABLE_MSG_ROUTE                               : bit_vector := "00000000000";

    ENABLE_RX_TD_ECRC_TRIM                         : string     := "TRUE";

    EXPANSION_ROM                                  : bit_vector := X"00000000";

    EXT_CFG_CAP_PTR                                : bit_vector := X"3F";

    EXT_CFG_XP_CAP_PTR                             : bit_vector := X"3FF";

    HEADER_TYPE                                    : bit_vector := X"00";

    INTERRUPT_PIN                                  : bit_vector := X"1";

    LAST_CONFIG_DWORD                              : bit_vector := X"3FF";

    LINK_CAP_ASPM_OPTIONALITY                      : string     := "FALSE";

    LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP         : string     := "FALSE";

    LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP       : string     := "FALSE";

    LINK_CAP_MAX_LINK_SPEED                        : bit_vector := X"2";

    LINK_CAP_MAX_LINK_SPEED_int                    : integer    := 2;

    LINK_CAP_MAX_LINK_WIDTH                        : bit_vector := X"04";

    LINK_CAP_MAX_LINK_WIDTH_int                    : integer    := 4;

    LINK_CTRL2_DEEMPHASIS                          : string     := "FALSE";

    LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE         : string     := "FALSE";

    LINK_CTRL2_TARGET_LINK_SPEED                   : bit_vector := X"2";

    LINK_STATUS_SLOT_CLOCK_CONFIG                  : string     := "TRUE";

    LL_ACK_TIMEOUT                                 : bit_vector := X"0000";

    LL_ACK_TIMEOUT_EN                              : string     := "FALSE";

    LL_ACK_TIMEOUT_FUNC                            : integer    := 0;

    LL_REPLAY_TIMEOUT                              : bit_vector := X"0000";

    LL_REPLAY_TIMEOUT_EN                           : string     := "FALSE";

    LL_REPLAY_TIMEOUT_FUNC                         : integer    := 1;

    LTSSM_MAX_LINK_WIDTH                           : bit_vector := X"04";

    MSI_CAP_MULTIMSGCAP                            : integer    := 0;

    MSI_CAP_MULTIMSG_EXTENSION                     : integer    := 0;

    MSI_CAP_ON                                     : string     := "FALSE";

    MSI_CAP_PER_VECTOR_MASKING_CAPABLE             : string     := "FALSE";

    MSI_CAP_64_BIT_ADDR_CAPABLE                    : string     := "TRUE";

    MSIX_CAP_ON                                    : string     := "FALSE";

    MSIX_CAP_PBA_BIR                               : integer    := 0;

    MSIX_CAP_PBA_OFFSET                            : bit_vector := X"0";

    MSIX_CAP_TABLE_BIR                             : integer    := 0;

    MSIX_CAP_TABLE_OFFSET                          : bit_vector := X"0";

    MSIX_CAP_TABLE_SIZE                            : bit_vector := X"0";

    PCIE_CAP_DEVICE_PORT_TYPE                      : bit_vector := X"0";

    PCIE_CAP_NEXTPTR                               : bit_vector := X"00";

    PM_CAP_DSI                                     : string     := "FALSE";

    PM_CAP_D1SUPPORT                               : string     := "FALSE";

    PM_CAP_D2SUPPORT                               : string     := "FALSE";

    PM_CAP_NEXTPTR                                 : bit_vector := X"60";

    PM_CAP_PMESUPPORT                              : bit_vector := X"0F";

    PM_CSR_NOSOFTRST                               : string     := "TRUE";

    PM_DATA_SCALE0                                 : bit_vector := X"0";

    PM_DATA_SCALE1                                 : bit_vector := X"0";

    PM_DATA_SCALE2                                 : bit_vector := X"0";

    PM_DATA_SCALE3                                 : bit_vector := X"0";

    PM_DATA_SCALE4                                 : bit_vector := X"0";

    PM_DATA_SCALE5                                 : bit_vector := X"0";

    PM_DATA_SCALE6                                 : bit_vector := X"0";

    PM_DATA_SCALE7                                 : bit_vector := X"0";

    PM_DATA0                                       : bit_vector := X"00";

    PM_DATA1                                       : bit_vector := X"00";

    PM_DATA2                                       : bit_vector := X"00";

    PM_DATA3                                       : bit_vector := X"00";

    PM_DATA4                                       : bit_vector := X"00";

    PM_DATA5                                       : bit_vector := X"00";

    PM_DATA6                                       : bit_vector := X"00";

    PM_DATA7                                       : bit_vector := X"00";

    RBAR_BASE_PTR                                  : bit_vector := X"000";

    RBAR_CAP_CONTROL_ENCODEDBAR0                   : bit_vector := X"00";

    RBAR_CAP_CONTROL_ENCODEDBAR1                   : bit_vector := X"00";

    RBAR_CAP_CONTROL_ENCODEDBAR2                   : bit_vector := X"00";

    RBAR_CAP_CONTROL_ENCODEDBAR3                   : bit_vector := X"00";

    RBAR_CAP_CONTROL_ENCODEDBAR4                   : bit_vector := X"00";

    RBAR_CAP_CONTROL_ENCODEDBAR5                   : bit_vector := X"00";

    RBAR_CAP_INDEX0                                : bit_vector := X"0";

    RBAR_CAP_INDEX1                                : bit_vector := X"0";

    RBAR_CAP_INDEX2                                : bit_vector := X"0";

    RBAR_CAP_INDEX3                                : bit_vector := X"0";

    RBAR_CAP_INDEX4                                : bit_vector := X"0";

    RBAR_CAP_INDEX5                                : bit_vector := X"0";

    RBAR_CAP_ON                                    : string     := "FALSE";

    RBAR_CAP_SUP0                                  : bit_vector := X"00001";

    RBAR_CAP_SUP1                                  : bit_vector := X"00001";

    RBAR_CAP_SUP2                                  : bit_vector := X"00001";

    RBAR_CAP_SUP3                                  : bit_vector := X"00001";

    RBAR_CAP_SUP4                                  : bit_vector := X"00001";

    RBAR_CAP_SUP5                                  : bit_vector := X"00001";

    RBAR_NUM                                       : bit_vector := X"0";

    RECRC_CHK                                      : integer    := 0;

    RECRC_CHK_TRIM                                 : string     := "FALSE";

    REF_CLK_FREQ                                   : integer    := 0;    -- 0 - 100 MHz; 1 - 125 MHz; 2 - 250 MHz

    --KEEP_WIDTH                                   : integer    := C_DATA_WIDTH / 8;

    TL_RX_RAM_RADDR_LATENCY                        : integer    := 0;

    TL_RX_RAM_RDATA_LATENCY                        : integer    := 2;

    TL_RX_RAM_WRITE_LATENCY                        : integer    := 0;

    TL_TX_RAM_RADDR_LATENCY                        : integer    := 0;

    TL_TX_RAM_RDATA_LATENCY                        : integer    := 2;

    TL_TX_RAM_WRITE_LATENCY                        : integer    := 0;

    TRN_NP_FC                                      : string     := "TRUE";

    TRN_DW                                         : string     := "FALSE";

    UPCONFIG_CAPABLE                               : string     := "TRUE";

    UPSTREAM_FACING                                : string     := "TRUE";

    UR_ATOMIC                                      : string     := "FALSE";

    UR_INV_REQ                                     : string     := "TRUE";

    UR_PRS_RESPONSE                                : string     := "TRUE";

    USER_CLK_FREQ                                  : integer    := 3;

    USER_CLK2_DIV2                                 : string     := "FALSE";

    VC_BASE_PTR                                    : bit_vector := X"000";

    VC_CAP_NEXTPTR                                 : bit_vector := X"000";

    VC_CAP_ON                                      : string     := "FALSE";

    VC_CAP_REJECT_SNOOP_TRANSACTIONS               : string     := "FALSE";

    VC0_CPL_INFINITE                               : string     := "TRUE";

    VC0_RX_RAM_LIMIT                               : bit_vector := X"3FF";

    VC0_TOTAL_CREDITS_CD                           : integer    := 370;

    VC0_TOTAL_CREDITS_CH                           : integer    := 72;

    VC0_TOTAL_CREDITS_NPH                          : integer    := 4;

    VC0_TOTAL_CREDITS_NPD                          : integer    := 8;

    VC0_TOTAL_CREDITS_PD                           : integer    := 32;

    VC0_TOTAL_CREDITS_PH                           : integer    := 4;

    VC0_TX_LASTPACKET                              : integer    := 28;

    VSEC_BASE_PTR                                  : bit_vector := X"000";

    VSEC_CAP_NEXTPTR                               : bit_vector := X"000";

    VSEC_CAP_ON                                    : string     := "FALSE";

    DISABLE_ASPM_L1_TIMER                          : string     := "FALSE";

    DISABLE_BAR_FILTERING                          : string     := "FALSE";

    DISABLE_ID_CHECK                               : string     := "FALSE";

    DISABLE_RX_TC_FILTER                           : string     := "FALSE";

    DNSTREAM_LINK_NUM                              : bit_vector := X"00";

    DSN_CAP_ID                                     : bit_vector := X"0003";

    DSN_CAP_VERSION                                : bit_vector := X"1";

    ENTER_RVRY_EI_L0                               : string     := "TRUE";

    INFER_EI                                       : bit_vector := X"00";

    IS_SWITCH                                      : string     := "FALSE";

    LINK_CAP_ASPM_SUPPORT                          : integer    := 1;

    LINK_CAP_CLOCK_POWER_MANAGEMENT                : string     := "FALSE";

    LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1          : integer    := 7;

    LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2          : integer    := 7;

    LINK_CAP_L0S_EXIT_LATENCY_GEN1                 : integer    := 7;

    LINK_CAP_L0S_EXIT_LATENCY_GEN2                 : integer    := 7;

    LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1           : integer    := 7;

    LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2           : integer    := 7;

    LINK_CAP_L1_EXIT_LATENCY_GEN1                  : integer    := 7;

    LINK_CAP_L1_EXIT_LATENCY_GEN2                  : integer    := 7;

    LINK_CAP_RSVD_23                               : integer    := 0;

    LINK_CONTROL_RCB                               : integer    := 0;

    MSI_BASE_PTR                                   : bit_vector := X"48";

    MSI_CAP_ID                                     : bit_vector := X"05";

    MSI_CAP_NEXTPTR                                : bit_vector := X"60";

    MSIX_BASE_PTR                                  : bit_vector := X"9c";

    MSIX_CAP_ID                                    : bit_vector := X"11";

    MSIX_CAP_NEXTPTR                               : bit_vector := X"00";

    N_FTS_COMCLK_GEN1                              : integer    := 255;

    N_FTS_COMCLK_GEN2                              : integer    := 255;

    N_FTS_GEN1                                     : integer    := 255;

    N_FTS_GEN2                                     : integer    := 255;

    PCIE_BASE_PTR                                  : bit_vector := X"60";

    PCIE_CAP_CAPABILITY_ID                         : bit_vector := X"10";

    PCIE_CAP_CAPABILITY_VERSION                    : bit_vector := X"2";

    PCIE_CAP_ON                                    : string     := "TRUE";

    PCIE_CAP_RSVD_15_14                            : integer    := 0;

    PCIE_CAP_SLOT_IMPLEMENTED                      : string     := "FALSE";

    PCIE_REVISION                                  : integer    := 2;

    PL_AUTO_CONFIG                                 : integer    := 0;

    PL_FAST_TRAIN                                  : string     := "FALSE";

    PCIE_EXT_CLK                                   : string     := "TRUE";

    PM_BASE_PTR                                    : bit_vector := X"40";

    PM_CAP_AUXCURRENT                              : integer    := 0;

    PM_CAP_ID                                      : bit_vector := X"01";

    PM_CAP_ON                                      : string     := "TRUE";

    PM_CAP_PME_CLOCK                               : string     := "FALSE";

    PM_CAP_RSVD_04                                 : integer    := 0;

    PM_CAP_VERSION                                 : integer    := 3;

    PM_CSR_BPCCEN                                  : string     := "FALSE";

    PM_CSR_B2B3                                    : string     := "FALSE";

    ROOT_CAP_CRS_SW_VISIBILITY                     : string     := "FALSE";

    SELECT_DLL_IF                                  : string     := "FALSE";

    SLOT_CAP_ATT_BUTTON_PRESENT                    : string     := "FALSE";

    SLOT_CAP_ATT_INDICATOR_PRESENT                 : string     := "FALSE";

    SLOT_CAP_ELEC_INTERLOCK_PRESENT                : string     := "FALSE";

    SLOT_CAP_HOTPLUG_CAPABLE                       : string     := "FALSE";

    SLOT_CAP_HOTPLUG_SURPRISE                      : string     := "FALSE";

    SLOT_CAP_MRL_SENSOR_PRESENT                    : string     := "FALSE";

    SLOT_CAP_NO_CMD_COMPLETED_SUPPORT              : string     := "FALSE";

    SLOT_CAP_PHYSICAL_SLOT_NUM                     : bit_vector := X"0000";

    SLOT_CAP_POWER_CONTROLLER_PRESENT              : string     := "FALSE";

    SLOT_CAP_POWER_INDICATOR_PRESENT               : string     := "FALSE";

    SLOT_CAP_SLOT_POWER_LIMIT_SCALE                : integer    := 0;

    SLOT_CAP_SLOT_POWER_LIMIT_VALUE                : bit_vector := X"00";

    SPARE_BIT0                                     : integer    := 0;

    SPARE_BIT1                                     : integer    := 0;

    SPARE_BIT2                                     : integer    := 0;

    SPARE_BIT3                                     : integer    := 0;

    SPARE_BIT4                                     : integer    := 0;

    SPARE_BIT5                                     : integer    := 0;

    SPARE_BIT6                                     : integer    := 0;

    SPARE_BIT7                                     : integer    := 0;

    SPARE_BIT8                                     : integer    := 0;

    SPARE_BYTE0                                    : bit_vector := X"00";

    SPARE_BYTE1                                    : bit_vector := X"00";

    SPARE_BYTE2                                    : bit_vector := X"00";

    SPARE_BYTE3                                    : bit_vector := X"00";

    SPARE_WORD0                                    : bit_vector := X"00000000";

    SPARE_WORD1                                    : bit_vector := X"00000000";

    SPARE_WORD2                                    : bit_vector := X"00000000";

    SPARE_WORD3                                    : bit_vector := X"00000000";

    TL_RBYPASS                                     : string     := "FALSE";

    TL_TFC_DISABLE                                 : string     := "FALSE";

    TL_TX_CHECKS_DISABLE                           : string     := "FALSE";

    EXIT_LOOPBACK_ON_EI                            : string     := "TRUE";

    CFG_ECRC_ERR_CPLSTAT                           : integer    := 0;

    CAPABILITIES_PTR                               : bit_vector := X"40";

    CRM_MODULE_RSTS                                : bit_vector := X"00";

    DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE            : string     := "TRUE";

    DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE            : string     := "TRUE";

    DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE           : string     := "FALSE";

    DEV_CAP_ROLE_BASED_ERROR                       : string     := "TRUE";

    DEV_CAP_RSVD_14_12                             : integer    := 0;

    DEV_CAP_RSVD_17_16                             : integer    := 0;

    DEV_CAP_RSVD_31_29                             : integer    := 0;

    DEV_CONTROL_AUX_POWER_SUPPORTED                : string     := "FALSE";

    VC_CAP_ID                                      : bit_vector := X"0002";

    VC_CAP_VERSION                                 : bit_vector := X"1";

    VSEC_CAP_HDR_ID                                : bit_vector := X"1234";

    VSEC_CAP_HDR_LENGTH                            : bit_vector := X"018";

    VSEC_CAP_HDR_REVISION                          : bit_vector := X"1";

    VSEC_CAP_ID                                    : bit_vector := X"000b";

    VSEC_CAP_IS_LINK_VISIBLE                       : string     := "TRUE";

    VSEC_CAP_VERSION                               : bit_vector := X"1";

    DISABLE_ERR_MSG                                : string     := "FALSE";

    DISABLE_LOCKED_FILTER                          : string     := "FALSE";

    DISABLE_PPM_FILTER                             : string     := "FALSE";

    ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED         : string     := "FALSE";

    INTERRUPT_STAT_AUTO                            : string     := "TRUE";

    MPS_FORCE                                      : string     := "FALSE";

    PM_ASPML0S_TIMEOUT                             : bit_vector := X"0000";

    PM_ASPML0S_TIMEOUT_EN                          : string     := "FALSE";

    PM_ASPML0S_TIMEOUT_FUNC                        : integer    := 0;

    PM_ASPM_FASTEXIT                               : string     := "FALSE";

    PM_MF                                          : string     := "FALSE";

    RP_AUTO_SPD                                    : bit_vector := X"1";

    RP_AUTO_SPD_LOOPCNT                            : bit_vector := X"1f";

    SIM_VERSION                                    : string     := "1.0";

    SSL_MESSAGE_AUTO                               : string     := "FALSE";

    TECRC_EP_INV                                   : string     := "FALSE";

    UR_CFG1                                        : string     := "TRUE";

    USE_RID_PINS                                   : string     := "FALSE";

    -- New Parameters

    DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED           : string     := "FALSE";

    DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED          : string     := "FALSE";

    DEV_CAP2_LTR_MECHANISM_SUPPORTED               : string     := "FALSE";

    DEV_CAP2_MAX_ENDEND_TLP_PREFIXES               : bit_vector := X"0";

    DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING            : string     := "FALSE";

    LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE           : string     := "FALSE";

    AER_CAP_ID                                     : bit_vector := X"0001";

    AER_CAP_VERSION                                : bit_vector := X"1";

    RBAR_CAP_ID                                    : bit_vector := X"0015";

    RBAR_CAP_NEXTPTR                               : bit_vector := X"000";

    RBAR_CAP_VERSION                               : bit_vector := X"1";

    PCIE_USE_MODE                                  : string     := "1.0";

    PCIE_GT_DEVICE                                 : string     := "GTP";

    PCIE_CHAN_BOND                                 : integer    := 1;

    PCIE_PLL_SEL                                   : string     := "CPLL";

    PCIE_ASYNC_EN                                  : string     := "FALSE";

    PCIE_TXBUF_EN                                  : string     := "FALSE"

  );

  port (

     -------------------------------------------------------------------------------------------------------------------

     -- 1. PCI Express (pci_exp) Interface                                                                            --

     -------------------------------------------------------------------------------------------------------------------

      pci_exp_txp                                : out std_logic_vector(3 downto 0);

      pci_exp_txn                                : out std_logic_vector(3 downto 0);

      pci_exp_rxp                                : in std_logic_vector(3 downto 0);

      pci_exp_rxn                                : in std_logic_vector(3 downto 0);

     -------------------------------------------------------------------------------------------------------------------

     -- 2. Clocking Interface                                                                                         --

     -------------------------------------------------------------------------------------------------------------------

      PIPE_PCLK_IN                               : in std_logic;

      PIPE_RXUSRCLK_IN                           : in std_logic;

      PIPE_RXOUTCLK_IN                           : in std_logic_vector(3 downto 0);

      PIPE_DCLK_IN                               : in std_logic;

      PIPE_USERCLK1_IN                           : in std_logic;

      PIPE_USERCLK2_IN                           : in std_logic;

      PIPE_OOBCLK_IN                             : in std_logic;

      PIPE_MMCM_LOCK_IN                          : in std_logic;

      PIPE_TXOUTCLK_OUT                          : out std_logic;

      PIPE_RXOUTCLK_OUT                          : out std_logic_vector(3 downto 0);

      PIPE_PCLK_SEL_OUT                          : out std_logic_vector(3 downto 0);

      PIPE_GEN3_OUT                              : out std_logic;

     -------------------------------------------------------------------------------------------------------------------

     -- 3. AXI-S Interface                                                                                            --

     -------------------------------------------------------------------------------------------------------------------

      -- Common

      user_clk_out                               : out std_logic;

      user_reset_out                             : out std_logic;

      user_lnk_up                                : out std_logic;

      -- TX

      tx_buf_av                                  : out std_logic_vector(5 downto 0);

      tx_cfg_req                                 : out std_logic;

      tx_err_drop                                : out std_logic;

      s_axis_tx_tready                           : out std_logic;

      s_axis_tx_tdata                            : in std_logic_vector((C_DATA_WIDTH - 1) downto 0);

      s_axis_tx_tkeep                            : in std_logic_vector((C_DATA_WIDTH / 8 - 1) downto 0);

      s_axis_tx_tlast                            : in std_logic;

      s_axis_tx_tvalid                           : in std_logic;

      s_axis_tx_tuser                            : in std_logic_vector(3 downto 0);

      tx_cfg_gnt                                 : in std_logic;

      -- RX

      m_axis_rx_tdata                            : out std_logic_vector((C_DATA_WIDTH - 1) downto 0);

      m_axis_rx_tkeep                            : out std_logic_vector((C_DATA_WIDTH / 8 - 1) downto 0);

      m_axis_rx_tlast                            : out std_logic;

      m_axis_rx_tvalid                           : out std_logic;

      m_axis_rx_tready                           : in std_logic;

      m_axis_rx_tuser                            : out std_logic_vector(21 downto 0);

      rx_np_ok                                   : in std_logic;

      rx_np_req                                  : in std_logic;

      -- Flow Control

      fc_cpld                                    : out std_logic_vector(11 downto 0);

      fc_cplh                                    : out std_logic_vector(7 downto 0);

      fc_npd                                     : out std_logic_vector(11 downto 0);

      fc_nph                                     : out std_logic_vector(7 downto 0);

      fc_pd                                      : out std_logic_vector(11 downto 0);

      fc_ph                                      : out std_logic_vector(7 downto 0);

      fc_sel                                     : in std_logic_vector(2 downto 0);

     -------------------------------------------------------------------------------------------------------------------

     -- 4. Configuration (CFG) Interface                                                                              --

     -------------------------------------------------------------------------------------------------------------------

     ---------------------------------------------------------------------

      -- EP and RP                                                      --

     ---------------------------------------------------------------------

      cfg_mgmt_do                                : out std_logic_vector (31 downto 0);

      cfg_mgmt_rd_wr_done                        : out std_logic;

      cfg_status                                 : out std_logic_vector(15 downto 0);

      cfg_command                                : out std_logic_vector(15 downto 0);

      cfg_dstatus                                : out std_logic_vector(15 downto 0);

      cfg_dcommand                               : out std_logic_vector(15 downto 0);

      cfg_lstatus                                : out std_logic_vector(15 downto 0);

      cfg_lcommand                               : out std_logic_vector(15 downto 0);

      cfg_dcommand2                              : out std_logic_vector(15 downto 0);

      cfg_pcie_link_state                        : out std_logic_vector(2 downto 0);

      cfg_pmcsr_pme_en                           : out std_logic;

      cfg_pmcsr_powerstate                       : out std_logic_vector(1 downto 0);

      cfg_pmcsr_pme_status                       : out std_logic;

      cfg_received_func_lvl_rst                  : out std_logic;

      -- Management Interface

      cfg_mgmt_di                                : in std_logic_vector (31 downto 0);

      cfg_mgmt_byte_en                           : in std_logic_vector (3 downto 0);

      cfg_mgmt_dwaddr                            : in std_logic_vector (9 downto 0);

      cfg_mgmt_wr_en                             : in std_logic;

      cfg_mgmt_rd_en                             : in std_logic;

      cfg_mgmt_wr_readonly                       : in std_logic;

      -- Error Reporting Interface

      cfg_err_ecrc                               : in std_logic;

      cfg_err_ur                                 : in std_logic;

      cfg_err_cpl_timeout                        : in std_logic;

      cfg_err_cpl_unexpect                       : in std_logic;

      cfg_err_cpl_abort                          : in std_logic;

      cfg_err_posted                             : in std_logic;

      cfg_err_cor                                : in std_logic;

      cfg_err_atomic_egress_blocked              : in std_logic;

      cfg_err_internal_cor                       : in std_logic;

      cfg_err_malformed                          : in std_logic;

      cfg_err_mc_blocked                         : in std_logic;

      cfg_err_poisoned                           : in std_logic;

      cfg_err_norecovery                         : in std_logic;

      cfg_err_tlp_cpl_header                     : in std_logic_vector(47 downto 0);

      cfg_err_cpl_rdy                            : out std_logic;

      cfg_err_locked                             : in std_logic;

      cfg_err_acs                                : in std_logic;

      cfg_err_internal_uncor                     : in std_logic;

      cfg_trn_pending                            : in std_logic;

      cfg_pm_halt_aspm_l0s                       : in std_logic;

      cfg_pm_halt_aspm_l1                        : in std_logic;

      cfg_pm_force_state_en                      : in std_logic;

      cfg_pm_force_state                         : std_logic_vector(1 downto 0);

      cfg_dsn                                    : std_logic_vector(63 downto 0);

     ---------------------------------------------------------------------

      -- EP Only                                                        --

     ---------------------------------------------------------------------

      cfg_interrupt                              : in std_logic;

      cfg_interrupt_rdy                          : out std_logic;

      cfg_interrupt_assert                       : in std_logic;

      cfg_interrupt_di                           : in std_logic_vector(7 downto 0);

      cfg_interrupt_do                           : out std_logic_vector(7 downto 0);

      cfg_interrupt_mmenable                     : out std_logic_vector(2 downto 0);

      cfg_interrupt_msienable                    : out std_logic;

      cfg_interrupt_msixenable                   : out std_logic;

      cfg_interrupt_msixfm                       : out std_logic;

      cfg_interrupt_stat                         : in std_logic;

      cfg_pciecap_interrupt_msgnum               : in std_logic_vector(4 downto 0);

      cfg_to_turnoff                             : out std_logic;

      cfg_turnoff_ok                             : in std_logic;

      cfg_bus_number                             : out std_logic_vector(7 downto 0);

      cfg_device_number                          : out std_logic_vector(4 downto 0);

      cfg_function_number                        : out std_logic_vector(2 downto 0);

      cfg_pm_wake                                : in std_logic;

     ---------------------------------------------------------------------

      -- RP Only                                                        --

     ---------------------------------------------------------------------

      cfg_pm_send_pme_to                         : in std_logic;

      cfg_ds_bus_number                          : in std_logic_vector(7 downto 0);

      cfg_ds_device_number                       : in std_logic_vector(4 downto 0);

      cfg_ds_function_number                     : in std_logic_vector(2 downto 0);

      cfg_mgmt_wr_rw1c_as_rw                     : in std_logic;

      cfg_msg_received                           : out std_logic;

      cfg_msg_data                               : out std_logic_vector(15 downto 0);

      cfg_bridge_serr_en                         : out std_logic;

      cfg_slot_control_electromech_il_ctl_pulse  : out std_logic;

      cfg_root_control_syserr_corr_err_en        : out std_logic;

      cfg_root_control_syserr_non_fatal_err_en   : out std_logic;

      cfg_root_control_syserr_fatal_err_en       : out std_logic;

      cfg_root_control_pme_int_en                : out std_logic;

      cfg_aer_rooterr_corr_err_reporting_en      : out std_logic;

      cfg_aer_rooterr_non_fatal_err_reporting_en : out std_logic;

      cfg_aer_rooterr_fatal_err_reporting_en     : out std_logic;

      cfg_aer_rooterr_corr_err_received          : out std_logic;

      cfg_aer_rooterr_non_fatal_err_received     : out std_logic;

      cfg_aer_rooterr_fatal_err_received         : out std_logic;

      cfg_msg_received_err_cor                   : out std_logic;

      cfg_msg_received_err_non_fatal             : out std_logic;

      cfg_msg_received_err_fatal                 : out std_logic;

      cfg_msg_received_pm_as_nak                 : out std_logic;

      cfg_msg_received_pm_pme                    : out std_logic;

      cfg_msg_received_pme_to_ack                : out std_logic;

      cfg_msg_received_assert_int_a              : out std_logic;

      cfg_msg_received_assert_int_b              : out std_logic;

      cfg_msg_received_assert_int_c              : out std_logic;

      cfg_msg_received_assert_int_d              : out std_logic;