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-------------------------------------------------------------------------------
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--
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-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
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--
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-- This file contains confidential and proprietary information
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-- of Xilinx, Inc. and is protected under U.S. and
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-- international copyright and other intellectual property
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-- laws.
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--
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-- DISCLAIMER
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-- This disclaimer is not a license and does not grant any
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-- rights to the materials distributed herewith. Except as
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-- otherwise provided in a valid license issued to you by
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-- Xilinx, and to the maximum extent permitted by applicable
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-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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-- (2) Xilinx shall not be liable (whether in contract or tort,
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-- including negligence, or under any other theory of
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-- liability) for any loss or damage of any kind or nature
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-- related to, arising under or in connection with these
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-- materials, including for any direct, or any indirect,
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-- special, incidental, or consequential loss or damage
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-- (including loss of data, profits, goodwill, or any type of
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-- loss or damage suffered as a result of any action brought
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-- by a third party) even if such damage or loss was
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-- reasonably foreseeable or Xilinx had been advised of the
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-- possibility of the same.
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--
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-- CRITICAL APPLICATIONS
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-- Xilinx products are not designed or intended to be fail-
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-- safe, or for use in any application requiring fail-safe
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-- performance, such as life-support or safety devices or
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-- systems, Class III medical devices, nuclear facilities,
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-- applications related to the deployment of airbags, or any
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-- other applications that could lead to death, personal
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-- injury, or severe property or environmental damage
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-- (individually and collectively, "Critical
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-- Applications"). Customer assumes the sole risk and
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-- liability of any use of Xilinx products in Critical
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-- Applications, subject only to applicable laws and
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-- regulations governing limitations on product liability.
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--
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-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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-- PART OF THIS FILE AT ALL TIMES.
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--
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-------------------------------------------------------------------------------
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-- Project : Series-7 Integrated Block for PCI Express
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-- File : cl_a7pcie_x4_gt_rx_valid_filter_7x.vhd
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-- Version : 1.11
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---- Description: GTX module for 7-series Integrated PCIe Block
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----
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----
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----
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----------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_misc.all;
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use ieee.std_logic_unsigned.all;
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entity cl_a7pcie_x4_gt_rx_valid_filter_7x is
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generic (
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CLK_COR_MIN_LAT : integer := 28;
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TCQ : integer := 1
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);
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port (
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USER_RXCHARISK : out std_logic_vector( 1 downto 0);
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USER_RXDATA : out std_logic_vector(15 downto 0);
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USER_RXVALID : out std_logic;
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USER_RXELECIDLE : out std_logic;
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USER_RX_STATUS : out std_logic_vector( 2 downto 0);
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USER_RX_PHY_STATUS : out std_logic;
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GT_RXCHARISK : in std_logic_vector( 1 downto 0);
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GT_RXDATA : in std_logic_vector(15 downto 0);
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GT_RXVALID : in std_logic;
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GT_RXELECIDLE : in std_logic;
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GT_RX_STATUS : in std_logic_vector( 2 downto 0);
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GT_RX_PHY_STATUS : in std_logic;
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PLM_IN_L0 : in std_logic;
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PLM_IN_RS : in std_logic;
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USER_CLK : in std_logic;
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RESET : in std_logic
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);
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end cl_a7pcie_x4_gt_rx_valid_filter_7x;
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architecture pcie_7x of cl_a7pcie_x4_gt_rx_valid_filter_7x is
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constant EIOS_DET_IDL : std_logic_vector(4 downto 0) := "00001";
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constant EIOS_DET_NO_STR0 : std_logic_vector(4 downto 0) := "00010";
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constant EIOS_DET_STR0 : std_logic_vector(4 downto 0) := "00100";
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constant EIOS_DET_STR1 : std_logic_vector(4 downto 0) := "01000";
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constant EIOS_DET_DONE : std_logic_vector(4 downto 0) := "10000";
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constant EIOS_COM : std_logic_vector(7 downto 0) := X"BC";
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constant EIOS_IDL : std_logic_vector(7 downto 0) := X"7C";
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constant FTSOS_COM : std_logic_vector(7 downto 0) := X"BC";
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constant FTSOS_FTS : std_logic_vector(7 downto 0) := X"3C";
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signal reg_state_eios_det : std_logic_vector(4 downto 0):= (others => '0');
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signal state_eios_det : std_logic_vector(4 downto 0):= (others => '0');
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signal reg_eios_detected : std_logic:= '0';
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signal eios_detected : std_logic:= '0';
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signal reg_symbol_after_eios : std_logic:= '0';
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signal symbol_after_eios : std_logic:= '0';
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constant USER_RXVLD_IDL : std_logic_vector(3 downto 0) := "0001";
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constant USER_RXVLD_EI : std_logic_vector(3 downto 0) := "0010";
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constant USER_RXVLD_EI_DB0 : std_logic_vector(3 downto 0) := "0100";
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constant USER_RXVLD_EI_DB1 : std_logic_vector(3 downto 0) := "1000";
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signal gt_rxcharisk_q : std_logic_vector( 1 downto 0):= (others => '0');
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signal gt_rxdata_q : std_logic_vector(15 downto 0):= (others => '0');
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signal gt_rxvalid_q : std_logic:= '0';
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signal gt_rxelecidle_q : std_logic:= '0';
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signal gt_rx_status_q : std_logic_vector( 2 downto 0):= (others => '0');
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signal gt_rx_phy_status_q : std_logic:= '0';
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signal gt_rx_is_skp0_q : std_logic:= '0';
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signal gt_rx_is_skp1_q : std_logic:= '0';
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begin
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-- EIOS detector
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process(USER_CLK)
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begin
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if rising_edge(USER_CLK) then
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if (RESET = '1') then
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reg_eios_detected <= '0' after (TCQ)*1 ps;
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reg_state_eios_det <= EIOS_DET_IDL after (TCQ)*1 ps ;
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reg_symbol_after_eios <= '0' after (TCQ)*1 ps ;
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gt_rxcharisk_q <= "00" after (TCQ)*1 ps ;
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gt_rxdata_q <= X"0000" after (TCQ)*1 ps ;
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gt_rxvalid_q <= '0' after (TCQ)*1 ps ;
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gt_rxelecidle_q <= '0' after (TCQ)*1 ps ;
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gt_rx_status_q <= "000" after (TCQ)*1 ps ;
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gt_rx_phy_status_q <= '0' after (TCQ)*1 ps ;
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gt_rx_is_skp0_q <= '0' after (TCQ)*1 ps ;
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gt_rx_is_skp1_q <= '0' after (TCQ)*1 ps ;
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else
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reg_eios_detected <= '0' after (TCQ)*1 ps ;
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reg_symbol_after_eios <= '0' after (TCQ)*1 ps ;
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gt_rxcharisk_q <= GT_RXCHARISK after (TCQ)*1 ps ;
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gt_rxelecidle_q <= GT_RXELECIDLE after (TCQ)*1 ps ;
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gt_rxdata_q <= GT_RXDATA after (TCQ)*1 ps ;
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gt_rx_phy_status_q <= GT_RX_PHY_STATUS after (TCQ)*1 ps ;
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--De-assert rx_valid signal when EIOS is detected on RXDATA
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if((reg_state_eios_det = "10000") and (PLM_IN_L0 = '1')) then
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gt_rxvalid_q <= '0' after (TCQ)*1 ps;
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elsif (GT_RXELECIDLE = '1' and gt_rxvalid_q = '0') then
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gt_rxvalid_q <= '0' after (TCQ)*1 ps;
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else
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gt_rxvalid_q <= GT_RXVALID;
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end if;
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if (gt_rxvalid_q = '1') then
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gt_rx_status_q <= GT_RX_STATUS after (TCQ)*1 ps ;
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elsif (gt_rxvalid_q = '0' and PLM_IN_L0 = '1') then
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gt_rx_status_q <= "000" after (TCQ)*1 ps;
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else
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gt_rx_status_q <= GT_RX_STATUS after (TCQ)*1 ps ;
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end if;
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if ((GT_RXCHARISK(0) = '1') and (GT_RXDATA(7 downto 0) = FTSOS_FTS)) then
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gt_rx_is_skp0_q <= '1' after (TCQ)*1 ps ;
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else
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gt_rx_is_skp0_q <= '0' after (TCQ)*1 ps ;
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end if;
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if ((GT_RXCHARISK(1) = '1') and (GT_RXDATA(15 downto 8) = FTSOS_FTS)) then
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gt_rx_is_skp1_q <= '1' after (TCQ)*1 ps ;
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else
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gt_rx_is_skp1_q <= '0' after (TCQ)*1 ps ;
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end if;
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case ( state_eios_det ) is
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when EIOS_DET_IDL =>
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if ((gt_rxcharisk_q(0) = '1' ) and (gt_rxdata_q( 7 downto 0) = EIOS_COM) and
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(gt_rxcharisk_q(1) = '1' ) and (gt_rxdata_q(15 downto 8) = EIOS_IDL)) then
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reg_state_eios_det <= EIOS_DET_NO_STR0 after (TCQ)*1 ps ;
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reg_eios_detected <= '1' after (TCQ)*1 ps;
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--gt_rxvalid_q <= '0' after (TCQ)*1 ps;
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elsif ((gt_rxcharisk_q(1) = '1' ) and (gt_rxdata_q(15 downto 8) = EIOS_COM)) then
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reg_state_eios_det <= EIOS_DET_STR0 after (TCQ)*1 ps ;
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else
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reg_state_eios_det <= EIOS_DET_IDL after (TCQ)*1 ps ;
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end if;
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when EIOS_DET_NO_STR0 =>
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if ((gt_rxcharisk_q(0) = '1' and (gt_rxdata_q( 7 downto 0) = EIOS_IDL)) and
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(gt_rxcharisk_q(1) = '1' and (gt_rxdata_q(15 downto 8) = EIOS_IDL))) then
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reg_state_eios_det <= EIOS_DET_DONE after (TCQ)*1 ps ;
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gt_rxvalid_q <= '0' after (TCQ)*1 ps ;
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elsif (gt_rxcharisk_q(0) = '1' and (gt_rxdata_q(7 downto 0) = EIOS_IDL)) then
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reg_state_eios_det <= EIOS_DET_DONE after (TCQ)*1 ps ;
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gt_rxvalid_q <= '0' after (TCQ)*1 ps;
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else
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reg_state_eios_det <= EIOS_DET_IDL after (TCQ)*1 ps ;
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end if;
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when EIOS_DET_STR0 =>
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if ((gt_rxcharisk_q(0) = '1' and (gt_rxdata_q( 7 downto 0) = EIOS_IDL)) and
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(gt_rxcharisk_q(1) = '1' and (gt_rxdata_q(15 downto 8) = EIOS_IDL))) then
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reg_state_eios_det <= EIOS_DET_STR1 after (TCQ)*1 ps ;
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reg_eios_detected <= '1' after (TCQ)*1 ps;
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gt_rxvalid_q <= '0' after (TCQ)*1 ps;
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reg_symbol_after_eios <= '1' after (TCQ)*1 ps;
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else
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reg_state_eios_det <= EIOS_DET_IDL after (TCQ)*1 ps ;
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end if;
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when EIOS_DET_STR1 =>
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if ((gt_rxcharisk_q(0) = '1' ) and (gt_rxdata_q(7 downto 0) = EIOS_IDL)) then
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reg_state_eios_det <= EIOS_DET_DONE after (TCQ)*1 ps ;
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gt_rxvalid_q <= '0' after (TCQ)*1 ps ;
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else
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reg_state_eios_det <= EIOS_DET_IDL after (TCQ)*1 ps ;
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end if;
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when EIOS_DET_DONE =>
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reg_state_eios_det <= EIOS_DET_IDL after (TCQ)*1 ps ;
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when others =>
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reg_state_eios_det <= EIOS_DET_IDL after (TCQ)*1 ps ;
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end case;
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end if;
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end if;
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end process;
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state_eios_det <= reg_state_eios_det;
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eios_detected <= reg_eios_detected;
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symbol_after_eios <= reg_symbol_after_eios;
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-- rx_elec_idle_delay : SRL16E
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-- generic map (
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-- INIT => X"0000"
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-- )
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-- port map (
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-- Q => USER_RXELECIDLE,
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-- D => gt_rxelecidle_q,
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-- CLK => USER_CLK,
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-- CE => '1',
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-- A3 => '1',
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-- A2 => '1',
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-- A1 => '1',
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-- A0 => '1'
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-- );
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USER_RXVALID <= gt_rxvalid_q;
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USER_RXCHARISK(0) <= gt_rxcharisk_q(0) when (gt_rxvalid_q = '1') else '0';
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USER_RXCHARISK(1) <= gt_rxcharisk_q(1) when (gt_rxvalid_q = '1' and symbol_after_eios = '0') else '0';
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USER_RXDATA(7 downto 0) <= gt_rxdata_q(7 downto 0);
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USER_RXDATA(15 downto 8) <= gt_rxdata_q(15 downto 8);
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USER_RX_STATUS <= gt_rx_status_q;
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USER_RX_PHY_STATUS <= gt_rx_phy_status_q;
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USER_RXELECIDLE <= gt_rxelecidle_q;
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end pcie_7x;
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