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//-----------------------------------------------------------------------------
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//
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// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//-----------------------------------------------------------------------------
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// Project : Series-7 Integrated Block for PCI Express
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// File : cl_a7pcie_x4_gtp_pipe_reset.v
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dsmv |
// Version : 1.11
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dsmv |
//------------------------------------------------------------------------------
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// Filename : gtp_pipe_reset.v
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// Description : GTP PIPE Reset Module for 7 Series Transceiver
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// Version : 19.0
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//------------------------------------------------------------------------------
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`timescale 1ns / 1ps
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//---------- PIPE Reset Module -------------------------------------------------
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module cl_a7pcie_x4_gtp_pipe_reset #
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(
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//---------- Global ------------------------------------
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parameter PCIE_SIM_SPEEDUP = "FALSE", // PCIe sim speedup
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parameter PCIE_LANE = 1, // PCIe number of lanes
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//---------- Local -------------------------------------
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parameter CFG_WAIT_MAX = 6'd63, // Configuration wait max
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parameter BYPASS_RXCDRLOCK = 1 // Bypass RXCDRLOCK
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)
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(
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//---------- Input -------------------------------------
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input RST_CLK,
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input RST_RXUSRCLK,
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input RST_DCLK,
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input RST_RST_N,
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input [PCIE_LANE-1:0] RST_DRP_DONE,
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input [PCIE_LANE-1:0] RST_RXPMARESETDONE,
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input RST_PLLLOCK,
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input [PCIE_LANE-1:0] RST_RATE_IDLE,
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input [PCIE_LANE-1:0] RST_RXCDRLOCK,
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input RST_MMCM_LOCK,
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input [PCIE_LANE-1:0] RST_RESETDONE,
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input [PCIE_LANE-1:0] RST_PHYSTATUS,
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input [PCIE_LANE-1:0] RST_TXSYNC_DONE,
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//---------- Output ------------------------------------
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output RST_CPLLRESET,
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output RST_CPLLPD,
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dsmv |
output reg RST_DRP_START,
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output reg RST_DRP_X16,
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dsmv |
output RST_RXUSRCLK_RESET,
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output RST_DCLK_RESET,
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output RST_GTRESET,
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output RST_USERRDY,
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output RST_TXSYNC_START,
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output RST_IDLE,
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output [ 4:0] RST_FSM
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);
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//---------- Input Register ----------------------------
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dsmv |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] drp_done_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rxpmaresetdone_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg plllock_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rate_idle_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rxcdrlock_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] resetdone_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] phystatus_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] txsync_done_reg1;
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dsmv |
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dsmv |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] drp_done_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rxpmaresetdone_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg plllock_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rate_idle_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rxcdrlock_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] resetdone_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] phystatus_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] txsync_done_reg2;
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dsmv |
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//---------- Internal Signal ---------------------------
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reg [ 5:0] cfg_wait_cnt = 6'd0;
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//---------- Output Register ---------------------------
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reg pllreset = 1'd0;
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reg pllpd = 1'd0;
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reg rxusrclk_rst_reg1 = 1'd0;
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reg rxusrclk_rst_reg2 = 1'd0;
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reg dclk_rst_reg1 = 1'd0;
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reg dclk_rst_reg2 = 1'd0;
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reg gtreset = 1'd0;
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reg userrdy = 1'd0;
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dsmv |
reg [ 4:0] fsm = 5'h1;
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dsmv |
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//---------- FSM ---------------------------------------
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dsmv |
localparam FSM_IDLE = 5'h0;
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localparam FSM_CFG_WAIT = 5'h1;
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localparam FSM_PLLRESET = 5'h2;
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localparam FSM_DRP_X16_START = 5'h3;
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localparam FSM_DRP_X16_DONE = 5'h4;
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localparam FSM_PLLLOCK = 5'h5;
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localparam FSM_GTRESET = 5'h6;
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localparam FSM_RXPMARESETDONE_1 = 5'h7;
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localparam FSM_RXPMARESETDONE_2 = 5'h8;
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localparam FSM_DRP_X20_START = 5'h9;
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localparam FSM_DRP_X20_DONE = 5'hA;
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localparam FSM_MMCM_LOCK = 5'hB;
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localparam FSM_RESETDONE = 5'hC;
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localparam FSM_TXSYNC_START = 5'hD;
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localparam FSM_TXSYNC_DONE = 5'hE;
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dsmv |
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//---------- Input FF ----------------------------------------------------------
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always @ (posedge RST_CLK)
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begin
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if (!RST_RST_N)
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begin
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//---------- 1st Stage FF --------------------------
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drp_done_reg1 <= {PCIE_LANE{1'd0}};
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rxpmaresetdone_reg1 <= {PCIE_LANE{1'd0}};
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plllock_reg1 <= 1'd0;
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rate_idle_reg1 <= {PCIE_LANE{1'd0}};
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rxcdrlock_reg1 <= {PCIE_LANE{1'd0}};
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mmcm_lock_reg1 <= 1'd0;
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resetdone_reg1 <= {PCIE_LANE{1'd0}};
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phystatus_reg1 <= {PCIE_LANE{1'd0}};
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txsync_done_reg1 <= {PCIE_LANE{1'd0}};
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//---------- 2nd Stage FF --------------------------
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drp_done_reg2 <= {PCIE_LANE{1'd0}};
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rxpmaresetdone_reg2 <= {PCIE_LANE{1'd0}};
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plllock_reg2 <= 1'd0;
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rate_idle_reg2 <= {PCIE_LANE{1'd0}};
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rxcdrlock_reg2 <= {PCIE_LANE{1'd0}};
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mmcm_lock_reg2 <= 1'd0;
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resetdone_reg2 <= {PCIE_LANE{1'd0}};
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phystatus_reg2 <= {PCIE_LANE{1'd0}};
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txsync_done_reg2 <= {PCIE_LANE{1'd0}};
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end
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else
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begin
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//---------- 1st Stage FF --------------------------
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drp_done_reg1 <= RST_DRP_DONE;
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rxpmaresetdone_reg1 <= RST_RXPMARESETDONE;
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plllock_reg1 <= RST_PLLLOCK;
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rate_idle_reg1 <= RST_RATE_IDLE;
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rxcdrlock_reg1 <= RST_RXCDRLOCK;
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mmcm_lock_reg1 <= RST_MMCM_LOCK;
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resetdone_reg1 <= RST_RESETDONE;
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phystatus_reg1 <= RST_PHYSTATUS;
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txsync_done_reg1 <= RST_TXSYNC_DONE;
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//---------- 2nd Stage FF --------------------------
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drp_done_reg2 <= drp_done_reg1;
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rxpmaresetdone_reg2 <= rxpmaresetdone_reg1;
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plllock_reg2 <= plllock_reg1;
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rate_idle_reg2 <= rate_idle_reg1;
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rxcdrlock_reg2 <= rxcdrlock_reg1;
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mmcm_lock_reg2 <= mmcm_lock_reg1;
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resetdone_reg2 <= resetdone_reg1;
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phystatus_reg2 <= phystatus_reg1;
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txsync_done_reg2 <= txsync_done_reg1;
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end
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end
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//---------- Configuration Reset Wait Counter ----------------------------------
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always @ (posedge RST_CLK)
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begin
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if (!RST_RST_N)
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cfg_wait_cnt <= 6'd0;
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else
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//---------- Increment Configuration Reset Wait Counter
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if ((fsm == FSM_CFG_WAIT) && (cfg_wait_cnt < CFG_WAIT_MAX))
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cfg_wait_cnt <= cfg_wait_cnt + 6'd1;
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//---------- Hold Configuration Reset Wait Counter -
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else if ((fsm == FSM_CFG_WAIT) && (cfg_wait_cnt == CFG_WAIT_MAX))
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cfg_wait_cnt <= cfg_wait_cnt;
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//---------- Reset Configuration Reset Wait Counter
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else
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cfg_wait_cnt <= 6'd0;
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end
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241 |
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242 |
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243 |
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//---------- PIPE Reset FSM ----------------------------------------------------
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always @ (posedge RST_CLK)
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begin
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247 |
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if (!RST_RST_N)
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begin
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249 |
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fsm <= FSM_CFG_WAIT;
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pllreset <= 1'd0;
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pllpd <= 1'd0;
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gtreset <= 1'd0;
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userrdy <= 1'd0;
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end
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else
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begin
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257 |
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258 |
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case (fsm)
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259 |
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260 |
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//---------- Idle State ----------------------------
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261 |
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FSM_IDLE :
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262 |
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begin
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264 |
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if (!RST_RST_N)
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begin
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266 |
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fsm <= FSM_CFG_WAIT;
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267 |
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pllreset <= 1'd0;
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268 |
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pllpd <= 1'd0;
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269 |
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gtreset <= 1'd0;
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270 |
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userrdy <= 1'd0;
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end
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else
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273 |
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begin
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274 |
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fsm <= FSM_IDLE;
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pllreset <= pllreset;
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pllpd <= pllpd;
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gtreset <= gtreset;
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userrdy <= userrdy;
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end
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end
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281 |
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282 |
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//---------- Wait for Configuration Reset Delay ---
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283 |
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FSM_CFG_WAIT :
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284 |
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285 |
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begin
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286 |
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fsm <= ((cfg_wait_cnt == CFG_WAIT_MAX) ? FSM_PLLRESET : FSM_CFG_WAIT);
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287 |
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pllreset <= pllreset;
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pllpd <= pllpd;
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gtreset <= gtreset;
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userrdy <= userrdy;
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end
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293 |
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//---------- Hold PLL and GTP Channel in Reset ----
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294 |
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FSM_PLLRESET :
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295 |
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296 |
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begin
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297 |
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fsm <= (((~plllock_reg2) && (&(~resetdone_reg2))) ? FSM_DRP_X16_START : FSM_PLLRESET);
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298 |
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pllreset <= 1'd1;
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pllpd <= pllpd;
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gtreset <= 1'd1;
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userrdy <= userrdy;
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end
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303 |
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304 |
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//---------- Start DRP x16 -------------------------
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305 |
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FSM_DRP_X16_START :
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306 |
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307 |
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begin
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308 |
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fsm <= &(~drp_done_reg2) ? FSM_DRP_X16_DONE : FSM_DRP_X16_START;
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pllreset <= pllreset;
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pllpd <= pllpd;
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gtreset <= gtreset;
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userrdy <= userrdy;
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end
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314 |
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315 |
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//---------- Wait for DRP x16 Done -----------------
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316 |
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FSM_DRP_X16_DONE :
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317 |
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318 |
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begin
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319 |
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fsm <= (&drp_done_reg2) ? FSM_PLLLOCK : FSM_DRP_X16_DONE;
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320 |
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pllreset <= pllreset;
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pllpd <= pllpd;
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322 |
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gtreset <= gtreset;
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323 |
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userrdy <= userrdy;
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324 |
|
|
end
|
325 |
|
|
|
326 |
|
|
//---------- Wait for PLL Lock --------------------
|
327 |
|
|
FSM_PLLLOCK :
|
328 |
|
|
|
329 |
|
|
begin
|
330 |
|
|
fsm <= (plllock_reg2 ? FSM_GTRESET : FSM_PLLLOCK);
|
331 |
|
|
pllreset <= 1'd0;
|
332 |
|
|
pllpd <= pllpd;
|
333 |
|
|
gtreset <= gtreset;
|
334 |
|
|
userrdy <= userrdy;
|
335 |
|
|
end
|
336 |
|
|
|
337 |
|
|
//---------- Release GTRESET -----------------------
|
338 |
|
|
FSM_GTRESET :
|
339 |
|
|
|
340 |
|
|
begin
|
341 |
|
|
fsm <= FSM_RXPMARESETDONE_1;
|
342 |
|
|
pllreset <= pllreset;
|
343 |
|
|
pllpd <= pllpd;
|
344 |
|
|
gtreset <= 1'b0;
|
345 |
|
|
userrdy <= userrdy;
|
346 |
|
|
end
|
347 |
|
|
|
348 |
|
|
//---------- Wait for RXPMARESETDONE Assertion -----
|
349 |
|
|
FSM_RXPMARESETDONE_1 :
|
350 |
|
|
|
351 |
|
|
begin
|
352 |
|
|
fsm <= (&rxpmaresetdone_reg2 || (PCIE_SIM_SPEEDUP == "TRUE")) ? FSM_RXPMARESETDONE_2 : FSM_RXPMARESETDONE_1;
|
353 |
|
|
pllreset <= pllreset;
|
354 |
|
|
pllpd <= pllpd;
|
355 |
|
|
gtreset <= gtreset;
|
356 |
|
|
userrdy <= userrdy;
|
357 |
|
|
end
|
358 |
|
|
|
359 |
|
|
//---------- Wait for RXPMARESETDONE De-assertion --
|
360 |
|
|
FSM_RXPMARESETDONE_2 :
|
361 |
|
|
|
362 |
|
|
begin
|
363 |
|
|
fsm <= (&(~rxpmaresetdone_reg2) || (PCIE_SIM_SPEEDUP == "TRUE")) ? FSM_DRP_X20_START : FSM_RXPMARESETDONE_2;
|
364 |
|
|
pllreset <= pllreset;
|
365 |
|
|
pllpd <= pllpd;
|
366 |
|
|
gtreset <= gtreset;
|
367 |
|
|
userrdy <= userrdy;
|
368 |
|
|
end
|
369 |
|
|
|
370 |
|
|
//---------- Start DRP x20 -------------------------
|
371 |
|
|
FSM_DRP_X20_START :
|
372 |
|
|
|
373 |
|
|
begin
|
374 |
|
|
fsm <= &(~drp_done_reg2) ? FSM_DRP_X20_DONE : FSM_DRP_X20_START;
|
375 |
|
|
pllreset <= pllreset;
|
376 |
|
|
pllpd <= pllpd;
|
377 |
|
|
gtreset <= gtreset;
|
378 |
|
|
userrdy <= userrdy;
|
379 |
|
|
end
|
380 |
|
|
|
381 |
|
|
//---------- Wait for DRP x20 Done -----------------
|
382 |
|
|
FSM_DRP_X20_DONE :
|
383 |
|
|
|
384 |
|
|
begin
|
385 |
|
|
fsm <= (&drp_done_reg2) ? FSM_MMCM_LOCK : FSM_DRP_X20_DONE;
|
386 |
|
|
pllreset <= pllreset;
|
387 |
|
|
pllpd <= pllpd;
|
388 |
|
|
gtreset <= gtreset;
|
389 |
|
|
userrdy <= userrdy;
|
390 |
|
|
end
|
391 |
|
|
|
392 |
|
|
//---------- Wait for MMCM and RX CDR Lock ---------
|
393 |
|
|
FSM_MMCM_LOCK :
|
394 |
|
|
|
395 |
|
|
begin
|
396 |
|
|
if (mmcm_lock_reg2 && (&rxcdrlock_reg2 || (BYPASS_RXCDRLOCK == 1)))
|
397 |
|
|
begin
|
398 |
|
|
fsm <= FSM_RESETDONE;
|
399 |
|
|
pllreset <= pllreset;
|
400 |
|
|
pllpd <= pllpd;
|
401 |
|
|
gtreset <= gtreset;
|
402 |
|
|
userrdy <= 1'd1;
|
403 |
|
|
end
|
404 |
|
|
else
|
405 |
|
|
begin
|
406 |
|
|
fsm <= FSM_MMCM_LOCK;
|
407 |
|
|
pllreset <= pllreset;
|
408 |
|
|
pllpd <= pllpd;
|
409 |
|
|
gtreset <= gtreset;
|
410 |
|
|
userrdy <= 1'd0;
|
411 |
|
|
end
|
412 |
|
|
end
|
413 |
|
|
|
414 |
|
|
//---------- Wait for [TX/RX]RESETDONE and PHYSTATUS
|
415 |
|
|
FSM_RESETDONE :
|
416 |
|
|
|
417 |
|
|
begin
|
418 |
|
|
fsm <= (&resetdone_reg2 && (&(~phystatus_reg2)) ? FSM_TXSYNC_START : FSM_RESETDONE);
|
419 |
|
|
pllreset <= pllreset;
|
420 |
|
|
pllpd <= pllpd;
|
421 |
|
|
gtreset <= gtreset;
|
422 |
|
|
userrdy <= userrdy;
|
423 |
|
|
end
|
424 |
|
|
|
425 |
|
|
//---------- Start TX Sync -------------------------
|
426 |
|
|
FSM_TXSYNC_START :
|
427 |
|
|
|
428 |
|
|
begin
|
429 |
|
|
fsm <= (&(~txsync_done_reg2) ? FSM_TXSYNC_DONE : FSM_TXSYNC_START);
|
430 |
|
|
pllreset <= pllreset;
|
431 |
|
|
pllpd <= pllpd;
|
432 |
|
|
gtreset <= gtreset;
|
433 |
|
|
userrdy <= userrdy;
|
434 |
|
|
end
|
435 |
|
|
|
436 |
|
|
//---------- Wait for TX Sync Done -----------------
|
437 |
|
|
FSM_TXSYNC_DONE :
|
438 |
|
|
|
439 |
|
|
begin
|
440 |
|
|
fsm <= (&txsync_done_reg2 ? FSM_IDLE : FSM_TXSYNC_DONE);
|
441 |
|
|
pllreset <= pllreset;
|
442 |
|
|
pllpd <= pllpd;
|
443 |
|
|
gtreset <= gtreset;
|
444 |
|
|
userrdy <= userrdy;
|
445 |
|
|
end
|
446 |
|
|
|
447 |
|
|
//---------- Default State -------------------------
|
448 |
|
|
default :
|
449 |
|
|
|
450 |
|
|
begin
|
451 |
|
|
fsm <= FSM_CFG_WAIT;
|
452 |
|
|
pllreset <= 1'd0;
|
453 |
|
|
pllpd <= 1'd0;
|
454 |
|
|
gtreset <= 1'd0;
|
455 |
|
|
userrdy <= 1'd0;
|
456 |
|
|
end
|
457 |
|
|
|
458 |
|
|
endcase
|
459 |
|
|
|
460 |
|
|
end
|
461 |
|
|
|
462 |
|
|
end
|
463 |
|
|
|
464 |
|
|
|
465 |
|
|
|
466 |
|
|
//---------- RXUSRCLK Reset Synchronizer ---------------------------------------
|
467 |
|
|
always @ (posedge RST_RXUSRCLK)
|
468 |
|
|
begin
|
469 |
|
|
|
470 |
|
|
if (pllreset)
|
471 |
|
|
begin
|
472 |
|
|
rxusrclk_rst_reg1 <= 1'd1;
|
473 |
|
|
rxusrclk_rst_reg2 <= 1'd1;
|
474 |
|
|
end
|
475 |
|
|
else
|
476 |
|
|
begin
|
477 |
|
|
rxusrclk_rst_reg1 <= 1'd0;
|
478 |
|
|
rxusrclk_rst_reg2 <= rxusrclk_rst_reg1;
|
479 |
|
|
end
|
480 |
|
|
|
481 |
|
|
end
|
482 |
|
|
|
483 |
|
|
//---------- DCLK Reset Synchronizer -------------------------------------------
|
484 |
|
|
always @ (posedge RST_DCLK)
|
485 |
|
|
begin
|
486 |
|
|
|
487 |
|
|
if (fsm == FSM_CFG_WAIT)
|
488 |
|
|
begin
|
489 |
|
|
dclk_rst_reg1 <= 1'd1;
|
490 |
48 |
dsmv |
dclk_rst_reg2 <= dclk_rst_reg1;
|
491 |
46 |
dsmv |
end
|
492 |
|
|
else
|
493 |
|
|
begin
|
494 |
|
|
dclk_rst_reg1 <= 1'd0;
|
495 |
|
|
dclk_rst_reg2 <= dclk_rst_reg1;
|
496 |
|
|
end
|
497 |
|
|
|
498 |
|
|
end
|
499 |
|
|
|
500 |
|
|
|
501 |
|
|
|
502 |
|
|
//---------- PIPE Reset Output -------------------------------------------------
|
503 |
|
|
assign RST_CPLLRESET = pllreset;
|
504 |
|
|
assign RST_CPLLPD = pllpd;
|
505 |
|
|
assign RST_RXUSRCLK_RESET = rxusrclk_rst_reg2;
|
506 |
|
|
assign RST_DCLK_RESET = dclk_rst_reg2;
|
507 |
|
|
assign RST_GTRESET = gtreset;
|
508 |
|
|
assign RST_USERRDY = userrdy;
|
509 |
|
|
assign RST_TXSYNC_START = (fsm == FSM_TXSYNC_START);
|
510 |
|
|
assign RST_IDLE = (fsm == FSM_IDLE);
|
511 |
48 |
dsmv |
assign RST_FSM = fsm;
|
512 |
46 |
dsmv |
|
513 |
|
|
|
514 |
|
|
|
515 |
48 |
dsmv |
//--------------------------------------------------------------------------------------------------
|
516 |
|
|
// Register Output
|
517 |
|
|
//--------------------------------------------------------------------------------------------------
|
518 |
|
|
always @ (posedge RST_CLK)
|
519 |
|
|
begin
|
520 |
|
|
|
521 |
|
|
if (!RST_RST_N)
|
522 |
|
|
begin
|
523 |
|
|
RST_DRP_START <= 1'd0;
|
524 |
|
|
RST_DRP_X16 <= 1'd0;
|
525 |
|
|
end
|
526 |
|
|
else
|
527 |
|
|
begin
|
528 |
|
|
RST_DRP_START <= (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X20_START);
|
529 |
|
|
RST_DRP_X16 <= (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X16_DONE);
|
530 |
|
|
end
|
531 |
|
|
|
532 |
|
|
end
|
533 |
|
|
|
534 |
|
|
|
535 |
|
|
|
536 |
46 |
dsmv |
endmodule
|