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-------------------------------------------------------------------------------
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--
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-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
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--
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-- This file contains confidential and proprietary information
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-- of Xilinx, Inc. and is protected under U.S. and
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-- international copyright and other intellectual property
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-- laws.
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--
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-- DISCLAIMER
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-- This disclaimer is not a license and does not grant any
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-- rights to the materials distributed herewith. Except as
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-- otherwise provided in a valid license issued to you by
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-- Xilinx, and to the maximum extent permitted by applicable
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-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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-- (2) Xilinx shall not be liable (whether in contract or tort,
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-- including negligence, or under any other theory of
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-- liability) for any loss or damage of any kind or nature
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-- related to, arising under or in connection with these
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-- materials, including for any direct, or any indirect,
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-- special, incidental, or consequential loss or damage
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-- (including loss of data, profits, goodwill, or any type of
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-- loss or damage suffered as a result of any action brought
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-- by a third party) even if such damage or loss was
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-- reasonably foreseeable or Xilinx had been advised of the
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-- possibility of the same.
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--
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-- CRITICAL APPLICATIONS
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-- Xilinx products are not designed or intended to be fail-
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-- safe, or for use in any application requiring fail-safe
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-- performance, such as life-support or safety devices or
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-- systems, Class III medical devices, nuclear facilities,
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-- applications related to the deployment of airbags, or any
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-- other applications that could lead to death, personal
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-- injury, or severe property or environmental damage
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-- (individually and collectively, "Critical
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-- Applications"). Customer assumes the sole risk and
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-- liability of any use of Xilinx products in Critical
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-- Applications, subject only to applicable laws and
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-- regulations governing limitations on product liability.
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--
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-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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-- PART OF THIS FILE AT ALL TIMES.
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--
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-------------------------------------------------------------------------------
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-- Project : Series-7 Integrated Block for PCI Express
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-- File : cl_a7pcie_x4_pcie_pipe_pipeline.vhd
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-- Version : 1.10
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-- Description: PIPE module for 7-Series PCIe Block
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--
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--
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--
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--------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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entity cl_a7pcie_x4_pcie_pipe_pipeline is
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generic (
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LINK_CAP_MAX_LINK_WIDTH_int : integer := 8;
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PIPE_PIPELINE_STAGES : integer := 0 -- 0 - 0 stages, 1 - 1 stage, 2 - 2 stages
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);
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port (
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-- Pipe Per-Link Signals
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pipe_tx_rcvr_det_i : in std_logic;
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pipe_tx_reset_i : in std_logic;
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pipe_tx_rate_i : in std_logic;
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pipe_tx_deemph_i : in std_logic;
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pipe_tx_margin_i : in std_logic_vector(2 downto 0);
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pipe_tx_swing_i : in std_logic;
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pipe_tx_rcvr_det_o : out std_logic;
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pipe_tx_reset_o : out std_logic;
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pipe_tx_rate_o : out std_logic;
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pipe_tx_deemph_o : out std_logic;
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pipe_tx_margin_o : out std_logic_vector(2 downto 0);
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pipe_tx_swing_o : out std_logic;
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-- Pipe Per-Lane Signals - Lane 0
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pipe_rx0_char_is_k_o : out std_logic_vector(1 downto 0);
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pipe_rx0_data_o : out std_logic_vector(15 downto 0);
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pipe_rx0_valid_o : out std_logic;
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pipe_rx0_chanisaligned_o : out std_logic;
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pipe_rx0_status_o : out std_logic_vector(2 downto 0);
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pipe_rx0_phy_status_o : out std_logic;
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pipe_rx0_elec_idle_o : out std_logic;
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pipe_rx0_polarity_i : in std_logic;
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pipe_tx0_compliance_i : in std_logic;
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pipe_tx0_char_is_k_i : in std_logic_vector(1 downto 0);
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pipe_tx0_data_i : in std_logic_vector(15 downto 0);
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pipe_tx0_elec_idle_i : in std_logic;
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pipe_tx0_powerdown_i : in std_logic_vector(1 downto 0);
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pipe_rx0_char_is_k_i : in std_logic_vector(1 downto 0);
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pipe_rx0_data_i : in std_logic_vector(15 downto 0);
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pipe_rx0_valid_i : in std_logic;
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pipe_rx0_chanisaligned_i : in std_logic;
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pipe_rx0_status_i : in std_logic_vector(2 downto 0);
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pipe_rx0_phy_status_i : in std_logic;
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pipe_rx0_elec_idle_i : in std_logic;
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pipe_rx0_polarity_o : out std_logic;
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pipe_tx0_compliance_o : out std_logic;
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pipe_tx0_char_is_k_o : out std_logic_vector(1 downto 0);
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pipe_tx0_data_o : out std_logic_vector(15 downto 0);
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pipe_tx0_elec_idle_o : out std_logic;
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pipe_tx0_powerdown_o : out std_logic_vector(1 downto 0);
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-- Pipe Per-Lane Signals - Lane 1
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pipe_rx1_char_is_k_o : out std_logic_vector(1 downto 0);
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pipe_rx1_data_o : out std_logic_vector(15 downto 0);
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pipe_rx1_valid_o : out std_logic;
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pipe_rx1_chanisaligned_o : out std_logic;
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pipe_rx1_status_o : out std_logic_vector(2 downto 0);
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pipe_rx1_phy_status_o : out std_logic;
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pipe_rx1_elec_idle_o : out std_logic;
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pipe_rx1_polarity_i : in std_logic;
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pipe_tx1_compliance_i : in std_logic;
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pipe_tx1_char_is_k_i : in std_logic_vector(1 downto 0);
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pipe_tx1_data_i : in std_logic_vector(15 downto 0);
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pipe_tx1_elec_idle_i : in std_logic;
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pipe_tx1_powerdown_i : in std_logic_vector(1 downto 0);
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pipe_rx1_char_is_k_i : in std_logic_vector(1 downto 0);
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pipe_rx1_data_i : in std_logic_vector(15 downto 0);
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pipe_rx1_valid_i : in std_logic;
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pipe_rx1_chanisaligned_i : in std_logic;
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pipe_rx1_status_i : in std_logic_vector(2 downto 0);
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pipe_rx1_phy_status_i : in std_logic;
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pipe_rx1_elec_idle_i : in std_logic;
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pipe_rx1_polarity_o : out std_logic;
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pipe_tx1_compliance_o : out std_logic;
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pipe_tx1_char_is_k_o : out std_logic_vector(1 downto 0);
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pipe_tx1_data_o : out std_logic_vector(15 downto 0);
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pipe_tx1_elec_idle_o : out std_logic;
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pipe_tx1_powerdown_o : out std_logic_vector(1 downto 0);
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-- Pipe Per-Lane Signals - Lane 2
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pipe_rx2_char_is_k_o : out std_logic_vector(1 downto 0);
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pipe_rx2_data_o : out std_logic_vector(15 downto 0);
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pipe_rx2_valid_o : out std_logic;
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pipe_rx2_chanisaligned_o : out std_logic;
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pipe_rx2_status_o : out std_logic_vector(2 downto 0);
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pipe_rx2_phy_status_o : out std_logic;
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pipe_rx2_elec_idle_o : out std_logic;
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pipe_rx2_polarity_i : in std_logic;
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pipe_tx2_compliance_i : in std_logic;
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pipe_tx2_char_is_k_i : in std_logic_vector(1 downto 0);
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pipe_tx2_data_i : in std_logic_vector(15 downto 0);
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pipe_tx2_elec_idle_i : in std_logic;
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pipe_tx2_powerdown_i : in std_logic_vector(1 downto 0);
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pipe_rx2_char_is_k_i : in std_logic_vector(1 downto 0);
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pipe_rx2_data_i : in std_logic_vector(15 downto 0);
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pipe_rx2_valid_i : in std_logic;
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pipe_rx2_chanisaligned_i : in std_logic;
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pipe_rx2_status_i : in std_logic_vector(2 downto 0);
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pipe_rx2_phy_status_i : in std_logic;
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pipe_rx2_elec_idle_i : in std_logic;
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pipe_rx2_polarity_o : out std_logic;
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pipe_tx2_compliance_o : out std_logic;
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pipe_tx2_char_is_k_o : out std_logic_vector(1 downto 0);
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pipe_tx2_data_o : out std_logic_vector(15 downto 0);
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pipe_tx2_elec_idle_o : out std_logic;
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pipe_tx2_powerdown_o : out std_logic_vector(1 downto 0);
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-- Pipe Per-Lane Signals - Lane 3
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pipe_rx3_char_is_k_o : out std_logic_vector(1 downto 0);
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pipe_rx3_data_o : out std_logic_vector(15 downto 0);
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pipe_rx3_valid_o : out std_logic;
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pipe_rx3_chanisaligned_o : out std_logic;
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pipe_rx3_status_o : out std_logic_vector(2 downto 0);
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pipe_rx3_phy_status_o : out std_logic;
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pipe_rx3_elec_idle_o : out std_logic;
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pipe_rx3_polarity_i : in std_logic;
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pipe_tx3_compliance_i : in std_logic;
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pipe_tx3_char_is_k_i : in std_logic_vector(1 downto 0);
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pipe_tx3_data_i : in std_logic_vector(15 downto 0);
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pipe_tx3_elec_idle_i : in std_logic;
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pipe_tx3_powerdown_i : in std_logic_vector(1 downto 0);
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pipe_rx3_char_is_k_i : in std_logic_vector(1 downto 0);
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pipe_rx3_data_i : in std_logic_vector(15 downto 0);
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pipe_rx3_valid_i : in std_logic;
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pipe_rx3_chanisaligned_i : in std_logic;
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pipe_rx3_status_i : in std_logic_vector(2 downto 0);
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pipe_rx3_phy_status_i : in std_logic;
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pipe_rx3_elec_idle_i : in std_logic;
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pipe_rx3_polarity_o : out std_logic;
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pipe_tx3_compliance_o : out std_logic;
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pipe_tx3_char_is_k_o : out std_logic_vector(1 downto 0);
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pipe_tx3_data_o : out std_logic_vector(15 downto 0);
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pipe_tx3_elec_idle_o : out std_logic;
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pipe_tx3_powerdown_o : out std_logic_vector(1 downto 0);
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-- Pipe Per-Lane Signals - Lane 4
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pipe_rx4_char_is_k_o : out std_logic_vector(1 downto 0);
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pipe_rx4_data_o : out std_logic_vector(15 downto 0);
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pipe_rx4_valid_o : out std_logic;
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pipe_rx4_chanisaligned_o : out std_logic;
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pipe_rx4_status_o : out std_logic_vector(2 downto 0);
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pipe_rx4_phy_status_o : out std_logic;
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pipe_rx4_elec_idle_o : out std_logic;
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pipe_rx4_polarity_i : in std_logic;
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pipe_tx4_compliance_i : in std_logic;
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pipe_tx4_char_is_k_i : in std_logic_vector(1 downto 0);
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pipe_tx4_data_i : in std_logic_vector(15 downto 0);
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pipe_tx4_elec_idle_i : in std_logic;
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pipe_tx4_powerdown_i : in std_logic_vector(1 downto 0);
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pipe_rx4_char_is_k_i : in std_logic_vector(1 downto 0);
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pipe_rx4_data_i : in std_logic_vector(15 downto 0);
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pipe_rx4_valid_i : in std_logic;
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pipe_rx4_chanisaligned_i : in std_logic;
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pipe_rx4_status_i : in std_logic_vector(2 downto 0);
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pipe_rx4_phy_status_i : in std_logic;
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pipe_rx4_elec_idle_i : in std_logic;
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pipe_rx4_polarity_o : out std_logic;
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pipe_tx4_compliance_o : out std_logic;
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pipe_tx4_char_is_k_o : out std_logic_vector(1 downto 0);
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pipe_tx4_data_o : out std_logic_vector(15 downto 0);
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pipe_tx4_elec_idle_o : out std_logic;
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pipe_tx4_powerdown_o : out std_logic_vector(1 downto 0);
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-- Pipe Per-Lane Signals - Lane 5
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pipe_rx5_char_is_k_o : out std_logic_vector(1 downto 0);
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pipe_rx5_data_o : out std_logic_vector(15 downto 0);
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pipe_rx5_valid_o : out std_logic;
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pipe_rx5_chanisaligned_o : out std_logic;
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pipe_rx5_status_o : out std_logic_vector(2 downto 0);
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pipe_rx5_phy_status_o : out std_logic;
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pipe_rx5_elec_idle_o : out std_logic;
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pipe_rx5_polarity_i : in std_logic;
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pipe_tx5_compliance_i : in std_logic;
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pipe_tx5_char_is_k_i : in std_logic_vector(1 downto 0);
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pipe_tx5_data_i : in std_logic_vector(15 downto 0);
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pipe_tx5_elec_idle_i : in std_logic;
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pipe_tx5_powerdown_i : in std_logic_vector(1 downto 0);
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pipe_rx5_char_is_k_i : in std_logic_vector(1 downto 0);
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pipe_rx5_data_i : in std_logic_vector(15 downto 0);
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pipe_rx5_valid_i : in std_logic;
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pipe_rx5_chanisaligned_i : in std_logic;
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pipe_rx5_status_i : in std_logic_vector(2 downto 0);
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pipe_rx5_phy_status_i : in std_logic;
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pipe_rx5_elec_idle_i : in std_logic;
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pipe_rx5_polarity_o : out std_logic;
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pipe_tx5_compliance_o : out std_logic;
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pipe_tx5_char_is_k_o : out std_logic_vector(1 downto 0);
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pipe_tx5_data_o : out std_logic_vector(15 downto 0);
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pipe_tx5_elec_idle_o : out std_logic;
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pipe_tx5_powerdown_o : out std_logic_vector(1 downto 0);
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-- Pipe Per-Lane Signals - Lane 6
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pipe_rx6_char_is_k_o : out std_logic_vector(1 downto 0);
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pipe_rx6_data_o : out std_logic_vector(15 downto 0);
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pipe_rx6_valid_o : out std_logic;
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pipe_rx6_chanisaligned_o : out std_logic;
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pipe_rx6_status_o : out std_logic_vector(2 downto 0);
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pipe_rx6_phy_status_o : out std_logic;
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pipe_rx6_elec_idle_o : out std_logic;
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pipe_rx6_polarity_i : in std_logic;
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pipe_tx6_compliance_i : in std_logic;
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pipe_tx6_char_is_k_i : in std_logic_vector(1 downto 0);
|
281 |
|
|
pipe_tx6_data_i : in std_logic_vector(15 downto 0);
|
282 |
|
|
pipe_tx6_elec_idle_i : in std_logic;
|
283 |
|
|
pipe_tx6_powerdown_i : in std_logic_vector(1 downto 0);
|
284 |
|
|
|
285 |
|
|
pipe_rx6_char_is_k_i : in std_logic_vector(1 downto 0);
|
286 |
|
|
pipe_rx6_data_i : in std_logic_vector(15 downto 0);
|
287 |
|
|
pipe_rx6_valid_i : in std_logic;
|
288 |
|
|
pipe_rx6_chanisaligned_i : in std_logic;
|
289 |
|
|
pipe_rx6_status_i : in std_logic_vector(2 downto 0);
|
290 |
|
|
pipe_rx6_phy_status_i : in std_logic;
|
291 |
|
|
pipe_rx6_elec_idle_i : in std_logic;
|
292 |
|
|
pipe_rx6_polarity_o : out std_logic;
|
293 |
|
|
|
294 |
|
|
pipe_tx6_compliance_o : out std_logic;
|
295 |
|
|
pipe_tx6_char_is_k_o : out std_logic_vector(1 downto 0);
|
296 |
|
|
pipe_tx6_data_o : out std_logic_vector(15 downto 0);
|
297 |
|
|
pipe_tx6_elec_idle_o : out std_logic;
|
298 |
|
|
pipe_tx6_powerdown_o : out std_logic_vector(1 downto 0);
|
299 |
|
|
|
300 |
|
|
-- Pipe Per-Lane Signals - Lane 7
|
301 |
|
|
pipe_rx7_char_is_k_o : out std_logic_vector(1 downto 0);
|
302 |
|
|
pipe_rx7_data_o : out std_logic_vector(15 downto 0);
|
303 |
|
|
pipe_rx7_valid_o : out std_logic;
|
304 |
|
|
pipe_rx7_chanisaligned_o : out std_logic;
|
305 |
|
|
pipe_rx7_status_o : out std_logic_vector(2 downto 0);
|
306 |
|
|
pipe_rx7_phy_status_o : out std_logic;
|
307 |
|
|
pipe_rx7_elec_idle_o : out std_logic;
|
308 |
|
|
pipe_rx7_polarity_i : in std_logic;
|
309 |
|
|
|
310 |
|
|
pipe_tx7_compliance_i : in std_logic;
|
311 |
|
|
pipe_tx7_char_is_k_i : in std_logic_vector(1 downto 0);
|
312 |
|
|
pipe_tx7_data_i : in std_logic_vector(15 downto 0);
|
313 |
|
|
pipe_tx7_elec_idle_i : in std_logic;
|
314 |
|
|
pipe_tx7_powerdown_i : in std_logic_vector(1 downto 0);
|
315 |
|
|
|
316 |
|
|
pipe_rx7_char_is_k_i : in std_logic_vector(1 downto 0);
|
317 |
|
|
pipe_rx7_data_i : in std_logic_vector(15 downto 0);
|
318 |
|
|
pipe_rx7_valid_i : in std_logic;
|
319 |
|
|
pipe_rx7_chanisaligned_i : in std_logic;
|
320 |
|
|
pipe_rx7_status_i : in std_logic_vector(2 downto 0);
|
321 |
|
|
pipe_rx7_phy_status_i : in std_logic;
|
322 |
|
|
pipe_rx7_elec_idle_i : in std_logic;
|
323 |
|
|
pipe_rx7_polarity_o : out std_logic;
|
324 |
|
|
|
325 |
|
|
pipe_tx7_compliance_o : out std_logic;
|
326 |
|
|
pipe_tx7_char_is_k_o : out std_logic_vector(1 downto 0);
|
327 |
|
|
pipe_tx7_data_o : out std_logic_vector(15 downto 0);
|
328 |
|
|
pipe_tx7_elec_idle_o : out std_logic;
|
329 |
|
|
pipe_tx7_powerdown_o : out std_logic_vector(1 downto 0);
|
330 |
|
|
|
331 |
|
|
-- Non PIPE signals
|
332 |
|
|
pl_ltssm_state : in std_logic_vector(5 downto 0);
|
333 |
|
|
pipe_clk : in std_logic;
|
334 |
|
|
rst_n : in std_logic
|
335 |
|
|
);
|
336 |
|
|
end cl_a7pcie_x4_pcie_pipe_pipeline;
|
337 |
|
|
|
338 |
|
|
architecture rtl of cl_a7pcie_x4_pcie_pipe_pipeline is
|
339 |
|
|
component cl_a7pcie_x4_pcie_pipe_lane is
|
340 |
|
|
generic (
|
341 |
|
|
PIPE_PIPELINE_STAGES : integer := 0
|
342 |
|
|
);
|
343 |
|
|
port (
|
344 |
|
|
pipe_rx_char_is_k_o : out std_logic_vector(1 downto 0);
|
345 |
|
|
pipe_rx_data_o : out std_logic_vector(15 downto 0);
|
346 |
|
|
pipe_rx_valid_o : out std_logic;
|
347 |
|
|
pipe_rx_chanisaligned_o : out std_logic;
|
348 |
|
|
pipe_rx_status_o : out std_logic_vector(2 downto 0);
|
349 |
|
|
pipe_rx_phy_status_o : out std_logic;
|
350 |
|
|
pipe_rx_elec_idle_o : out std_logic;
|
351 |
|
|
pipe_rx_polarity_i : in std_logic;
|
352 |
|
|
pipe_tx_compliance_i : in std_logic;
|
353 |
|
|
pipe_tx_char_is_k_i : in std_logic_vector(1 downto 0);
|
354 |
|
|
pipe_tx_data_i : in std_logic_vector(15 downto 0);
|
355 |
|
|
pipe_tx_elec_idle_i : in std_logic;
|
356 |
|
|
pipe_tx_powerdown_i : in std_logic_vector(1 downto 0);
|
357 |
|
|
pipe_rx_char_is_k_i : in std_logic_vector(1 downto 0);
|
358 |
|
|
pipe_rx_data_i : in std_logic_vector(15 downto 0);
|
359 |
|
|
pipe_rx_valid_i : in std_logic;
|
360 |
|
|
pipe_rx_chanisaligned_i : in std_logic;
|
361 |
|
|
pipe_rx_status_i : in std_logic_vector(2 downto 0);
|
362 |
|
|
pipe_rx_phy_status_i : in std_logic;
|
363 |
|
|
pipe_rx_elec_idle_i : in std_logic;
|
364 |
|
|
pipe_rx_polarity_o : out std_logic;
|
365 |
|
|
pipe_tx_compliance_o : out std_logic;
|
366 |
|
|
pipe_tx_char_is_k_o : out std_logic_vector(1 downto 0);
|
367 |
|
|
pipe_tx_data_o : out std_logic_vector(15 downto 0);
|
368 |
|
|
pipe_tx_elec_idle_o : out std_logic;
|
369 |
|
|
pipe_tx_powerdown_o : out std_logic_vector(1 downto 0);
|
370 |
|
|
pipe_clk : in std_logic;
|
371 |
|
|
rst_n : in std_logic
|
372 |
|
|
);
|
373 |
|
|
end component;
|
374 |
|
|
|
375 |
|
|
component cl_a7pcie_x4_pcie_pipe_misc is
|
376 |
|
|
generic (
|
377 |
|
|
PIPE_PIPELINE_STAGES : integer := 0
|
378 |
|
|
);
|
379 |
|
|
port (
|
380 |
|
|
pipe_tx_rcvr_det_i : in std_logic;
|
381 |
|
|
pipe_tx_reset_i : in std_logic;
|
382 |
|
|
pipe_tx_rate_i : in std_logic;
|
383 |
|
|
pipe_tx_deemph_i : in std_logic;
|
384 |
|
|
pipe_tx_margin_i : in std_logic_vector(2 downto 0);
|
385 |
|
|
pipe_tx_swing_i : in std_logic;
|
386 |
|
|
pipe_tx_rcvr_det_o : out std_logic;
|
387 |
|
|
pipe_tx_reset_o : out std_logic;
|
388 |
|
|
pipe_tx_rate_o : out std_logic;
|
389 |
|
|
pipe_tx_deemph_o : out std_logic;
|
390 |
|
|
pipe_tx_margin_o : out std_logic_vector(2 downto 0);
|
391 |
|
|
pipe_tx_swing_o : out std_logic;
|
392 |
|
|
pipe_clk : in std_logic;
|
393 |
|
|
rst_n : in std_logic
|
394 |
|
|
);
|
395 |
|
|
end component;
|
396 |
|
|
|
397 |
|
|
--******************************************************************//
|
398 |
|
|
-- Reality check. //
|
399 |
|
|
--******************************************************************//
|
400 |
|
|
|
401 |
|
|
constant Tc2o : integer := 1; -- clock to out delay model
|
402 |
|
|
|
403 |
|
|
begin
|
404 |
|
|
--synthesis translate_off
|
405 |
|
|
-- initial begin
|
406 |
|
|
-- $display("[%t] %m LINK_CAP_MAX_LINK_WIDTH_int %0d PIPE_PIPELINE_STAGES %0d", $time, LINK_CAP_MAX_LINK_WIDTH_int,
|
407 |
|
|
-- PIPE_PIPELINE_STAGES);
|
408 |
|
|
-- end
|
409 |
|
|
--synthesis translate_on
|
410 |
|
|
|
411 |
|
|
pipe_misc_i : cl_a7pcie_x4_pcie_pipe_misc
|
412 |
|
|
generic map (
|
413 |
|
|
PIPE_PIPELINE_STAGES => PIPE_PIPELINE_STAGES
|
414 |
|
|
)
|
415 |
|
|
port map (
|
416 |
|
|
|
417 |
|
|
pipe_tx_rcvr_det_i => pipe_tx_rcvr_det_i,
|
418 |
|
|
pipe_tx_reset_i => pipe_tx_reset_i,
|
419 |
|
|
pipe_tx_rate_i => pipe_tx_rate_i,
|
420 |
|
|
pipe_tx_deemph_i => pipe_tx_deemph_i,
|
421 |
|
|
pipe_tx_margin_i => pipe_tx_margin_i,
|
422 |
|
|
pipe_tx_swing_i => pipe_tx_swing_i,
|
423 |
|
|
|
424 |
|
|
pipe_tx_rcvr_det_o => pipe_tx_rcvr_det_o,
|
425 |
|
|
pipe_tx_reset_o => pipe_tx_reset_o,
|
426 |
|
|
pipe_tx_rate_o => pipe_tx_rate_o,
|
427 |
|
|
pipe_tx_deemph_o => pipe_tx_deemph_o,
|
428 |
|
|
pipe_tx_margin_o => pipe_tx_margin_o,
|
429 |
|
|
pipe_tx_swing_o => pipe_tx_swing_o,
|
430 |
|
|
|
431 |
|
|
pipe_clk => pipe_clk,
|
432 |
|
|
rst_n => rst_n
|
433 |
|
|
);
|
434 |
|
|
|
435 |
|
|
pipe_lane_0_i : cl_a7pcie_x4_pcie_pipe_lane
|
436 |
|
|
generic map (
|
437 |
|
|
PIPE_PIPELINE_STAGES => PIPE_PIPELINE_STAGES)
|
438 |
|
|
port map (
|
439 |
|
|
pipe_rx_char_is_k_o => pipe_rx0_char_is_k_o,
|
440 |
|
|
pipe_rx_data_o => pipe_rx0_data_o,
|
441 |
|
|
pipe_rx_valid_o => pipe_rx0_valid_o,
|
442 |
|
|
pipe_rx_chanisaligned_o => pipe_rx0_chanisaligned_o,
|
443 |
|
|
pipe_rx_status_o => pipe_rx0_status_o,
|
444 |
|
|
pipe_rx_phy_status_o => pipe_rx0_phy_status_o,
|
445 |
|
|
pipe_rx_elec_idle_o => pipe_rx0_elec_idle_o,
|
446 |
|
|
pipe_rx_polarity_i => pipe_rx0_polarity_i,
|
447 |
|
|
pipe_tx_compliance_i => pipe_tx0_compliance_i,
|
448 |
|
|
pipe_tx_char_is_k_i => pipe_tx0_char_is_k_i,
|
449 |
|
|
pipe_tx_data_i => pipe_tx0_data_i,
|
450 |
|
|
pipe_tx_elec_idle_i => pipe_tx0_elec_idle_i,
|
451 |
|
|
pipe_tx_powerdown_i => pipe_tx0_powerdown_i,
|
452 |
|
|
pipe_rx_char_is_k_i => pipe_rx0_char_is_k_i,
|
453 |
|
|
pipe_rx_data_i => pipe_rx0_data_i,
|
454 |
|
|
pipe_rx_valid_i => pipe_rx0_valid_i,
|
455 |
|
|
pipe_rx_chanisaligned_i => pipe_rx0_chanisaligned_i,
|
456 |
|
|
pipe_rx_status_i => pipe_rx0_status_i,
|
457 |
|
|
pipe_rx_phy_status_i => pipe_rx0_phy_status_i,
|
458 |
|
|
pipe_rx_elec_idle_i => pipe_rx0_elec_idle_i,
|
459 |
|
|
pipe_rx_polarity_o => pipe_rx0_polarity_o,
|
460 |
|
|
pipe_tx_compliance_o => pipe_tx0_compliance_o,
|
461 |
|
|
pipe_tx_char_is_k_o => pipe_tx0_char_is_k_o,
|
462 |
|
|
pipe_tx_data_o => pipe_tx0_data_o,
|
463 |
|
|
pipe_tx_elec_idle_o => pipe_tx0_elec_idle_o,
|
464 |
|
|
pipe_tx_powerdown_o => pipe_tx0_powerdown_o,
|
465 |
|
|
pipe_clk => pipe_clk,
|
466 |
|
|
rst_n => rst_n);
|
467 |
|
|
|
468 |
|
|
pipe_lane_2 : if (LINK_CAP_MAX_LINK_WIDTH_int >= 2) generate
|
469 |
|
|
|
470 |
|
|
pipe_lane_1_i : cl_a7pcie_x4_pcie_pipe_lane
|
471 |
|
|
generic map (
|
472 |
|
|
PIPE_PIPELINE_STAGES => PIPE_PIPELINE_STAGES)
|
473 |
|
|
port map (
|
474 |
|
|
pipe_rx_char_is_k_o => pipe_rx1_char_is_k_o,
|
475 |
|
|
pipe_rx_data_o => pipe_rx1_data_o,
|
476 |
|
|
pipe_rx_valid_o => pipe_rx1_valid_o,
|
477 |
|
|
pipe_rx_chanisaligned_o => pipe_rx1_chanisaligned_o,
|
478 |
|
|
pipe_rx_status_o => pipe_rx1_status_o,
|
479 |
|
|
pipe_rx_phy_status_o => pipe_rx1_phy_status_o,
|
480 |
|
|
pipe_rx_elec_idle_o => pipe_rx1_elec_idle_o,
|
481 |
|
|
pipe_rx_polarity_i => pipe_rx1_polarity_i,
|
482 |
|
|
pipe_tx_compliance_i => pipe_tx1_compliance_i,
|
483 |
|
|
pipe_tx_char_is_k_i => pipe_tx1_char_is_k_i,
|
484 |
|
|
pipe_tx_data_i => pipe_tx1_data_i,
|
485 |
|
|
pipe_tx_elec_idle_i => pipe_tx1_elec_idle_i,
|
486 |
|
|
pipe_tx_powerdown_i => pipe_tx1_powerdown_i,
|
487 |
|
|
pipe_rx_char_is_k_i => pipe_rx1_char_is_k_i,
|
488 |
|
|
pipe_rx_data_i => pipe_rx1_data_i,
|
489 |
|
|
pipe_rx_valid_i => pipe_rx1_valid_i,
|
490 |
|
|
pipe_rx_chanisaligned_i => pipe_rx1_chanisaligned_i,
|
491 |
|
|
pipe_rx_status_i => pipe_rx1_status_i,
|
492 |
|
|
pipe_rx_phy_status_i => pipe_rx1_phy_status_i,
|
493 |
|
|
pipe_rx_elec_idle_i => pipe_rx1_elec_idle_i,
|
494 |
|
|
pipe_rx_polarity_o => pipe_rx1_polarity_o,
|
495 |
|
|
pipe_tx_compliance_o => pipe_tx1_compliance_o,
|
496 |
|
|
pipe_tx_char_is_k_o => pipe_tx1_char_is_k_o,
|
497 |
|
|
pipe_tx_data_o => pipe_tx1_data_o,
|
498 |
|
|
pipe_tx_elec_idle_o => pipe_tx1_elec_idle_o,
|
499 |
|
|
pipe_tx_powerdown_o => pipe_tx1_powerdown_o,
|
500 |
|
|
pipe_clk => pipe_clk,
|
501 |
|
|
rst_n => rst_n);
|
502 |
|
|
|
503 |
|
|
end generate;
|
504 |
|
|
|
505 |
|
|
pipe_lane_lt2 : if (LINK_CAP_MAX_LINK_WIDTH_int < 2) generate
|
506 |
|
|
--<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
507 |
|
|
--<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
508 |
|
|
pipe_rx1_char_is_k_o <= "00";
|
509 |
|
|
pipe_rx1_data_o <= (others => '0');
|
510 |
|
|
pipe_rx1_valid_o<= '0';
|
511 |
|
|
pipe_rx1_chanisaligned_o<= '0';
|
512 |
|
|
pipe_rx1_status_o<= "000";
|
513 |
|
|
pipe_rx1_phy_status_o<= '0';
|
514 |
|
|
pipe_rx1_elec_idle_o<= '1';
|
515 |
|
|
pipe_rx1_polarity_o<= '0';
|
516 |
|
|
pipe_tx1_compliance_o<= '0';
|
517 |
|
|
pipe_tx1_char_is_k_o<= "00";
|
518 |
|
|
pipe_tx1_data_o<= (others => '0');
|
519 |
|
|
pipe_tx1_elec_idle_o<= '1';
|
520 |
|
|
pipe_tx1_powerdown_o<= "00";
|
521 |
|
|
--<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
522 |
|
|
--<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
523 |
|
|
|
524 |
|
|
end generate;
|
525 |
|
|
|
526 |
|
|
pipe_lane_4 : if (LINK_CAP_MAX_LINK_WIDTH_int >= 4) generate
|
527 |
|
|
pipe_lane_2_i : cl_a7pcie_x4_pcie_pipe_lane
|
528 |
|
|
generic map (
|
529 |
|
|
PIPE_PIPELINE_STAGES => PIPE_PIPELINE_STAGES)
|
530 |
|
|
port map (
|
531 |
|
|
pipe_rx_char_is_k_o => pipe_rx2_char_is_k_o,
|
532 |
|
|
pipe_rx_data_o => pipe_rx2_data_o,
|
533 |
|
|
pipe_rx_valid_o => pipe_rx2_valid_o,
|
534 |
|
|
pipe_rx_chanisaligned_o => pipe_rx2_chanisaligned_o,
|
535 |
|
|
pipe_rx_status_o => pipe_rx2_status_o,
|
536 |
|
|
pipe_rx_phy_status_o => pipe_rx2_phy_status_o,
|
537 |
|
|
pipe_rx_elec_idle_o => pipe_rx2_elec_idle_o,
|
538 |
|
|
pipe_rx_polarity_i => pipe_rx2_polarity_i,
|
539 |
|
|
pipe_tx_compliance_i => pipe_tx2_compliance_i,
|
540 |
|
|
pipe_tx_char_is_k_i => pipe_tx2_char_is_k_i,
|
541 |
|
|
pipe_tx_data_i => pipe_tx2_data_i,
|
542 |
|
|
pipe_tx_elec_idle_i => pipe_tx2_elec_idle_i,
|
543 |
|
|
pipe_tx_powerdown_i => pipe_tx2_powerdown_i,
|
544 |
|
|
pipe_rx_char_is_k_i => pipe_rx2_char_is_k_i,
|
545 |
|
|
pipe_rx_data_i => pipe_rx2_data_i,
|
546 |
|
|
pipe_rx_valid_i => pipe_rx2_valid_i,
|
547 |
|
|
pipe_rx_chanisaligned_i => pipe_rx2_chanisaligned_i,
|
548 |
|
|
pipe_rx_status_i => pipe_rx2_status_i,
|
549 |
|
|
pipe_rx_phy_status_i => pipe_rx2_phy_status_i,
|
550 |
|
|
pipe_rx_elec_idle_i => pipe_rx2_elec_idle_i,
|
551 |
|
|
pipe_rx_polarity_o => pipe_rx2_polarity_o,
|
552 |
|
|
pipe_tx_compliance_o => pipe_tx2_compliance_o,
|
553 |
|
|
pipe_tx_char_is_k_o => pipe_tx2_char_is_k_o,
|
554 |
|
|
pipe_tx_data_o => pipe_tx2_data_o,
|
555 |
|
|
pipe_tx_elec_idle_o => pipe_tx2_elec_idle_o,
|
556 |
|
|
pipe_tx_powerdown_o => pipe_tx2_powerdown_o,
|
557 |
|
|
pipe_clk => pipe_clk,
|
558 |
|
|
rst_n => rst_n);
|
559 |
|
|
|
560 |
|
|
pipe_lane_3_i : cl_a7pcie_x4_pcie_pipe_lane
|
561 |
|
|
generic map (
|
562 |
|
|
PIPE_PIPELINE_STAGES => PIPE_PIPELINE_STAGES)
|
563 |
|
|
port map (
|
564 |
|
|
pipe_rx_char_is_k_o => pipe_rx3_char_is_k_o,
|
565 |
|
|
pipe_rx_data_o => pipe_rx3_data_o,
|
566 |
|
|
pipe_rx_valid_o => pipe_rx3_valid_o,
|
567 |
|
|
pipe_rx_chanisaligned_o => pipe_rx3_chanisaligned_o,
|
568 |
|
|
pipe_rx_status_o => pipe_rx3_status_o,
|
569 |
|
|
pipe_rx_phy_status_o => pipe_rx3_phy_status_o,
|
570 |
|
|
pipe_rx_elec_idle_o => pipe_rx3_elec_idle_o,
|
571 |
|
|
pipe_rx_polarity_i => pipe_rx3_polarity_i,
|
572 |
|
|
pipe_tx_compliance_i => pipe_tx3_compliance_i,
|
573 |
|
|
pipe_tx_char_is_k_i => pipe_tx3_char_is_k_i,
|
574 |
|
|
pipe_tx_data_i => pipe_tx3_data_i,
|
575 |
|
|
pipe_tx_elec_idle_i => pipe_tx3_elec_idle_i,
|
576 |
|
|
pipe_tx_powerdown_i => pipe_tx3_powerdown_i,
|
577 |
|
|
pipe_rx_char_is_k_i => pipe_rx3_char_is_k_i,
|
578 |
|
|
pipe_rx_data_i => pipe_rx3_data_i,
|
579 |
|
|
pipe_rx_valid_i => pipe_rx3_valid_i,
|
580 |
|
|
pipe_rx_chanisaligned_i => pipe_rx3_chanisaligned_i,
|
581 |
|
|
pipe_rx_status_i => pipe_rx3_status_i,
|
582 |
|
|
pipe_rx_phy_status_i => pipe_rx3_phy_status_i,
|
583 |
|
|
pipe_rx_elec_idle_i => pipe_rx3_elec_idle_i,
|
584 |
|
|
pipe_rx_polarity_o => pipe_rx3_polarity_o,
|
585 |
|
|
pipe_tx_compliance_o => pipe_tx3_compliance_o,
|
586 |
|
|
pipe_tx_char_is_k_o => pipe_tx3_char_is_k_o,
|
587 |
|
|
pipe_tx_data_o => pipe_tx3_data_o,
|
588 |
|
|
pipe_tx_elec_idle_o => pipe_tx3_elec_idle_o,
|
589 |
|
|
pipe_tx_powerdown_o => pipe_tx3_powerdown_o,
|
590 |
|
|
pipe_clk => pipe_clk,
|
591 |
|
|
rst_n => rst_n);
|
592 |
|
|
|
593 |
|
|
end generate;
|
594 |
|
|
pipe_lane_lt4 : if (LINK_CAP_MAX_LINK_WIDTH_int < 4) generate
|
595 |
|
|
--<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
596 |
|
|
--<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
597 |
|
|
pipe_rx2_char_is_k_o <= "00";
|
598 |
|
|
pipe_rx2_data_o <= (others => '0');
|
599 |
|
|
pipe_rx2_valid_o<= '0';
|
600 |
|
|
pipe_rx2_chanisaligned_o<= '0';
|
601 |
|
|
pipe_rx2_status_o<= "000";
|
602 |
|
|
pipe_rx2_phy_status_o<= '0';
|
603 |
|
|
pipe_rx2_elec_idle_o<= '1';
|
604 |
|
|
pipe_rx2_polarity_o<= '0';
|
605 |
|
|
pipe_tx2_compliance_o<= '0';
|
606 |
|
|
pipe_tx2_char_is_k_o<= "00";
|
607 |
|
|
pipe_tx2_data_o<= (others => '0');
|
608 |
|
|
pipe_tx2_elec_idle_o<= '1';
|
609 |
|
|
pipe_tx2_powerdown_o<= "00";
|
610 |
|
|
|
611 |
|
|
pipe_rx3_char_is_k_o <= "00";
|
612 |
|
|
pipe_rx3_data_o <= (others => '0');
|
613 |
|
|
pipe_rx3_valid_o<= '0';
|
614 |
|
|
pipe_rx3_chanisaligned_o<= '0';
|
615 |
|
|
pipe_rx3_status_o<= "000";
|
616 |
|
|
pipe_rx3_phy_status_o<= '0';
|
617 |
|
|
pipe_rx3_elec_idle_o<= '1';
|
618 |
|
|
pipe_rx3_polarity_o<= '0';
|
619 |
|
|
pipe_tx3_compliance_o<= '0';
|
620 |
|
|
pipe_tx3_char_is_k_o<= "00";
|
621 |
|
|
pipe_tx3_data_o<= (others => '0');
|
622 |
|
|
pipe_tx3_elec_idle_o<= '1';
|
623 |
|
|
pipe_tx3_powerdown_o<= "00";
|
624 |
|
|
--<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
625 |
|
|
--<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
626 |
|
|
|
627 |
|
|
end generate;
|
628 |
|
|
|
629 |
|
|
pipe_lane_8 : if (LINK_CAP_MAX_LINK_WIDTH_int >= 8) generate
|
630 |
|
|
|
631 |
|
|
pipe_lane_4_i : cl_a7pcie_x4_pcie_pipe_lane
|
632 |
|
|
generic map (
|
633 |
|
|
PIPE_PIPELINE_STAGES => PIPE_PIPELINE_STAGES)
|
634 |
|
|
port map (
|
635 |
|
|
pipe_rx_char_is_k_o => pipe_rx4_char_is_k_o,
|
636 |
|
|
pipe_rx_data_o => pipe_rx4_data_o,
|
637 |
|
|
pipe_rx_valid_o => pipe_rx4_valid_o,
|
638 |
|
|
pipe_rx_chanisaligned_o => pipe_rx4_chanisaligned_o,
|
639 |
|
|
pipe_rx_status_o => pipe_rx4_status_o,
|
640 |
|
|
pipe_rx_phy_status_o => pipe_rx4_phy_status_o,
|
641 |
|
|
pipe_rx_elec_idle_o => pipe_rx4_elec_idle_o,
|
642 |
|
|
pipe_rx_polarity_i => pipe_rx4_polarity_i,
|
643 |
|
|
pipe_tx_compliance_i => pipe_tx4_compliance_i,
|
644 |
|
|
pipe_tx_char_is_k_i => pipe_tx4_char_is_k_i,
|
645 |
|
|
pipe_tx_data_i => pipe_tx4_data_i,
|
646 |
|
|
pipe_tx_elec_idle_i => pipe_tx4_elec_idle_i,
|
647 |
|
|
pipe_tx_powerdown_i => pipe_tx4_powerdown_i,
|
648 |
|
|
pipe_rx_char_is_k_i => pipe_rx4_char_is_k_i,
|
649 |
|
|
pipe_rx_data_i => pipe_rx4_data_i,
|
650 |
|
|
pipe_rx_valid_i => pipe_rx4_valid_i,
|
651 |
|
|
pipe_rx_chanisaligned_i => pipe_rx4_chanisaligned_i,
|
652 |
|
|
pipe_rx_status_i => pipe_rx4_status_i,
|
653 |
|
|
pipe_rx_phy_status_i => pipe_rx4_phy_status_i,
|
654 |
|
|
pipe_rx_elec_idle_i => pipe_rx4_elec_idle_i,
|
655 |
|
|
pipe_rx_polarity_o => pipe_rx4_polarity_o,
|
656 |
|
|
pipe_tx_compliance_o => pipe_tx4_compliance_o,
|
657 |
|
|
pipe_tx_char_is_k_o => pipe_tx4_char_is_k_o,
|
658 |
|
|
pipe_tx_data_o => pipe_tx4_data_o,
|
659 |
|
|
pipe_tx_elec_idle_o => pipe_tx4_elec_idle_o,
|
660 |
|
|
pipe_tx_powerdown_o => pipe_tx4_powerdown_o,
|
661 |
|
|
pipe_clk => pipe_clk,
|
662 |
|
|
rst_n => rst_n);
|
663 |
|
|
|
664 |
|
|
pipe_lane_5_i : cl_a7pcie_x4_pcie_pipe_lane
|
665 |
|
|
generic map (
|
666 |
|
|
PIPE_PIPELINE_STAGES => PIPE_PIPELINE_STAGES)
|
667 |
|
|
port map (
|
668 |
|
|
pipe_rx_char_is_k_o => pipe_rx5_char_is_k_o,
|
669 |
|
|
pipe_rx_data_o => pipe_rx5_data_o,
|
670 |
|
|
pipe_rx_valid_o => pipe_rx5_valid_o,
|
671 |
|
|
pipe_rx_chanisaligned_o => pipe_rx5_chanisaligned_o,
|
672 |
|
|
pipe_rx_status_o => pipe_rx5_status_o,
|
673 |
|
|
pipe_rx_phy_status_o => pipe_rx5_phy_status_o,
|
674 |
|
|
pipe_rx_elec_idle_o => pipe_rx5_elec_idle_o,
|
675 |
|
|
pipe_rx_polarity_i => pipe_rx5_polarity_i,
|
676 |
|
|
pipe_tx_compliance_i => pipe_tx5_compliance_i,
|
677 |
|
|
pipe_tx_char_is_k_i => pipe_tx5_char_is_k_i,
|
678 |
|
|
pipe_tx_data_i => pipe_tx5_data_i,
|
679 |
|
|
pipe_tx_elec_idle_i => pipe_tx5_elec_idle_i,
|
680 |
|
|
pipe_tx_powerdown_i => pipe_tx5_powerdown_i,
|
681 |
|
|
pipe_rx_char_is_k_i => pipe_rx5_char_is_k_i,
|
682 |
|
|
pipe_rx_data_i => pipe_rx5_data_i,
|
683 |
|
|
pipe_rx_valid_i => pipe_rx5_valid_i,
|
684 |
|
|
pipe_rx_chanisaligned_i => pipe_rx5_chanisaligned_i,
|
685 |
|
|
pipe_rx_status_i => pipe_rx5_status_i,
|
686 |
|
|
pipe_rx_phy_status_i => pipe_rx5_phy_status_i,
|
687 |
|
|
pipe_rx_elec_idle_i => pipe_rx5_elec_idle_i,
|
688 |
|
|
pipe_rx_polarity_o => pipe_rx5_polarity_o,
|
689 |
|
|
pipe_tx_compliance_o => pipe_tx5_compliance_o,
|
690 |
|
|
pipe_tx_char_is_k_o => pipe_tx5_char_is_k_o,
|
691 |
|
|
pipe_tx_data_o => pipe_tx5_data_o,
|
692 |
|
|
pipe_tx_elec_idle_o => pipe_tx5_elec_idle_o,
|
693 |
|
|
pipe_tx_powerdown_o => pipe_tx5_powerdown_o,
|
694 |
|
|
pipe_clk => pipe_clk,
|
695 |
|
|
rst_n => rst_n);
|
696 |
|
|
|
697 |
|
|
pipe_lane_6_i : cl_a7pcie_x4_pcie_pipe_lane
|
698 |
|
|
generic map (
|
699 |
|
|
PIPE_PIPELINE_STAGES => PIPE_PIPELINE_STAGES)
|
700 |
|
|
port map (
|
701 |
|
|
pipe_rx_char_is_k_o => pipe_rx6_char_is_k_o,
|
702 |
|
|
pipe_rx_data_o => pipe_rx6_data_o,
|
703 |
|
|
pipe_rx_valid_o => pipe_rx6_valid_o,
|
704 |
|
|
pipe_rx_chanisaligned_o => pipe_rx6_chanisaligned_o,
|
705 |
|
|
pipe_rx_status_o => pipe_rx6_status_o,
|
706 |
|
|
pipe_rx_phy_status_o => pipe_rx6_phy_status_o,
|
707 |
|
|
pipe_rx_elec_idle_o => pipe_rx6_elec_idle_o,
|
708 |
|
|
pipe_rx_polarity_i => pipe_rx6_polarity_i,
|
709 |
|
|
pipe_tx_compliance_i => pipe_tx6_compliance_i,
|
710 |
|
|
pipe_tx_char_is_k_i => pipe_tx6_char_is_k_i,
|
711 |
|
|
pipe_tx_data_i => pipe_tx6_data_i,
|
712 |
|
|
pipe_tx_elec_idle_i => pipe_tx6_elec_idle_i,
|
713 |
|
|
pipe_tx_powerdown_i => pipe_tx6_powerdown_i,
|
714 |
|
|
pipe_rx_char_is_k_i => pipe_rx6_char_is_k_i,
|
715 |
|
|
pipe_rx_data_i => pipe_rx6_data_i,
|
716 |
|
|
pipe_rx_valid_i => pipe_rx6_valid_i,
|
717 |
|
|
pipe_rx_chanisaligned_i => pipe_rx6_chanisaligned_i,
|
718 |
|
|
pipe_rx_status_i => pipe_rx6_status_i,
|
719 |
|
|
pipe_rx_phy_status_i => pipe_rx6_phy_status_i,
|
720 |
|
|
pipe_rx_elec_idle_i => pipe_rx6_elec_idle_i,
|
721 |
|
|
pipe_rx_polarity_o => pipe_rx6_polarity_o,
|
722 |
|
|
pipe_tx_compliance_o => pipe_tx6_compliance_o,
|
723 |
|
|
pipe_tx_char_is_k_o => pipe_tx6_char_is_k_o,
|
724 |
|
|
pipe_tx_data_o => pipe_tx6_data_o,
|
725 |
|
|
pipe_tx_elec_idle_o => pipe_tx6_elec_idle_o,
|
726 |
|
|
pipe_tx_powerdown_o => pipe_tx6_powerdown_o,
|
727 |
|
|
pipe_clk => pipe_clk,
|
728 |
|
|
rst_n => rst_n);
|
729 |
|
|
|
730 |
|
|
pipe_lane_7_i : cl_a7pcie_x4_pcie_pipe_lane
|
731 |
|
|
generic map (
|
732 |
|
|
PIPE_PIPELINE_STAGES => PIPE_PIPELINE_STAGES)
|
733 |
|
|
port map (
|
734 |
|
|
pipe_rx_char_is_k_o => pipe_rx7_char_is_k_o,
|
735 |
|
|
pipe_rx_data_o => pipe_rx7_data_o,
|
736 |
|
|
pipe_rx_valid_o => pipe_rx7_valid_o,
|
737 |
|
|
pipe_rx_chanisaligned_o => pipe_rx7_chanisaligned_o,
|
738 |
|
|
pipe_rx_status_o => pipe_rx7_status_o,
|
739 |
|
|
pipe_rx_phy_status_o => pipe_rx7_phy_status_o,
|
740 |
|
|
pipe_rx_elec_idle_o => pipe_rx7_elec_idle_o,
|
741 |
|
|
pipe_rx_polarity_i => pipe_rx7_polarity_i,
|
742 |
|
|
pipe_tx_compliance_i => pipe_tx7_compliance_i,
|
743 |
|
|
pipe_tx_char_is_k_i => pipe_tx7_char_is_k_i,
|
744 |
|
|
pipe_tx_data_i => pipe_tx7_data_i,
|
745 |
|
|
pipe_tx_elec_idle_i => pipe_tx7_elec_idle_i,
|
746 |
|
|
pipe_tx_powerdown_i => pipe_tx7_powerdown_i,
|
747 |
|
|
pipe_rx_char_is_k_i => pipe_rx7_char_is_k_i,
|
748 |
|
|
pipe_rx_data_i => pipe_rx7_data_i,
|
749 |
|
|
pipe_rx_valid_i => pipe_rx7_valid_i,
|
750 |
|
|
pipe_rx_chanisaligned_i => pipe_rx7_chanisaligned_i,
|
751 |
|
|
pipe_rx_status_i => pipe_rx7_status_i,
|
752 |
|
|
pipe_rx_phy_status_i => pipe_rx7_phy_status_i,
|
753 |
|
|
pipe_rx_elec_idle_i => pipe_rx7_elec_idle_i,
|
754 |
|
|
pipe_rx_polarity_o => pipe_rx7_polarity_o,
|
755 |
|
|
pipe_tx_compliance_o => pipe_tx7_compliance_o,
|
756 |
|
|
pipe_tx_char_is_k_o => pipe_tx7_char_is_k_o,
|
757 |
|
|
pipe_tx_data_o => pipe_tx7_data_o,
|
758 |
|
|
pipe_tx_elec_idle_o => pipe_tx7_elec_idle_o,
|
759 |
|
|
pipe_tx_powerdown_o => pipe_tx7_powerdown_o,
|
760 |
|
|
pipe_clk => pipe_clk,
|
761 |
|
|
rst_n => rst_n);
|
762 |
|
|
|
763 |
|
|
|
764 |
|
|
end generate;
|
765 |
|
|
pipe_lane_lt8 : if (LINK_CAP_MAX_LINK_WIDTH_int < 8) generate
|
766 |
|
|
--<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
767 |
|
|
--<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
768 |
|
|
pipe_rx4_char_is_k_o <= "00";
|
769 |
|
|
pipe_rx4_data_o <= (others => '0');
|
770 |
|
|
pipe_rx4_valid_o<= '0';
|
771 |
|
|
pipe_rx4_chanisaligned_o<= '0';
|
772 |
|
|
pipe_rx4_status_o<= "000";
|
773 |
|
|
pipe_rx4_phy_status_o<= '0';
|
774 |
|
|
pipe_rx4_elec_idle_o<= '1';
|
775 |
|
|
pipe_rx4_polarity_o<= '0';
|
776 |
|
|
pipe_tx4_compliance_o<= '0';
|
777 |
|
|
pipe_tx4_char_is_k_o<= "00";
|
778 |
|
|
pipe_tx4_data_o<= (others => '0');
|
779 |
|
|
pipe_tx4_elec_idle_o<= '1';
|
780 |
|
|
pipe_tx4_powerdown_o<= "00";
|
781 |
|
|
|
782 |
|
|
pipe_rx5_char_is_k_o <= "00";
|
783 |
|
|
pipe_rx5_data_o <= (others => '0');
|
784 |
|
|
pipe_rx5_valid_o<= '0';
|
785 |
|
|
pipe_rx5_chanisaligned_o<= '0';
|
786 |
|
|
pipe_rx5_status_o<= "000";
|
787 |
|
|
pipe_rx5_phy_status_o<= '0';
|
788 |
|
|
pipe_rx5_elec_idle_o<= '1';
|
789 |
|
|
pipe_rx5_polarity_o<= '0';
|
790 |
|
|
pipe_tx5_compliance_o<= '0';
|
791 |
|
|
pipe_tx5_char_is_k_o<= "00";
|
792 |
|
|
pipe_tx5_data_o<= (others => '0');
|
793 |
|
|
pipe_tx5_elec_idle_o<= '1';
|
794 |
|
|
pipe_tx5_powerdown_o<= "00";
|
795 |
|
|
|
796 |
|
|
pipe_rx6_char_is_k_o <= "00";
|
797 |
|
|
pipe_rx6_data_o <= (others => '0');
|
798 |
|
|
pipe_rx6_valid_o<= '0';
|
799 |
|
|
pipe_rx6_chanisaligned_o<= '0';
|
800 |
|
|
pipe_rx6_status_o<= "000";
|
801 |
|
|
pipe_rx6_phy_status_o<= '0';
|
802 |
|
|
pipe_rx6_elec_idle_o<= '1';
|
803 |
|
|
pipe_rx6_polarity_o<= '0';
|
804 |
|
|
pipe_tx6_compliance_o<= '0';
|
805 |
|
|
pipe_tx6_char_is_k_o<= "00";
|
806 |
|
|
pipe_tx6_data_o<= (others => '0');
|
807 |
|
|
pipe_tx6_elec_idle_o<= '1';
|
808 |
|
|
pipe_tx6_powerdown_o<= "00";
|
809 |
|
|
|
810 |
|
|
pipe_rx7_char_is_k_o <= "00";
|
811 |
|
|
pipe_rx7_data_o <= (others => '0');
|
812 |
|
|
pipe_rx7_valid_o<= '0';
|
813 |
|
|
pipe_rx7_chanisaligned_o<= '0';
|
814 |
|
|
pipe_rx7_status_o<= "000";
|
815 |
|
|
pipe_rx7_phy_status_o<= '0';
|
816 |
|
|
pipe_rx7_elec_idle_o<= '1';
|
817 |
|
|
pipe_rx7_polarity_o<= '0';
|
818 |
|
|
pipe_tx7_compliance_o<= '0';
|
819 |
|
|
pipe_tx7_char_is_k_o<= "00";
|
820 |
|
|
pipe_tx7_data_o<= (others => '0');
|
821 |
|
|
pipe_tx7_elec_idle_o<= '1';
|
822 |
|
|
pipe_tx7_powerdown_o<= "00";
|
823 |
|
|
--<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
824 |
|
|
--<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
825 |
|
|
|
826 |
|
|
end generate;
|
827 |
|
|
|
828 |
|
|
--<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
829 |
|
|
--<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
830 |
|
|
|
831 |
|
|
--<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
832 |
|
|
--<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
833 |
|
|
|
834 |
|
|
|
835 |
|
|
end rtl;
|
836 |
|
|
|