Subversion Repositories pcie_ds_dma

-------------------------------------------------------------------------------

--

-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.

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-------------------------------------------------------------------------------

-- Project    : Series-7 Integrated Block for PCI Express

-- File       : cl_a7pcie_x4_pcie_top.vhd

-- Version    : 1.10

-- Description: Solution wrapper for Virtex7 Hard Block for PCI Express

--

--

--

----------------------------------------------------------------------------------

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_misc.all;

use ieee.std_logic_unsigned.all;

--library unisim;

--use unisim.vcomponents.all;

entity cl_a7pcie_x4_pcie_top is

  generic (

  -- PCIE_2_1 params

  C_DATA_WIDTH                                   : INTEGER range 64 to 128 := 64;

  C_REM_WIDTH                                    : INTEGER range 0 to 128  :=  1;

  PIPE_PIPELINE_STAGES                           : INTEGER range 0 to 2 := 0;      -- 0 - 0 stages, 1 - 1 stage, 2 - 2 stages

  -- PCIE_2_1 params

  AER_BASE_PTR                                   : bit_vector := X"140";

  AER_CAP_ECRC_CHECK_CAPABLE                     : string     := "FALSE";

  AER_CAP_ECRC_GEN_CAPABLE                       : string     := "FALSE";

  AER_CAP_ID                                     : bit_vector := X"0001";

  AER_CAP_MULTIHEADER                            : string     := "FALSE";

  AER_CAP_NEXTPTR                                : bit_vector := X"178";

  AER_CAP_ON                                     : string     := "FALSE";

  AER_CAP_OPTIONAL_ERR_SUPPORT                   : bit_vector := X"000000";

  AER_CAP_PERMIT_ROOTERR_UPDATE                  : string     := "TRUE";

  AER_CAP_VERSION                                : bit_vector := X"2";

  ALLOW_X8_GEN2                                  : string     := "FALSE";

  BAR0                                           : bit_vector := X"FFFFFF00";

  BAR1                                           : bit_vector := X"FFFF0000";

  BAR2                                           : bit_vector := X"FFFF000C";

  BAR3                                           : bit_vector := X"FFFFFFFF";

  BAR4                                           : bit_vector := X"00000000";

  BAR5                                           : bit_vector := X"00000000";

  CAPABILITIES_PTR                               : bit_vector := X"40";

  CARDBUS_CIS_POINTER                            : bit_vector := X"00000000";

  CFG_ECRC_ERR_CPLSTAT                           : integer    := 0;

  CLASS_CODE                                     : bit_vector := X"000000";

  CMD_INTX_IMPLEMENTED                           : string     := "TRUE";

  CPL_TIMEOUT_DISABLE_SUPPORTED                  : string     := "FALSE";

  CPL_TIMEOUT_RANGES_SUPPORTED                   : bit_vector := X"0";

  CRM_MODULE_RSTS                                : bit_vector := X"00";

  DEV_CAP2_ARI_FORWARDING_SUPPORTED              : string     := "FALSE";

  DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED        : string     := "FALSE";

  DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED        : string     := "FALSE";

  DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED            : string     := "FALSE";

  DEV_CAP2_CAS128_COMPLETER_SUPPORTED            : string     := "FALSE";

  DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED           : string     := "FALSE";

  DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED          : string     := "FALSE";

  DEV_CAP2_LTR_MECHANISM_SUPPORTED               : string     := "FALSE";

  DEV_CAP2_MAX_ENDEND_TLP_PREFIXES               : bit_vector := X"0";

  DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING            : string     := "FALSE";

  DEV_CAP2_TPH_COMPLETER_SUPPORTED               : bit_vector := X"0";

  DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE            : string     := "TRUE";

  DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE            : string     := "TRUE";

  DEV_CAP_ENDPOINT_L0S_LATENCY                   : integer    := 0;

  DEV_CAP_ENDPOINT_L1_LATENCY                    : integer    := 0;

  DEV_CAP_EXT_TAG_SUPPORTED                      : string     := "TRUE";

  DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE           : string     := "FALSE";

  DEV_CAP_MAX_PAYLOAD_SUPPORTED                  : integer    := 2;

  DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT              : integer    := 0;

  DEV_CAP_ROLE_BASED_ERROR                       : string     := "TRUE";

  DEV_CAP_RSVD_14_12                             : integer    := 0;

  DEV_CAP_RSVD_17_16                             : integer    := 0;

  DEV_CAP_RSVD_31_29                             : integer    := 0;

  DEV_CONTROL_AUX_POWER_SUPPORTED                : string     := "FALSE";

  DEV_CONTROL_EXT_TAG_DEFAULT                    : string     := "FALSE";

  DISABLE_ASPM_L1_TIMER                          : string     := "FALSE";

  DISABLE_BAR_FILTERING                          : string     := "FALSE";

  DISABLE_ERR_MSG                                : string     := "FALSE";

  DISABLE_ID_CHECK                               : string     := "FALSE";

  DISABLE_LANE_REVERSAL                          : string     := "FALSE";

  DISABLE_LOCKED_FILTER                          : string     := "FALSE";

  DISABLE_PPM_FILTER                             : string     := "FALSE";

  DISABLE_RX_POISONED_RESP                       : string     := "FALSE";

  DISABLE_RX_TC_FILTER                           : string     := "FALSE";

  DISABLE_SCRAMBLING                             : string     := "FALSE";

  DNSTREAM_LINK_NUM                              : bit_vector := X"00";

  DSN_BASE_PTR                                   : bit_vector := X"100";

  DSN_CAP_ID                                     : bit_vector := X"0003";

  DSN_CAP_NEXTPTR                                : bit_vector := X"10C";

  DSN_CAP_ON                                     : string     := "TRUE";

  DSN_CAP_VERSION                                : bit_vector := X"1";

  ENABLE_MSG_ROUTE                               : bit_vector := X"000";

  ENABLE_RX_TD_ECRC_TRIM                         : string     := "FALSE";

  ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED         : string     := "FALSE";

  ENTER_RVRY_EI_L0                               : string     := "TRUE";

  EXIT_LOOPBACK_ON_EI                            : string     := "TRUE";

  EXPANSION_ROM                                  : bit_vector := X"FFFFF001";

  EXT_CFG_CAP_PTR                                : bit_vector := X"3F";

  EXT_CFG_XP_CAP_PTR                             : bit_vector := X"3FF";

  HEADER_TYPE                                    : bit_vector := X"00";

  INFER_EI                                       : bit_vector := X"00";

  INTERRUPT_PIN                                  : bit_vector := X"01";

  INTERRUPT_STAT_AUTO                            : string     := "TRUE";

  IS_SWITCH                                      : string     := "FALSE";

  LAST_CONFIG_DWORD                              : bit_vector := X"3FF";

  LINK_CAP_ASPM_OPTIONALITY                      : string     := "TRUE";

  LINK_CAP_ASPM_SUPPORT                          : integer    := 1;

  LINK_CAP_CLOCK_POWER_MANAGEMENT                : string     := "FALSE";

  LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP         : string     := "FALSE";

  LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1          : integer    := 7;

  LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2          : integer    := 7;

  LINK_CAP_L0S_EXIT_LATENCY_GEN1                 : integer    := 7;

  LINK_CAP_L0S_EXIT_LATENCY_GEN2                 : integer    := 7;

  LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1           : integer    := 7;

  LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2           : integer    := 7;

  LINK_CAP_L1_EXIT_LATENCY_GEN1                  : integer    := 7;

  LINK_CAP_L1_EXIT_LATENCY_GEN2                  : integer    := 7;

  LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP       : string     := "FALSE";

  LINK_CAP_MAX_LINK_SPEED                        : bit_vector := X"1";

  LINK_CAP_MAX_LINK_SPEED_int                    : integer    := 1;

  LINK_CAP_MAX_LINK_WIDTH                        : bit_vector := X"08";

  LINK_CAP_MAX_LINK_WIDTH_int                    : integer    := 8;

  LINK_CAP_RSVD_23                               : integer    := 0;

  LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE           : string     := "FALSE";

  LINK_CONTROL_RCB                               : integer    := 0;

  LINK_CTRL2_DEEMPHASIS                          : string     := "FALSE";

  LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE         : string     := "FALSE";

  LINK_CTRL2_TARGET_LINK_SPEED                   : bit_vector := X"2";

  LINK_STATUS_SLOT_CLOCK_CONFIG                  : string     := "TRUE";

  LL_ACK_TIMEOUT                                 : bit_vector := X"0000";

  LL_ACK_TIMEOUT_EN                              : string     := "FALSE";

  LL_ACK_TIMEOUT_FUNC                            : integer    := 0;

  LL_REPLAY_TIMEOUT                              : bit_vector := X"0000";

  LL_REPLAY_TIMEOUT_EN                           : string     := "FALSE";

  LL_REPLAY_TIMEOUT_FUNC                         : integer    := 0;

  LTSSM_MAX_LINK_WIDTH                           : bit_vector := X"01";

  MPS_FORCE                                      : string     := "FALSE";

  MSIX_BASE_PTR                                  : bit_vector := X"9C";

  MSIX_CAP_ID                                    : bit_vector := X"11";

  MSIX_CAP_NEXTPTR                               : bit_vector := X"00";

  MSIX_CAP_ON                                    : string     := "FALSE";

  MSIX_CAP_PBA_BIR                               : integer    := 0;

  MSIX_CAP_PBA_OFFSET                            : bit_vector := X"00000050";

  MSIX_CAP_TABLE_BIR                             : integer    := 0;

  MSIX_CAP_TABLE_OFFSET                          : bit_vector := X"00000040";

  MSIX_CAP_TABLE_SIZE                            : bit_vector := X"000";

  MSI_BASE_PTR                                   : bit_vector := X"48";

  MSI_CAP_64_BIT_ADDR_CAPABLE                    : string     := "TRUE";

  MSI_CAP_ID                                     : bit_vector := X"05";

  MSI_CAP_MULTIMSGCAP                            : integer    := 0;

  MSI_CAP_MULTIMSG_EXTENSION                     : integer    := 0;

  MSI_CAP_NEXTPTR                                : bit_vector := X"60";

  MSI_CAP_ON                                     : string     := "FALSE";

  MSI_CAP_PER_VECTOR_MASKING_CAPABLE             : string     := "TRUE";

  N_FTS_COMCLK_GEN1                              : integer    := 255;

  N_FTS_COMCLK_GEN2                              : integer    := 255;

  N_FTS_GEN1                                     : integer    := 255;

  N_FTS_GEN2                                     : integer    := 255;

  PCIE_BASE_PTR                                  : bit_vector := X"60";

  PCIE_CAP_CAPABILITY_ID                         : bit_vector := X"10";

  PCIE_CAP_CAPABILITY_VERSION                    : bit_vector := X"2";

  PCIE_CAP_DEVICE_PORT_TYPE                      : bit_vector := X"0";

  PCIE_CAP_NEXTPTR                               : bit_vector := X"9C";

  PCIE_CAP_ON                                    : string     := "TRUE";

  PCIE_CAP_RSVD_15_14                            : integer    := 0;

  PCIE_CAP_SLOT_IMPLEMENTED                      : string     := "FALSE";

  PCIE_REVISION                                  : integer    := 2;

  PL_AUTO_CONFIG                                 : integer    := 0;

  PL_FAST_TRAIN                                  : string     := "FALSE";

  PM_ASPML0S_TIMEOUT                             : bit_vector := X"0000";

  PM_ASPML0S_TIMEOUT_EN                          : string     := "FALSE";

  PM_ASPML0S_TIMEOUT_FUNC                        : integer    := 0;

  PM_ASPM_FASTEXIT                               : string     := "FALSE";

  PM_BASE_PTR                                    : bit_vector := X"40";

  PM_CAP_AUXCURRENT                              : integer    := 0;

  PM_CAP_D1SUPPORT                               : string     := "TRUE";

  PM_CAP_D2SUPPORT                               : string     := "TRUE";

  PM_CAP_DSI                                     : string     := "FALSE";

  PM_CAP_ID                                      : bit_vector := X"01";

  PM_CAP_NEXTPTR                                 : bit_vector := X"48";

  PM_CAP_ON                                      : string     := "TRUE";

  PM_CAP_PMESUPPORT                              : bit_vector := X"0F";

  PM_CAP_PME_CLOCK                               : string     := "FALSE";

  PM_CAP_RSVD_04                                 : integer    := 0;

  PM_CAP_VERSION                                 : integer    := 3;

  PM_CSR_B2B3                                    : string     := "FALSE";

  PM_CSR_BPCCEN                                  : string     := "FALSE";

  PM_CSR_NOSOFTRST                               : string     := "TRUE";

  PM_DATA0                                       : bit_vector := X"01";

  PM_DATA1                                       : bit_vector := X"01";

  PM_DATA2                                       : bit_vector := X"01";

  PM_DATA3                                       : bit_vector := X"01";

  PM_DATA4                                       : bit_vector := X"01";

  PM_DATA5                                       : bit_vector := X"01";

  PM_DATA6                                       : bit_vector := X"01";

  PM_DATA7                                       : bit_vector := X"01";

  PM_DATA_SCALE0                                 : bit_vector := X"1";

  PM_DATA_SCALE1                                 : bit_vector := X"1";

  PM_DATA_SCALE2                                 : bit_vector := X"1";

  PM_DATA_SCALE3                                 : bit_vector := X"1";

  PM_DATA_SCALE4                                 : bit_vector := X"1";

  PM_DATA_SCALE5                                 : bit_vector := X"1";

  PM_DATA_SCALE6                                 : bit_vector := X"1";

  PM_DATA_SCALE7                                 : bit_vector := X"1";

  PM_MF                                          : string     := "FALSE";

  RBAR_BASE_PTR                                  : bit_vector := X"178";

  RBAR_CAP_CONTROL_ENCODEDBAR0                   : bit_vector := X"00";

  RBAR_CAP_CONTROL_ENCODEDBAR1                   : bit_vector := X"00";

  RBAR_CAP_CONTROL_ENCODEDBAR2                   : bit_vector := X"00";

  RBAR_CAP_CONTROL_ENCODEDBAR3                   : bit_vector := X"00";

  RBAR_CAP_CONTROL_ENCODEDBAR4                   : bit_vector := X"00";

  RBAR_CAP_CONTROL_ENCODEDBAR5                   : bit_vector := X"00";

  RBAR_CAP_ID                                    : bit_vector := X"0015";

  RBAR_CAP_INDEX0                                : bit_vector := X"0";

  RBAR_CAP_INDEX1                                : bit_vector := X"0";

  RBAR_CAP_INDEX2                                : bit_vector := X"0";

  RBAR_CAP_INDEX3                                : bit_vector := X"0";

  RBAR_CAP_INDEX4                                : bit_vector := X"0";

  RBAR_CAP_INDEX5                                : bit_vector := X"0";

  RBAR_CAP_NEXTPTR                               : bit_vector := X"000";

  RBAR_CAP_ON                                    : string     := "FALSE";

  RBAR_CAP_SUP0                                  : bit_vector := X"00000000";

  RBAR_CAP_SUP1                                  : bit_vector := X"00000000";

  RBAR_CAP_SUP2                                  : bit_vector := X"00000000";

  RBAR_CAP_SUP3                                  : bit_vector := X"00000000";

  RBAR_CAP_SUP4                                  : bit_vector := X"00000000";

  RBAR_CAP_SUP5                                  : bit_vector := X"00000000";

  RBAR_CAP_VERSION                               : bit_vector := X"1";

  RBAR_NUM                                       : bit_vector := X"1";

  RECRC_CHK                                      : integer    := 0;

  RECRC_CHK_TRIM                                 : string     := "FALSE";

  ROOT_CAP_CRS_SW_VISIBILITY                     : string     := "FALSE";

  RP_AUTO_SPD                                    : bit_vector := X"1";

  RP_AUTO_SPD_LOOPCNT                            : bit_vector := X"1F";

  SELECT_DLL_IF                                  : string     := "FALSE";

  SIM_VERSION                                    : string     := "1.0";

  SLOT_CAP_ATT_BUTTON_PRESENT                    : string     := "FALSE";

  SLOT_CAP_ATT_INDICATOR_PRESENT                 : string     := "FALSE";

  SLOT_CAP_ELEC_INTERLOCK_PRESENT                : string     := "FALSE";

  SLOT_CAP_HOTPLUG_CAPABLE                       : string     := "FALSE";

  SLOT_CAP_HOTPLUG_SURPRISE                      : string     := "FALSE";

  SLOT_CAP_MRL_SENSOR_PRESENT                    : string     := "FALSE";

  SLOT_CAP_NO_CMD_COMPLETED_SUPPORT              : string     := "FALSE";

  SLOT_CAP_PHYSICAL_SLOT_NUM                     : bit_vector := X"0000";

  SLOT_CAP_POWER_CONTROLLER_PRESENT              : string     := "FALSE";

  SLOT_CAP_POWER_INDICATOR_PRESENT               : string     := "FALSE";

  SLOT_CAP_SLOT_POWER_LIMIT_SCALE                : integer    := 0;

  SLOT_CAP_SLOT_POWER_LIMIT_VALUE                : bit_vector := X"00";

  SPARE_BIT0                                     : integer    := 0;

  SPARE_BIT1                                     : integer    := 0;

  SPARE_BIT2                                     : integer    := 0;

  SPARE_BIT3                                     : integer    := 0;

  SPARE_BIT4                                     : integer    := 0;

  SPARE_BIT5                                     : integer    := 0;

  SPARE_BIT6                                     : integer    := 0;

  SPARE_BIT7                                     : integer    := 0;

  SPARE_BIT8                                     : integer    := 0;

  SPARE_BYTE0                                    : bit_vector := X"00";

  SPARE_BYTE1                                    : bit_vector := X"00";

  SPARE_BYTE2                                    : bit_vector := X"00";

  SPARE_BYTE3                                    : bit_vector := X"00";

  SPARE_WORD0                                    : bit_vector := X"00000000";

  SPARE_WORD1                                    : bit_vector := X"00000000";

  SPARE_WORD2                                    : bit_vector := X"00000000";

  SPARE_WORD3                                    : bit_vector := X"00000000";

  SSL_MESSAGE_AUTO                               : string     := "FALSE";

  TECRC_EP_INV                                   : string     := "FALSE";

  TL_RBYPASS                                     : string     := "FALSE";

  TL_RX_RAM_RADDR_LATENCY                        : integer    := 0;

  TL_RX_RAM_RDATA_LATENCY                        : integer    := 2;

  TL_RX_RAM_WRITE_LATENCY                        : integer    := 0;

  TL_TFC_DISABLE                                 : string     := "FALSE";

  TL_TX_CHECKS_DISABLE                           : string     := "FALSE";

  TL_TX_RAM_RADDR_LATENCY                        : integer    := 0;

  TL_TX_RAM_RDATA_LATENCY                        : integer    := 2;

  TL_TX_RAM_WRITE_LATENCY                        : integer    := 0;

  TRN_DW                                         : string     := "FALSE";

  TRN_NP_FC                                      : string     := "FALSE";

  UPCONFIG_CAPABLE                               : string     := "TRUE";

  UPSTREAM_FACING                                : string     := "TRUE";

  UR_ATOMIC                                      : string     := "TRUE";

  UR_CFG1                                        : string     := "TRUE";

  UR_INV_REQ                                     : string     := "TRUE";

  UR_PRS_RESPONSE                                : string     := "TRUE";

  USER_CLK2_DIV2                                 : string     := "FALSE";

  USER_CLK_FREQ                                  : integer    := 3;

  USE_RID_PINS                                   : string     := "FALSE";

  VC0_CPL_INFINITE                               : string     := "TRUE";

  VC0_RX_RAM_LIMIT                               : bit_vector := X"03FF";

  VC0_TOTAL_CREDITS_CD                           : integer    := 127;

  VC0_TOTAL_CREDITS_CH                           : integer    := 31;

  VC0_TOTAL_CREDITS_NPD                          : integer    := 24;

  VC0_TOTAL_CREDITS_NPH                          : integer    := 12;

  VC0_TOTAL_CREDITS_PD                           : integer    := 288;

  VC0_TOTAL_CREDITS_PH                           : integer    := 32;

  VC0_TX_LASTPACKET                              : integer    := 31;

  VC_BASE_PTR                                    : bit_vector := X"10C";

  VC_CAP_ID                                      : bit_vector := X"0002";

  VC_CAP_NEXTPTR                                 : bit_vector := X"000";

  VC_CAP_ON                                      : string     := "FALSE";

  VC_CAP_REJECT_SNOOP_TRANSACTIONS               : string     := "FALSE";

  VC_CAP_VERSION                                 : bit_vector := X"1";

  VSEC_BASE_PTR                                  : bit_vector := X"128";

  VSEC_CAP_HDR_ID                                : bit_vector := X"1234";

  VSEC_CAP_HDR_LENGTH                            : bit_vector := X"018";

  VSEC_CAP_HDR_REVISION                          : bit_vector := X"1";

  VSEC_CAP_ID                                    : bit_vector := X"000B";

  VSEC_CAP_IS_LINK_VISIBLE                       : string     := "TRUE";

  VSEC_CAP_NEXTPTR                               : bit_vector := X"140";

  VSEC_CAP_ON                                    : string     := "FALSE";

  VSEC_CAP_VERSION                               : bit_vector := X"1"

  );

  port (

  -- wrapper input

  -- Common

  user_clk_out                                   : out std_logic;

  user_reset                                     : in std_logic;

  user_lnk_up                                    : in std_logic;

  trn_lnk_up                                     : out std_logic;

  user_rst_n                                     : out std_logic;

  -- Tx

  tx_buf_av                                      : out std_logic_vector(5 downto 0);

  tx_cfg_req                                     : out std_logic;

  tx_err_drop                                    : out std_logic;

  s_axis_tx_tready                               : out std_logic;

  s_axis_tx_tdata                                : in std_logic_vector((C_DATA_WIDTH - 1) downto 0);

  s_axis_tx_tkeep                                : in std_logic_vector((C_DATA_WIDTH / 8 - 1) downto 0);

  s_axis_tx_tlast                                : in std_logic;

  s_axis_tx_tvalid                               : in std_logic;

  s_axis_tx_tuser                                : in std_logic_vector(3 downto 0);

  tx_cfg_gnt                                     : in std_logic;

  -- Rx

  m_axis_rx_tdata                                : out std_logic_vector((C_DATA_WIDTH - 1) downto 0);

  m_axis_rx_tkeep                                : out std_logic_vector((C_DATA_WIDTH / 8 - 1) downto 0);

  m_axis_rx_tlast                                : out std_logic;

  m_axis_rx_tvalid                               : out std_logic;

  m_axis_rx_tready                               : in std_logic;

  m_axis_rx_tuser                                : out std_logic_vector(21 downto 0);

  rx_np_ok                                       : in std_logic;

  rx_np_req                                      : in std_logic;

  -- Flow Control

  fc_cpld                                        : out std_logic_vector(11 downto 0);

  fc_cplh                                        : out std_logic_vector(7 downto 0);

  fc_npd                                         : out std_logic_vector(11 downto 0);

  fc_nph                                         : out std_logic_vector(7 downto 0);

  fc_pd                                          : out std_logic_vector(11 downto 0);

  fc_ph                                          : out std_logic_vector(7 downto 0);

  fc_sel                                         : in std_logic_vector(2 downto 0);

  pl_directed_link_change                        : in std_logic_vector(1 downto 0);

  pl_directed_link_width                         : in std_logic_vector(1 downto 0);

  pl_directed_link_speed                         : in std_logic;

  pl_directed_link_auton                         : in std_logic;

  pl_upstream_prefer_deemph                      : in std_logic;

  pl_downstream_deemph_source                    : in std_logic;

  pl_directed_ltssm_new_vld                      : in std_logic;

  pl_directed_ltssm_new                          : in std_logic_vector (5 downto 0);

  pl_directed_ltssm_stall                        : in std_logic;

  cm_rst_n                                       : in std_logic;

  func_lvl_rst_n                                 : in std_logic;

  pl_transmit_hot_rst                            : in std_logic;

  cfg_mgmt_di                                    : in std_logic_vector(31 downto 0);

  cfg_mgmt_byte_en_n                             : in std_logic_vector(3 downto 0);

  cfg_mgmt_dwaddr                                : in std_logic_vector(9 downto 0);

  cfg_mgmt_wr_rw1c_as_rw_n                       : in std_logic;

  cfg_mgmt_wr_readonly_n                         : in std_logic;

  cfg_mgmt_wr_en_n                               : in std_logic;

  cfg_mgmt_rd_en_n                               : in std_logic;

  cfg_err_malformed_n                            : in std_logic;

  cfg_err_cor_n                                  : in std_logic;

  cfg_err_ur_n                                   : in std_logic;

  cfg_err_ecrc_n                                 : in std_logic;

  cfg_err_cpl_timeout_n                          : in std_logic;

  cfg_err_cpl_abort_n                            : in std_logic;

  cfg_err_cpl_unexpect_n                         : in std_logic;

  cfg_err_poisoned_n                             : in std_logic;

  cfg_err_acs_n                                  : in std_logic;

  cfg_err_atomic_egress_blocked_n                : in std_logic;

  cfg_err_mc_blocked_n                           : in std_logic;

  cfg_err_internal_uncor_n                       : in std_logic;

  cfg_err_internal_cor_n                         : in std_logic;

  cfg_err_posted_n                               : in std_logic;

  cfg_err_locked_n                               : in std_logic;

  cfg_err_norecovery_n                           : in std_logic;

  cfg_err_aer_headerlog                          : in std_logic_vector(127 downto 0);

  cfg_err_tlp_cpl_header                         : in std_logic_vector(47 downto 0);

  cfg_interrupt_n                                : in std_logic;

  cfg_interrupt_di                               : in std_logic_vector(7 downto 0);

  cfg_interrupt_assert_n                         : in std_logic;

  cfg_interrupt_stat_n                           : in std_logic;

  cfg_ds_bus_number                              : in std_logic_vector(7 downto 0);

  cfg_ds_device_number                           : in std_logic_vector(4 downto 0);

  cfg_ds_function_number                         : in std_logic_vector( 2 downto 0);

  cfg_port_number                                : in std_logic_vector(7 downto 0);

  cfg_pm_halt_aspm_l0s_n                         : in std_logic;

  cfg_pm_halt_aspm_l1_n                          : in std_logic;

  cfg_pm_force_state_en_n                        : in std_logic;

  cfg_pm_force_state                             : in std_logic_vector(1 downto 0);

  cfg_pm_wake_n                                  : in std_logic;

  cfg_turnoff_ok                                 : in std_logic;

  cfg_pm_send_pme_to_n                           : in std_logic;

  cfg_pciecap_interrupt_msgnum                   : in std_logic_vector(4 downto 0);

  cfg_trn_pending                                : in std_logic;

  cfg_force_mps                                  : in std_logic_vector( 2 downto 0);

  cfg_force_common_clock_off                     : in std_logic;

  cfg_force_extended_sync_on                     : in std_logic;

  cfg_dsn                                        : in std_logic_vector(63 downto 0);

  cfg_aer_interrupt_msgnum                       : in std_logic_vector(4 downto 0);

  cfg_dev_id                                     : in std_logic_vector(15 downto 0);

  cfg_vend_id                                    : in std_logic_vector(15 downto 0);

  cfg_rev_id                                     : in std_logic_vector(7 downto 0);

  cfg_subsys_id                                  : in std_logic_vector(15 downto 0);

  cfg_subsys_vend_id                             : in std_logic_vector(15 downto 0);

  drp_clk                                        : in std_logic;

  drp_en                                         : in std_logic;

  drp_we                                         : in std_logic;

  drp_addr                                       : in std_logic_vector(8 downto 0);

  drp_di                                         : in std_logic_vector(15 downto 0);

  drp_rdy                                        : out std_logic;

  drp_do                                         : out std_logic_vector(15 downto 0);

  dbg_mode                                       : in std_logic_vector(1 downto 0);

  dbg_sub_mode                                   : in std_logic;

  pl_dbg_mode                                    : in std_logic_vector(2 downto 0);

  pl_sel_lnk_rate                                : out std_logic;

  pl_sel_lnk_width                               : out std_logic_vector(1 downto 0);

  pl_ltssm_state                                 : out std_logic_vector(5 downto 0);

  pl_lane_reversal_mode                          : out std_logic_vector(1 downto 0);

  pl_phy_lnk_up                                  : out std_logic;

  pl_tx_pm_state                                 : out std_logic_vector(2 downto 0);

  pl_rx_pm_state                                 : out std_logic_vector(1 downto 0);

  pl_link_upcfg_cap                              : out std_logic;

  pl_link_gen2_cap                               : out std_logic;

  pl_link_partner_gen2_supported                 : out std_logic;

  pl_initial_link_width                          : out std_logic_vector(2 downto 0);

  pl_directed_change_done                        : out std_logic;

  pl_received_hot_rst                            : out std_logic;

  lnk_clk_en                                     : out std_logic;

  cfg_mgmt_do                                    : out std_logic_vector(31 downto 0);

  cfg_mgmt_rd_wr_done                            : out std_logic;

  cfg_err_aer_headerlog_set                      : out std_logic;

  cfg_err_cpl_rdy                                : out std_logic;

  cfg_interrupt_rdy                              : out std_logic;

  cfg_interrupt_mmenable                         : out std_logic_vector(2 downto 0);

  cfg_interrupt_msienable                        : out std_logic;

  cfg_interrupt_do                               : out std_logic_vector(7 downto 0);

  cfg_interrupt_msixenable                       : out std_logic;

  cfg_interrupt_msixfm                           : out std_logic;

  cfg_bus_number                                 : out std_logic_vector(7 downto 0);

  cfg_device_number                              : out std_logic_vector(4 downto 0);

  cfg_function_number                            : out std_logic_vector(2 downto 0);

  cfg_status                                     : out std_logic_vector(15 downto 0);

  cfg_command                                    : out std_logic_vector(15 downto 0);

  cfg_dstatus                                    : out std_logic_vector(15 downto 0);

  cfg_dcommand                                   : out std_logic_vector(15 downto 0);

  cfg_lstatus                                    : out std_logic_vector(15 downto 0);

  cfg_lcommand                                   : out std_logic_vector(15 downto 0);

  cfg_dcommand2                                  : out std_logic_vector(15 downto 0);

  cfg_received_func_lvl_rst                      : out std_logic;

  cfg_msg_received                               : out std_logic;

  cfg_msg_data                                   : out std_logic_vector(15 downto 0);

  cfg_msg_received_err_cor                       : out std_logic;

  cfg_msg_received_err_non_fatal                 : out std_logic;

  cfg_msg_received_err_fatal                     : out std_logic;

  cfg_msg_received_assert_int_a                  : out std_logic;

  cfg_msg_received_deassert_int_a                : out std_logic;

  cfg_msg_received_assert_int_b                  : out std_logic;

  cfg_msg_received_deassert_int_b                : out std_logic;

  cfg_msg_received_assert_int_c                  : out std_logic;

  cfg_msg_received_deassert_int_c                : out std_logic;

  cfg_msg_received_assert_int_d                  : out std_logic;

  cfg_msg_received_deassert_int_d                : out std_logic;

  cfg_msg_received_pm_pme                        : out std_logic;

  cfg_msg_received_pme_to_ack                    : out std_logic;

  cfg_msg_received_pme_to                        : out std_logic;

  cfg_msg_received_setslotpowerlimit             : out std_logic;

  cfg_msg_received_unlock                        : out std_logic;

  cfg_msg_received_pm_as_nak                     : out std_logic;

  cfg_to_turnoff                                 : out std_logic;

  cfg_pcie_link_state                            : out std_logic_vector(2 downto 0);

  cfg_pm_rcv_as_req_l1_n                         : out std_logic;

  cfg_pm_rcv_enter_l1_n                          : out std_logic;

  cfg_pm_rcv_enter_l23_n                         : out std_logic;

  cfg_pm_rcv_req_ack_n                           : out std_logic;

  cfg_pmcsr_powerstate                           : out std_logic_vector(1 downto 0);

  cfg_pmcsr_pme_en                               : out std_logic;

  cfg_pmcsr_pme_status                           : out std_logic;

  cfg_transaction                                : out std_logic;

  cfg_transaction_type                           : out std_logic;

  cfg_transaction_addr                           : out std_logic_vector(6 downto 0);

  cfg_command_io_enable                          : out std_logic;

  cfg_command_mem_enable                         : out std_logic;

  cfg_command_bus_master_enable                  : out std_logic;

  cfg_command_interrupt_disable                  : out std_logic;

  cfg_command_serr_en                            : out std_logic;

  cfg_bridge_serr_en                             : out std_logic;

  cfg_dev_status_corr_err_detected               : out std_logic;

  cfg_dev_status_non_fatal_err_detected          : out std_logic;

  cfg_dev_status_fatal_err_detected              : out std_logic;

  cfg_dev_status_ur_detected                     : out std_logic;

  cfg_dev_control_corr_err_reporting_en          : out std_logic;

  cfg_dev_control_non_fatal_reporting_en         : out std_logic;

  cfg_dev_control_fatal_err_reporting_en         : out std_logic;

  cfg_dev_control_ur_err_reporting_en            : out std_logic;

  cfg_dev_control_enable_ro                      : out std_logic;

  cfg_dev_control_max_payload                    : out std_logic_vector(2 downto 0);

  cfg_dev_control_ext_tag_en                     : out std_logic;

  cfg_dev_control_phantom_en                     : out std_logic;