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//-----------------------------------------------------------------------------
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//
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// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//-----------------------------------------------------------------------------
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// Project : Series-7 Integrated Block for PCI Express
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// File : cl_a7pcie_x4_pipe_eq.v
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// Version : 1.10
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//------------------------------------------------------------------------------
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// Filename : pipe_eq.v
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// Description : PIPE Equalization Module for 7 Series Transceiver
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// Version : 20.1
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//------------------------------------------------------------------------------
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`timescale 1ns / 1ps
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//---------- PIPE Equalization Module ------------------------------------------
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module cl_a7pcie_x4_pipe_eq #
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(
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parameter PCIE_SIM_MODE = "FALSE",
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parameter PCIE_GT_DEVICE = "GTX",
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parameter PCIE_RXEQ_MODE_GEN3 = 1
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)
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(
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//---------- Input -------------------------------------
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input EQ_CLK,
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input EQ_RST_N,
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input EQ_GEN3,
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input [ 1:0] EQ_TXEQ_CONTROL,
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input [ 3:0] EQ_TXEQ_PRESET,
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input [ 3:0] EQ_TXEQ_PRESET_DEFAULT,
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input [ 5:0] EQ_TXEQ_DEEMPH_IN,
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input [ 1:0] EQ_RXEQ_CONTROL,
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input [ 2:0] EQ_RXEQ_PRESET,
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input [ 5:0] EQ_RXEQ_LFFS,
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input [ 3:0] EQ_RXEQ_TXPRESET,
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input EQ_RXEQ_USER_EN,
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input [17:0] EQ_RXEQ_USER_TXCOEFF,
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input EQ_RXEQ_USER_MODE,
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//---------- Output ------------------------------------
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output EQ_TXEQ_DEEMPH,
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output [ 4:0] EQ_TXEQ_PRECURSOR,
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output [ 6:0] EQ_TXEQ_MAINCURSOR,
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output [ 4:0] EQ_TXEQ_POSTCURSOR,
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output [17:0] EQ_TXEQ_DEEMPH_OUT,
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output EQ_TXEQ_DONE,
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output [ 5:0] EQ_TXEQ_FSM,
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output [17:0] EQ_RXEQ_NEW_TXCOEFF,
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output EQ_RXEQ_LFFS_SEL,
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output EQ_RXEQ_ADAPT_DONE,
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output EQ_RXEQ_DONE,
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output [ 5:0] EQ_RXEQ_FSM
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);
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//---------- Input Registers ---------------------------
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gen3_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gen3_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] txeq_control_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 3:0] txeq_preset_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 5:0] txeq_deemph_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] txeq_control_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 3:0] txeq_preset_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 5:0] txeq_deemph_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rxeq_control_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 2:0] rxeq_preset_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 5:0] rxeq_lffs_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 3:0] rxeq_txpreset_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxeq_user_en_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [17:0] rxeq_user_txcoeff_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxeq_user_mode_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rxeq_control_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 2:0] rxeq_preset_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 5:0] rxeq_lffs_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 3:0] rxeq_txpreset_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxeq_user_en_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [17:0] rxeq_user_txcoeff_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxeq_user_mode_reg2;
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dsmv |
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//---------- Internal Signals --------------------------
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reg [18:0] txeq_preset = 19'd0;
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reg txeq_preset_done = 1'd0;
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reg [ 1:0] txeq_txcoeff_cnt = 2'd0;
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reg [ 2:0] rxeq_preset = 3'd0;
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reg rxeq_preset_valid = 1'd0;
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reg [ 3:0] rxeq_txpreset = 4'd0;
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reg [17:0] rxeq_txcoeff = 18'd0;
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reg [ 2:0] rxeq_cnt = 3'd0;
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reg [ 5:0] rxeq_fs = 6'd0;
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reg [ 5:0] rxeq_lf = 6'd0;
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reg rxeq_new_txcoeff_req = 1'd0;
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//---------- Output Registers --------------------------
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reg [18:0] txeq_txcoeff = 19'd0;
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reg txeq_done = 1'd0;
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reg [ 5:0] fsm_tx = 6'd0;
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reg [17:0] rxeq_new_txcoeff = 18'd0;
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reg rxeq_lffs_sel = 1'd0;
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reg rxeq_adapt_done_reg = 1'd0;
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reg rxeq_adapt_done = 1'd0;
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reg rxeq_done = 1'd0;
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reg [ 5:0] fsm_rx = 6'd0;
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//---------- RXEQ Eye Scan Module Output ---------------
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wire rxeqscan_lffs_sel;
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wire rxeqscan_preset_done;
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wire [17:0] rxeqscan_new_txcoeff;
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wire rxeqscan_new_txcoeff_done;
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wire rxeqscan_adapt_done;
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//---------- FSM ---------------------------------------
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localparam FSM_TXEQ_IDLE = 6'b000001;
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localparam FSM_TXEQ_PRESET = 6'b000010;
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localparam FSM_TXEQ_TXCOEFF = 6'b000100;
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localparam FSM_TXEQ_REMAP = 6'b001000;
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localparam FSM_TXEQ_QUERY = 6'b010000;
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localparam FSM_TXEQ_DONE = 6'b100000;
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localparam FSM_RXEQ_IDLE = 6'b000001;
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localparam FSM_RXEQ_PRESET = 6'b000010;
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localparam FSM_RXEQ_TXCOEFF = 6'b000100;
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localparam FSM_RXEQ_LF = 6'b001000;
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localparam FSM_RXEQ_NEW_TXCOEFF_REQ = 6'b010000;
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localparam FSM_RXEQ_DONE = 6'b100000;
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//---------- TXEQ Presets Look-up Table ----------------
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// TXPRECURSOR = Coefficient range between 0 and 20 units
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// TXMAINCURSOR = Coefficient range between 29 and 80 units
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// TXPOSTCURSOR = Coefficient range between 0 and 31 units
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//------------------------------------------------------
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// Actual Full Swing (FS) = 80
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// Actual Low Frequency (LF) = 29
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// Advertise Full Swing (FS) = 40
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// Advertise Low Frequency (LF) = 15
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//------------------------------------------------------
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// Pre-emphasis = 20 log [80 - (2 * TXPRECURSOR)] / 80], assuming no de-emphasis
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// Main-emphasis = 80 - (TXPRECURSOR + TXPOSTCURSOR)
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// De-emphasis = 20 log [80 - (2 * TXPOSTCURSOR)] / 80], assuming no pre-emphasis
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//------------------------------------------------------
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// Note: TXMAINCURSOR calculated internally in GT
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//------------------------------------------------------
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localparam TXPRECURSOR_00 = 6'd0; // 0.0 dB
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localparam TXMAINCURSOR_00 = 7'd60;
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localparam TXPOSTCURSOR_00 = 6'd20; // -6.0 +/- 1 dB
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localparam TXPRECURSOR_01 = 6'd0; // 0.0 dB
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localparam TXMAINCURSOR_01 = 7'd68; // added 1 to compensate decimal
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localparam TXPOSTCURSOR_01 = 6'd13; // -3.5 +/- 1 dB
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localparam TXPRECURSOR_02 = 6'd0; // 0.0 dB
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localparam TXMAINCURSOR_02 = 7'd64;
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localparam TXPOSTCURSOR_02 = 6'd16; // -4.4 +/- 1.5 dB
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localparam TXPRECURSOR_03 = 6'd0; // 0.0 dB
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localparam TXMAINCURSOR_03 = 7'd70;
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localparam TXPOSTCURSOR_03 = 6'd10; // -2.5 +/- 1 dB
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localparam TXPRECURSOR_04 = 6'd0; // 0.0 dB
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localparam TXMAINCURSOR_04 = 7'd80;
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localparam TXPOSTCURSOR_04 = 6'd0; // 0.0 dB
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localparam TXPRECURSOR_05 = 6'd8; // -1.9 +/- 1 dB
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localparam TXMAINCURSOR_05 = 7'd72;
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localparam TXPOSTCURSOR_05 = 6'd0; // 0.0 dB
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localparam TXPRECURSOR_06 = 6'd10; // -2.5 +/- 1 dB
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localparam TXMAINCURSOR_06 = 7'd70;
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localparam TXPOSTCURSOR_06 = 6'd0; // 0.0 dB
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localparam TXPRECURSOR_07 = 6'd8; // -3.5 +/- 1 dB
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localparam TXMAINCURSOR_07 = 7'd56;
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localparam TXPOSTCURSOR_07 = 6'd16; // -6.0 +/- 1 dB
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localparam TXPRECURSOR_08 = 6'd10; // -3.5 +/- 1 dB
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localparam TXMAINCURSOR_08 = 7'd60;
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localparam TXPOSTCURSOR_08 = 6'd10; // -3.5 +/- 1 dB
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localparam TXPRECURSOR_09 = 6'd13; // -3.5 +/- 1 dB
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localparam TXMAINCURSOR_09 = 7'd68; // added 1 to compensate decimal
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localparam TXPOSTCURSOR_09 = 6'd0; // 0.0 dB
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localparam TXPRECURSOR_10 = 6'd0; // 0.0 dB
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localparam TXMAINCURSOR_10 = 7'd56; // added 1 to compensate decimal
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localparam TXPOSTCURSOR_10 = 6'd25; // 9.5 +/- 1 dB, updated for coefficient rules
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//---------- Input FF ----------------------------------------------------------
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always @ (posedge EQ_CLK)
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begin
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if (!EQ_RST_N)
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begin
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//---------- 1st Stage FF --------------------------
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gen3_reg1 <= 1'd0;
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txeq_control_reg1 <= 2'd0;
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txeq_preset_reg1 <= 4'd0;
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txeq_deemph_reg1 <= 6'd1;
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rxeq_control_reg1 <= 2'd0;
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rxeq_preset_reg1 <= 3'd0;
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rxeq_lffs_reg1 <= 6'd0;
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rxeq_txpreset_reg1 <= 4'd0;
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rxeq_user_en_reg1 <= 1'd0;
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rxeq_user_txcoeff_reg1 <= 18'd0;
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rxeq_user_mode_reg1 <= 1'd0;
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//---------- 2nd Stage FF --------------------------
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gen3_reg2 <= 1'd0;
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txeq_control_reg2 <= 2'd0;
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txeq_preset_reg2 <= 4'd0;
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txeq_deemph_reg2 <= 6'd1;
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rxeq_control_reg2 <= 2'd0;
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rxeq_preset_reg2 <= 3'd0;
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rxeq_lffs_reg2 <= 6'd0;
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rxeq_txpreset_reg2 <= 4'd0;
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rxeq_user_en_reg2 <= 1'd0;
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rxeq_user_txcoeff_reg2 <= 18'd0;
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rxeq_user_mode_reg2 <= 1'd0;
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end
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else
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begin
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//---------- 1st Stage FF --------------------------
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gen3_reg1 <= EQ_GEN3;
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txeq_control_reg1 <= EQ_TXEQ_CONTROL;
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txeq_preset_reg1 <= EQ_TXEQ_PRESET;
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txeq_deemph_reg1 <= EQ_TXEQ_DEEMPH_IN;
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| 293 |
|
|
rxeq_control_reg1 <= EQ_RXEQ_CONTROL;
|
| 294 |
|
|
rxeq_preset_reg1 <= EQ_RXEQ_PRESET;
|
| 295 |
|
|
rxeq_lffs_reg1 <= EQ_RXEQ_LFFS;
|
| 296 |
|
|
rxeq_txpreset_reg1 <= EQ_RXEQ_TXPRESET;
|
| 297 |
|
|
rxeq_user_en_reg1 <= EQ_RXEQ_USER_EN;
|
| 298 |
|
|
rxeq_user_txcoeff_reg1 <= EQ_RXEQ_USER_TXCOEFF;
|
| 299 |
|
|
rxeq_user_mode_reg1 <= EQ_RXEQ_USER_MODE;
|
| 300 |
|
|
//---------- 2nd Stage FF --------------------------
|
| 301 |
|
|
gen3_reg2 <= gen3_reg1;
|
| 302 |
|
|
|
| 303 |
|
|
txeq_control_reg2 <= txeq_control_reg1;
|
| 304 |
|
|
txeq_preset_reg2 <= txeq_preset_reg1;
|
| 305 |
|
|
txeq_deemph_reg2 <= txeq_deemph_reg1;
|
| 306 |
|
|
|
| 307 |
|
|
rxeq_control_reg2 <= rxeq_control_reg1;
|
| 308 |
|
|
rxeq_preset_reg2 <= rxeq_preset_reg1;
|
| 309 |
|
|
rxeq_lffs_reg2 <= rxeq_lffs_reg1;
|
| 310 |
|
|
rxeq_txpreset_reg2 <= rxeq_txpreset_reg1;
|
| 311 |
|
|
rxeq_user_en_reg2 <= rxeq_user_en_reg1;
|
| 312 |
|
|
rxeq_user_txcoeff_reg2 <= rxeq_user_txcoeff_reg1;
|
| 313 |
|
|
rxeq_user_mode_reg2 <= rxeq_user_mode_reg1;
|
| 314 |
|
|
end
|
| 315 |
|
|
|
| 316 |
|
|
end
|
| 317 |
|
|
|
| 318 |
|
|
|
| 319 |
|
|
|
| 320 |
|
|
//---------- TXEQ Preset -------------------------------------------------------
|
| 321 |
|
|
always @ (posedge EQ_CLK)
|
| 322 |
|
|
begin
|
| 323 |
|
|
|
| 324 |
|
|
if (!EQ_RST_N)
|
| 325 |
|
|
begin
|
| 326 |
|
|
|
| 327 |
|
|
//---------- Select TXEQ Preset ----------------
|
| 328 |
|
|
case (EQ_TXEQ_PRESET_DEFAULT)
|
| 329 |
|
|
4'd0 : txeq_preset <= {TXPOSTCURSOR_00, TXMAINCURSOR_00, TXPRECURSOR_00};
|
| 330 |
|
|
4'd1 : txeq_preset <= {TXPOSTCURSOR_01, TXMAINCURSOR_01, TXPRECURSOR_01};
|
| 331 |
|
|
4'd2 : txeq_preset <= {TXPOSTCURSOR_02, TXMAINCURSOR_02, TXPRECURSOR_02};
|
| 332 |
|
|
4'd3 : txeq_preset <= {TXPOSTCURSOR_03, TXMAINCURSOR_03, TXPRECURSOR_03};
|
| 333 |
|
|
4'd4 : txeq_preset <= {TXPOSTCURSOR_04, TXMAINCURSOR_04, TXPRECURSOR_04};
|
| 334 |
|
|
4'd5 : txeq_preset <= {TXPOSTCURSOR_05, TXMAINCURSOR_05, TXPRECURSOR_05};
|
| 335 |
|
|
4'd6 : txeq_preset <= {TXPOSTCURSOR_06, TXMAINCURSOR_06, TXPRECURSOR_06};
|
| 336 |
|
|
4'd7 : txeq_preset <= {TXPOSTCURSOR_07, TXMAINCURSOR_07, TXPRECURSOR_07};
|
| 337 |
|
|
4'd8 : txeq_preset <= {TXPOSTCURSOR_08, TXMAINCURSOR_08, TXPRECURSOR_08};
|
| 338 |
|
|
4'd9 : txeq_preset <= {TXPOSTCURSOR_09, TXMAINCURSOR_09, TXPRECURSOR_09};
|
| 339 |
|
|
4'd10 : txeq_preset <= {TXPOSTCURSOR_10, TXMAINCURSOR_10, TXPRECURSOR_10};
|
| 340 |
|
|
default : txeq_preset <= 19'd4;
|
| 341 |
|
|
endcase
|
| 342 |
|
|
|
| 343 |
|
|
txeq_preset_done <= 1'd0;
|
| 344 |
|
|
end
|
| 345 |
|
|
else
|
| 346 |
|
|
begin
|
| 347 |
|
|
if (fsm_tx == FSM_TXEQ_PRESET)
|
| 348 |
|
|
begin
|
| 349 |
|
|
|
| 350 |
|
|
//---------- Select TXEQ Preset ----------------
|
| 351 |
|
|
case (txeq_preset_reg2)
|
| 352 |
|
|
4'd0 : txeq_preset <= {TXPOSTCURSOR_00, TXMAINCURSOR_00, TXPRECURSOR_00};
|
| 353 |
|
|
4'd1 : txeq_preset <= {TXPOSTCURSOR_01, TXMAINCURSOR_01, TXPRECURSOR_01};
|
| 354 |
|
|
4'd2 : txeq_preset <= {TXPOSTCURSOR_02, TXMAINCURSOR_02, TXPRECURSOR_02};
|
| 355 |
|
|
4'd3 : txeq_preset <= {TXPOSTCURSOR_03, TXMAINCURSOR_03, TXPRECURSOR_03};
|
| 356 |
|
|
4'd4 : txeq_preset <= {TXPOSTCURSOR_04, TXMAINCURSOR_04, TXPRECURSOR_04};
|
| 357 |
|
|
4'd5 : txeq_preset <= {TXPOSTCURSOR_05, TXMAINCURSOR_05, TXPRECURSOR_05};
|
| 358 |
|
|
4'd6 : txeq_preset <= {TXPOSTCURSOR_06, TXMAINCURSOR_06, TXPRECURSOR_06};
|
| 359 |
|
|
4'd7 : txeq_preset <= {TXPOSTCURSOR_07, TXMAINCURSOR_07, TXPRECURSOR_07};
|
| 360 |
|
|
4'd8 : txeq_preset <= {TXPOSTCURSOR_08, TXMAINCURSOR_08, TXPRECURSOR_08};
|
| 361 |
|
|
4'd9 : txeq_preset <= {TXPOSTCURSOR_09, TXMAINCURSOR_09, TXPRECURSOR_09};
|
| 362 |
|
|
4'd10 : txeq_preset <= {TXPOSTCURSOR_10, TXMAINCURSOR_10, TXPRECURSOR_10};
|
| 363 |
|
|
default : txeq_preset <= 19'd4;
|
| 364 |
|
|
endcase
|
| 365 |
|
|
|
| 366 |
|
|
txeq_preset_done <= 1'd1;
|
| 367 |
|
|
end
|
| 368 |
|
|
else
|
| 369 |
|
|
begin
|
| 370 |
|
|
txeq_preset <= txeq_preset;
|
| 371 |
|
|
txeq_preset_done <= 1'd0;
|
| 372 |
|
|
end
|
| 373 |
|
|
end
|
| 374 |
|
|
|
| 375 |
|
|
end
|
| 376 |
|
|
|
| 377 |
|
|
|
| 378 |
|
|
|
| 379 |
|
|
//---------- TXEQ FSM ----------------------------------------------------------
|
| 380 |
|
|
always @ (posedge EQ_CLK)
|
| 381 |
|
|
begin
|
| 382 |
|
|
|
| 383 |
|
|
if (!EQ_RST_N)
|
| 384 |
|
|
begin
|
| 385 |
|
|
fsm_tx <= FSM_TXEQ_IDLE;
|
| 386 |
|
|
txeq_txcoeff <= 19'd0;
|
| 387 |
|
|
txeq_txcoeff_cnt <= 2'd0;
|
| 388 |
|
|
txeq_done <= 1'd0;
|
| 389 |
|
|
end
|
| 390 |
|
|
else
|
| 391 |
|
|
begin
|
| 392 |
|
|
|
| 393 |
|
|
case (fsm_tx)
|
| 394 |
|
|
|
| 395 |
|
|
//---------- Idle State ----------------------------
|
| 396 |
|
|
FSM_TXEQ_IDLE :
|
| 397 |
|
|
|
| 398 |
|
|
begin
|
| 399 |
|
|
|
| 400 |
|
|
case (txeq_control_reg2)
|
| 401 |
|
|
|
| 402 |
|
|
//---------- Idle ------------------------------
|
| 403 |
|
|
2'd0 :
|
| 404 |
|
|
begin
|
| 405 |
|
|
fsm_tx <= FSM_TXEQ_IDLE;
|
| 406 |
|
|
txeq_txcoeff <= txeq_txcoeff;
|
| 407 |
|
|
txeq_txcoeff_cnt <= 2'd0;
|
| 408 |
|
|
txeq_done <= 1'd0;
|
| 409 |
|
|
end
|
| 410 |
|
|
|
| 411 |
|
|
//---------- Process TXEQ Preset ---------------
|
| 412 |
|
|
2'd1 :
|
| 413 |
|
|
begin
|
| 414 |
|
|
fsm_tx <= FSM_TXEQ_PRESET;
|
| 415 |
|
|
txeq_txcoeff <= txeq_txcoeff;
|
| 416 |
|
|
txeq_txcoeff_cnt <= 2'd0;
|
| 417 |
|
|
txeq_done <= 1'd0;
|
| 418 |
|
|
end
|
| 419 |
|
|
|
| 420 |
|
|
//---------- Coefficient -----------------------
|
| 421 |
|
|
2'd2 :
|
| 422 |
|
|
begin
|
| 423 |
|
|
fsm_tx <= FSM_TXEQ_TXCOEFF;
|
| 424 |
|
|
txeq_txcoeff <= {txeq_deemph_reg2, txeq_txcoeff[18:6]};
|
| 425 |
|
|
txeq_txcoeff_cnt <= 2'd1;
|
| 426 |
|
|
txeq_done <= 1'd0;
|
| 427 |
|
|
end
|
| 428 |
|
|
|
| 429 |
|
|
//---------- Query -----------------------------
|
| 430 |
|
|
2'd3 :
|
| 431 |
|
|
begin
|
| 432 |
|
|
fsm_tx <= FSM_TXEQ_QUERY;
|
| 433 |
|
|
txeq_txcoeff <= txeq_txcoeff;
|
| 434 |
|
|
txeq_txcoeff_cnt <= 2'd0;
|
| 435 |
|
|
txeq_done <= 1'd0;
|
| 436 |
|
|
end
|
| 437 |
|
|
|
| 438 |
|
|
//---------- Default ---------------------------
|
| 439 |
|
|
default :
|
| 440 |
|
|
begin
|
| 441 |
|
|
fsm_tx <= FSM_TXEQ_IDLE;
|
| 442 |
|
|
txeq_txcoeff <= txeq_txcoeff;
|
| 443 |
|
|
txeq_txcoeff_cnt <= 2'd0;
|
| 444 |
|
|
txeq_done <= 1'd0;
|
| 445 |
|
|
end
|
| 446 |
|
|
|
| 447 |
|
|
endcase
|
| 448 |
|
|
|
| 449 |
|
|
end
|
| 450 |
|
|
|
| 451 |
|
|
//---------- Process TXEQ Preset -------------------
|
| 452 |
|
|
FSM_TXEQ_PRESET :
|
| 453 |
|
|
|
| 454 |
|
|
begin
|
| 455 |
|
|
fsm_tx <= (txeq_preset_done ? FSM_TXEQ_DONE : FSM_TXEQ_PRESET);
|
| 456 |
|
|
txeq_txcoeff <= txeq_preset;
|
| 457 |
|
|
txeq_txcoeff_cnt <= 2'd0;
|
| 458 |
|
|
txeq_done <= 1'd0;
|
| 459 |
|
|
end
|
| 460 |
|
|
|
| 461 |
|
|
//---------- Latch Link Partner TX Coefficient -----
|
| 462 |
|
|
FSM_TXEQ_TXCOEFF :
|
| 463 |
|
|
|
| 464 |
|
|
begin
|
| 465 |
|
|
fsm_tx <= ((txeq_txcoeff_cnt == 2'd2) ? FSM_TXEQ_REMAP : FSM_TXEQ_TXCOEFF);
|
| 466 |
|
|
|
| 467 |
|
|
//---------- Shift in extra bit for TXMAINCURSOR
|
| 468 |
|
|
if (txeq_txcoeff_cnt == 2'd1)
|
| 469 |
|
|
txeq_txcoeff <= {1'd0, txeq_deemph_reg2, txeq_txcoeff[18:7]};
|
| 470 |
|
|
else
|
| 471 |
|
|
txeq_txcoeff <= {txeq_deemph_reg2, txeq_txcoeff[18:6]};
|
| 472 |
|
|
|
| 473 |
|
|
txeq_txcoeff_cnt <= txeq_txcoeff_cnt + 2'd1;
|
| 474 |
|
|
txeq_done <= 1'd0;
|
| 475 |
|
|
end
|
| 476 |
|
|
|
| 477 |
|
|
//---------- Remap to GT TX Coefficient ------------
|
| 478 |
|
|
FSM_TXEQ_REMAP :
|
| 479 |
|
|
|
| 480 |
|
|
begin
|
| 481 |
|
|
fsm_tx <= FSM_TXEQ_DONE;
|
| 482 |
|
|
txeq_txcoeff <= txeq_txcoeff << 1; // Multiply by 2x
|
| 483 |
|
|
txeq_txcoeff_cnt <= 2'd0;
|
| 484 |
|
|
txeq_done <= 1'd0;
|
| 485 |
|
|
end
|
| 486 |
|
|
|
| 487 |
|
|
//---------- Query TXEQ Coefficient ----------------
|
| 488 |
|
|
FSM_TXEQ_QUERY:
|
| 489 |
|
|
|
| 490 |
|
|
begin
|
| 491 |
|
|
fsm_tx <= FSM_TXEQ_DONE;
|
| 492 |
|
|
txeq_txcoeff <= txeq_txcoeff;
|
| 493 |
|
|
txeq_txcoeff_cnt <= 2'd0;
|
| 494 |
|
|
txeq_done <= 1'd0;
|
| 495 |
|
|
end
|
| 496 |
|
|
|
| 497 |
|
|
//---------- Done ----------------------------------
|
| 498 |
|
|
FSM_TXEQ_DONE :
|
| 499 |
|
|
|
| 500 |
|
|
begin
|
| 501 |
|
|
fsm_tx <= ((txeq_control_reg2 == 2'd0) ? FSM_TXEQ_IDLE : FSM_TXEQ_DONE);
|
| 502 |
|
|
txeq_txcoeff <= txeq_txcoeff;
|
| 503 |
|
|
txeq_txcoeff_cnt <= 2'd0;
|
| 504 |
|
|
txeq_done <= 1'd1;
|
| 505 |
|
|
end
|
| 506 |
|
|
|
| 507 |
|
|
//---------- Default State -------------------------
|
| 508 |
|
|
default :
|
| 509 |
|
|
begin
|
| 510 |
|
|
fsm_tx <= FSM_TXEQ_IDLE;
|
| 511 |
|
|
txeq_txcoeff <= 19'd0;
|
| 512 |
|
|
txeq_txcoeff_cnt <= 2'd0;
|
| 513 |
|
|
txeq_done <= 1'd0;
|
| 514 |
|
|
end
|
| 515 |
|
|
|
| 516 |
|
|
endcase
|
| 517 |
|
|
|
| 518 |
|
|
end
|
| 519 |
|
|
|
| 520 |
|
|
end
|
| 521 |
|
|
|
| 522 |
|
|
|
| 523 |
|
|
|
| 524 |
|
|
//---------- RXEQ FSM ----------------------------------------------------------
|
| 525 |
|
|
always @ (posedge EQ_CLK)
|
| 526 |
|
|
begin
|
| 527 |
|
|
|
| 528 |
|
|
if (!EQ_RST_N)
|
| 529 |
|
|
begin
|
| 530 |
|
|
fsm_rx <= FSM_RXEQ_IDLE;
|
| 531 |
|
|
rxeq_preset <= 3'd0;
|
| 532 |
|
|
rxeq_preset_valid <= 1'd0;
|
| 533 |
|
|
rxeq_txpreset <= 4'd0;
|
| 534 |
|
|
rxeq_txcoeff <= 18'd0;
|
| 535 |
|
|
rxeq_cnt <= 3'd0;
|
| 536 |
|
|
rxeq_fs <= 6'd0;
|
| 537 |
|
|
rxeq_lf <= 6'd0;
|
| 538 |
|
|
rxeq_new_txcoeff_req <= 1'd0;
|
| 539 |
|
|
rxeq_new_txcoeff <= 18'd0;
|
| 540 |
|
|
rxeq_lffs_sel <= 1'd0;
|
| 541 |
|
|
rxeq_adapt_done_reg <= 1'd0;
|
| 542 |
|
|
rxeq_adapt_done <= 1'd0;
|
| 543 |
|
|
rxeq_done <= 1'd0;
|
| 544 |
|
|
end
|
| 545 |
|
|
else
|
| 546 |
|
|
begin
|
| 547 |
|
|
|
| 548 |
|
|
case (fsm_rx)
|
| 549 |
|
|
|
| 550 |
|
|
//---------- Idle State ----------------------------
|
| 551 |
|
|
FSM_RXEQ_IDLE :
|
| 552 |
|
|
|
| 553 |
|
|
begin
|
| 554 |
|
|
|
| 555 |
|
|
case (rxeq_control_reg2)
|
| 556 |
|
|
|
| 557 |
|
|
//---------- Process RXEQ Preset ---------------
|
| 558 |
|
|
2'd1 :
|
| 559 |
|
|
begin
|
| 560 |
|
|
fsm_rx <= FSM_RXEQ_PRESET;
|
| 561 |
|
|
rxeq_preset <= rxeq_preset_reg2;
|
| 562 |
|
|
rxeq_preset_valid <= 1'd0;
|
| 563 |
|
|
rxeq_txpreset <= rxeq_txpreset;
|
| 564 |
|
|
rxeq_txcoeff <= rxeq_txcoeff;
|
| 565 |
|
|
rxeq_cnt <= 3'd0;
|
| 566 |
|
|
rxeq_fs <= rxeq_fs;
|
| 567 |
|
|
rxeq_lf <= rxeq_lf;
|
| 568 |
|
|
rxeq_new_txcoeff_req <= 1'd0;
|
| 569 |
|
|
rxeq_new_txcoeff <= rxeq_new_txcoeff;
|
| 570 |
|
|
rxeq_lffs_sel <= 1'd0;
|
| 571 |
|
|
rxeq_adapt_done_reg <= 1'd0;
|
| 572 |
|
|
rxeq_adapt_done <= 1'd0;
|
| 573 |
|
|
rxeq_done <= 1'd0;
|
| 574 |
|
|
end
|
| 575 |
|
|
|
| 576 |
|
|
//---------- Request New TX Coefficient --------
|
| 577 |
|
|
2'd2 :
|
| 578 |
|
|
begin
|
| 579 |
|
|
fsm_rx <= FSM_RXEQ_TXCOEFF;
|
| 580 |
|
|
rxeq_preset <= rxeq_preset;
|
| 581 |
|
|
rxeq_preset_valid <= 1'd0;
|
| 582 |
|
|
rxeq_txpreset <= rxeq_txpreset_reg2;
|
| 583 |
|
|
rxeq_txcoeff <= {txeq_deemph_reg2, rxeq_txcoeff[17:6]};
|
| 584 |
|
|
rxeq_cnt <= 3'd1;
|
| 585 |
|
|
rxeq_fs <= rxeq_lffs_reg2;
|
| 586 |
|
|
rxeq_lf <= rxeq_lf;
|
| 587 |
|
|
rxeq_new_txcoeff_req <= 1'd0;
|
| 588 |
|
|
rxeq_new_txcoeff <= rxeq_new_txcoeff;
|
| 589 |
|
|
rxeq_lffs_sel <= 1'd0;
|
| 590 |
|
|
rxeq_adapt_done_reg <= rxeq_adapt_done_reg;
|
| 591 |
|
|
rxeq_adapt_done <= 1'd0;
|
| 592 |
|
|
rxeq_done <= 1'd0;
|
| 593 |
|
|
end
|
| 594 |
|
|
|
| 595 |
|
|
//---------- Phase2/3 Bypass (reuse logic from rxeq_control = 2 ----
|
| 596 |
|
|
2'd3 :
|
| 597 |
|
|
begin
|
| 598 |
|
|
fsm_rx <= FSM_RXEQ_TXCOEFF;
|
| 599 |
|
|
rxeq_preset <= rxeq_preset;
|
| 600 |
|
|
rxeq_preset_valid <= 1'd0;
|
| 601 |
|
|
rxeq_txpreset <= rxeq_txpreset_reg2;
|
| 602 |
|
|
rxeq_txcoeff <= {txeq_deemph_reg2, rxeq_txcoeff[17:6]};
|
| 603 |
|
|
rxeq_cnt <= 3'd1;
|
| 604 |
|
|
rxeq_fs <= rxeq_lffs_reg2;
|
| 605 |
|
|
rxeq_lf <= rxeq_lf;
|
| 606 |
|
|
rxeq_new_txcoeff_req <= 1'd0;
|
| 607 |
|
|
rxeq_new_txcoeff <= rxeq_new_txcoeff;
|
| 608 |
|
|
rxeq_lffs_sel <= 1'd0;
|
| 609 |
|
|
rxeq_adapt_done_reg <= rxeq_adapt_done_reg;
|
| 610 |
|
|
rxeq_adapt_done <= 1'd0;
|
| 611 |
|
|
rxeq_done <= 1'd0;
|
| 612 |
|
|
end
|
| 613 |
|
|
|
| 614 |
|
|
//---------- Default ---------------------------
|
| 615 |
|
|
default :
|
| 616 |
|
|
begin
|
| 617 |
|
|
fsm_rx <= FSM_RXEQ_IDLE;
|
| 618 |
|
|
rxeq_preset <= rxeq_preset;
|
| 619 |
|
|
rxeq_preset_valid <= 1'd0;
|
| 620 |
|
|
rxeq_txpreset <= rxeq_txpreset;
|
| 621 |
|
|
rxeq_txcoeff <= rxeq_txcoeff;
|
| 622 |
|
|
rxeq_cnt <= 3'd0;
|
| 623 |
|
|
rxeq_fs <= rxeq_fs;
|
| 624 |
|
|
rxeq_lf <= rxeq_lf;
|
| 625 |
|
|
rxeq_new_txcoeff_req <= 1'd0;
|
| 626 |
|
|
rxeq_new_txcoeff <= rxeq_new_txcoeff;
|
| 627 |
|
|
rxeq_lffs_sel <= 1'd0;
|
| 628 |
|
|
rxeq_adapt_done_reg <= rxeq_adapt_done_reg;
|
| 629 |
|
|
rxeq_adapt_done <= 1'd0;
|
| 630 |
|
|
rxeq_done <= 1'd0;
|
| 631 |
|
|
end
|
| 632 |
|
|
|
| 633 |
|
|
endcase
|
| 634 |
|
|
|
| 635 |
|
|
end
|
| 636 |
|
|
|
| 637 |
|
|
//---------- Process RXEQ Preset -------------------
|
| 638 |
|
|
FSM_RXEQ_PRESET :
|
| 639 |
|
|
|
| 640 |
|
|
begin
|
| 641 |
|
|
fsm_rx <= (rxeqscan_preset_done ? FSM_RXEQ_DONE : FSM_RXEQ_PRESET);
|
| 642 |
|
|
rxeq_preset <= rxeq_preset_reg2;
|
| 643 |
|
|
rxeq_preset_valid <= 1'd1;
|
| 644 |
|
|
rxeq_txpreset <= rxeq_txpreset;
|
| 645 |
|
|
rxeq_txcoeff <= rxeq_txcoeff;
|
| 646 |
|
|
rxeq_cnt <= 3'd0;
|
| 647 |
|
|
rxeq_fs <= rxeq_fs;
|
| 648 |
|
|
rxeq_lf <= rxeq_lf;
|
| 649 |
|
|
rxeq_new_txcoeff_req <= 1'd0;
|
| 650 |
|
|
rxeq_new_txcoeff <= rxeq_new_txcoeff;
|
| 651 |
|
|
rxeq_lffs_sel <= 1'd0;
|
| 652 |
|
|
rxeq_adapt_done_reg <= rxeq_adapt_done_reg;
|
| 653 |
|
|
rxeq_adapt_done <= 1'd0;
|
| 654 |
|
|
rxeq_done <= 1'd0;
|
| 655 |
|
|
end
|
| 656 |
|
|
|
| 657 |
|
|
//---------- Shift-in Link Partner TX Coefficient and Preset
|
| 658 |
|
|
FSM_RXEQ_TXCOEFF :
|
| 659 |
|
|
|
| 660 |
|
|
begin
|
| 661 |
|
|
fsm_rx <= ((rxeq_cnt == 3'd2) ? FSM_RXEQ_LF : FSM_RXEQ_TXCOEFF);
|
| 662 |
|
|
rxeq_preset <= rxeq_preset;
|
| 663 |
|
|
rxeq_preset_valid <= 1'd0;
|
| 664 |
|
|
rxeq_txpreset <= rxeq_txpreset_reg2;
|
| 665 |
|
|
rxeq_txcoeff <= {txeq_deemph_reg2, rxeq_txcoeff[17:6]};
|
| 666 |
|
|
rxeq_cnt <= rxeq_cnt + 2'd1;
|
| 667 |
|
|
rxeq_fs <= rxeq_fs;
|
| 668 |
|
|
rxeq_lf <= rxeq_lf;
|
| 669 |
|
|
rxeq_new_txcoeff_req <= 1'd0;
|
| 670 |
|
|
rxeq_new_txcoeff <= rxeq_new_txcoeff;
|
| 671 |
|
|
rxeq_lffs_sel <= 1'd1;
|
| 672 |
|
|
rxeq_adapt_done_reg <= rxeq_adapt_done_reg;
|
| 673 |
|
|
rxeq_adapt_done <= 1'd0;
|
| 674 |
|
|
rxeq_done <= 1'd0;
|
| 675 |
|
|
end
|
| 676 |
|
|
|
| 677 |
|
|
//---------- Read Low Frequency (LF) Value ---------
|
| 678 |
|
|
FSM_RXEQ_LF :
|
| 679 |
|
|
begin
|
| 680 |
|
|
fsm_rx <= ((rxeq_cnt == 3'd7) ? FSM_RXEQ_NEW_TXCOEFF_REQ : FSM_RXEQ_LF);
|
| 681 |
|
|
rxeq_preset <= rxeq_preset;
|
| 682 |
|
|
rxeq_preset_valid <= 1'd0;
|
| 683 |
|
|
rxeq_txpreset <= rxeq_txpreset;
|
| 684 |
|
|
rxeq_txcoeff <= rxeq_txcoeff;
|
| 685 |
|
|
rxeq_cnt <= rxeq_cnt + 2'd1;
|
| 686 |
|
|
rxeq_fs <= rxeq_fs;
|
| 687 |
|
|
rxeq_lf <= ((rxeq_cnt == 3'd7) ? rxeq_lffs_reg2 : rxeq_lf);
|
| 688 |
|
|
rxeq_new_txcoeff_req <= 1'd0;
|
| 689 |
|
|
rxeq_new_txcoeff <= rxeq_new_txcoeff;
|
| 690 |
|
|
rxeq_lffs_sel <= 1'd1;
|
| 691 |
|
|
rxeq_adapt_done_reg <= rxeq_adapt_done_reg;
|
| 692 |
|
|
rxeq_adapt_done <= 1'd0;
|
| 693 |
|
|
rxeq_done <= 1'd0;
|
| 694 |
|
|
end
|
| 695 |
|
|
|
| 696 |
|
|
//---------- Request New TX Coefficient ------------
|
| 697 |
|
|
FSM_RXEQ_NEW_TXCOEFF_REQ :
|
| 698 |
|
|
|
| 699 |
|
|
begin
|
| 700 |
|
|
rxeq_preset <= rxeq_preset;
|
| 701 |
|
|
rxeq_preset_valid <= 1'd0;
|
| 702 |
|
|
rxeq_txpreset <= rxeq_txpreset;
|
| 703 |
|
|
rxeq_txcoeff <= rxeq_txcoeff;
|
| 704 |
|
|
rxeq_cnt <= 3'd0;
|
| 705 |
|
|
rxeq_fs <= rxeq_fs;
|
| 706 |
|
|
rxeq_lf <= rxeq_lf;
|
| 707 |
|
|
|
| 708 |
|
|
if (rxeqscan_new_txcoeff_done)
|
| 709 |
|
|
begin
|
| 710 |
|
|
fsm_rx <= FSM_RXEQ_DONE;
|
| 711 |
|
|
rxeq_new_txcoeff_req <= 1'd0;
|
| 712 |
|
|
rxeq_new_txcoeff <= rxeqscan_lffs_sel ? {14'd0, rxeqscan_new_txcoeff[3:0]} : rxeqscan_new_txcoeff;
|
| 713 |
|
|
rxeq_lffs_sel <= rxeqscan_lffs_sel;
|
| 714 |
|
|
rxeq_adapt_done_reg <= rxeqscan_adapt_done || rxeq_adapt_done_reg;
|
| 715 |
|
|
rxeq_adapt_done <= rxeqscan_adapt_done || rxeq_adapt_done_reg;
|
| 716 |
|
|
rxeq_done <= 1'd1;
|
| 717 |
|
|
end
|
| 718 |
|
|
else
|
| 719 |
|
|
begin
|
| 720 |
|
|
fsm_rx <= FSM_RXEQ_NEW_TXCOEFF_REQ;
|
| 721 |
|
|
rxeq_new_txcoeff_req <= 1'd1;
|
| 722 |
|
|
rxeq_new_txcoeff <= rxeq_new_txcoeff;
|
| 723 |
|
|
rxeq_lffs_sel <= 1'd0;
|
| 724 |
|
|
rxeq_adapt_done_reg <= rxeq_adapt_done_reg;
|
| 725 |
|
|
rxeq_adapt_done <= 1'd0;
|
| 726 |
|
|
rxeq_done <= 1'd0;
|
| 727 |
|
|
end
|
| 728 |
|
|
|
| 729 |
|
|
end
|
| 730 |
|
|
|
| 731 |
|
|
//---------- RXEQ Done -----------------------------
|
| 732 |
|
|
FSM_RXEQ_DONE :
|
| 733 |
|
|
|
| 734 |
|
|
begin
|
| 735 |
|
|
fsm_rx <= ((rxeq_control_reg2 == 2'd0) ? FSM_RXEQ_IDLE : FSM_RXEQ_DONE);
|
| 736 |
|
|
rxeq_preset <= rxeq_preset;
|
| 737 |
|
|
rxeq_preset_valid <= 1'd0;
|
| 738 |
|
|
rxeq_txpreset <= rxeq_txpreset;
|
| 739 |
|
|
rxeq_txcoeff <= rxeq_txcoeff;
|
| 740 |
|
|
rxeq_cnt <= 3'd0;
|
| 741 |
|
|
rxeq_fs <= rxeq_fs;
|
| 742 |
|
|
rxeq_lf <= rxeq_lf;
|
| 743 |
|
|
rxeq_new_txcoeff_req <= 1'd0;
|
| 744 |
|
|
rxeq_new_txcoeff <= rxeq_new_txcoeff;
|
| 745 |
|
|
rxeq_lffs_sel <= rxeq_lffs_sel;
|
| 746 |
|
|
rxeq_adapt_done_reg <= rxeq_adapt_done_reg;
|
| 747 |
|
|
rxeq_adapt_done <= rxeq_adapt_done;
|
| 748 |
|
|
rxeq_done <= 1'd1;
|
| 749 |
|
|
end
|
| 750 |
|
|
|
| 751 |
|
|
//---------- Default State -------------------------
|
| 752 |
|
|
default :
|
| 753 |
|
|
begin
|
| 754 |
|
|
fsm_rx <= FSM_RXEQ_IDLE;
|
| 755 |
|
|
rxeq_preset <= 3'd0;
|
| 756 |
|
|
rxeq_preset_valid <= 1'd0;
|
| 757 |
|
|
rxeq_txpreset <= 4'd0;
|
| 758 |
|
|
rxeq_txcoeff <= 18'd0;
|
| 759 |
|
|
rxeq_cnt <= 3'd0;
|
| 760 |
|
|
rxeq_fs <= 6'd0;
|
| 761 |
|
|
rxeq_lf <= 6'd0;
|
| 762 |
|
|
rxeq_new_txcoeff_req <= 1'd0;
|
| 763 |
|
|
rxeq_new_txcoeff <= 18'd0;
|
| 764 |
|
|
rxeq_lffs_sel <= 1'd0;
|
| 765 |
|
|
rxeq_adapt_done_reg <= 1'd0;
|
| 766 |
|
|
rxeq_adapt_done <= 1'd0;
|
| 767 |
|
|
rxeq_done <= 1'd0;
|
| 768 |
|
|
end
|
| 769 |
|
|
|
| 770 |
|
|
endcase
|
| 771 |
|
|
|
| 772 |
|
|
end
|
| 773 |
|
|
|
| 774 |
|
|
end
|
| 775 |
|
|
|
| 776 |
|
|
|
| 777 |
|
|
|
| 778 |
|
|
//---------- RXEQ Eye Scan Module ----------------------------------------------
|
| 779 |
|
|
cl_a7pcie_x4_rxeq_scan #
|
| 780 |
|
|
(
|
| 781 |
|
|
.PCIE_SIM_MODE (PCIE_SIM_MODE),
|
| 782 |
|
|
.PCIE_GT_DEVICE (PCIE_GT_DEVICE),
|
| 783 |
|
|
.PCIE_RXEQ_MODE_GEN3 (PCIE_RXEQ_MODE_GEN3)
|
| 784 |
|
|
)
|
| 785 |
|
|
|
| 786 |
|
|
rxeq_scan_i
|
| 787 |
|
|
(
|
| 788 |
|
|
|
| 789 |
|
|
//---------- Input -------------------------------------
|
| 790 |
|
|
.RXEQSCAN_CLK (EQ_CLK),
|
| 791 |
|
|
.RXEQSCAN_RST_N (EQ_RST_N),
|
| 792 |
|
|
.RXEQSCAN_CONTROL (rxeq_control_reg2),
|
| 793 |
|
|
.RXEQSCAN_FS (rxeq_fs),
|
| 794 |
|
|
.RXEQSCAN_LF (rxeq_lf),
|
| 795 |
|
|
.RXEQSCAN_PRESET (rxeq_preset),
|
| 796 |
|
|
.RXEQSCAN_PRESET_VALID (rxeq_preset_valid),
|
| 797 |
|
|
.RXEQSCAN_TXPRESET (rxeq_txpreset),
|
| 798 |
|
|
.RXEQSCAN_TXCOEFF (rxeq_txcoeff),
|
| 799 |
|
|
.RXEQSCAN_NEW_TXCOEFF_REQ (rxeq_new_txcoeff_req),
|
| 800 |
|
|
|
| 801 |
|
|
//---------- Output ------------------------------------
|
| 802 |
|
|
.RXEQSCAN_PRESET_DONE (rxeqscan_preset_done),
|
| 803 |
|
|
.RXEQSCAN_NEW_TXCOEFF (rxeqscan_new_txcoeff),
|
| 804 |
|
|
.RXEQSCAN_NEW_TXCOEFF_DONE (rxeqscan_new_txcoeff_done),
|
| 805 |
|
|
.RXEQSCAN_LFFS_SEL (rxeqscan_lffs_sel),
|
| 806 |
|
|
.RXEQSCAN_ADAPT_DONE (rxeqscan_adapt_done)
|
| 807 |
|
|
|
| 808 |
|
|
);
|
| 809 |
|
|
|
| 810 |
|
|
|
| 811 |
|
|
|
| 812 |
|
|
//---------- PIPE EQ Output ----------------------------------------------------
|
| 813 |
|
|
assign EQ_TXEQ_DEEMPH = txeq_txcoeff[0];
|
| 814 |
|
|
assign EQ_TXEQ_PRECURSOR = gen3_reg2 ? txeq_txcoeff[ 4: 0] : 5'h00;
|
| 815 |
|
|
assign EQ_TXEQ_MAINCURSOR = gen3_reg2 ? txeq_txcoeff[12: 6] : 7'h00;
|
| 816 |
|
|
assign EQ_TXEQ_POSTCURSOR = gen3_reg2 ? txeq_txcoeff[17:13] : 5'h00;
|
| 817 |
|
|
assign EQ_TXEQ_DEEMPH_OUT = {1'd0, txeq_txcoeff[18:14], txeq_txcoeff[12:7], 1'd0, txeq_txcoeff[5:1]}; // Divide by 2x
|
| 818 |
|
|
assign EQ_TXEQ_DONE = txeq_done;
|
| 819 |
|
|
assign EQ_TXEQ_FSM = fsm_tx;
|
| 820 |
|
|
|
| 821 |
|
|
assign EQ_RXEQ_NEW_TXCOEFF = rxeq_user_en_reg2 ? rxeq_user_txcoeff_reg2 : rxeq_new_txcoeff;
|
| 822 |
|
|
assign EQ_RXEQ_LFFS_SEL = rxeq_user_en_reg2 ? rxeq_user_mode_reg2 : rxeq_lffs_sel;
|
| 823 |
|
|
assign EQ_RXEQ_ADAPT_DONE = rxeq_adapt_done;
|
| 824 |
|
|
assign EQ_RXEQ_DONE = rxeq_done;
|
| 825 |
|
|
assign EQ_RXEQ_FSM = fsm_rx;
|
| 826 |
|
|
|
| 827 |
|
|
|
| 828 |
|
|
|
| 829 |
|
|
endmodule
|
