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//-----------------------------------------------------------------------------
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//
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// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//-----------------------------------------------------------------------------
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// Project : Series-7 Integrated Block for PCI Express
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// File : cl_a7pcie_x4_qpll_drp.v
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// Version : 1.11
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//------------------------------------------------------------------------------
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// Filename : qpll_drp.v
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// Description : QPLL DRP Module for 7 Series Transceiver
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// Version : 18.2
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//------------------------------------------------------------------------------
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`timescale 1ns / 1ps
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//---------- QPLL DRP Module ---------------------------------------------------
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module cl_a7pcie_x4_qpll_drp #
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(
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parameter PCIE_GT_DEVICE = "GTX", // PCIe GT device
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parameter PCIE_USE_MODE = "3.0", // PCIe use mode
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parameter PCIE_PLL_SEL = "CPLL", // PCIe PLL select for Gen1/Gen2 only
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parameter PCIE_REFCLK_FREQ = 0, // PCIe reference clock frequency
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parameter LOAD_CNT_MAX = 2'd3, // Load max count
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parameter INDEX_MAX = 3'd6 // Index max count
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)
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(
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//---------- Input -------------------------------------
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input DRP_CLK,
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input DRP_RST_N,
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input DRP_OVRD,
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input DRP_GEN3,
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input DRP_QPLLLOCK,
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input DRP_START,
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input [15:0] DRP_DO,
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input DRP_RDY,
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//---------- Output ------------------------------------
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output [ 7:0] DRP_ADDR,
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output DRP_EN,
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output [15:0] DRP_DI,
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output DRP_WE,
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output DRP_DONE,
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output DRP_QPLLRESET,
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output [ 5:0] DRP_CRSCODE,
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output [ 8:0] DRP_FSM
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);
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//---------- Input Registers ---------------------------
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg ovrd_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gen3_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg qplllock_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg start_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [15:0] do_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rdy_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg ovrd_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gen3_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg qplllock_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg start_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [15:0] do_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rdy_reg2;
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//---------- Internal Signals --------------------------
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reg [ 1:0] load_cnt = 2'd0;
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reg [ 2:0] index = 3'd0;
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reg mode = 1'd0;
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reg [ 5:0] crscode = 6'd0;
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//---------- Output Registers --------------------------
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reg [ 7:0] addr = 8'd0;
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reg [15:0] di = 16'd0;
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reg done = 1'd0;
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reg [ 8:0] fsm = 7'd1;
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//---------- DRP Address -------------------------------
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localparam ADDR_QPLL_FBDIV = 8'h36;
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localparam ADDR_QPLL_CFG = 8'h32;
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localparam ADDR_QPLL_LPF = 8'h31;
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localparam ADDR_CRSCODE = 8'h88;
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localparam ADDR_QPLL_COARSE_FREQ_OVRD = 8'h35;
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localparam ADDR_QPLL_COARSE_FREQ_OVRD_EN = 8'h36;
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localparam ADDR_QPLL_LOCK_CFG = 8'h34;
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//---------- DRP Mask ----------------------------------
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localparam MASK_QPLL_FBDIV = 16'b1111110000000000; // Unmask bit [ 9: 0]
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localparam MASK_QPLL_CFG = 16'b1111111110111111; // Unmask bit [ 6]
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localparam MASK_QPLL_LPF = 16'b1000011111111111; // Unmask bit [14:11]
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localparam MASK_QPLL_COARSE_FREQ_OVRD = 16'b0000001111111111; // Unmask bit [15:10]
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localparam MASK_QPLL_COARSE_FREQ_OVRD_EN = 16'b1111011111111111; // Unmask bit [ 11]
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localparam MASK_QPLL_LOCK_CFG = 16'b1110011111111111; // Unmask bit [12:11]
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//---------- DRP Data for Normal QPLLLOCK Mode ---------
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localparam NORM_QPLL_COARSE_FREQ_OVRD = 16'b0000000000000000; // Coarse freq value
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localparam NORM_QPLL_COARSE_FREQ_OVRD_EN = 16'b0000000000000000; // Normal QPLL lock
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localparam NORM_QPLL_LOCK_CFG = 16'b0000000000000000; // Normal QPLL lock config
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//---------- DRP Data for Optimize QPLLLOCK Mode -------
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localparam OVRD_QPLL_COARSE_FREQ_OVRD = 16'b0000000000000000; // Coarse freq value
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localparam OVRD_QPLL_COARSE_FREQ_OVRD_EN = 16'b0000100000000000; // Override QPLL lock
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localparam OVRD_QPLL_LOCK_CFG = 16'b0000000000000000; // Override QPLL lock config
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//---------- Select QPLL Feedback Divider --------------
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// N = 100 for 100 MHz ref clk and 10Gb/s line rate
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// N = 80 for 125 MHz ref clk and 10Gb/s line rate
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// N = 40 for 250 MHz ref clk and 10Gb/s line rate
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//------------------------------------------------------
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// N = 80 for 100 MHz ref clk and 8Gb/s line rate
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// N = 64 for 125 MHz ref clk and 8Gb/s line rate
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// N = 32 for 250 MHz ref clk and 8Gb/s line rate
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//------------------------------------------------------
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localparam QPLL_FBDIV = (PCIE_REFCLK_FREQ == 2) && (PCIE_PLL_SEL == "QPLL") ? 16'b0000000010000000 :
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(PCIE_REFCLK_FREQ == 1) && (PCIE_PLL_SEL == "QPLL") ? 16'b0000000100100000 :
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(PCIE_REFCLK_FREQ == 0) && (PCIE_PLL_SEL == "QPLL") ? 16'b0000000101110000 :
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(PCIE_REFCLK_FREQ == 2) && (PCIE_PLL_SEL == "CPLL") ? 16'b0000000001100000 :
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(PCIE_REFCLK_FREQ == 1) && (PCIE_PLL_SEL == "CPLL") ? 16'b0000000011100000 : 16'b0000000100100000;
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localparam GEN12_QPLL_FBDIV = (PCIE_REFCLK_FREQ == 2) ? 16'b0000000010000000 :
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(PCIE_REFCLK_FREQ == 1) ? 16'b0000000100100000 : 16'b0000000101110000;
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localparam GEN3_QPLL_FBDIV = (PCIE_REFCLK_FREQ == 2) ? 16'b0000000001100000 :
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(PCIE_REFCLK_FREQ == 1) ? 16'b0000000011100000 : 16'b0000000100100000;
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//---------- Select QPLL Configuration ---------------------------
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// QPLL_CFG[6] = 0 for upper band
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// = 1 for lower band
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//----------------------------------------------------------------
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localparam GEN12_QPLL_CFG = (PCIE_PLL_SEL == "QPLL") ? 16'b0000000000000000 : 16'b0000000001000000;
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localparam GEN3_QPLL_CFG = 16'b0000000001000000;
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//---------- Select QPLL LPF -------------------------------------
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localparam GEN12_QPLL_LPF = (PCIE_PLL_SEL == "QPLL") ? 16'b0_0100_00000000000 : 16'b0_1101_00000000000;
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localparam GEN3_QPLL_LPF = 16'b0_1101_00000000000;
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//---------- DRP Data ----------------------------------
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wire [15:0] data_qpll_fbdiv;
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wire [15:0] data_qpll_cfg;
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wire [15:0] data_qpll_lpf;
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wire [15:0] data_qpll_coarse_freq_ovrd;
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wire [15:0] data_qpll_coarse_freq_ovrd_en;
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wire [15:0] data_qpll_lock_cfg;
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//---------- FSM ---------------------------------------
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localparam FSM_IDLE = 9'b000000001;
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localparam FSM_LOAD = 9'b000000010;
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localparam FSM_READ = 9'b000000100;
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localparam FSM_RRDY = 9'b000001000;
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localparam FSM_WRITE = 9'b000010000;
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localparam FSM_WRDY = 9'b000100000;
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localparam FSM_DONE = 9'b001000000;
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localparam FSM_QPLLRESET = 9'b010000000;
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localparam FSM_QPLLLOCK = 9'b100000000;
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//---------- Input FF ----------------------------------------------------------
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always @ (posedge DRP_CLK)
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begin
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if (!DRP_RST_N)
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begin
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//---------- 1st Stage FF --------------------------
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ovrd_reg1 <= 1'd0;
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gen3_reg1 <= 1'd0;
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qplllock_reg1 <= 1'd0;
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start_reg1 <= 1'd0;
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do_reg1 <= 16'd0;
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rdy_reg1 <= 1'd0;
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//---------- 2nd Stage FF --------------------------
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ovrd_reg2 <= 1'd0;
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gen3_reg2 <= 1'd0;
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qplllock_reg2 <= 1'd0;
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start_reg2 <= 1'd0;
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do_reg2 <= 16'd0;
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rdy_reg2 <= 1'd0;
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end
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else
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begin
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//---------- 1st Stage FF --------------------------
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ovrd_reg1 <= DRP_OVRD;
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gen3_reg1 <= DRP_GEN3;
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qplllock_reg1 <= DRP_QPLLLOCK;
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start_reg1 <= DRP_START;
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do_reg1 <= DRP_DO;
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rdy_reg1 <= DRP_RDY;
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//---------- 2nd Stage FF --------------------------
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ovrd_reg2 <= ovrd_reg1;
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gen3_reg2 <= gen3_reg1;
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qplllock_reg2 <= qplllock_reg1;
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start_reg2 <= start_reg1;
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do_reg2 <= do_reg1;
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rdy_reg2 <= rdy_reg1;
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end
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end
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//---------- Select DRP Data ---------------------------------------------------
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assign data_qpll_fbdiv = (gen3_reg2) ? GEN3_QPLL_FBDIV : GEN12_QPLL_FBDIV;
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assign data_qpll_cfg = (gen3_reg2) ? GEN3_QPLL_CFG : GEN12_QPLL_CFG;
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assign data_qpll_lpf = (gen3_reg2) ? GEN3_QPLL_LPF : GEN12_QPLL_LPF;
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assign data_qpll_coarse_freq_ovrd = NORM_QPLL_COARSE_FREQ_OVRD;
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assign data_qpll_coarse_freq_ovrd_en = (ovrd_reg2) ? OVRD_QPLL_COARSE_FREQ_OVRD_EN : NORM_QPLL_COARSE_FREQ_OVRD_EN;
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assign data_qpll_lock_cfg = (ovrd_reg2) ? OVRD_QPLL_LOCK_CFG : NORM_QPLL_LOCK_CFG;
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//---------- Load Counter ------------------------------------------------------
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always @ (posedge DRP_CLK)
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begin
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if (!DRP_RST_N)
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load_cnt <= 2'd0;
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else
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//---------- Increment Load Counter ----------------
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if ((fsm == FSM_LOAD) && (load_cnt < LOAD_CNT_MAX))
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load_cnt <= load_cnt + 2'd1;
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//---------- Hold Load Counter ---------------------
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else if ((fsm == FSM_LOAD) && (load_cnt == LOAD_CNT_MAX))
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load_cnt <= load_cnt;
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//---------- Reset Load Counter --------------------
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else
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load_cnt <= 2'd0;
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end
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//---------- Update DRP Address and Data ---------------------------------------
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always @ (posedge DRP_CLK)
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begin
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if (!DRP_RST_N)
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begin
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addr <= 8'd0;
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di <= 16'd0;
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crscode <= 6'd0;
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end
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else
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begin
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case (index)
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//--------------------------------------------------
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3'd0 :
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begin
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addr <= ADDR_QPLL_FBDIV;
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di <= (do_reg2 & MASK_QPLL_FBDIV) | (mode ? data_qpll_fbdiv : QPLL_FBDIV);
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crscode <= crscode;
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end
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//--------------------------------------------------
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3'd1 :
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begin
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addr <= ADDR_QPLL_CFG;
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if (PCIE_GT_DEVICE == "GTX")
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di <= (do_reg2 & MASK_QPLL_CFG) | data_qpll_cfg;
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else
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|
|
di <= (do_reg2 & 16'hFFFF) | data_qpll_cfg;
|
319 |
|
|
crscode <= crscode;
|
320 |
|
|
end
|
321 |
|
|
|
322 |
|
|
//--------------------------------------------------
|
323 |
|
|
3'd2 :
|
324 |
|
|
begin
|
325 |
|
|
addr <= ADDR_QPLL_LPF;
|
326 |
|
|
if (PCIE_GT_DEVICE == "GTX")
|
327 |
|
|
di <= (do_reg2 & MASK_QPLL_LPF) | data_qpll_lpf;
|
328 |
|
|
else
|
329 |
|
|
di <= (do_reg2 & 16'hFFFF) | data_qpll_lpf;
|
330 |
|
|
crscode <= crscode;
|
331 |
|
|
end
|
332 |
|
|
|
333 |
|
|
//--------------------------------------------------
|
334 |
|
|
3'd3 :
|
335 |
|
|
begin
|
336 |
|
|
addr <= ADDR_CRSCODE;
|
337 |
|
|
di <= do_reg2;
|
338 |
|
|
|
339 |
|
|
//---------- Latch CRS Code --------------------
|
340 |
|
|
if (ovrd_reg2)
|
341 |
|
|
crscode <= do_reg2[6:1];
|
342 |
|
|
else
|
343 |
|
|
crscode <= crscode;
|
344 |
|
|
end
|
345 |
|
|
|
346 |
|
|
//--------------------------------------------------
|
347 |
|
|
3'd4 :
|
348 |
|
|
begin
|
349 |
|
|
addr <= ADDR_QPLL_COARSE_FREQ_OVRD;
|
350 |
|
|
di <= (do_reg2 & MASK_QPLL_COARSE_FREQ_OVRD) | {(crscode - 6'd1), data_qpll_coarse_freq_ovrd[9:0]};
|
351 |
|
|
crscode <= crscode;
|
352 |
|
|
end
|
353 |
|
|
|
354 |
|
|
//--------------------------------------------------
|
355 |
|
|
3'd5 :
|
356 |
|
|
begin
|
357 |
|
|
addr <= ADDR_QPLL_COARSE_FREQ_OVRD_EN;
|
358 |
|
|
di <= (do_reg2 & MASK_QPLL_COARSE_FREQ_OVRD_EN) | data_qpll_coarse_freq_ovrd_en;
|
359 |
|
|
crscode <= crscode;
|
360 |
|
|
end
|
361 |
|
|
|
362 |
|
|
//--------------------------------------------------
|
363 |
|
|
3'd6 :
|
364 |
|
|
begin
|
365 |
|
|
addr <= ADDR_QPLL_LOCK_CFG;
|
366 |
|
|
di <= (do_reg2 & MASK_QPLL_LOCK_CFG) | data_qpll_lock_cfg;
|
367 |
|
|
crscode <= crscode;
|
368 |
|
|
end
|
369 |
|
|
|
370 |
|
|
//--------------------------------------------------
|
371 |
|
|
default :
|
372 |
|
|
begin
|
373 |
|
|
addr <= 8'd0;
|
374 |
|
|
di <= 16'd0;
|
375 |
|
|
crscode <= 6'd0;
|
376 |
|
|
end
|
377 |
|
|
|
378 |
|
|
endcase
|
379 |
|
|
|
380 |
|
|
end
|
381 |
|
|
|
382 |
|
|
end
|
383 |
|
|
|
384 |
|
|
|
385 |
|
|
|
386 |
|
|
//---------- QPLL DRP FSM ------------------------------------------------------
|
387 |
|
|
always @ (posedge DRP_CLK)
|
388 |
|
|
begin
|
389 |
|
|
|
390 |
|
|
if (!DRP_RST_N)
|
391 |
|
|
begin
|
392 |
|
|
fsm <= FSM_IDLE;
|
393 |
|
|
index <= 3'd0;
|
394 |
|
|
mode <= 1'd0;
|
395 |
|
|
done <= 1'd0;
|
396 |
|
|
end
|
397 |
|
|
else
|
398 |
|
|
begin
|
399 |
|
|
|
400 |
|
|
case (fsm)
|
401 |
|
|
|
402 |
|
|
//---------- Idle State ----------------------------
|
403 |
|
|
FSM_IDLE :
|
404 |
|
|
|
405 |
|
|
begin
|
406 |
|
|
if (start_reg2)
|
407 |
|
|
begin
|
408 |
|
|
fsm <= FSM_LOAD;
|
409 |
|
|
index <= 3'd0;
|
410 |
|
|
mode <= 1'd0;
|
411 |
|
|
done <= 1'd0;
|
412 |
|
|
end
|
413 |
|
|
else if ((gen3_reg2 != gen3_reg1) && (PCIE_PLL_SEL == "QPLL"))
|
414 |
|
|
begin
|
415 |
|
|
fsm <= FSM_LOAD;
|
416 |
|
|
index <= 3'd0;
|
417 |
|
|
mode <= 1'd1;
|
418 |
|
|
done <= 1'd0;
|
419 |
|
|
end
|
420 |
|
|
else
|
421 |
|
|
begin
|
422 |
|
|
fsm <= FSM_IDLE;
|
423 |
|
|
index <= 3'd0;
|
424 |
|
|
mode <= 1'd0;
|
425 |
|
|
done <= 1'd1;
|
426 |
|
|
end
|
427 |
|
|
end
|
428 |
|
|
|
429 |
|
|
//---------- Load DRP Address ---------------------
|
430 |
|
|
FSM_LOAD :
|
431 |
|
|
|
432 |
|
|
begin
|
433 |
|
|
fsm <= (load_cnt == LOAD_CNT_MAX) ? FSM_READ : FSM_LOAD;
|
434 |
|
|
index <= index;
|
435 |
|
|
mode <= mode;
|
436 |
|
|
done <= 1'd0;
|
437 |
|
|
end
|
438 |
|
|
|
439 |
|
|
//---------- Read DRP ------------------------------
|
440 |
|
|
FSM_READ :
|
441 |
|
|
|
442 |
|
|
begin
|
443 |
|
|
fsm <= FSM_RRDY;
|
444 |
|
|
index <= index;
|
445 |
|
|
mode <= mode;
|
446 |
|
|
done <= 1'd0;
|
447 |
|
|
end
|
448 |
|
|
|
449 |
|
|
//---------- Read DRP Ready ------------------------
|
450 |
|
|
FSM_RRDY :
|
451 |
|
|
|
452 |
|
|
begin
|
453 |
|
|
fsm <= (rdy_reg2 ? FSM_WRITE : FSM_RRDY);
|
454 |
|
|
index <= index;
|
455 |
|
|
mode <= mode;
|
456 |
|
|
done <= 1'd0;
|
457 |
|
|
end
|
458 |
|
|
|
459 |
|
|
//---------- Write DRP -----------------------------
|
460 |
|
|
FSM_WRITE :
|
461 |
|
|
|
462 |
|
|
begin
|
463 |
|
|
fsm <= FSM_WRDY;
|
464 |
|
|
index <= index;
|
465 |
|
|
mode <= mode;
|
466 |
|
|
done <= 1'd0;
|
467 |
|
|
end
|
468 |
|
|
|
469 |
|
|
//---------- Write DRP Ready -----------------------
|
470 |
|
|
FSM_WRDY :
|
471 |
|
|
|
472 |
|
|
begin
|
473 |
|
|
fsm <= (rdy_reg2 ? FSM_DONE : FSM_WRDY);
|
474 |
|
|
index <= index;
|
475 |
|
|
mode <= mode;
|
476 |
|
|
done <= 1'd0;
|
477 |
|
|
end
|
478 |
|
|
|
479 |
|
|
//---------- DRP Done ------------------------------
|
480 |
|
|
FSM_DONE :
|
481 |
|
|
|
482 |
|
|
begin
|
483 |
|
|
if ((index == INDEX_MAX) || (mode && (index == 3'd2)))
|
484 |
|
|
begin
|
485 |
|
|
fsm <= mode ? FSM_QPLLRESET : FSM_IDLE;
|
486 |
|
|
index <= 3'd0;
|
487 |
|
|
mode <= mode;
|
488 |
|
|
done <= 1'd0;
|
489 |
|
|
end
|
490 |
|
|
else
|
491 |
|
|
begin
|
492 |
|
|
fsm <= FSM_LOAD;
|
493 |
|
|
index <= index + 3'd1;
|
494 |
|
|
mode <= mode;
|
495 |
|
|
done <= 1'd0;
|
496 |
|
|
end
|
497 |
|
|
end
|
498 |
|
|
|
499 |
|
|
//---------- QPLL Reset ----------------------------
|
500 |
|
|
FSM_QPLLRESET :
|
501 |
|
|
|
502 |
|
|
begin
|
503 |
|
|
fsm <= !qplllock_reg2 ? FSM_QPLLLOCK : FSM_QPLLRESET;
|
504 |
|
|
index <= 3'd0;
|
505 |
|
|
mode <= mode;
|
506 |
|
|
done <= 1'd0;
|
507 |
|
|
end
|
508 |
|
|
|
509 |
|
|
//---------- QPLL Reset ----------------------------
|
510 |
|
|
FSM_QPLLLOCK :
|
511 |
|
|
|
512 |
|
|
begin
|
513 |
|
|
fsm <= qplllock_reg2 ? FSM_IDLE : FSM_QPLLLOCK;
|
514 |
|
|
index <= 3'd0;
|
515 |
|
|
mode <= mode;
|
516 |
|
|
done <= 1'd0;
|
517 |
|
|
end
|
518 |
|
|
|
519 |
|
|
//---------- Default State -------------------------
|
520 |
|
|
default :
|
521 |
|
|
|
522 |
|
|
begin
|
523 |
|
|
fsm <= FSM_IDLE;
|
524 |
|
|
index <= 3'd0;
|
525 |
|
|
mode <= 1'd0;
|
526 |
|
|
done <= 1'd0;
|
527 |
|
|
end
|
528 |
|
|
|
529 |
|
|
endcase
|
530 |
|
|
|
531 |
|
|
end
|
532 |
|
|
|
533 |
|
|
end
|
534 |
|
|
|
535 |
|
|
|
536 |
|
|
|
537 |
|
|
//---------- QPLL DRP Output ---------------------------------------------------
|
538 |
|
|
assign DRP_ADDR = addr;
|
539 |
|
|
assign DRP_EN = (fsm == FSM_READ) || (fsm == FSM_WRITE);
|
540 |
|
|
assign DRP_DI = di;
|
541 |
|
|
assign DRP_WE = (fsm == FSM_WRITE); // || (fsm == FSM_WRDY);
|
542 |
|
|
assign DRP_DONE = done;
|
543 |
|
|
assign DRP_QPLLRESET = (fsm == FSM_QPLLRESET);
|
544 |
|
|
assign DRP_CRSCODE = crscode;
|
545 |
|
|
assign DRP_FSM = fsm;
|
546 |
|
|
|
547 |
|
|
|
548 |
|
|
|
549 |
|
|
endmodule
|