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-------------------------------------------------------------------------------
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--
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-- (c) Copyright 2008, 2009 Xilinx, Inc. All rights reserved.
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--
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-- This file contains confidential and proprietary information
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-- of Xilinx, Inc. and is protected under U.S. and
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-- international copyright and other intellectual property
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-- laws.
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--
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-- DISCLAIMER
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-- This disclaimer is not a license and does not grant any
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-- rights to the materials distributed herewith. Except as
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-- otherwise provided in a valid license issued to you by
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-- Xilinx, and to the maximum extent permitted by applicable
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-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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-- (2) Xilinx shall not be liable (whether in contract or tort,
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-- including negligence, or under any other theory of
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-- liability) for any loss or damage of any kind or nature
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-- related to, arising under or in connection with these
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-- materials, including for any direct, or any indirect,
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-- special, incidental, or consequential loss or damage
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-- (including loss of data, profits, goodwill, or any type of
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-- loss or damage suffered as a result of any action brought
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-- by a third party) even if such damage or loss was
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-- reasonably foreseeable or Xilinx had been advised of the
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-- possibility of the same.
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--
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-- CRITICAL APPLICATIONS
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-- Xilinx products are not designed or intended to be fail-
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-- safe, or for use in any application requiring fail-safe
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-- performance, such as life-support or safety devices or
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-- systems, Class III medical devices, nuclear facilities,
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-- applications related to the deployment of airbags, or any
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-- other applications that could lead to death, personal
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-- injury, or severe property or environmental damage
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-- (individually and collectively, "Critical
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-- Applications"). Customer assumes the sole risk and
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-- liability of any use of Xilinx products in Critical
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-- Applications, subject only to applicable laws and
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-- regulations governing limitations on product liability.
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--
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-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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-- PART OF THIS FILE AT ALL TIMES.
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--
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-------------------------------------------------------------------------------
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-- Project : Spartan-6 Integrated Block for PCI Express
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-- File : cl_s6pcie_m2.vhd
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-- Description: Spartan-6 solution wrapper : Endpoint for PCI Express
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--
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_bit.all;
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library unisim;
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use unisim.vcomponents.all;
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--synthesis translate_off
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use unisim.vpkg.all;
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library secureip;
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use secureip.all;
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--synthesis translate_on
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entity cl_s6pcie_m2 is
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generic (
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TL_TX_RAM_RADDR_LATENCY : integer := 0;
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TL_TX_RAM_RDATA_LATENCY : integer := 2;
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TL_RX_RAM_RADDR_LATENCY : integer := 0;
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TL_RX_RAM_RDATA_LATENCY : integer := 2;
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TL_RX_RAM_WRITE_LATENCY : integer := 0;
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VC0_TX_LASTPACKET : integer := 28;
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VC0_RX_RAM_LIMIT : bit_vector := x"7FF";
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VC0_TOTAL_CREDITS_PH : integer := 32;
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VC0_TOTAL_CREDITS_PD : integer := 211;
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VC0_TOTAL_CREDITS_NPH : integer := 8;
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VC0_TOTAL_CREDITS_CH : integer := 40;
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VC0_TOTAL_CREDITS_CD : integer := 211;
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VC0_CPL_INFINITE : boolean := TRUE;
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BAR0 : bit_vector := x"FFE00000";
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BAR1 : bit_vector := x"FFE00000";
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BAR2 : bit_vector := x"00000000";
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BAR3 : bit_vector := x"00000000";
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BAR4 : bit_vector := x"00000000";
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BAR5 : bit_vector := x"00000000";
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EXPANSION_ROM : bit_vector := "0000000000000000000000";
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DISABLE_BAR_FILTERING : boolean := FALSE;
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DISABLE_ID_CHECK : boolean := FALSE;
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TL_TFC_DISABLE : boolean := FALSE;
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TL_TX_CHECKS_DISABLE : boolean := FALSE;
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USR_CFG : boolean := FALSE;
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USR_EXT_CFG : boolean := FALSE;
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DEV_CAP_MAX_PAYLOAD_SUPPORTED : integer := 1;
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CLASS_CODE : bit_vector := x"FFFFFF";
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CARDBUS_CIS_POINTER : bit_vector := x"00000000";
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PCIE_CAP_CAPABILITY_VERSION : bit_vector := x"1";
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PCIE_CAP_DEVICE_PORT_TYPE : bit_vector := x"0";
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PCIE_CAP_SLOT_IMPLEMENTED : boolean := FALSE;
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PCIE_CAP_INT_MSG_NUM : bit_vector := "00000";
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DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT : integer := 0;
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DEV_CAP_EXT_TAG_SUPPORTED : boolean := FALSE;
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DEV_CAP_ENDPOINT_L0S_LATENCY : integer := 7;
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DEV_CAP_ENDPOINT_L1_LATENCY : integer := 7;
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SLOT_CAP_ATT_BUTTON_PRESENT : boolean := FALSE;
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SLOT_CAP_ATT_INDICATOR_PRESENT : boolean := FALSE;
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SLOT_CAP_POWER_INDICATOR_PRESENT : boolean := FALSE;
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DEV_CAP_ROLE_BASED_ERROR : boolean := TRUE;
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LINK_CAP_ASPM_SUPPORT : integer := 1;
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LINK_CAP_L0S_EXIT_LATENCY : integer := 7;
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LINK_CAP_L1_EXIT_LATENCY : integer := 7;
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LL_ACK_TIMEOUT : bit_vector := x"0000";
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LL_ACK_TIMEOUT_EN : boolean := FALSE;
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LL_REPLAY_TIMEOUT : bit_vector := x"0000";
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LL_REPLAY_TIMEOUT_EN : boolean := FALSE;
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MSI_CAP_MULTIMSGCAP : integer := 0;
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MSI_CAP_MULTIMSG_EXTENSION : integer := 0;
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LINK_STATUS_SLOT_CLOCK_CONFIG : boolean := TRUE;
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PLM_AUTO_CONFIG : boolean := FALSE;
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FAST_TRAIN : boolean := FALSE;
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ENABLE_RX_TD_ECRC_TRIM : boolean := TRUE;
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DISABLE_SCRAMBLING : boolean := FALSE;
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PM_CAP_VERSION : integer := 3;
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PM_CAP_PME_CLOCK : boolean := FALSE;
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PM_CAP_DSI : boolean := FALSE;
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PM_CAP_AUXCURRENT : integer := 0;
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PM_CAP_D1SUPPORT : boolean := TRUE;
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PM_CAP_D2SUPPORT : boolean := TRUE;
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PM_CAP_PMESUPPORT : bit_vector := x"0F";
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PM_DATA0 : bit_vector := x"00";
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PM_DATA_SCALE0 : bit_vector := x"0";
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PM_DATA1 : bit_vector := x"00";
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PM_DATA_SCALE1 : bit_vector := x"0";
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PM_DATA2 : bit_vector := x"00";
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PM_DATA_SCALE2 : bit_vector := x"0";
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PM_DATA3 : bit_vector := x"00";
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PM_DATA_SCALE3 : bit_vector := x"0";
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PM_DATA4 : bit_vector := x"00";
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PM_DATA_SCALE4 : bit_vector := x"0";
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PM_DATA5 : bit_vector := x"00";
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PM_DATA_SCALE5 : bit_vector := x"0";
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PM_DATA6 : bit_vector := x"00";
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PM_DATA_SCALE6 : bit_vector := x"0";
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PM_DATA7 : bit_vector := x"00";
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PM_DATA_SCALE7 : bit_vector := x"0";
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PCIE_GENERIC : bit_vector := "000010101111";
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GTP_SEL : integer := 0;
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CFG_VEN_ID : std_logic_vector(15 downto 0) := x"4953";
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CFG_DEV_ID : std_logic_vector(15 downto 0) := x"5507";
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CFG_REV_ID : std_logic_vector(7 downto 0) := x"10";
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CFG_SUBSYS_VEN_ID : std_logic_vector(15 downto 0) := x"4953";
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CFG_SUBSYS_ID : std_logic_vector(15 downto 0) := x"0008";
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REF_CLK_FREQ : integer := 1
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);
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port (
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-- PCI Express Fabric Interface
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pci_exp_txp : out std_logic;
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pci_exp_txn : out std_logic;
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pci_exp_rxp : in std_logic;
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pci_exp_rxn : in std_logic;
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-- Transaction (TRN) Interface
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trn_lnk_up_n : out std_logic;
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-- Tx
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trn_td : in std_logic_vector(31 downto 0);
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trn_tsof_n : in std_logic;
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trn_teof_n : in std_logic;
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trn_tsrc_rdy_n : in std_logic;
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trn_tdst_rdy_n : out std_logic;
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trn_terr_drop_n : out std_logic;
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trn_tsrc_dsc_n : in std_logic;
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trn_terrfwd_n : in std_logic;
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trn_tbuf_av : out std_logic_vector(5 downto 0);
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trn_tstr_n : in std_logic;
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trn_tcfg_req_n : out std_logic;
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trn_tcfg_gnt_n : in std_logic;
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-- Rx
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trn_rd : out std_logic_vector(31 downto 0);
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trn_rsof_n : out std_logic;
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trn_reof_n : out std_logic;
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trn_rsrc_rdy_n : out std_logic;
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trn_rsrc_dsc_n : out std_logic;
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trn_rdst_rdy_n : in std_logic;
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trn_rerrfwd_n : out std_logic;
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trn_rnp_ok_n : in std_logic;
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trn_rbar_hit_n : out std_logic_vector(6 downto 0);
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trn_fc_sel : in std_logic_vector(2 downto 0);
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trn_fc_nph : out std_logic_vector(7 downto 0);
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trn_fc_npd : out std_logic_vector(11 downto 0);
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trn_fc_ph : out std_logic_vector(7 downto 0);
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trn_fc_pd : out std_logic_vector(11 downto 0);
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trn_fc_cplh : out std_logic_vector(7 downto 0);
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trn_fc_cpld : out std_logic_vector(11 downto 0);
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-- Host (CFG) Interface
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cfg_do : out std_logic_vector(31 downto 0);
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cfg_rd_wr_done_n : out std_logic;
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cfg_dwaddr : in std_logic_vector(9 downto 0);
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cfg_rd_en_n : in std_logic;
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cfg_err_ur_n : in std_logic;
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cfg_err_cor_n : in std_logic;
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cfg_err_ecrc_n : in std_logic;
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cfg_err_cpl_timeout_n : in std_logic;
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cfg_err_cpl_abort_n : in std_logic;
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cfg_err_posted_n : in std_logic;
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cfg_err_locked_n : in std_logic;
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cfg_err_tlp_cpl_header : in std_logic_vector(47 downto 0);
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cfg_err_cpl_rdy_n : out std_logic;
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cfg_interrupt_n : in std_logic;
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cfg_interrupt_rdy_n : out std_logic;
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cfg_interrupt_assert_n : in std_logic;
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cfg_interrupt_do : out std_logic_vector(7 downto 0);
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cfg_interrupt_di : in std_logic_vector(7 downto 0);
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cfg_interrupt_mmenable : out std_logic_vector(2 downto 0);
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cfg_interrupt_msienable : out std_logic;
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cfg_turnoff_ok_n : in std_logic;
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cfg_to_turnoff_n : out std_logic;
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cfg_pm_wake_n : in std_logic;
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cfg_pcie_link_state_n : out std_logic_vector(2 downto 0);
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cfg_trn_pending_n : in std_logic;
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cfg_dsn : in std_logic_vector(63 downto 0);
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cfg_bus_number : out std_logic_vector(7 downto 0);
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cfg_device_number : out std_logic_vector(4 downto 0);
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cfg_function_number : out std_logic_vector(2 downto 0);
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cfg_status : out std_logic_vector(15 downto 0);
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cfg_command : out std_logic_vector(15 downto 0);
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cfg_dstatus : out std_logic_vector(15 downto 0);
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cfg_dcommand : out std_logic_vector(15 downto 0);
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cfg_lstatus : out std_logic_vector(15 downto 0);
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cfg_lcommand : out std_logic_vector(15 downto 0);
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-- System Interface
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sys_clk : in std_logic;
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sys_reset_n : in std_logic;
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trn_clk : out std_logic;
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trn_reset_n : out std_logic;
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received_hot_reset : out std_logic
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);
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end cl_s6pcie_m2;
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architecture rtl of cl_s6pcie_m2 is
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attribute CORE_GENERATION_INFO : STRING;
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attribute CORE_GENERATION_INFO of rtl : architecture is
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"cl_s6pcie_m2,s6_pcie_v1_4,{TL_TX_RAM_RADDR_LATENCY=0,TL_TX_RAM_RDATA_LATENCY=2,TL_RX_RAM_RADDR_LATENCY=0,TL_RX_RAM_RDATA_LATENCY=2,TL_RX_RAM_WRITE_LATENCY=0,VC0_TX_LASTPACKET=28,VC0_RX_RAM_LIMIT=7FF,VC0_TOTAL_CREDITS_PH=32,VC0_TOTAL_CREDITS_PD=211,VC0_TOTAL_CREDITS_NPH=8,VC0_TOTAL_CREDITS_CH=40,VC0_TOTAL_CREDITS_CD=211,VC0_CPL_INFINITE=TRUE,BAR0=FFE00000,BAR1=FFE00000,BAR2=00000000,BAR3=00000000,BAR4=00000000,BAR5=00000000,EXPANSION_ROM=000000,USR_CFG=FALSE,USR_EXT_CFG=FALSE,DEV_CAP_MAX_PAYLOAD_SUPPORTED=1,CLASS_CODE=FFFFFF,CARDBUS_CIS_POINTER=00000000,PCIE_CAP_CAPABILITY_VERSION=1,PCIE_CAP_DEVICE_PORT_TYPE=0,DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT=0,DEV_CAP_EXT_TAG_SUPPORTED=FALSE,DEV_CAP_ENDPOINT_L0S_LATENCY=7,DEV_CAP_ENDPOINT_L1_LATENCY=7,LINK_CAP_ASPM_SUPPORT=1,MSI_CAP_MULTIMSGCAP=0,MSI_CAP_MULTIMSG_EXTENSION=0,LINK_STATUS_SLOT_CLOCK_CONFIG=TRUE,ENABLE_RX_TD_ECRC_TRIM=TRUE,DISABLE_SCRAMBLING=FALSE,PM_CAP_DSI=FALSE,PM_CAP_D1SUPPORT=TRUE,PM_CAP_D2SUPPORT=TRUE,PM_CAP_PMESUPPORT=0F,PM_DATA0=00,PM_DATA_SCALE0=0,PM_DATA1=00,PM_DATA_SCALE1=0,PM_DATA2=00,PM_DATA_SCALE2=0,PM_DATA3=00,PM_DATA_SCALE3=0,PM_DATA4=00,PM_DATA_SCALE4=0,PM_DATA5=00,PM_DATA_SCALE5=0,PM_DATA6=00,PM_DATA_SCALE6=0,PM_DATA7=00,PM_DATA_SCALE7=0,PCIE_GENERIC=000010101111,GTP_SEL=0,CFG_VEN_ID=4953,CFG_DEV_ID=5507,CFG_REV_ID=10,CFG_SUBSYS_VEN_ID=4953,CFG_SUBSYS_ID=0008,REF_CLK_FREQ=1}";
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------------------------
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-- Function Declarations
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------------------------
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function CALC_CLKFBOUT_MULT(FREQ_SEL : integer) return integer is
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begin
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case FREQ_SEL is
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when 0 => return 5; -- 100 MHz
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when others => return 4; -- 125 MHz
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end case;
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end CALC_CLKFBOUT_MULT;
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function CALC_CLKIN_PERIOD(FREQ_SEL : integer) return real is
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begin
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case FREQ_SEL is
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when 0 => return 10.0; -- 100 MHz
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when others => return 8.0; -- 125 MHz
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end case;
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end CALC_CLKIN_PERIOD;
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function CALC_CLK25_DIVIDER(FREQ_SEL : integer) return integer is
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begin
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case FREQ_SEL is
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when 0 => return 4; -- 100 MHz
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when others => return 5; -- 125 MHz
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end case;
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|
end CALC_CLK25_DIVIDER;
|
276 |
|
|
function CALC_PLL_DIVSEL_FB(FREQ_SEL : integer) return integer is
|
277 |
|
|
begin
|
278 |
|
|
case FREQ_SEL is
|
279 |
|
|
when 0 => return 5; -- 100 MHz
|
280 |
|
|
when others => return 2; -- 125 MHz
|
281 |
|
|
end case;
|
282 |
|
|
end CALC_PLL_DIVSEL_FB;
|
283 |
|
|
function CALC_PLL_DIVSEL_REF(FREQ_SEL : integer) return integer is
|
284 |
|
|
begin
|
285 |
|
|
case FREQ_SEL is
|
286 |
|
|
when 0 => return 2; -- 100 MHz
|
287 |
|
|
when others => return 1; -- 125 MHz
|
288 |
|
|
end case;
|
289 |
|
|
end CALC_PLL_DIVSEL_REF;
|
290 |
|
|
function SIM_INT(SIMULATION : boolean) return integer is
|
291 |
|
|
begin
|
292 |
|
|
if SIMULATION then
|
293 |
|
|
return 1;
|
294 |
|
|
else
|
295 |
|
|
return 0;
|
296 |
|
|
end if;
|
297 |
|
|
end SIM_INT;
|
298 |
|
|
|
299 |
|
|
------------------------
|
300 |
|
|
-- Constant Declarations
|
301 |
|
|
------------------------
|
302 |
|
|
|
303 |
|
|
constant CLKFBOUT_MULT : integer := CALC_CLKFBOUT_MULT(REF_CLK_FREQ);
|
304 |
|
|
constant CLKIN_PERIOD : real := CALC_CLKIN_PERIOD(REF_CLK_FREQ);
|
305 |
|
|
constant GT_CLK25_DIVIDER : integer := CALC_CLK25_DIVIDER(REF_CLK_FREQ);
|
306 |
|
|
constant GT_PLL_DIVSEL_FB : integer := CALC_PLL_DIVSEL_FB(REF_CLK_FREQ);
|
307 |
|
|
constant GT_PLL_DIVSEL_REF : integer := CALC_PLL_DIVSEL_REF(REF_CLK_FREQ);
|
308 |
|
|
|
309 |
|
|
-------------------------
|
310 |
|
|
-- Component Declarations
|
311 |
|
|
-------------------------
|
312 |
|
|
component pcie_bram_top_s6 is
|
313 |
|
|
generic (
|
314 |
|
|
DEV_CAP_MAX_PAYLOAD_SUPPORTED : integer := 0;
|
315 |
|
|
|
316 |
|
|
VC0_TX_LASTPACKET : integer := 31;
|
317 |
|
|
TLM_TX_OVERHEAD : integer := 24;
|
318 |
|
|
TL_TX_RAM_RADDR_LATENCY : integer := 1;
|
319 |
|
|
TL_TX_RAM_RDATA_LATENCY : integer := 1;
|
320 |
|
|
TL_TX_RAM_WRITE_LATENCY : integer := 1;
|
321 |
|
|
|
322 |
|
|
VC0_RX_LIMIT : integer := 16#1FFF#;
|
323 |
|
|
TL_RX_RAM_RADDR_LATENCY : integer := 1;
|
324 |
|
|
TL_RX_RAM_RDATA_LATENCY : integer := 1;
|
325 |
|
|
TL_RX_RAM_WRITE_LATENCY : integer := 1
|
326 |
|
|
);
|
327 |
|
|
port (
|
328 |
|
|
user_clk_i : in std_logic;
|
329 |
|
|
reset_i : in std_logic;
|
330 |
|
|
|
331 |
|
|
mim_tx_wen : in std_logic;
|
332 |
|
|
mim_tx_waddr : in std_logic_vector(11 downto 0);
|
333 |
|
|
mim_tx_wdata : in std_logic_vector(35 downto 0);
|
334 |
|
|
mim_tx_ren : in std_logic;
|
335 |
|
|
mim_tx_rce : in std_logic;
|
336 |
|
|
mim_tx_raddr : in std_logic_vector(11 downto 0);
|
337 |
|
|
mim_tx_rdata : out std_logic_vector(35 downto 0);
|
338 |
|
|
|
339 |
|
|
mim_rx_wen : in std_logic;
|
340 |
|
|
mim_rx_waddr : in std_logic_vector(11 downto 0);
|
341 |
|
|
mim_rx_wdata : in std_logic_vector(35 downto 0);
|
342 |
|
|
mim_rx_ren : in std_logic;
|
343 |
|
|
mim_rx_rce : in std_logic;
|
344 |
|
|
mim_rx_raddr : in std_logic_vector(11 downto 0);
|
345 |
|
|
mim_rx_rdata : out std_logic_vector(35 downto 0)
|
346 |
|
|
);
|
347 |
|
|
end component pcie_bram_top_s6;
|
348 |
|
|
|
349 |
|
|
component GTPA1_DUAL_WRAPPER is
|
350 |
|
|
generic
|
351 |
|
|
(
|
352 |
|
|
-- Simulation attributes
|
353 |
|
|
WRAPPER_SIM_GTPRESET_SPEEDUP : integer := 0; -- Set to 1 to speed up sim reset
|
354 |
|
|
WRAPPER_CLK25_DIVIDER_0 : integer := 4;
|
355 |
|
|
WRAPPER_CLK25_DIVIDER_1 : integer := 4;
|
356 |
|
|
WRAPPER_PLL_DIVSEL_FB_0 : integer := 5;
|
357 |
|
|
WRAPPER_PLL_DIVSEL_FB_1 : integer := 5;
|
358 |
|
|
WRAPPER_PLL_DIVSEL_REF_0 : integer := 2;
|
359 |
|
|
WRAPPER_PLL_DIVSEL_REF_1 : integer := 2;
|
360 |
|
|
WRAPPER_SIMULATION : integer := 0 -- Set to 1 for simulation
|
361 |
|
|
);
|
362 |
|
|
port
|
363 |
|
|
(
|
364 |
|
|
|
365 |
|
|
--_________________________________________________________________________
|
366 |
|
|
--_________________________________________________________________________
|
367 |
|
|
--TILE0 (X0_Y0)
|
368 |
|
|
|
369 |
|
|
------------------------ Loopback and Powerdown Ports ----------------------
|
370 |
|
|
TILE0_RXPOWERDOWN0_IN : in std_logic_vector(1 downto 0);
|
371 |
|
|
TILE0_RXPOWERDOWN1_IN : in std_logic_vector(1 downto 0);
|
372 |
|
|
TILE0_TXPOWERDOWN0_IN : in std_logic_vector(1 downto 0);
|
373 |
|
|
TILE0_TXPOWERDOWN1_IN : in std_logic_vector(1 downto 0);
|
374 |
|
|
--------------------------------- PLL Ports --------------------------------
|
375 |
|
|
TILE0_CLK00_IN : in std_logic;
|
376 |
|
|
TILE0_CLK01_IN : in std_logic;
|
377 |
|
|
TILE0_GTPRESET0_IN : in std_logic;
|
378 |
|
|
TILE0_GTPRESET1_IN : in std_logic;
|
379 |
|
|
TILE0_PLLLKDET0_OUT : out std_logic;
|
380 |
|
|
TILE0_PLLLKDET1_OUT : out std_logic;
|
381 |
|
|
TILE0_RESETDONE0_OUT : out std_logic;
|
382 |
|
|
TILE0_RESETDONE1_OUT : out std_logic;
|
383 |
|
|
----------------------- Receive Ports - 8b10b Decoder ----------------------
|
384 |
|
|
TILE0_RXCHARISK0_OUT : out std_logic_vector(1 downto 0);
|
385 |
|
|
TILE0_RXCHARISK1_OUT : out std_logic_vector(1 downto 0);
|
386 |
|
|
TILE0_RXDISPERR0_OUT : out std_logic_vector(1 downto 0);
|
387 |
|
|
TILE0_RXDISPERR1_OUT : out std_logic_vector(1 downto 0);
|
388 |
|
|
TILE0_RXNOTINTABLE0_OUT : out std_logic_vector(1 downto 0);
|
389 |
|
|
TILE0_RXNOTINTABLE1_OUT : out std_logic_vector(1 downto 0);
|
390 |
|
|
---------------------- Receive Ports - Clock Correction --------------------
|
391 |
|
|
TILE0_RXCLKCORCNT0_OUT : out std_logic_vector(2 downto 0);
|
392 |
|
|
TILE0_RXCLKCORCNT1_OUT : out std_logic_vector(2 downto 0);
|
393 |
|
|
--------------- Receive Ports - Comma Detection and Alignment --------------
|
394 |
|
|
TILE0_RXENMCOMMAALIGN0_IN : in std_logic;
|
395 |
|
|
TILE0_RXENMCOMMAALIGN1_IN : in std_logic;
|
396 |
|
|
TILE0_RXENPCOMMAALIGN0_IN : in std_logic;
|
397 |
|
|
TILE0_RXENPCOMMAALIGN1_IN : in std_logic;
|
398 |
|
|
------------------- Receive Ports - RX Data Path interface -----------------
|
399 |
|
|
TILE0_RXDATA0_OUT : out std_logic_vector(15 downto 0);
|
400 |
|
|
TILE0_RXDATA1_OUT : out std_logic_vector(15 downto 0);
|
401 |
|
|
TILE0_RXRESET0_IN : in std_logic;
|
402 |
|
|
TILE0_RXRESET1_IN : in std_logic;
|
403 |
|
|
TILE0_RXUSRCLK0_IN : in std_logic;
|
404 |
|
|
TILE0_RXUSRCLK1_IN : in std_logic;
|
405 |
|
|
TILE0_RXUSRCLK20_IN : in std_logic;
|
406 |
|
|
TILE0_RXUSRCLK21_IN : in std_logic;
|
407 |
|
|
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
|
408 |
|
|
TILE0_GATERXELECIDLE0_IN : in std_logic;
|
409 |
|
|
TILE0_GATERXELECIDLE1_IN : in std_logic;
|
410 |
|
|
TILE0_IGNORESIGDET0_IN : in std_logic;
|
411 |
|
|
TILE0_IGNORESIGDET1_IN : in std_logic;
|
412 |
|
|
TILE0_RXELECIDLE0_OUT : out std_logic;
|
413 |
|
|
TILE0_RXELECIDLE1_OUT : out std_logic;
|
414 |
|
|
TILE0_RXN0_IN : in std_logic;
|
415 |
|
|
TILE0_RXN1_IN : in std_logic;
|
416 |
|
|
TILE0_RXP0_IN : in std_logic;
|
417 |
|
|
TILE0_RXP1_IN : in std_logic;
|
418 |
|
|
----------- Receive Ports - RX Elastic Buffer and Phase Alignment ----------
|
419 |
|
|
TILE0_RXSTATUS0_OUT : out std_logic_vector(2 downto 0);
|
420 |
|
|
TILE0_RXSTATUS1_OUT : out std_logic_vector(2 downto 0);
|
421 |
|
|
-------------- Receive Ports - RX Pipe Control for PCI Express -------------
|
422 |
|
|
TILE0_PHYSTATUS0_OUT : out std_logic;
|
423 |
|
|
TILE0_PHYSTATUS1_OUT : out std_logic;
|
424 |
|
|
TILE0_RXVALID0_OUT : out std_logic;
|
425 |
|
|
TILE0_RXVALID1_OUT : out std_logic;
|
426 |
|
|
-------------------- Receive Ports - RX Polarity Control -------------------
|
427 |
|
|
TILE0_RXPOLARITY0_IN : in std_logic;
|
428 |
|
|
TILE0_RXPOLARITY1_IN : in std_logic;
|
429 |
|
|
---------------------------- TX/RX Datapath Ports --------------------------
|
430 |
|
|
TILE0_GTPCLKOUT0_OUT : out std_logic_vector(1 downto 0);
|
431 |
|
|
TILE0_GTPCLKOUT1_OUT : out std_logic_vector(1 downto 0);
|
432 |
|
|
------------------- Transmit Ports - 8b10b Encoder Control -----------------
|
433 |
|
|
TILE0_TXCHARDISPMODE0_IN : in std_logic_vector(1 downto 0);
|
434 |
|
|
TILE0_TXCHARDISPMODE1_IN : in std_logic_vector(1 downto 0);
|
435 |
|
|
TILE0_TXCHARISK0_IN : in std_logic_vector(1 downto 0);
|
436 |
|
|
TILE0_TXCHARISK1_IN : in std_logic_vector(1 downto 0);
|
437 |
|
|
------------------ Transmit Ports - TX Data Path interface -----------------
|
438 |
|
|
TILE0_TXDATA0_IN : in std_logic_vector(15 downto 0);
|
439 |
|
|
TILE0_TXDATA1_IN : in std_logic_vector(15 downto 0);
|
440 |
|
|
TILE0_TXUSRCLK0_IN : in std_logic;
|
441 |
|
|
TILE0_TXUSRCLK1_IN : in std_logic;
|
442 |
|
|
TILE0_TXUSRCLK20_IN : in std_logic;
|
443 |
|
|
TILE0_TXUSRCLK21_IN : in std_logic;
|
444 |
|
|
--------------- Transmit Ports - TX Driver and OOB signalling --------------
|
445 |
|
|
TILE0_TXN0_OUT : out std_logic;
|
446 |
|
|
TILE0_TXN1_OUT : out std_logic;
|
447 |
|
|
TILE0_TXP0_OUT : out std_logic;
|
448 |
|
|
TILE0_TXP1_OUT : out std_logic;
|
449 |
|
|
----------------- Transmit Ports - TX Ports for PCI Express ----------------
|
450 |
|
|
TILE0_TXDETECTRX0_IN : in std_logic;
|
451 |
|
|
TILE0_TXDETECTRX1_IN : in std_logic;
|
452 |
|
|
TILE0_TXELECIDLE0_IN : in std_logic;
|
453 |
|
|
TILE0_TXELECIDLE1_IN : in std_logic
|
454 |
|
|
);
|
455 |
|
|
end component GTPA1_DUAL_WRAPPER;
|
456 |
|
|
|
457 |
|
|
----------------------
|
458 |
|
|
-- Signal Declarations
|
459 |
|
|
----------------------
|
460 |
|
|
|
461 |
|
|
-- PLL Signals
|
462 |
|
|
signal mgt_clk : std_logic;
|
463 |
|
|
signal mgt_clk_2x : std_logic;
|
464 |
|
|
signal clock_locked : std_logic;
|
465 |
|
|
signal gt_refclk_out : std_logic_vector(1 downto 0);
|
466 |
|
|
signal gt_clk_fb_west_out : std_logic;
|
467 |
|
|
signal pll_rst : std_logic;
|
468 |
|
|
signal clk_125 : std_logic;
|
469 |
|
|
signal clk_250 : std_logic;
|
470 |
|
|
signal clk_62_5 : std_logic;
|
471 |
|
|
signal gt_refclk_buf : std_logic;
|
472 |
|
|
signal gt_refclk_fb : std_logic;
|
473 |
|
|
|
474 |
|
|
signal w_cfg_ven_id : std_logic_vector(15 downto 0);
|
475 |
|
|
signal w_cfg_dev_id : std_logic_vector(15 downto 0);
|
476 |
|
|
signal w_cfg_rev_id : std_logic_vector(7 downto 0);
|
477 |
|
|
signal w_cfg_subsys_ven_id : std_logic_vector(15 downto 0);
|
478 |
|
|
signal w_cfg_subsys_id : std_logic_vector(15 downto 0);
|
479 |
|
|
|
480 |
|
|
signal cfg_ltssm_state : std_logic_vector(4 downto 0);
|
481 |
|
|
signal cfg_link_control_aspm_control : std_logic_vector(1 downto 0);
|
482 |
|
|
signal cfg_link_control_rcb : std_logic;
|
483 |
|
|
signal cfg_link_control_common_clock : std_logic;
|
484 |
|
|
signal cfg_link_control_extended_sync : std_logic;
|
485 |
|
|
signal cfg_command_interrupt_disable : std_logic;
|
486 |
|
|
signal cfg_command_serr_en : std_logic;
|
487 |
|
|
signal cfg_command_bus_master_enable : std_logic;
|
488 |
|
|
signal cfg_command_mem_enable : std_logic;
|
489 |
|
|
signal cfg_command_io_enable : std_logic;
|
490 |
|
|
signal cfg_dev_status_ur_detected : std_logic;
|
491 |
|
|
signal cfg_dev_status_fatal_err_detected : std_logic;
|
492 |
|
|
signal cfg_dev_status_nonfatal_err_detected : std_logic;
|
493 |
|
|
signal cfg_dev_status_corr_err_detected : std_logic;
|
494 |
|
|
signal cfg_dev_control_max_read_req : std_logic_vector(2 downto 0);
|
495 |
|
|
signal cfg_dev_control_no_snoop_en : std_logic;
|
496 |
|
|
signal cfg_dev_control_aux_power_en : std_logic;
|
497 |
|
|
signal cfg_dev_control_phantom_en : std_logic;
|
498 |
|
|
signal cfg_dev_cntrol_ext_tag_en : std_logic;
|
499 |
|
|
signal cfg_dev_control_max_payload : std_logic_vector(2 downto 0);
|
500 |
|
|
signal cfg_dev_control_enable_ro : std_logic;
|
501 |
|
|
signal cfg_dev_control_ext_tag_en : std_logic;
|
502 |
|
|
signal cfg_dev_control_ur_err_reporting_en : std_logic;
|
503 |
|
|
signal cfg_dev_control_fatal_err_reporting_en : std_logic;
|
504 |
|
|
signal cfg_dev_control_non_fatal_reporting_en : std_logic;
|
505 |
|
|
signal cfg_dev_control_corr_err_reporting_en : std_logic;
|
506 |
|
|
|
507 |
|
|
signal mim_tx_waddr : std_logic_vector(11 downto 0);
|
508 |
|
|
signal mim_tx_raddr : std_logic_vector(11 downto 0);
|
509 |
|
|
signal mim_rx_waddr : std_logic_vector(11 downto 0);
|
510 |
|
|
signal mim_rx_raddr : std_logic_vector(11 downto 0);
|
511 |
|
|
signal mim_tx_wdata : std_logic_vector(35 downto 0);
|
512 |
|
|
signal mim_tx_rdata : std_logic_vector(35 downto 0);
|
513 |
|
|
signal mim_rx_wdata : std_logic_vector(34 downto 0);
|
514 |
|
|
signal mim_rx_rdata_unused : std_logic;
|
515 |
|
|
signal mim_rx_rdata : std_logic_vector(34 downto 0);
|
516 |
|
|
signal mim_tx_wen : std_logic;
|
517 |
|
|
signal mim_tx_ren : std_logic;
|
518 |
|
|
signal mim_rx_wen : std_logic;
|
519 |
|
|
signal mim_rx_ren : std_logic;
|
520 |
|
|
|
521 |
|
|
signal dbg_bad_dllp_status : std_logic;
|
522 |
|
|
signal dbg_bad_tlp_lcrc : std_logic;
|
523 |
|
|
signal dbg_bad_tlp_seq_num : std_logic;
|
524 |
|
|
signal dbg_bad_tlp_status : std_logic;
|
525 |
|
|
signal dbg_dl_protocol_status : std_logic;
|
526 |
|
|
signal dbg_fc_protocol_err_status : std_logic;
|
527 |
|
|
signal dbg_mlfrmd_length : std_logic;
|
528 |
|
|
signal dbg_mlfrmd_mps : std_logic;
|
529 |
|
|
signal dbg_mlfrmd_tcvc : std_logic;
|
530 |
|
|
signal dbg_mlfrmd_tlp_status : std_logic;
|
531 |
|
|
signal dbg_mlfrmd_unrec_type : std_logic;
|
532 |
|
|
signal dbg_poistlpstatus : std_logic;
|
533 |
|
|
signal dbg_rcvr_overflow_status : std_logic;
|
534 |
|
|
signal dbg_reg_detected_correctable : std_logic;
|
535 |
|
|
signal dbg_reg_detected_fatal : std_logic;
|
536 |
|
|
signal dbg_reg_detected_non_fatal : std_logic;
|
537 |
|
|
signal dbg_reg_detected_unsupported : std_logic;
|
538 |
|
|
signal dbg_rply_rollover_status : std_logic;
|
539 |
|
|
signal dbg_rply_timeout_status : std_logic;
|
540 |
|
|
signal dbg_ur_no_bar_hit : std_logic;
|
541 |
|
|
signal dbg_ur_pois_cfg_wr : std_logic;
|
542 |
|
|
signal dbg_ur_status : std_logic;
|
543 |
|
|
signal dbg_ur_unsup_msg : std_logic;
|
544 |
|
|
|
545 |
|
|
signal pipe_gt_power_down_a : std_logic_vector(1 downto 0);
|
546 |
|
|
signal pipe_gt_power_down_b : std_logic_vector(1 downto 0);
|
547 |
|
|
signal pipe_gt_reset_done_a : std_logic;
|
548 |
|
|
signal pipe_gt_reset_done_b : std_logic;
|
549 |
|
|
signal pipe_gt_tx_elec_idle_a : std_logic;
|
550 |
|
|
signal pipe_gt_tx_elec_idle_b : std_logic;
|
551 |
|
|
signal pipe_phy_status_a : std_logic;
|
552 |
|
|
signal pipe_phy_status_b : std_logic;
|
553 |
|
|
signal pipe_rx_charisk_a : std_logic_vector(1 downto 0);
|
554 |
|
|
signal pipe_rx_charisk_b : std_logic_vector(1 downto 0);
|
555 |
|
|
signal pipe_rx_data_a : std_logic_vector(15 downto 0);
|
556 |
|
|
signal pipe_rx_data_b : std_logic_vector(15 downto 0);
|
557 |
|
|
signal pipe_rx_enter_elec_idle_a : std_logic;
|
558 |
|
|
signal pipe_rx_enter_elec_idle_b : std_logic;
|
559 |
|
|
signal pipe_rx_polarity_a : std_logic;
|
560 |
|
|
signal pipe_rx_polarity_b : std_logic;
|
561 |
|
|
signal pipe_rxreset_a : std_logic;
|
562 |
|
|
signal pipe_rxreset_b : std_logic;
|
563 |
|
|
signal pipe_rx_status_a : std_logic_vector(2 downto 0);
|
564 |
|
|
signal pipe_rx_status_b : std_logic_vector(2 downto 0);
|
565 |
|
|
signal pipe_tx_char_disp_mode_a : std_logic_vector(1 downto 0);
|
566 |
|
|
signal pipe_tx_char_disp_mode_b : std_logic_vector(1 downto 0);
|
567 |
|
|
signal pipe_tx_char_disp_val_a : std_logic_vector(1 downto 0);
|
568 |
|
|
signal pipe_tx_char_disp_val_b : std_logic_vector(1 downto 0);
|
569 |
|
|
signal pipe_tx_char_is_k_a : std_logic_vector(1 downto 0);
|
570 |
|
|
signal pipe_tx_char_is_k_b : std_logic_vector(1 downto 0);
|
571 |
|
|
signal pipe_tx_data_a : std_logic_vector(15 downto 0);
|
572 |
|
|
signal pipe_tx_data_b : std_logic_vector(15 downto 0);
|
573 |
|
|
signal pipe_tx_rcvr_det_a : std_logic;
|
574 |
|
|
signal pipe_tx_rcvr_det_b : std_logic;
|
575 |
|
|
|
576 |
|
|
-- GT->PLM PIPE Interface rx
|
577 |
|
|
signal rx_char_is_k : std_logic_vector(1 downto 0);
|
578 |
|
|
signal rx_data : std_logic_vector(15 downto 0);
|
579 |
|
|
signal rx_enter_elecidle : std_logic;
|
580 |
|
|
signal rx_status : std_logic_vector(2 downto 0);
|
581 |
|
|
signal rx_polarity : std_logic;
|
582 |
|
|
|
583 |
|
|
-- GT<-PLM PIPE Interface tx
|
584 |
|
|
signal tx_char_disp_mode : std_logic_vector(1 downto 0);
|
585 |
|
|
signal tx_char_is_k : std_logic_vector(1 downto 0);
|
586 |
|
|
signal tx_rcvr_det : std_logic;
|
587 |
|
|
signal tx_data : std_logic_vector(15 downto 0);
|
588 |
|
|
|
589 |
|
|
-- GT<->PLM PIPE Interface Misc
|
590 |
|
|
signal phystatus : std_logic;
|
591 |
|
|
|
592 |
|
|
-- GT<->PLM PIPE Interface MGT Logic I/O
|
593 |
|
|
signal gt_reset_done : std_logic;
|
594 |
|
|
signal gt_rx_valid : std_logic;
|
595 |
|
|
signal gt_tx_elec_idle : std_logic;
|
596 |
|
|
signal gt_power_down : std_logic_vector(1 downto 0);
|
597 |
|
|
signal rxreset : std_logic;
|
598 |
|
|
signal gt_plllkdet_out : std_logic;
|
599 |
|
|
signal sys_reset : std_logic;
|
600 |
|
|
|
601 |
|
|
-- Core outputs which are also used in this module - must make local copies
|
602 |
|
|
signal trn_clk_c : std_logic;
|
603 |
|
|
signal trn_reset_n_c : std_logic;
|
604 |
|
|
signal trn_reset : std_logic;
|
605 |
|
|
|
606 |
|
|
begin
|
607 |
|
|
|
608 |
|
|
-- These values may be brought out and driven dynamically
|
609 |
|
|
-- from pins rather than attributes if desired. Note -
|
610 |
|
|
-- if they are not statically driven, the values must be
|
611 |
|
|
-- stable before sys_reset_n is released
|
612 |
|
|
w_cfg_ven_id <= CFG_VEN_ID;
|
613 |
|
|
w_cfg_dev_id <= CFG_DEV_ID;
|
614 |
|
|
w_cfg_rev_id <= CFG_REV_ID;
|
615 |
|
|
w_cfg_subsys_ven_id <= CFG_SUBSYS_VEN_ID;
|
616 |
|
|
w_cfg_subsys_id <= CFG_SUBSYS_ID;
|
617 |
|
|
|
618 |
|
|
-- Assign outputs from internal copies
|
619 |
|
|
trn_clk <= trn_clk_c;
|
620 |
|
|
trn_reset_n <= trn_reset_n_c;
|
621 |
|
|
trn_reset <= not trn_reset_n_c;
|
622 |
|
|
|
623 |
|
|
-- Buffer reference clock from MGT
|
624 |
|
|
gt_refclk_bufio2 : BUFIO2
|
625 |
|
|
port map (
|
626 |
|
|
DIVCLK => gt_refclk_buf,
|
627 |
|
|
IOCLK => OPEN,
|
628 |
|
|
SERDESSTROBE => OPEN,
|
629 |
|
|
I => gt_refclk_out(0)
|
630 |
|
|
);
|
631 |
|
|
|
632 |
|
|
pll_base_i : PLL_BASE
|
633 |
|
|
generic map (
|
634 |
|
|
CLKFBOUT_MULT => CLKFBOUT_MULT,
|
635 |
|
|
CLKFBOUT_PHASE => 0.0,
|
636 |
|
|
CLKIN_PERIOD => CLKIN_PERIOD,
|
637 |
|
|
CLKOUT0_DIVIDE => 2,
|
638 |
|
|
CLKOUT0_PHASE => 0.0,
|
639 |
|
|
CLKOUT1_DIVIDE => 4,
|
640 |
|
|
CLKOUT1_PHASE => 0.0,
|
641 |
|
|
CLKOUT2_DIVIDE => 8,
|
642 |
|
|
CLKOUT2_PHASE => 0.0,
|
643 |
|
|
COMPENSATION => "INTERNAL"
|
644 |
|
|
)
|
645 |
|
|
port map (
|
646 |
|
|
CLKIN => gt_refclk_buf,
|
647 |
|
|
CLKFBIN => gt_refclk_fb,
|
648 |
|
|
RST => pll_rst,
|
649 |
|
|
CLKOUT0 => clk_250,
|
650 |
|
|
CLKOUT1 => clk_125,
|
651 |
|
|
CLKOUT2 => clk_62_5,
|
652 |
|
|
CLKOUT3 => OPEN,
|
653 |
|
|
CLKOUT4 => OPEN,
|
654 |
|
|
CLKOUT5 => OPEN,
|
655 |
|
|
CLKFBOUT => gt_refclk_fb,
|
656 |
|
|
LOCKED => clock_locked
|
657 |
|
|
);
|
658 |
|
|
|
659 |
|
|
-------------------------------------
|
660 |
|
|
-- Instantiate buffers where required
|
661 |
|
|
-------------------------------------
|
662 |
|
|
mgt_bufg : BUFG port map (O => mgt_clk, I => clk_125);
|
663 |
|
|
mgt2x_bufg : BUFG port map (O => mgt_clk_2x, I => clk_250);
|
664 |
|
|
phy_bufg : BUFG port map (O => trn_clk_c, I => clk_62_5);
|
665 |
|
|
|
666 |
|
|
----------------------------
|
667 |
|
|
-- PCI Express BRAM Instance
|
668 |
|
|
----------------------------
|
669 |
|
|
pcie_bram_top: pcie_bram_top_s6
|
670 |
|
|
generic map (
|
671 |
|
|
DEV_CAP_MAX_PAYLOAD_SUPPORTED => DEV_CAP_MAX_PAYLOAD_SUPPORTED,
|
672 |
|
|
|
673 |
|
|
VC0_TX_LASTPACKET => VC0_TX_LASTPACKET,
|
674 |
|
|
TLM_TX_OVERHEAD => 20,
|
675 |
|
|
TL_TX_RAM_RADDR_LATENCY => TL_TX_RAM_RADDR_LATENCY,
|
676 |
|
|
TL_TX_RAM_RDATA_LATENCY => TL_TX_RAM_RDATA_LATENCY,
|
677 |
|
|
-- NOTE: use the RX value here since there is no separate TX value
|
678 |
|
|
TL_TX_RAM_WRITE_LATENCY => TL_RX_RAM_WRITE_LATENCY,
|
679 |
|
|
|
680 |
|
|
VC0_RX_LIMIT => conv_integer(to_stdlogicvector(VC0_RX_RAM_LIMIT)),
|
681 |
|
|
TL_RX_RAM_RADDR_LATENCY => TL_RX_RAM_RADDR_LATENCY,
|
682 |
|
|
TL_RX_RAM_RDATA_LATENCY => TL_RX_RAM_RDATA_LATENCY,
|
683 |
|
|
TL_RX_RAM_WRITE_LATENCY => TL_RX_RAM_WRITE_LATENCY
|
684 |
|
|
)
|
685 |
|
|
port map (
|
686 |
|
|
user_clk_i => trn_clk_c,
|
687 |
|
|
reset_i => trn_reset,
|
688 |
|
|
|
689 |
|
|
mim_tx_waddr => mim_tx_waddr,
|
690 |
|
|
mim_tx_wen => mim_tx_wen,
|
691 |
|
|
mim_tx_ren => mim_tx_ren,
|
692 |
|
|
mim_tx_rce => '1',
|
693 |
|
|
mim_tx_wdata => mim_tx_wdata,
|
694 |
|
|
mim_tx_raddr => mim_tx_raddr,
|
695 |
|
|
mim_tx_rdata => mim_tx_rdata,
|
696 |
|
|
|
697 |
|
|
mim_rx_waddr => mim_rx_waddr,
|
698 |
|
|
mim_rx_wen => mim_rx_wen,
|
699 |
|
|
mim_rx_ren => mim_rx_ren,
|
700 |
|
|
mim_rx_rce => '1',
|
701 |
|
|
mim_rx_wdata(35) => '0',
|
702 |
|
|
mim_rx_wdata(34 downto 0) => mim_rx_wdata,
|
703 |
|
|
mim_rx_raddr => mim_rx_raddr,
|
704 |
|
|
mim_rx_rdata(35) => mim_rx_rdata_unused,
|
705 |
|
|
mim_rx_rdata(34 downto 0) => mim_rx_rdata
|
706 |
|
|
);
|
707 |
|
|
|
708 |
|
|
---------------------------------
|
709 |
|
|
-- PCI Express GTA1_DUAL Instance
|
710 |
|
|
---------------------------------
|
711 |
|
|
sys_reset <= not sys_reset_n;
|
712 |
|
|
GT_i : GTPA1_DUAL_WRAPPER
|
713 |
|
|
generic map (
|
714 |
|
|
-- Simulation attributes
|
715 |
|
|
WRAPPER_SIM_GTPRESET_SPEEDUP => 1,
|
716 |
|
|
WRAPPER_CLK25_DIVIDER_0 => GT_CLK25_DIVIDER,
|
717 |
|
|
WRAPPER_CLK25_DIVIDER_1 => GT_CLK25_DIVIDER,
|
718 |
|
|
WRAPPER_PLL_DIVSEL_FB_0 => GT_PLL_DIVSEL_FB,
|
719 |
|
|
WRAPPER_PLL_DIVSEL_FB_1 => GT_PLL_DIVSEL_FB,
|
720 |
|
|
WRAPPER_PLL_DIVSEL_REF_0 => GT_PLL_DIVSEL_REF,
|
721 |
|
|
WRAPPER_PLL_DIVSEL_REF_1 => GT_PLL_DIVSEL_REF,
|
722 |
|
|
WRAPPER_SIMULATION => SIM_INT(FAST_TRAIN)
|
723 |
|
|
)
|
724 |
|
|
port map (
|
725 |
|
|
|
726 |
|
|
------------------------ Loopback and Powerdown Ports ----------------------
|
727 |
|
|
TILE0_RXPOWERDOWN0_IN => gt_power_down,
|
728 |
|
|
TILE0_RXPOWERDOWN1_IN => "10",
|
729 |
|
|
TILE0_TXPOWERDOWN0_IN => gt_power_down,
|
730 |
|
|
TILE0_TXPOWERDOWN1_IN => "10",
|
731 |
|
|
--------------------------------- PLL Ports --------------------------------
|
732 |
|
|
TILE0_CLK00_IN => sys_clk,
|
733 |
|
|
TILE0_CLK01_IN => '0',
|
734 |
|
|
TILE0_GTPRESET0_IN => sys_reset,
|
735 |
|
|
TILE0_GTPRESET1_IN => '1',
|
736 |
|
|
TILE0_PLLLKDET0_OUT => gt_plllkdet_out,
|
737 |
|
|
TILE0_PLLLKDET1_OUT => OPEN,
|
738 |
|
|
TILE0_RESETDONE0_OUT => gt_reset_done,
|
739 |
|
|
TILE0_RESETDONE1_OUT => OPEN,
|
740 |
|
|
----------------------- Receive Ports - 8b10b Decoder ----------------------
|
741 |
|
|
TILE0_RXCHARISK0_OUT(1) => rx_char_is_k(0),
|
742 |
|
|
TILE0_RXCHARISK0_OUT(0) => rx_char_is_k(1),
|
743 |
|
|
TILE0_RXCHARISK1_OUT => OPEN,
|
744 |
|
|
TILE0_RXDISPERR0_OUT => OPEN,
|
745 |
|
|
TILE0_RXDISPERR1_OUT => OPEN,
|
746 |
|
|
TILE0_RXNOTINTABLE0_OUT => OPEN,
|
747 |
|
|
TILE0_RXNOTINTABLE1_OUT => OPEN,
|
748 |
|
|
---------------------- Receive Ports - Clock Correction --------------------
|
749 |
|
|
TILE0_RXCLKCORCNT0_OUT => OPEN,
|
750 |
|
|
TILE0_RXCLKCORCNT1_OUT => OPEN,
|
751 |
|
|
--------------- Receive Ports - Comma Detection and Alignment --------------
|
752 |
|
|
TILE0_RXENMCOMMAALIGN0_IN => '1',
|
753 |
|
|
TILE0_RXENMCOMMAALIGN1_IN => '1',
|
754 |
|
|
TILE0_RXENPCOMMAALIGN0_IN => '1',
|
755 |
|
|
TILE0_RXENPCOMMAALIGN1_IN => '1',
|
756 |
|
|
------------------- Receive Ports - RX Data Path interface -----------------
|
757 |
|
|
TILE0_RXDATA0_OUT(15 downto 8) => rx_data(7 downto 0),
|
758 |
|
|
TILE0_RXDATA0_OUT(7 downto 0) => rx_data(15 downto 8),
|
759 |
|
|
TILE0_RXDATA1_OUT => OPEN,
|
760 |
|
|
TILE0_RXRESET0_IN => rxreset,
|
761 |
|
|
TILE0_RXRESET1_IN => '1',
|
762 |
|
|
TILE0_RXUSRCLK0_IN => mgt_clk_2x,
|
763 |
|
|
TILE0_RXUSRCLK1_IN => '0',
|
764 |
|
|
TILE0_RXUSRCLK20_IN => mgt_clk,
|
765 |
|
|
TILE0_RXUSRCLK21_IN => '0',
|
766 |
|
|
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
|
767 |
|
|
TILE0_GATERXELECIDLE0_IN => '0',
|
768 |
|
|
TILE0_GATERXELECIDLE1_IN => '0',
|
769 |
|
|
TILE0_IGNORESIGDET0_IN => '0',
|
770 |
|
|
TILE0_IGNORESIGDET1_IN => '0',
|
771 |
|
|
TILE0_RXELECIDLE0_OUT => rx_enter_elecidle,
|
772 |
|
|
TILE0_RXELECIDLE1_OUT => OPEN,
|
773 |
|
|
TILE0_RXN0_IN => pci_exp_rxn,
|
774 |
|
|
TILE0_RXN1_IN => '0',
|
775 |
|
|
TILE0_RXP0_IN => pci_exp_rxp,
|
776 |
|
|
TILE0_RXP1_IN => '0',
|
777 |
|
|
----------- Receive Ports - RX Elastic Buffer and Phase Alignment ----------
|
778 |
|
|
TILE0_RXSTATUS0_OUT => rx_status,
|
779 |
|
|
TILE0_RXSTATUS1_OUT => OPEN,
|
780 |
|
|
-------------- Receive Ports - RX Pipe Control for PCI Express -------------
|
781 |
|
|
TILE0_PHYSTATUS0_OUT => phystatus,
|
782 |
|
|
TILE0_PHYSTATUS1_OUT => OPEN,
|
783 |
|
|
TILE0_RXVALID0_OUT => gt_rx_valid,
|
784 |
|
|
TILE0_RXVALID1_OUT => OPEN,
|
785 |
|
|
-------------------- Receive Ports - RX Polarity Control -------------------
|
786 |
|
|
TILE0_RXPOLARITY0_IN => rx_polarity,
|
787 |
|
|
TILE0_RXPOLARITY1_IN => '0',
|
788 |
|
|
---------------------------- TX/RX Datapath Ports --------------------------
|
789 |
|
|
TILE0_GTPCLKOUT0_OUT => gt_refclk_out,
|
790 |
|
|
TILE0_GTPCLKOUT1_OUT => OPEN,
|
791 |
|
|
------------------- Transmit Ports - 8b10b Encoder Control -----------------
|
792 |
|
|
TILE0_TXCHARDISPMODE0_IN(1) => tx_char_disp_mode(0),
|
793 |
|
|
TILE0_TXCHARDISPMODE0_IN(0) => tx_char_disp_mode(1),
|
794 |
|
|
TILE0_TXCHARDISPMODE1_IN(1) => '0',
|
795 |
|
|
TILE0_TXCHARDISPMODE1_IN(0) => '0',
|
796 |
|
|
TILE0_TXCHARISK0_IN(1) => tx_char_is_k(0),
|
797 |
|
|
TILE0_TXCHARISK0_IN(0) => tx_char_is_k(1),
|
798 |
|
|
TILE0_TXCHARISK1_IN(1) => '0',
|
799 |
|
|
TILE0_TXCHARISK1_IN(0) => '0',
|
800 |
|
|
------------------ Transmit Ports - TX Data Path interface -----------------
|
801 |
|
|
TILE0_TXDATA0_IN(15 downto 8) => tx_data(7 downto 0),
|
802 |
|
|
TILE0_TXDATA0_IN(7 downto 0) => tx_data(15 downto 8),
|
803 |
|
|
TILE0_TXDATA1_IN(15 downto 8) => x"00",
|
804 |
|
|
TILE0_TXDATA1_IN(7 downto 0) => x"00",
|
805 |
|
|
TILE0_TXUSRCLK0_IN => mgt_clk_2x,
|
806 |
|
|
TILE0_TXUSRCLK1_IN => '0',
|
807 |
|
|
TILE0_TXUSRCLK20_IN => mgt_clk,
|
808 |
|
|
TILE0_TXUSRCLK21_IN => '0',
|
809 |
|
|
--------------- Transmit Ports - TX Driver and OOB signalling --------------
|
810 |
|
|
TILE0_TXN0_OUT => pci_exp_txn,
|
811 |
|
|
TILE0_TXN1_OUT => OPEN,
|
812 |
|
|
TILE0_TXP0_OUT => pci_exp_txp,
|
813 |
|
|
TILE0_TXP1_OUT => OPEN,
|
814 |
|
|
----------------- Transmit Ports - TX Ports for PCI Express ----------------
|
815 |
|
|
TILE0_TXDETECTRX0_IN => tx_rcvr_det,
|
816 |
|
|
TILE0_TXDETECTRX1_IN => '0',
|
817 |
|
|
TILE0_TXELECIDLE0_IN => gt_tx_elec_idle,
|
818 |
|
|
TILE0_TXELECIDLE1_IN => '0' );
|
819 |
|
|
|
820 |
|
|
-- Generate the reset for the PLL
|
821 |
|
|
pll_rst <= (not gt_plllkdet_out) or (not sys_reset_n);
|
822 |
|
|
|
823 |
|
|
---------------------------------------------------------------------------
|
824 |
|
|
-- Generate the connection between PCIE_A1 block and the GTPA1_DUAL. When
|
825 |
|
|
-- the parameter GTP_SEL is 0, connect to PIPEA, when it is a 1, connect to
|
826 |
|
|
-- PIPEB.
|
827 |
|
|
---------------------------------------------------------------------------
|
828 |
|
|
PIPE_A_SEL : if (GTP_SEL = 0) generate
|
829 |
|
|
-- Signals from GTPA1_DUAL to PCIE_A1
|
830 |
|
|
pipe_rx_charisk_a <= rx_char_is_k;
|
831 |
|
|
pipe_rx_data_a <= rx_data;
|
832 |
|
|
pipe_rx_enter_elec_idle_a <= rx_enter_elecidle;
|
833 |
|
|
pipe_rx_status_a <= rx_status;
|
834 |
|
|
pipe_phy_status_a <= phystatus;
|
835 |
|
|
pipe_gt_reset_done_a <= gt_reset_done;
|
836 |
|
|
|
837 |
|
|
-- Unused PCIE_A1 inputs
|
838 |
|
|
pipe_rx_charisk_b <= "00";
|
839 |
|
|
pipe_rx_data_b <= x"0000";
|
840 |
|
|
pipe_rx_enter_elec_idle_b <= '0';
|
841 |
|
|
pipe_rx_status_b <= "000";
|
842 |
|
|
pipe_phy_status_b <= '0';
|
843 |
|
|
pipe_gt_reset_done_b <= '0';
|
844 |
|
|
|
845 |
|
|
-- Signals from PCIE_A1 to GTPA1_DUAL
|
846 |
|
|
rx_polarity <= pipe_rx_polarity_a;
|
847 |
|
|
tx_char_disp_mode <= pipe_tx_char_disp_mode_a;
|
848 |
|
|
tx_char_is_k <= pipe_tx_char_is_k_a;
|
849 |
|
|
tx_rcvr_det <= pipe_tx_rcvr_det_a;
|
850 |
|
|
tx_data <= pipe_tx_data_a;
|
851 |
|
|
gt_tx_elec_idle <= pipe_gt_tx_elec_idle_a;
|
852 |
|
|
gt_power_down <= pipe_gt_power_down_a;
|
853 |
|
|
rxreset <= pipe_rxreset_a;
|
854 |
|
|
end generate PIPE_A_SEL;
|
855 |
|
|
|
856 |
|
|
PIPE_B_SEL : if (GTP_SEL = 1) generate
|
857 |
|
|
-- Signals from GTPA1_DUAL to PCIE_A1
|
858 |
|
|
pipe_rx_charisk_b <= rx_char_is_k;
|
859 |
|
|
pipe_rx_data_b <= rx_data;
|
860 |
|
|
pipe_rx_enter_elec_idle_b <= rx_enter_elecidle;
|
861 |
|
|
pipe_rx_status_b <= rx_status;
|
862 |
|
|
pipe_phy_status_b <= phystatus;
|
863 |
|
|
pipe_gt_reset_done_b <= gt_reset_done;
|
864 |
|
|
|
865 |
|
|
-- Unused PCIE_A1 inputs
|
866 |
|
|
pipe_rx_charisk_a <= "00";
|
867 |
|
|
pipe_rx_data_a <= x"0000";
|
868 |
|
|
pipe_rx_enter_elec_idle_a <= '0';
|
869 |
|
|
pipe_rx_status_a <= "000";
|
870 |
|
|
pipe_phy_status_a <= '0';
|
871 |
|
|
pipe_gt_reset_done_a <= '0';
|
872 |
|
|
|
873 |
|
|
-- Signals from PCIE_A1 to GTPA1_DUAL
|
874 |
|
|
rx_polarity <= pipe_rx_polarity_b;
|
875 |
|
|
tx_char_disp_mode <= pipe_tx_char_disp_mode_b;
|
876 |
|
|
tx_char_is_k <= pipe_tx_char_is_k_b;
|
877 |
|
|
tx_rcvr_det <= pipe_tx_rcvr_det_b;
|
878 |
|
|
tx_data <= pipe_tx_data_b;
|
879 |
|
|
gt_tx_elec_idle <= pipe_gt_tx_elec_idle_b;
|
880 |
|
|
gt_power_down <= pipe_gt_power_down_b;
|
881 |
|
|
rxreset <= pipe_rxreset_b;
|
882 |
|
|
end generate PIPE_B_SEL;
|
883 |
|
|
|
884 |
|
|
---------------------------------------------------------------
|
885 |
|
|
-- Integrated Endpoint Block for PCI Express Instance (PCIE_A1)
|
886 |
|
|
---------------------------------------------------------------
|
887 |
|
|
|
888 |
|
|
PCIE_A1_inst : PCIE_A1
|
889 |
|
|
generic map (
|
890 |
|
|
BAR0 => BAR0,
|
891 |
|
|
BAR1 => BAR1,
|
892 |
|
|
BAR2 => BAR2,
|
893 |
|
|
BAR3 => BAR3,
|
894 |
|
|
BAR4 => BAR4,
|
895 |
|
|
BAR5 => BAR5,
|
896 |
|
|
CARDBUS_CIS_POINTER => CARDBUS_CIS_POINTER,
|
897 |
|
|
CLASS_CODE => CLASS_CODE,
|
898 |
|
|
DEV_CAP_ENDPOINT_L0S_LATENCY => DEV_CAP_ENDPOINT_L0S_LATENCY,
|
899 |
|
|
DEV_CAP_ENDPOINT_L1_LATENCY => DEV_CAP_ENDPOINT_L1_LATENCY,
|
900 |
|
|
DEV_CAP_EXT_TAG_SUPPORTED => DEV_CAP_EXT_TAG_SUPPORTED,
|
901 |
|
|
DEV_CAP_MAX_PAYLOAD_SUPPORTED => DEV_CAP_MAX_PAYLOAD_SUPPORTED,
|
902 |
|
|
DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT => DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT,
|
903 |
|
|
DEV_CAP_ROLE_BASED_ERROR => DEV_CAP_ROLE_BASED_ERROR,
|
904 |
|
|
DISABLE_BAR_FILTERING => DISABLE_BAR_FILTERING,
|
905 |
|
|
DISABLE_ID_CHECK => DISABLE_ID_CHECK,
|
906 |
|
|
DISABLE_SCRAMBLING => DISABLE_SCRAMBLING,
|
907 |
|
|
ENABLE_RX_TD_ECRC_TRIM => ENABLE_RX_TD_ECRC_TRIM,
|
908 |
|
|
EXPANSION_ROM => EXPANSION_ROM,
|
909 |
|
|
FAST_TRAIN => FAST_TRAIN,
|
910 |
|
|
GTP_SEL => GTP_SEL,
|
911 |
|
|
LINK_CAP_ASPM_SUPPORT => LINK_CAP_ASPM_SUPPORT,
|
912 |
|
|
LINK_CAP_L0S_EXIT_LATENCY => LINK_CAP_L0S_EXIT_LATENCY,
|
913 |
|
|
LINK_CAP_L1_EXIT_LATENCY => LINK_CAP_L1_EXIT_LATENCY,
|
914 |
|
|
LINK_STATUS_SLOT_CLOCK_CONFIG => LINK_STATUS_SLOT_CLOCK_CONFIG,
|
915 |
|
|
LL_ACK_TIMEOUT => LL_ACK_TIMEOUT,
|
916 |
|
|
LL_ACK_TIMEOUT_EN => LL_ACK_TIMEOUT_EN,
|
917 |
|
|
LL_REPLAY_TIMEOUT => LL_REPLAY_TIMEOUT,
|
918 |
|
|
LL_REPLAY_TIMEOUT_EN => LL_REPLAY_TIMEOUT_EN,
|
919 |
|
|
MSI_CAP_MULTIMSG_EXTENSION => MSI_CAP_MULTIMSG_EXTENSION,
|
920 |
|
|
MSI_CAP_MULTIMSGCAP => MSI_CAP_MULTIMSGCAP,
|
921 |
|
|
PCIE_CAP_CAPABILITY_VERSION => PCIE_CAP_CAPABILITY_VERSION,
|
922 |
|
|
PCIE_CAP_DEVICE_PORT_TYPE => PCIE_CAP_DEVICE_PORT_TYPE,
|
923 |
|
|
PCIE_CAP_INT_MSG_NUM => PCIE_CAP_INT_MSG_NUM,
|
924 |
|
|
PCIE_CAP_SLOT_IMPLEMENTED => PCIE_CAP_SLOT_IMPLEMENTED,
|
925 |
|
|
PCIE_GENERIC => PCIE_GENERIC,
|
926 |
|
|
PLM_AUTO_CONFIG => PLM_AUTO_CONFIG,
|
927 |
|
|
PM_CAP_AUXCURRENT => PM_CAP_AUXCURRENT,
|
928 |
|
|
PM_CAP_DSI => PM_CAP_DSI,
|
929 |
|
|
PM_CAP_D1SUPPORT => PM_CAP_D1SUPPORT,
|
930 |
|
|
PM_CAP_D2SUPPORT => PM_CAP_D2SUPPORT,
|
931 |
|
|
PM_CAP_PME_CLOCK => PM_CAP_PME_CLOCK,
|
932 |
|
|
PM_CAP_PMESUPPORT => PM_CAP_PMESUPPORT,
|
933 |
|
|
PM_CAP_VERSION => PM_CAP_VERSION,
|
934 |
|
|
PM_DATA_SCALE0 => PM_DATA_SCALE0,
|
935 |
|
|
PM_DATA_SCALE1 => PM_DATA_SCALE1,
|
936 |
|
|
PM_DATA_SCALE2 => PM_DATA_SCALE2,
|
937 |
|
|
PM_DATA_SCALE3 => PM_DATA_SCALE3,
|
938 |
|
|
PM_DATA_SCALE4 => PM_DATA_SCALE4,
|
939 |
|
|
PM_DATA_SCALE5 => PM_DATA_SCALE5,
|
940 |
|
|
PM_DATA_SCALE6 => PM_DATA_SCALE6,
|
941 |
|
|
PM_DATA_SCALE7 => PM_DATA_SCALE7,
|
942 |
|
|
PM_DATA0 => PM_DATA0,
|
943 |
|
|
PM_DATA1 => PM_DATA1,
|
944 |
|
|
PM_DATA2 => PM_DATA2,
|
945 |
|
|
PM_DATA3 => PM_DATA3,
|
946 |
|
|
PM_DATA4 => PM_DATA4,
|
947 |
|
|
PM_DATA5 => PM_DATA5,
|
948 |
|
|
PM_DATA6 => PM_DATA6,
|
949 |
|
|
PM_DATA7 => PM_DATA7,
|
950 |
|
|
SLOT_CAP_ATT_BUTTON_PRESENT => SLOT_CAP_ATT_BUTTON_PRESENT,
|
951 |
|
|
SLOT_CAP_ATT_INDICATOR_PRESENT => SLOT_CAP_ATT_INDICATOR_PRESENT,
|
952 |
|
|
SLOT_CAP_POWER_INDICATOR_PRESENT => SLOT_CAP_POWER_INDICATOR_PRESENT,
|
953 |
|
|
TL_RX_RAM_RADDR_LATENCY => TL_RX_RAM_RADDR_LATENCY,
|
954 |
|
|
TL_RX_RAM_RDATA_LATENCY => TL_RX_RAM_RDATA_LATENCY,
|
955 |
|
|
TL_RX_RAM_WRITE_LATENCY => TL_RX_RAM_WRITE_LATENCY,
|
956 |
|
|
TL_TFC_DISABLE => TL_TFC_DISABLE,
|
957 |
|
|
TL_TX_CHECKS_DISABLE => TL_TX_CHECKS_DISABLE,
|
958 |
|
|
TL_TX_RAM_RADDR_LATENCY => TL_TX_RAM_RADDR_LATENCY,
|
959 |
|
|
TL_TX_RAM_RDATA_LATENCY => TL_TX_RAM_RDATA_LATENCY,
|
960 |
|
|
USR_CFG => USR_CFG,
|
961 |
|
|
USR_EXT_CFG => USR_EXT_CFG,
|
962 |
|
|
VC0_CPL_INFINITE => VC0_CPL_INFINITE,
|
963 |
|
|
VC0_RX_RAM_LIMIT => VC0_RX_RAM_LIMIT,
|
964 |
|
|
VC0_TOTAL_CREDITS_CD => VC0_TOTAL_CREDITS_CD,
|
965 |
|
|
VC0_TOTAL_CREDITS_CH => VC0_TOTAL_CREDITS_CH,
|
966 |
|
|
VC0_TOTAL_CREDITS_NPH => VC0_TOTAL_CREDITS_NPH,
|
967 |
|
|
VC0_TOTAL_CREDITS_PD => VC0_TOTAL_CREDITS_PD,
|
968 |
|
|
VC0_TOTAL_CREDITS_PH => VC0_TOTAL_CREDITS_PH,
|
969 |
|
|
VC0_TX_LASTPACKET => VC0_TX_LASTPACKET
|
970 |
|
|
)
|
971 |
|
|
port map (
|
972 |
|
|
CFGBUSNUMBER => cfg_bus_number,
|
973 |
|
|
CFGCOMMANDBUSMASTERENABLE => cfg_command_bus_master_enable,
|
974 |
|
|
CFGCOMMANDINTERRUPTDISABLE => cfg_command_interrupt_disable,
|
975 |
|
|
CFGCOMMANDIOENABLE => cfg_command_io_enable,
|
976 |
|
|
CFGCOMMANDMEMENABLE => cfg_command_mem_enable,
|
977 |
|
|
CFGCOMMANDSERREN => cfg_command_serr_en,
|
978 |
|
|
CFGDEVCONTROLAUXPOWEREN => cfg_dev_control_aux_power_en,
|
979 |
|
|
CFGDEVCONTROLCORRERRREPORTINGEN => cfg_dev_control_corr_err_reporting_en,
|
980 |
|
|
CFGDEVCONTROLENABLERO => cfg_dev_control_enable_ro,
|
981 |
|
|
CFGDEVCONTROLEXTTAGEN => cfg_dev_control_ext_tag_en,
|
982 |
|
|
CFGDEVCONTROLFATALERRREPORTINGEN => cfg_dev_control_fatal_err_reporting_en,
|
983 |
|
|
CFGDEVCONTROLMAXPAYLOAD => cfg_dev_control_max_payload,
|
984 |
|
|
CFGDEVCONTROLMAXREADREQ => cfg_dev_control_max_read_req,
|
985 |
|
|
CFGDEVCONTROLNONFATALREPORTINGEN => cfg_dev_control_non_fatal_reporting_en,
|
986 |
|
|
CFGDEVCONTROLNOSNOOPEN => cfg_dev_control_no_snoop_en,
|
987 |
|
|
CFGDEVCONTROLPHANTOMEN => cfg_dev_control_phantom_en,
|
988 |
|
|
CFGDEVCONTROLURERRREPORTINGEN => cfg_dev_control_ur_err_reporting_en,
|
989 |
|
|
CFGDEVICENUMBER => cfg_device_number,
|
990 |
|
|
CFGDEVID => w_cfg_dev_id,
|
991 |
|
|
CFGDEVSTATUSCORRERRDETECTED => cfg_dev_status_corr_err_detected,
|
992 |
|
|
CFGDEVSTATUSFATALERRDETECTED => cfg_dev_status_fatal_err_detected,
|
993 |
|
|
CFGDEVSTATUSNONFATALERRDETECTED => cfg_dev_status_nonfatal_err_detected,
|
994 |
|
|
CFGDEVSTATUSURDETECTED => cfg_dev_status_ur_detected,
|
995 |
|
|
CFGDO => cfg_do,
|
996 |
|
|
CFGDSN => cfg_dsn,
|
997 |
|
|
CFGDWADDR => cfg_dwaddr,
|
998 |
|
|
CFGERRCORN => cfg_err_cor_n,
|
999 |
|
|
CFGERRCPLABORTN => cfg_err_cpl_abort_n,
|
1000 |
|
|
CFGERRCPLRDYN => cfg_err_cpl_rdy_n,
|
1001 |
|
|
CFGERRCPLTIMEOUTN => cfg_err_cpl_timeout_n,
|
1002 |
|
|
CFGERRECRCN => cfg_err_ecrc_n,
|
1003 |
|
|
CFGERRLOCKEDN => cfg_err_locked_n,
|
1004 |
|
|
CFGERRPOSTEDN => cfg_err_posted_n,
|
1005 |
|
|
CFGERRTLPCPLHEADER => cfg_err_tlp_cpl_header,
|
1006 |
|
|
CFGERRURN => cfg_err_ur_n,
|
1007 |
|
|
CFGFUNCTIONNUMBER => cfg_function_number,
|
1008 |
|
|
CFGINTERRUPTASSERTN => cfg_interrupt_assert_n,
|
1009 |
|
|
CFGINTERRUPTDI => cfg_interrupt_di,
|
1010 |
|
|
CFGINTERRUPTDO => cfg_interrupt_do,
|
1011 |
|
|
CFGINTERRUPTMMENABLE => cfg_interrupt_mmenable,
|
1012 |
|
|
CFGINTERRUPTMSIENABLE => cfg_interrupt_msienable,
|
1013 |
|
|
CFGINTERRUPTN => cfg_interrupt_n,
|
1014 |
|
|
CFGINTERRUPTRDYN => cfg_interrupt_rdy_n,
|
1015 |
|
|
CFGLINKCONTOLRCB => cfg_link_control_rcb,
|
1016 |
|
|
CFGLINKCONTROLASPMCONTROL => cfg_link_control_aspm_control,
|
1017 |
|
|
CFGLINKCONTROLCOMMONCLOCK => cfg_link_control_common_clock,
|
1018 |
|
|
CFGLINKCONTROLEXTENDEDSYNC => cfg_link_control_extended_sync,
|
1019 |
|
|
CFGLTSSMSTATE => cfg_ltssm_state,
|
1020 |
|
|
CFGPCIELINKSTATEN => cfg_pcie_link_state_n,
|
1021 |
|
|
CFGPMWAKEN => cfg_pm_wake_n,
|
1022 |
|
|
CFGRDENN => cfg_rd_en_n,
|
1023 |
|
|
CFGRDWRDONEN => cfg_rd_wr_done_n,
|
1024 |
|
|
CFGREVID => w_cfg_rev_id,
|
1025 |
|
|
CFGSUBSYSID => w_cfg_subsys_id,
|
1026 |
|
|
CFGSUBSYSVENID => w_cfg_subsys_ven_id,
|
1027 |
|
|
CFGTOTURNOFFN => cfg_to_turnoff_n,
|
1028 |
|
|
CFGTRNPENDINGN => cfg_trn_pending_n,
|
1029 |
|
|
CFGTURNOFFOKN => cfg_turnoff_ok_n,
|
1030 |
|
|
CFGVENID => w_cfg_ven_id,
|
1031 |
|
|
CLOCKLOCKED => clock_locked,
|
1032 |
|
|
DBGBADDLLPSTATUS => dbg_bad_dllp_status,
|
1033 |
|
|
DBGBADTLPLCRC => dbg_bad_tlp_lcrc,
|
1034 |
|
|
DBGBADTLPSEQNUM => dbg_bad_tlp_seq_num,
|
1035 |
|
|
DBGBADTLPSTATUS => dbg_bad_tlp_status,
|
1036 |
|
|
DBGDLPROTOCOLSTATUS => dbg_dl_protocol_status,
|
1037 |
|
|
DBGFCPROTOCOLERRSTATUS => dbg_fc_protocol_err_status,
|
1038 |
|
|
DBGMLFRMDLENGTH => dbg_mlfrmd_length,
|
1039 |
|
|
DBGMLFRMDMPS => dbg_mlfrmd_mps,
|
1040 |
|
|
DBGMLFRMDTCVC => dbg_mlfrmd_tcvc,
|
1041 |
|
|
DBGMLFRMDTLPSTATUS => dbg_mlfrmd_tlp_status,
|
1042 |
|
|
DBGMLFRMDUNRECTYPE => dbg_mlfrmd_unrec_type,
|
1043 |
|
|
DBGPOISTLPSTATUS => dbg_poistlpstatus,
|
1044 |
|
|
DBGRCVROVERFLOWSTATUS => dbg_rcvr_overflow_status,
|
1045 |
|
|
DBGREGDETECTEDCORRECTABLE => dbg_reg_detected_correctable,
|
1046 |
|
|
DBGREGDETECTEDFATAL => dbg_reg_detected_fatal,
|
1047 |
|
|
DBGREGDETECTEDNONFATAL => dbg_reg_detected_non_fatal,
|
1048 |
|
|
DBGREGDETECTEDUNSUPPORTED => dbg_reg_detected_unsupported,
|
1049 |
|
|
DBGRPLYROLLOVERSTATUS => dbg_rply_rollover_status,
|
1050 |
|
|
DBGRPLYTIMEOUTSTATUS => dbg_rply_timeout_status,
|
1051 |
|
|
DBGURNOBARHIT => dbg_ur_no_bar_hit,
|
1052 |
|
|
DBGURPOISCFGWR => dbg_ur_pois_cfg_wr,
|
1053 |
|
|
DBGURSTATUS => dbg_ur_status,
|
1054 |
|
|
DBGURUNSUPMSG => dbg_ur_unsup_msg,
|
1055 |
|
|
MGTCLK => mgt_clk,
|
1056 |
|
|
MIMRXRADDR => mim_rx_raddr,
|
1057 |
|
|
MIMRXRDATA => mim_rx_rdata,
|
1058 |
|
|
MIMRXREN => mim_rx_ren,
|
1059 |
|
|
MIMRXWADDR => mim_rx_waddr,
|
1060 |
|
|
MIMRXWDATA => mim_rx_wdata,
|
1061 |
|
|
MIMRXWEN => mim_rx_wen,
|
1062 |
|
|
MIMTXRADDR => mim_tx_raddr,
|
1063 |
|
|
MIMTXRDATA => mim_tx_rdata,
|
1064 |
|
|
MIMTXREN => mim_tx_ren,
|
1065 |
|
|
MIMTXWADDR => mim_tx_waddr,
|
1066 |
|
|
MIMTXWDATA => mim_tx_wdata,
|
1067 |
|
|
MIMTXWEN => mim_tx_wen,
|
1068 |
|
|
PIPEGTPOWERDOWNA => pipe_gt_power_down_a,
|
1069 |
|
|
PIPEGTPOWERDOWNB => pipe_gt_power_down_b,
|
1070 |
|
|
PIPEGTRESETDONEA => pipe_gt_reset_done_a,
|
1071 |
|
|
PIPEGTRESETDONEB => pipe_gt_reset_done_b,
|
1072 |
|
|
PIPEGTTXELECIDLEA => pipe_gt_tx_elec_idle_a,
|
1073 |
|
|
PIPEGTTXELECIDLEB => pipe_gt_tx_elec_idle_b,
|
1074 |
|
|
PIPEPHYSTATUSA => pipe_phy_status_a,
|
1075 |
|
|
PIPEPHYSTATUSB => pipe_phy_status_b,
|
1076 |
|
|
PIPERXCHARISKA => pipe_rx_charisk_a,
|
1077 |
|
|
PIPERXCHARISKB => pipe_rx_charisk_b,
|
1078 |
|
|
PIPERXDATAA => pipe_rx_data_a,
|
1079 |
|
|
PIPERXDATAB => pipe_rx_data_b,
|
1080 |
|
|
PIPERXENTERELECIDLEA => pipe_rx_enter_elec_idle_a,
|
1081 |
|
|
PIPERXENTERELECIDLEB => pipe_rx_enter_elec_idle_b,
|
1082 |
|
|
PIPERXPOLARITYA => pipe_rx_polarity_a,
|
1083 |
|
|
PIPERXPOLARITYB => pipe_rx_polarity_b,
|
1084 |
|
|
PIPERXRESETA => pipe_rxreset_a,
|
1085 |
|
|
PIPERXRESETB => pipe_rxreset_b,
|
1086 |
|
|
PIPERXSTATUSA => pipe_rx_status_a,
|
1087 |
|
|
PIPERXSTATUSB => pipe_rx_status_b,
|
1088 |
|
|
PIPETXCHARDISPMODEA => pipe_tx_char_disp_mode_a,
|
1089 |
|
|
PIPETXCHARDISPMODEB => pipe_tx_char_disp_mode_b,
|
1090 |
|
|
PIPETXCHARDISPVALA => pipe_tx_char_disp_val_a,
|
1091 |
|
|
PIPETXCHARDISPVALB => pipe_tx_char_disp_val_b,
|
1092 |
|
|
PIPETXCHARISKA => pipe_tx_char_is_k_a,
|
1093 |
|
|
PIPETXCHARISKB => pipe_tx_char_is_k_b,
|
1094 |
|
|
PIPETXDATAA => pipe_tx_data_a,
|
1095 |
|
|
PIPETXDATAB => pipe_tx_data_b,
|
1096 |
|
|
PIPETXRCVRDETA => pipe_tx_rcvr_det_a,
|
1097 |
|
|
PIPETXRCVRDETB => pipe_tx_rcvr_det_b,
|
1098 |
|
|
RECEIVEDHOTRESET => received_hot_reset,
|
1099 |
|
|
SYSRESETN => sys_reset_n,
|
1100 |
|
|
TRNFCCPLD => trn_fc_cpld,
|
1101 |
|
|
TRNFCCPLH => trn_fc_cplh,
|
1102 |
|
|
TRNFCNPD => trn_fc_npd,
|
1103 |
|
|
TRNFCNPH => trn_fc_nph,
|
1104 |
|
|
TRNFCPD => trn_fc_pd,
|
1105 |
|
|
TRNFCPH => trn_fc_ph,
|
1106 |
|
|
TRNFCSEL => trn_fc_sel,
|
1107 |
|
|
TRNLNKUPN => trn_lnk_up_n,
|
1108 |
|
|
TRNRBARHITN => trn_rbar_hit_n,
|
1109 |
|
|
TRNRD => trn_rd,
|
1110 |
|
|
TRNRDSTRDYN => trn_rdst_rdy_n,
|
1111 |
|
|
TRNREOFN => trn_reof_n,
|
1112 |
|
|
TRNRERRFWDN => trn_rerrfwd_n,
|
1113 |
|
|
TRNRNPOKN => trn_rnp_ok_n,
|
1114 |
|
|
TRNRSOFN => trn_rsof_n,
|
1115 |
|
|
TRNRSRCDSCN => trn_rsrc_dsc_n,
|
1116 |
|
|
TRNRSRCRDYN => trn_rsrc_rdy_n,
|
1117 |
|
|
TRNTBUFAV => trn_tbuf_av,
|
1118 |
|
|
TRNTCFGGNTN => trn_tcfg_gnt_n,
|
1119 |
|
|
TRNTCFGREQN => trn_tcfg_req_n,
|
1120 |
|
|
TRNTD => trn_td,
|
1121 |
|
|
TRNTDSTRDYN => trn_tdst_rdy_n,
|
1122 |
|
|
TRNTEOFN => trn_teof_n,
|
1123 |
|
|
TRNTERRDROPN => trn_terr_drop_n,
|
1124 |
|
|
TRNTERRFWDN => trn_terrfwd_n,
|
1125 |
|
|
TRNTSOFN => trn_tsof_n,
|
1126 |
|
|
TRNTSRCDSCN => trn_tsrc_dsc_n,
|
1127 |
|
|
TRNTSRCRDYN => trn_tsrc_rdy_n,
|
1128 |
|
|
TRNTSTRN => trn_tstr_n,
|
1129 |
|
|
USERCLK => trn_clk_c,
|
1130 |
|
|
USERRSTN => trn_reset_n_c
|
1131 |
|
|
);
|
1132 |
|
|
|
1133 |
|
|
----------------------------------------------------
|
1134 |
|
|
-- Recreate wrapper outputs from the PCIE_A1 signals
|
1135 |
|
|
----------------------------------------------------
|
1136 |
|
|
cfg_status <= x"0000";
|
1137 |
|
|
|
1138 |
|
|
cfg_command <= "00000" &
|
1139 |
|
|
cfg_command_interrupt_disable &
|
1140 |
|
|
"0" &
|
1141 |
|
|
cfg_command_serr_en &
|
1142 |
|
|
"00000" &
|
1143 |
|
|
cfg_command_bus_master_enable &
|
1144 |
|
|
cfg_command_mem_enable &
|
1145 |
|
|
cfg_command_io_enable;
|
1146 |
|
|
|
1147 |
|
|
cfg_dstatus <= "0000000000" &
|
1148 |
|
|
not cfg_trn_pending_n &
|
1149 |
|
|
'0' &
|
1150 |
|
|
cfg_dev_status_ur_detected &
|
1151 |
|
|
cfg_dev_status_fatal_err_detected &
|
1152 |
|
|
cfg_dev_status_nonfatal_err_detected &
|
1153 |
|
|
cfg_dev_status_corr_err_detected;
|
1154 |
|
|
|
1155 |
|
|
cfg_dcommand <= '0' &
|
1156 |
|
|
cfg_dev_control_max_read_req &
|
1157 |
|
|
cfg_dev_control_no_snoop_en &
|
1158 |
|
|
cfg_dev_control_aux_power_en &
|
1159 |
|
|
cfg_dev_control_phantom_en &
|
1160 |
|
|
cfg_dev_control_ext_tag_en &
|
1161 |
|
|
cfg_dev_control_max_payload &
|
1162 |
|
|
cfg_dev_control_enable_ro &
|
1163 |
|
|
cfg_dev_control_ur_err_reporting_en &
|
1164 |
|
|
cfg_dev_control_fatal_err_reporting_en &
|
1165 |
|
|
cfg_dev_control_non_fatal_reporting_en &
|
1166 |
|
|
cfg_dev_control_corr_err_reporting_en;
|
1167 |
|
|
|
1168 |
|
|
cfg_lstatus <= x"0011";
|
1169 |
|
|
|
1170 |
|
|
cfg_lcommand <= x"00" &
|
1171 |
|
|
cfg_link_control_extended_sync &
|
1172 |
|
|
cfg_link_control_common_clock &
|
1173 |
|
|
"00" &
|
1174 |
|
|
cfg_link_control_rcb &
|
1175 |
|
|
'0' &
|
1176 |
|
|
cfg_link_control_aspm_control;
|
1177 |
|
|
|
1178 |
|
|
end rtl;
|