Subversion Repositories pcie_ds_dma

-------------------------------------------------------------------------------

--

-- (c) Copyright 2008, 2009 Xilinx, Inc. All rights reserved.

--

-- This file contains confidential and proprietary information

-- of Xilinx, Inc. and is protected under U.S. and

-- international copyright and other intellectual property

-- laws.

--

-- DISCLAIMER

-- This disclaimer is not a license and does not grant any

-- rights to the materials distributed herewith. Except as

-- otherwise provided in a valid license issued to you by

-- Xilinx, and to the maximum extent permitted by applicable

-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND

-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES

-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING

-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-

-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and

-- (2) Xilinx shall not be liable (whether in contract or tort,

-- including negligence, or under any other theory of

-- liability) for any loss or damage of any kind or nature

-- related to, arising under or in connection with these

-- materials, including for any direct, or any indirect,

-- special, incidental, or consequential loss or damage

-- (including loss of data, profits, goodwill, or any type of

-- loss or damage suffered as a result of any action brought

-- by a third party) even if such damage or loss was

-- reasonably foreseeable or Xilinx had been advised of the

-- possibility of the same.

--

-- CRITICAL APPLICATIONS

-- Xilinx products are not designed or intended to be fail-

-- safe, or for use in any application requiring fail-safe

-- performance, such as life-support or safety devices or

-- systems, Class III medical devices, nuclear facilities,

-- applications related to the deployment of airbags, or any

-- other applications that could lead to death, personal

-- injury, or severe property or environmental damage

-- (individually and collectively, "Critical

-- Applications"). Customer assumes the sole risk and

-- liability of any use of Xilinx products in Critical

-- Applications, subject only to applicable laws and

-- regulations governing limitations on product liability.

--

-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS

-- PART OF THIS FILE AT ALL TIMES.

--

-------------------------------------------------------------------------------

-- Project    : Spartan-6 Integrated Block for PCI Express

-- File       : cl_s6pcie_m2.vhd

-- Description: Spartan-6 solution wrapper : Endpoint for PCI Express

--

-------------------------------------------------------------------------------

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

use ieee.numeric_bit.all;

library unisim;

use unisim.vcomponents.all;

--synthesis translate_off

use unisim.vpkg.all;

library secureip;

use secureip.all;

--synthesis translate_on

entity cl_s6pcie_m2 is

  generic (

    TL_TX_RAM_RADDR_LATENCY           : integer    := 0;

    TL_TX_RAM_RDATA_LATENCY           : integer    := 2;

    TL_RX_RAM_RADDR_LATENCY           : integer    := 0;

    TL_RX_RAM_RDATA_LATENCY           : integer    := 2;

    TL_RX_RAM_WRITE_LATENCY           : integer    := 0;

    VC0_TX_LASTPACKET                 : integer    := 28;

    VC0_RX_RAM_LIMIT                  : bit_vector := x"7FF";

    VC0_TOTAL_CREDITS_PH              : integer    := 32;

    VC0_TOTAL_CREDITS_PD              : integer    := 211;

    VC0_TOTAL_CREDITS_NPH             : integer    := 8;

    VC0_TOTAL_CREDITS_CH              : integer    := 40;

    VC0_TOTAL_CREDITS_CD              : integer    := 211;

    VC0_CPL_INFINITE                  : boolean    := TRUE;

    BAR0                              : bit_vector := x"FFE00000";

    BAR1                              : bit_vector := x"FFE00000";

    BAR2                              : bit_vector := x"00000000";

    BAR3                              : bit_vector := x"00000000";

    BAR4                              : bit_vector := x"00000000";

    BAR5                              : bit_vector := x"00000000";

    EXPANSION_ROM                     : bit_vector := "0000000000000000000000";

    DISABLE_BAR_FILTERING             : boolean    := FALSE;

    DISABLE_ID_CHECK                  : boolean    := FALSE;

    TL_TFC_DISABLE                    : boolean    := FALSE;

    TL_TX_CHECKS_DISABLE              : boolean    := FALSE;

    USR_CFG                           : boolean    := FALSE;

    USR_EXT_CFG                       : boolean    := FALSE;

    DEV_CAP_MAX_PAYLOAD_SUPPORTED     : integer    := 1;

    CLASS_CODE                        : bit_vector := x"FFFFFF";

    CARDBUS_CIS_POINTER               : bit_vector := x"00000000";

    PCIE_CAP_CAPABILITY_VERSION       : bit_vector := x"1";

    PCIE_CAP_DEVICE_PORT_TYPE         : bit_vector := x"0";

    PCIE_CAP_SLOT_IMPLEMENTED         : boolean    := FALSE;

    PCIE_CAP_INT_MSG_NUM              : bit_vector := "00000";

    DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT : integer    := 0;

    DEV_CAP_EXT_TAG_SUPPORTED         : boolean    := FALSE;

    DEV_CAP_ENDPOINT_L0S_LATENCY      : integer    := 7;

    DEV_CAP_ENDPOINT_L1_LATENCY       : integer    := 7;

    SLOT_CAP_ATT_BUTTON_PRESENT       : boolean    := FALSE;

    SLOT_CAP_ATT_INDICATOR_PRESENT    : boolean    := FALSE;

    SLOT_CAP_POWER_INDICATOR_PRESENT  : boolean    := FALSE;

    DEV_CAP_ROLE_BASED_ERROR          : boolean    := TRUE;

    LINK_CAP_ASPM_SUPPORT             : integer    := 1;

    LINK_CAP_L0S_EXIT_LATENCY         : integer    := 7;

    LINK_CAP_L1_EXIT_LATENCY          : integer    := 7;

    LL_ACK_TIMEOUT                    : bit_vector := x"0000";

    LL_ACK_TIMEOUT_EN                 : boolean    := FALSE;

    LL_REPLAY_TIMEOUT                 : bit_vector := x"0000";

    LL_REPLAY_TIMEOUT_EN              : boolean    := FALSE;

    MSI_CAP_MULTIMSGCAP               : integer    := 0;

    MSI_CAP_MULTIMSG_EXTENSION        : integer    := 0;

    LINK_STATUS_SLOT_CLOCK_CONFIG     : boolean    := TRUE;

    PLM_AUTO_CONFIG                   : boolean    := FALSE;

    FAST_TRAIN                        : boolean    := FALSE;

    ENABLE_RX_TD_ECRC_TRIM            : boolean    := TRUE;

    DISABLE_SCRAMBLING                : boolean    := FALSE;

    PM_CAP_VERSION                    : integer    := 3;

    PM_CAP_PME_CLOCK                  : boolean    := FALSE;

    PM_CAP_DSI                        : boolean    := FALSE;

    PM_CAP_AUXCURRENT                 : integer    := 0;

    PM_CAP_D1SUPPORT                  : boolean    := TRUE;

    PM_CAP_D2SUPPORT                  : boolean    := TRUE;

    PM_CAP_PMESUPPORT                 : bit_vector := x"0F";

    PM_DATA0                          : bit_vector := x"00";

    PM_DATA_SCALE0                    : bit_vector := x"0";

    PM_DATA1                          : bit_vector := x"00";

    PM_DATA_SCALE1                    : bit_vector := x"0";

    PM_DATA2                          : bit_vector := x"00";

    PM_DATA_SCALE2                    : bit_vector := x"0";

    PM_DATA3                          : bit_vector := x"00";

    PM_DATA_SCALE3                    : bit_vector := x"0";

    PM_DATA4                          : bit_vector := x"00";

    PM_DATA_SCALE4                    : bit_vector := x"0";

    PM_DATA5                          : bit_vector := x"00";

    PM_DATA_SCALE5                    : bit_vector := x"0";

    PM_DATA6                          : bit_vector := x"00";

    PM_DATA_SCALE6                    : bit_vector := x"0";

    PM_DATA7                          : bit_vector := x"00";

    PM_DATA_SCALE7                    : bit_vector := x"0";

    PCIE_GENERIC                      : bit_vector := "000010101111";

    GTP_SEL                           : integer    := 0;

    CFG_VEN_ID                        : std_logic_vector(15 downto 0) := x"4953";

    CFG_DEV_ID                        : std_logic_vector(15 downto 0) := x"5507";

    CFG_REV_ID                        : std_logic_vector(7 downto 0)  := x"10";

    CFG_SUBSYS_VEN_ID                 : std_logic_vector(15 downto 0) := x"4953";

    CFG_SUBSYS_ID                     : std_logic_vector(15 downto 0) := x"0008";

    REF_CLK_FREQ                      : integer    := 1

  );

  port (

    -- PCI Express Fabric Interface

    pci_exp_txp             : out std_logic;

    pci_exp_txn             : out std_logic;

    pci_exp_rxp             : in  std_logic;

    pci_exp_rxn             : in  std_logic;

    -- Transaction (TRN) Interface

    trn_lnk_up_n            : out std_logic;

    -- Tx

    trn_td                  : in  std_logic_vector(31 downto 0);

    trn_tsof_n              : in  std_logic;

    trn_teof_n              : in  std_logic;

    trn_tsrc_rdy_n          : in  std_logic;

    trn_tdst_rdy_n          : out std_logic;

    trn_terr_drop_n         : out std_logic;

    trn_tsrc_dsc_n          : in  std_logic;

    trn_terrfwd_n           : in  std_logic;

    trn_tbuf_av             : out std_logic_vector(5 downto 0);

    trn_tstr_n              : in  std_logic;

    trn_tcfg_req_n          : out std_logic;

    trn_tcfg_gnt_n          : in  std_logic;

    -- Rx

    trn_rd                  : out std_logic_vector(31 downto 0);

    trn_rsof_n              : out std_logic;

    trn_reof_n              : out std_logic;

    trn_rsrc_rdy_n          : out std_logic;

    trn_rsrc_dsc_n          : out std_logic;

    trn_rdst_rdy_n          : in  std_logic;

    trn_rerrfwd_n           : out std_logic;

    trn_rnp_ok_n            : in  std_logic;

    trn_rbar_hit_n          : out std_logic_vector(6 downto 0);

    trn_fc_sel              : in  std_logic_vector(2 downto 0);

    trn_fc_nph              : out std_logic_vector(7 downto 0);

    trn_fc_npd              : out std_logic_vector(11 downto 0);

    trn_fc_ph               : out std_logic_vector(7 downto 0);

    trn_fc_pd               : out std_logic_vector(11 downto 0);

    trn_fc_cplh             : out std_logic_vector(7 downto 0);

    trn_fc_cpld             : out std_logic_vector(11 downto 0);

    -- Host (CFG) Interface

    cfg_do                  : out std_logic_vector(31 downto 0);

    cfg_rd_wr_done_n        : out std_logic;

    cfg_dwaddr              : in  std_logic_vector(9 downto 0);

    cfg_rd_en_n             : in  std_logic;

    cfg_err_ur_n            : in  std_logic;

    cfg_err_cor_n           : in  std_logic;

    cfg_err_ecrc_n          : in  std_logic;

    cfg_err_cpl_timeout_n   : in  std_logic;

    cfg_err_cpl_abort_n     : in  std_logic;

    cfg_err_posted_n        : in  std_logic;

    cfg_err_locked_n        : in  std_logic;

    cfg_err_tlp_cpl_header  : in  std_logic_vector(47 downto 0);

    cfg_err_cpl_rdy_n       : out std_logic;

    cfg_interrupt_n         : in  std_logic;

    cfg_interrupt_rdy_n     : out std_logic;

    cfg_interrupt_assert_n  : in  std_logic;

    cfg_interrupt_do        : out std_logic_vector(7 downto 0);

    cfg_interrupt_di        : in  std_logic_vector(7 downto 0);

    cfg_interrupt_mmenable  : out std_logic_vector(2 downto 0);

    cfg_interrupt_msienable : out std_logic;

    cfg_turnoff_ok_n        : in  std_logic;

    cfg_to_turnoff_n        : out std_logic;

    cfg_pm_wake_n           : in  std_logic;

    cfg_pcie_link_state_n   : out std_logic_vector(2 downto 0);

    cfg_trn_pending_n       : in  std_logic;

    cfg_dsn                 : in  std_logic_vector(63 downto 0);

    cfg_bus_number          : out std_logic_vector(7 downto 0);

    cfg_device_number       : out std_logic_vector(4 downto 0);

    cfg_function_number     : out std_logic_vector(2 downto 0);

    cfg_status              : out std_logic_vector(15 downto 0);

    cfg_command             : out std_logic_vector(15 downto 0);

    cfg_dstatus             : out std_logic_vector(15 downto 0);

    cfg_dcommand            : out std_logic_vector(15 downto 0);

    cfg_lstatus             : out std_logic_vector(15 downto 0);

    cfg_lcommand            : out std_logic_vector(15 downto 0);

    -- System Interface

    sys_clk                 : in  std_logic;

    sys_reset_n             : in  std_logic;

    trn_clk                 : out std_logic;

    trn_reset_n             : out std_logic;

    received_hot_reset      : out std_logic

  );

end cl_s6pcie_m2;

architecture rtl of cl_s6pcie_m2 is

  attribute CORE_GENERATION_INFO : STRING;

  attribute CORE_GENERATION_INFO of rtl : architecture is

    "cl_s6pcie_m2,s6_pcie_v1_4,{TL_TX_RAM_RADDR_LATENCY=0,TL_TX_RAM_RDATA_LATENCY=2,TL_RX_RAM_RADDR_LATENCY=0,TL_RX_RAM_RDATA_LATENCY=2,TL_RX_RAM_WRITE_LATENCY=0,VC0_TX_LASTPACKET=28,VC0_RX_RAM_LIMIT=7FF,VC0_TOTAL_CREDITS_PH=32,VC0_TOTAL_CREDITS_PD=211,VC0_TOTAL_CREDITS_NPH=8,VC0_TOTAL_CREDITS_CH=40,VC0_TOTAL_CREDITS_CD=211,VC0_CPL_INFINITE=TRUE,BAR0=FFE00000,BAR1=FFE00000,BAR2=00000000,BAR3=00000000,BAR4=00000000,BAR5=00000000,EXPANSION_ROM=000000,USR_CFG=FALSE,USR_EXT_CFG=FALSE,DEV_CAP_MAX_PAYLOAD_SUPPORTED=1,CLASS_CODE=FFFFFF,CARDBUS_CIS_POINTER=00000000,PCIE_CAP_CAPABILITY_VERSION=1,PCIE_CAP_DEVICE_PORT_TYPE=0,DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT=0,DEV_CAP_EXT_TAG_SUPPORTED=FALSE,DEV_CAP_ENDPOINT_L0S_LATENCY=7,DEV_CAP_ENDPOINT_L1_LATENCY=7,LINK_CAP_ASPM_SUPPORT=1,MSI_CAP_MULTIMSGCAP=0,MSI_CAP_MULTIMSG_EXTENSION=0,LINK_STATUS_SLOT_CLOCK_CONFIG=TRUE,ENABLE_RX_TD_ECRC_TRIM=TRUE,DISABLE_SCRAMBLING=FALSE,PM_CAP_DSI=FALSE,PM_CAP_D1SUPPORT=TRUE,PM_CAP_D2SUPPORT=TRUE,PM_CAP_PMESUPPORT=0F,PM_DATA0=00,PM_DATA_SCALE0=0,PM_DATA1=00,PM_DATA_SCALE1=0,PM_DATA2=00,PM_DATA_SCALE2=0,PM_DATA3=00,PM_DATA_SCALE3=0,PM_DATA4=00,PM_DATA_SCALE4=0,PM_DATA5=00,PM_DATA_SCALE5=0,PM_DATA6=00,PM_DATA_SCALE6=0,PM_DATA7=00,PM_DATA_SCALE7=0,PCIE_GENERIC=000010101111,GTP_SEL=0,CFG_VEN_ID=4953,CFG_DEV_ID=5507,CFG_REV_ID=10,CFG_SUBSYS_VEN_ID=4953,CFG_SUBSYS_ID=0008,REF_CLK_FREQ=1}";

  ------------------------

  -- Function Declarations

  ------------------------

  function CALC_CLKFBOUT_MULT(FREQ_SEL : integer) return integer is

  begin

    case FREQ_SEL is

      when 0 => return 5;      -- 100 MHz

      when others => return 4; -- 125 MHz

    end case;

  end CALC_CLKFBOUT_MULT;

  function CALC_CLKIN_PERIOD(FREQ_SEL : integer) return real is

  begin

    case FREQ_SEL is

      when 0 => return 10.0;     -- 100 MHz

      when others => return 8.0; -- 125 MHz

    end case;

  end CALC_CLKIN_PERIOD;

  function CALC_CLK25_DIVIDER(FREQ_SEL : integer) return integer is

  begin

    case FREQ_SEL is

      when 0 => return 4;      -- 100 MHz

      when others => return 5; -- 125 MHz

    end case;

  end CALC_CLK25_DIVIDER;

  function CALC_PLL_DIVSEL_FB(FREQ_SEL : integer) return integer is

  begin

    case FREQ_SEL is

      when 0 => return 5;      -- 100 MHz

      when others => return 2; -- 125 MHz

    end case;

  end CALC_PLL_DIVSEL_FB;

  function CALC_PLL_DIVSEL_REF(FREQ_SEL : integer) return integer is

  begin

    case FREQ_SEL is

      when 0 => return 2;      -- 100 MHz

      when others => return 1; -- 125 MHz

    end case;

  end CALC_PLL_DIVSEL_REF;

  function SIM_INT(SIMULATION : boolean) return integer is

  begin

    if SIMULATION then

      return 1;

    else

      return 0;

    end if;

  end SIM_INT;

  ------------------------

  -- Constant Declarations

  ------------------------

  constant CLKFBOUT_MULT     : integer := CALC_CLKFBOUT_MULT(REF_CLK_FREQ);

  constant CLKIN_PERIOD      : real    := CALC_CLKIN_PERIOD(REF_CLK_FREQ);

  constant GT_CLK25_DIVIDER  : integer := CALC_CLK25_DIVIDER(REF_CLK_FREQ);

  constant GT_PLL_DIVSEL_FB  : integer := CALC_PLL_DIVSEL_FB(REF_CLK_FREQ);

  constant GT_PLL_DIVSEL_REF : integer := CALC_PLL_DIVSEL_REF(REF_CLK_FREQ);

  -------------------------

  -- Component Declarations

  -------------------------

  component pcie_bram_top_s6 is

  generic (

    DEV_CAP_MAX_PAYLOAD_SUPPORTED : integer    := 0;

    VC0_TX_LASTPACKET             : integer    := 31;

    TLM_TX_OVERHEAD               : integer    := 24;

    TL_TX_RAM_RADDR_LATENCY       : integer    := 1;

    TL_TX_RAM_RDATA_LATENCY       : integer    := 1;

    TL_TX_RAM_WRITE_LATENCY       : integer    := 1;

    VC0_RX_LIMIT                  : integer    := 16#1FFF#;

    TL_RX_RAM_RADDR_LATENCY       : integer    := 1;

    TL_RX_RAM_RDATA_LATENCY       : integer    := 1;

    TL_RX_RAM_WRITE_LATENCY       : integer    := 1

    );

  port (

    user_clk_i                    : in std_logic;

    reset_i                       : in std_logic;

    mim_tx_wen                    : in std_logic;

    mim_tx_waddr                  : in std_logic_vector(11 downto 0);

    mim_tx_wdata                  : in std_logic_vector(35 downto 0);

    mim_tx_ren                    : in std_logic;

    mim_tx_rce                    : in std_logic;

    mim_tx_raddr                  : in std_logic_vector(11 downto 0);

    mim_tx_rdata                  : out std_logic_vector(35 downto 0);

    mim_rx_wen                    : in std_logic;

    mim_rx_waddr                  : in std_logic_vector(11 downto 0);

    mim_rx_wdata                  : in std_logic_vector(35 downto 0);

    mim_rx_ren                    : in std_logic;

    mim_rx_rce                    : in std_logic;

    mim_rx_raddr                  : in std_logic_vector(11 downto 0);

    mim_rx_rdata                  : out std_logic_vector(35 downto 0)

  );

  end component pcie_bram_top_s6;

  component GTPA1_DUAL_WRAPPER is

  generic

  (

    -- Simulation attributes

    WRAPPER_SIM_GTPRESET_SPEEDUP    : integer   := 0; -- Set to 1 to speed up sim reset

    WRAPPER_CLK25_DIVIDER_0         : integer   := 4;

    WRAPPER_CLK25_DIVIDER_1         : integer   := 4;

    WRAPPER_PLL_DIVSEL_FB_0         : integer   := 5;

    WRAPPER_PLL_DIVSEL_FB_1         : integer   := 5;

    WRAPPER_PLL_DIVSEL_REF_0        : integer   := 2;

    WRAPPER_PLL_DIVSEL_REF_1        : integer   := 2;

    WRAPPER_SIMULATION              : integer   := 0  -- Set to 1 for simulation

  );

  port

  (

    --_________________________________________________________________________

    --_________________________________________________________________________

    --TILE0  (X0_Y0)

    ------------------------ Loopback and Powerdown Ports ----------------------

    TILE0_RXPOWERDOWN0_IN                   : in   std_logic_vector(1 downto 0);

    TILE0_RXPOWERDOWN1_IN                   : in   std_logic_vector(1 downto 0);

    TILE0_TXPOWERDOWN0_IN                   : in   std_logic_vector(1 downto 0);

    TILE0_TXPOWERDOWN1_IN                   : in   std_logic_vector(1 downto 0);

    --------------------------------- PLL Ports --------------------------------

    TILE0_CLK00_IN                          : in   std_logic;

    TILE0_CLK01_IN                          : in   std_logic;

    TILE0_GTPRESET0_IN                      : in   std_logic;

    TILE0_GTPRESET1_IN                      : in   std_logic;

    TILE0_PLLLKDET0_OUT                     : out  std_logic;

    TILE0_PLLLKDET1_OUT                     : out  std_logic;

    TILE0_RESETDONE0_OUT                    : out  std_logic;

    TILE0_RESETDONE1_OUT                    : out  std_logic;

    ----------------------- Receive Ports - 8b10b Decoder ----------------------

    TILE0_RXCHARISK0_OUT                    : out  std_logic_vector(1 downto 0);

    TILE0_RXCHARISK1_OUT                    : out  std_logic_vector(1 downto 0);

    TILE0_RXDISPERR0_OUT                    : out  std_logic_vector(1 downto 0);

    TILE0_RXDISPERR1_OUT                    : out  std_logic_vector(1 downto 0);

    TILE0_RXNOTINTABLE0_OUT                 : out  std_logic_vector(1 downto 0);

    TILE0_RXNOTINTABLE1_OUT                 : out  std_logic_vector(1 downto 0);

    ---------------------- Receive Ports - Clock Correction --------------------

    TILE0_RXCLKCORCNT0_OUT                  : out  std_logic_vector(2 downto 0);

    TILE0_RXCLKCORCNT1_OUT                  : out  std_logic_vector(2 downto 0);

    --------------- Receive Ports - Comma Detection and Alignment --------------

    TILE0_RXENMCOMMAALIGN0_IN               : in   std_logic;

    TILE0_RXENMCOMMAALIGN1_IN               : in   std_logic;

    TILE0_RXENPCOMMAALIGN0_IN               : in   std_logic;

    TILE0_RXENPCOMMAALIGN1_IN               : in   std_logic;

    ------------------- Receive Ports - RX Data Path interface -----------------

    TILE0_RXDATA0_OUT                       : out  std_logic_vector(15 downto 0);

    TILE0_RXDATA1_OUT                       : out  std_logic_vector(15 downto 0);

    TILE0_RXRESET0_IN                       : in   std_logic;

    TILE0_RXRESET1_IN                       : in   std_logic;

    TILE0_RXUSRCLK0_IN                      : in   std_logic;

    TILE0_RXUSRCLK1_IN                      : in   std_logic;

    TILE0_RXUSRCLK20_IN                     : in   std_logic;

    TILE0_RXUSRCLK21_IN                     : in   std_logic;

    ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------

    TILE0_GATERXELECIDLE0_IN                : in   std_logic;

    TILE0_GATERXELECIDLE1_IN                : in   std_logic;

    TILE0_IGNORESIGDET0_IN                  : in   std_logic;

    TILE0_IGNORESIGDET1_IN                  : in   std_logic;

    TILE0_RXELECIDLE0_OUT                   : out  std_logic;

    TILE0_RXELECIDLE1_OUT                   : out  std_logic;

    TILE0_RXN0_IN                           : in   std_logic;

    TILE0_RXN1_IN                           : in   std_logic;

    TILE0_RXP0_IN                           : in   std_logic;

    TILE0_RXP1_IN                           : in   std_logic;

    ----------- Receive Ports - RX Elastic Buffer and Phase Alignment ----------

    TILE0_RXSTATUS0_OUT                     : out  std_logic_vector(2 downto 0);

    TILE0_RXSTATUS1_OUT                     : out  std_logic_vector(2 downto 0);

    -------------- Receive Ports - RX Pipe Control for PCI Express -------------

    TILE0_PHYSTATUS0_OUT                    : out  std_logic;

    TILE0_PHYSTATUS1_OUT                    : out  std_logic;

    TILE0_RXVALID0_OUT                      : out  std_logic;

    TILE0_RXVALID1_OUT                      : out  std_logic;

    -------------------- Receive Ports - RX Polarity Control -------------------

    TILE0_RXPOLARITY0_IN                    : in   std_logic;

    TILE0_RXPOLARITY1_IN                    : in   std_logic;

    ---------------------------- TX/RX Datapath Ports --------------------------

    TILE0_GTPCLKOUT0_OUT                    : out  std_logic_vector(1 downto 0);

    TILE0_GTPCLKOUT1_OUT                    : out  std_logic_vector(1 downto 0);

    ------------------- Transmit Ports - 8b10b Encoder Control -----------------

    TILE0_TXCHARDISPMODE0_IN                : in   std_logic_vector(1 downto 0);

    TILE0_TXCHARDISPMODE1_IN                : in   std_logic_vector(1 downto 0);

    TILE0_TXCHARISK0_IN                     : in   std_logic_vector(1 downto 0);

    TILE0_TXCHARISK1_IN                     : in   std_logic_vector(1 downto 0);

    ------------------ Transmit Ports - TX Data Path interface -----------------

    TILE0_TXDATA0_IN                        : in   std_logic_vector(15 downto 0);

    TILE0_TXDATA1_IN                        : in   std_logic_vector(15 downto 0);

    TILE0_TXUSRCLK0_IN                      : in   std_logic;

    TILE0_TXUSRCLK1_IN                      : in   std_logic;

    TILE0_TXUSRCLK20_IN                     : in   std_logic;

    TILE0_TXUSRCLK21_IN                     : in   std_logic;

    --------------- Transmit Ports - TX Driver and OOB signalling --------------

    TILE0_TXN0_OUT                          : out  std_logic;

    TILE0_TXN1_OUT                          : out  std_logic;

    TILE0_TXP0_OUT                          : out  std_logic;

    TILE0_TXP1_OUT                          : out  std_logic;

    ----------------- Transmit Ports - TX Ports for PCI Express ----------------

    TILE0_TXDETECTRX0_IN                    : in   std_logic;

    TILE0_TXDETECTRX1_IN                    : in   std_logic;

    TILE0_TXELECIDLE0_IN                    : in   std_logic;

    TILE0_TXELECIDLE1_IN                    : in   std_logic

  );

  end component GTPA1_DUAL_WRAPPER;

  ----------------------

  -- Signal Declarations

  ----------------------

  -- PLL Signals

  signal mgt_clk            : std_logic;

  signal mgt_clk_2x         : std_logic;

  signal clock_locked       : std_logic;

  signal gt_refclk_out      : std_logic_vector(1 downto 0);

  signal gt_clk_fb_west_out : std_logic;

  signal pll_rst            : std_logic;

  signal clk_125            : std_logic;

  signal clk_250            : std_logic;

  signal clk_62_5           : std_logic;

  signal gt_refclk_buf      : std_logic;

  signal gt_refclk_fb       : std_logic;

  signal w_cfg_ven_id        : std_logic_vector(15 downto 0);

  signal w_cfg_dev_id        : std_logic_vector(15 downto 0);

  signal w_cfg_rev_id        : std_logic_vector(7 downto 0);

  signal w_cfg_subsys_ven_id : std_logic_vector(15 downto 0);

  signal w_cfg_subsys_id     : std_logic_vector(15 downto 0);

  signal cfg_ltssm_state                        : std_logic_vector(4 downto 0);

  signal cfg_link_control_aspm_control          : std_logic_vector(1 downto 0);

  signal cfg_link_control_rcb                   : std_logic;

  signal cfg_link_control_common_clock          : std_logic;

  signal cfg_link_control_extended_sync         : std_logic;

  signal cfg_command_interrupt_disable          : std_logic;

  signal cfg_command_serr_en                    : std_logic;

  signal cfg_command_bus_master_enable          : std_logic;

  signal cfg_command_mem_enable                 : std_logic;

  signal cfg_command_io_enable                  : std_logic;

  signal cfg_dev_status_ur_detected             : std_logic;

  signal cfg_dev_status_fatal_err_detected      : std_logic;

  signal cfg_dev_status_nonfatal_err_detected   : std_logic;

  signal cfg_dev_status_corr_err_detected       : std_logic;

  signal cfg_dev_control_max_read_req           : std_logic_vector(2 downto 0);

  signal cfg_dev_control_no_snoop_en            : std_logic;

  signal cfg_dev_control_aux_power_en           : std_logic;

  signal cfg_dev_control_phantom_en             : std_logic;

  signal cfg_dev_cntrol_ext_tag_en              : std_logic;

  signal cfg_dev_control_max_payload            : std_logic_vector(2 downto 0);

  signal cfg_dev_control_enable_ro              : std_logic;

  signal cfg_dev_control_ext_tag_en             : std_logic;

  signal cfg_dev_control_ur_err_reporting_en    : std_logic;

  signal cfg_dev_control_fatal_err_reporting_en : std_logic;

  signal cfg_dev_control_non_fatal_reporting_en : std_logic;

  signal cfg_dev_control_corr_err_reporting_en  : std_logic;

  signal mim_tx_waddr                           : std_logic_vector(11 downto 0);

  signal mim_tx_raddr                           : std_logic_vector(11 downto 0);

  signal mim_rx_waddr                           : std_logic_vector(11 downto 0);

  signal mim_rx_raddr                           : std_logic_vector(11 downto 0);

  signal mim_tx_wdata                           : std_logic_vector(35 downto 0);

  signal mim_tx_rdata                           : std_logic_vector(35 downto 0);

  signal mim_rx_wdata                           : std_logic_vector(34 downto 0);

  signal mim_rx_rdata_unused                    : std_logic;

  signal mim_rx_rdata                           : std_logic_vector(34 downto 0);

  signal mim_tx_wen                             : std_logic;

  signal mim_tx_ren                             : std_logic;

  signal mim_rx_wen                             : std_logic;

  signal mim_rx_ren                             : std_logic;

  signal dbg_bad_dllp_status                    : std_logic;

  signal dbg_bad_tlp_lcrc                       : std_logic;

  signal dbg_bad_tlp_seq_num                    : std_logic;

  signal dbg_bad_tlp_status                     : std_logic;

  signal dbg_dl_protocol_status                 : std_logic;

  signal dbg_fc_protocol_err_status             : std_logic;

  signal dbg_mlfrmd_length                      : std_logic;

  signal dbg_mlfrmd_mps                         : std_logic;

  signal dbg_mlfrmd_tcvc                        : std_logic;

  signal dbg_mlfrmd_tlp_status                  : std_logic;

  signal dbg_mlfrmd_unrec_type                  : std_logic;

  signal dbg_poistlpstatus                      : std_logic;

  signal dbg_rcvr_overflow_status               : std_logic;

  signal dbg_reg_detected_correctable           : std_logic;

  signal dbg_reg_detected_fatal                 : std_logic;

  signal dbg_reg_detected_non_fatal             : std_logic;

  signal dbg_reg_detected_unsupported           : std_logic;

  signal dbg_rply_rollover_status               : std_logic;

  signal dbg_rply_timeout_status                : std_logic;

  signal dbg_ur_no_bar_hit                      : std_logic;

  signal dbg_ur_pois_cfg_wr                     : std_logic;

  signal dbg_ur_status                          : std_logic;

  signal dbg_ur_unsup_msg                       : std_logic;

  signal pipe_gt_power_down_a                   : std_logic_vector(1 downto 0);

  signal pipe_gt_power_down_b                   : std_logic_vector(1 downto 0);

  signal pipe_gt_reset_done_a                   : std_logic;

  signal pipe_gt_reset_done_b                   : std_logic;

  signal pipe_gt_tx_elec_idle_a                 : std_logic;

  signal pipe_gt_tx_elec_idle_b                 : std_logic;

  signal pipe_phy_status_a                      : std_logic;

  signal pipe_phy_status_b                      : std_logic;

  signal pipe_rx_charisk_a                      : std_logic_vector(1 downto 0);

  signal pipe_rx_charisk_b                      : std_logic_vector(1 downto 0);

  signal pipe_rx_data_a                         : std_logic_vector(15 downto 0);

  signal pipe_rx_data_b                         : std_logic_vector(15 downto 0);

  signal pipe_rx_enter_elec_idle_a              : std_logic;

  signal pipe_rx_enter_elec_idle_b              : std_logic;

  signal pipe_rx_polarity_a                     : std_logic;

  signal pipe_rx_polarity_b                     : std_logic;

  signal pipe_rxreset_a                         : std_logic;

  signal pipe_rxreset_b                         : std_logic;

  signal pipe_rx_status_a                       : std_logic_vector(2 downto 0);

  signal pipe_rx_status_b                       : std_logic_vector(2 downto 0);

  signal pipe_tx_char_disp_mode_a               : std_logic_vector(1 downto 0);

  signal pipe_tx_char_disp_mode_b               : std_logic_vector(1 downto 0);

  signal pipe_tx_char_disp_val_a                : std_logic_vector(1 downto 0);

  signal pipe_tx_char_disp_val_b                : std_logic_vector(1 downto 0);

  signal pipe_tx_char_is_k_a                    : std_logic_vector(1 downto 0);

  signal pipe_tx_char_is_k_b                    : std_logic_vector(1 downto 0);

  signal pipe_tx_data_a                         : std_logic_vector(15 downto 0);

  signal pipe_tx_data_b                         : std_logic_vector(15 downto 0);

  signal pipe_tx_rcvr_det_a                     : std_logic;

  signal pipe_tx_rcvr_det_b                     : std_logic;

  -- GT->PLM PIPE Interface rx

  signal rx_char_is_k                           : std_logic_vector(1 downto 0);

  signal rx_data                                : std_logic_vector(15 downto 0);

  signal rx_enter_elecidle                      : std_logic;

  signal rx_status                              : std_logic_vector(2 downto 0);

  signal rx_polarity                            : std_logic;

  -- GT<-PLM PIPE Interface tx

  signal tx_char_disp_mode                      : std_logic_vector(1 downto 0);