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-------------------------------------------------------------------------------
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-- ____ ____
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-- / /\/ /
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-- /___/ \ / Vendor: Xilinx
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-- \ \ \/ Version : 1.7
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-- \ \ Application : Spartan-6 FPGA GTP Transceiver Wizard
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-- / / Filename : gtpa1_dual_wrapper_tile.vhd
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-- /___/ /\ Timestamp :
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-- \ \ / \
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-- \___\/\___\
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--
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--
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-- Module GTPA1_DUAL_WRAPPER_TILE (a GTPA1_DUAL Tile Wrapper)
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-- Generated by Xilinx Spartan-6 FPGA GTP Transceiver Wizard
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--
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--
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-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
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--
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-- This file contains confidential and proprietary information
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-- of Xilinx, Inc. and is protected under U.S. and
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-- international copyright and other intellectual property
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-- laws.
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--
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-- DISCLAIMER
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-- This disclaimer is not a license and does not grant any
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-- rights to the materials distributed herewith. Except as
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-- otherwise provided in a valid license issued to you by
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-- Xilinx, and to the maximum extent permitted by applicable
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-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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-- (2) Xilinx shall not be liable (whether in contract or tort,
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-- including negligence, or under any other theory of
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-- liability) for any loss or damage of any kind or nature
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-- related to, arising under or in connection with these
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-- materials, including for any direct, or any indirect,
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-- special, incidental, or consequential loss or damage
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-- (including loss of data, profits, goodwill, or any type of
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-- loss or damage suffered as a result of any action brought
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-- by a third party) even if such damage or loss was
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-- reasonably foreseeable or Xilinx had been advised of the
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-- possibility of the same.
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--
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-- CRITICAL APPLICATIONS
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-- Xilinx products are not designed or intended to be fail-
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-- safe, or for use in any application requiring fail-safe
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-- performance, such as life-support or safety devices or
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-- systems, Class III medical devices, nuclear facilities,
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-- applications related to the deployment of airbags, or any
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-- other applications that could lead to death, personal
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-- injury, or severe property or environmental damage
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-- (individually and collectively, "Critical
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-- Applications"). Customer assumes the sole risk and
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-- liability of any use of Xilinx products in Critical
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-- Applications, subject only to applicable laws and
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-- regulations governing limitations on product liability.
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--
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-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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-- PART OF THIS FILE AT ALL TIMES.
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library UNISIM;
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use UNISIM.VCOMPONENTS.ALL;
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--***************************** Entity Declaration ****************************
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entity GTPA1_DUAL_WRAPPER_TILE is
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generic
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(
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-- Simulation attributes
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TILE_SIM_GTPRESET_SPEEDUP : integer := 0; -- Set to 1 to speed up sim reset
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TILE_CLK25_DIVIDER_0 : integer := 4;
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TILE_CLK25_DIVIDER_1 : integer := 4;
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TILE_PLL_DIVSEL_FB_0 : integer := 5;
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TILE_PLL_DIVSEL_FB_1 : integer := 5;
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TILE_PLL_DIVSEL_REF_0 : integer := 2;
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TILE_PLL_DIVSEL_REF_1 : integer := 2;
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--
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TILE_PLL_SOURCE_0 : string := "PLL0";
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TILE_PLL_SOURCE_1 : string := "PLL1"
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);
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port
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(
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------------------------ Loopback and Powerdown Ports ----------------------
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RXPOWERDOWN0_IN : in std_logic_vector(1 downto 0);
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RXPOWERDOWN1_IN : in std_logic_vector(1 downto 0);
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TXPOWERDOWN0_IN : in std_logic_vector(1 downto 0);
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TXPOWERDOWN1_IN : in std_logic_vector(1 downto 0);
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--------------------------------- PLL Ports --------------------------------
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CLK00_IN : in std_logic;
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CLK01_IN : in std_logic;
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GTPRESET0_IN : in std_logic;
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GTPRESET1_IN : in std_logic;
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PLLLKDET0_OUT : out std_logic;
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PLLLKDET1_OUT : out std_logic;
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RESETDONE0_OUT : out std_logic;
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RESETDONE1_OUT : out std_logic;
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----------------------- Receive Ports - 8b10b Decoder ----------------------
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RXCHARISK0_OUT : out std_logic_vector(1 downto 0);
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RXCHARISK1_OUT : out std_logic_vector(1 downto 0);
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RXDISPERR0_OUT : out std_logic_vector(1 downto 0);
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RXDISPERR1_OUT : out std_logic_vector(1 downto 0);
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RXNOTINTABLE0_OUT : out std_logic_vector(1 downto 0);
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RXNOTINTABLE1_OUT : out std_logic_vector(1 downto 0);
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---------------------- Receive Ports - Clock Correction --------------------
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RXCLKCORCNT0_OUT : out std_logic_vector(2 downto 0);
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RXCLKCORCNT1_OUT : out std_logic_vector(2 downto 0);
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--------------- Receive Ports - Comma Detection and Alignment --------------
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RXENMCOMMAALIGN0_IN : in std_logic;
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RXENMCOMMAALIGN1_IN : in std_logic;
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RXENPCOMMAALIGN0_IN : in std_logic;
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RXENPCOMMAALIGN1_IN : in std_logic;
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------------------- Receive Ports - RX Data Path interface -----------------
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RXDATA0_OUT : out std_logic_vector(15 downto 0);
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RXDATA1_OUT : out std_logic_vector(15 downto 0);
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RXRESET0_IN : in std_logic;
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RXRESET1_IN : in std_logic;
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RXUSRCLK0_IN : in std_logic;
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RXUSRCLK1_IN : in std_logic;
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RXUSRCLK20_IN : in std_logic;
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RXUSRCLK21_IN : in std_logic;
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------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
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GATERXELECIDLE0_IN : in std_logic;
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GATERXELECIDLE1_IN : in std_logic;
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IGNORESIGDET0_IN : in std_logic;
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IGNORESIGDET1_IN : in std_logic;
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RXELECIDLE0_OUT : out std_logic;
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RXELECIDLE1_OUT : out std_logic;
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RXN0_IN : in std_logic;
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RXN1_IN : in std_logic;
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RXP0_IN : in std_logic;
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RXP1_IN : in std_logic;
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----------- Receive Ports - RX Elastic Buffer and Phase Alignment ----------
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RXSTATUS0_OUT : out std_logic_vector(2 downto 0);
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RXSTATUS1_OUT : out std_logic_vector(2 downto 0);
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-------------- Receive Ports - RX Pipe Control for PCI Express -------------
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PHYSTATUS0_OUT : out std_logic;
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PHYSTATUS1_OUT : out std_logic;
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RXVALID0_OUT : out std_logic;
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RXVALID1_OUT : out std_logic;
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-------------------- Receive Ports - RX Polarity Control -------------------
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RXPOLARITY0_IN : in std_logic;
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RXPOLARITY1_IN : in std_logic;
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---------------------------- TX/RX Datapath Ports --------------------------
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GTPCLKOUT0_OUT : out std_logic_vector(1 downto 0);
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GTPCLKOUT1_OUT : out std_logic_vector(1 downto 0);
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------------------- Transmit Ports - 8b10b Encoder Control -----------------
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TXCHARDISPMODE0_IN : in std_logic_vector(1 downto 0);
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TXCHARDISPMODE1_IN : in std_logic_vector(1 downto 0);
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TXCHARISK0_IN : in std_logic_vector(1 downto 0);
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TXCHARISK1_IN : in std_logic_vector(1 downto 0);
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------------------ Transmit Ports - TX Data Path interface -----------------
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TXDATA0_IN : in std_logic_vector(15 downto 0);
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TXDATA1_IN : in std_logic_vector(15 downto 0);
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TXUSRCLK0_IN : in std_logic;
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TXUSRCLK1_IN : in std_logic;
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TXUSRCLK20_IN : in std_logic;
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TXUSRCLK21_IN : in std_logic;
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--------------- Transmit Ports - TX Driver and OOB signalling --------------
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TXN0_OUT : out std_logic;
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TXN1_OUT : out std_logic;
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TXP0_OUT : out std_logic;
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TXP1_OUT : out std_logic;
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----------------- Transmit Ports - TX Ports for PCI Express ----------------
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TXDETECTRX0_IN : in std_logic;
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TXDETECTRX1_IN : in std_logic;
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TXELECIDLE0_IN : in std_logic;
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TXELECIDLE1_IN : in std_logic
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);
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end GTPA1_DUAL_WRAPPER_TILE;
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architecture RTL of GTPA1_DUAL_WRAPPER_TILE is
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--**************************** Signal Declarations ****************************
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-- ground and tied_to_vcc_i signals
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signal tied_to_ground_i : std_logic;
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signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
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signal tied_to_vcc_i : std_logic;
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signal tied_to_vcc_vec_i : std_logic_vector(63 downto 0);
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-- RX Datapath signals
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signal rxdata0_i : std_logic_vector(31 downto 0);
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signal rxchariscomma0_float_i : std_logic_vector(1 downto 0);
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signal rxcharisk0_float_i : std_logic_vector(1 downto 0);
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signal rxdisperr0_float_i : std_logic_vector(1 downto 0);
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signal rxnotintable0_float_i : std_logic_vector(1 downto 0);
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signal rxrundisp0_float_i : std_logic_vector(1 downto 0);
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-- TX Datapath signals
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signal txdata0_i : std_logic_vector(31 downto 0);
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signal txkerr0_float_i : std_logic_vector(1 downto 0);
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signal txrundisp0_float_i : std_logic_vector(1 downto 0);
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-- RX Datapath signals
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signal rxdata1_i : std_logic_vector(31 downto 0);
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signal rxchariscomma1_float_i : std_logic_vector(1 downto 0);
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signal rxcharisk1_float_i : std_logic_vector(1 downto 0);
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signal rxdisperr1_float_i : std_logic_vector(1 downto 0);
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signal rxnotintable1_float_i : std_logic_vector(1 downto 0);
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signal rxrundisp1_float_i : std_logic_vector(1 downto 0);
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-- TX Datapath signals
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signal txdata1_i : std_logic_vector(31 downto 0);
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signal txkerr1_float_i : std_logic_vector(1 downto 0);
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signal txrundisp1_float_i : std_logic_vector(1 downto 0);
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--******************************** Main Body of Code***************************
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begin
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--------------------------- Static signal Assignments ---------------------
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tied_to_ground_i <= '0';
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tied_to_ground_vec_i(63 downto 0) <= (others => '0');
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tied_to_vcc_i <= '1';
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tied_to_vcc_vec_i(63 downto 0) <= (others => '1');
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------------------- GTP Datapath byte mapping -----------------
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-- The GTP provides little endian data (first byte received on RXDATA(7 downto 0))
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RXDATA0_OUT <= rxdata0_i(15 downto 0);
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txdata0_i <= (tied_to_ground_vec_i(15 downto 0) & TXDATA0_IN);
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-- The GTP provides little endian data (first byte received on RXDATA(7 downto 0))
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RXDATA1_OUT <= rxdata1_i(15 downto 0);
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txdata1_i <= (tied_to_ground_vec_i(15 downto 0) & TXDATA1_IN);
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----------------------------- GTPA1_DUAL Instance --------------------------
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gtpa1_dual_i:GTPA1_DUAL
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generic map
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(
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--_______________________ Simulation-Only Attributes ___________________
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SIM_RECEIVER_DETECT_PASS => (TRUE),
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SIM_TX_ELEC_IDLE_LEVEL => ("Z"),
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SIM_VERSION => ("2.0"),
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SIM_REFCLK0_SOURCE => ("000"),
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SIM_REFCLK1_SOURCE => ("000"),
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SIM_GTPRESET_SPEEDUP => (TILE_SIM_GTPRESET_SPEEDUP),
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CLK25_DIVIDER_0 => (TILE_CLK25_DIVIDER_0),
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CLK25_DIVIDER_1 => (TILE_CLK25_DIVIDER_1),
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PLL_DIVSEL_FB_0 => (TILE_PLL_DIVSEL_FB_0),
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PLL_DIVSEL_FB_1 => (TILE_PLL_DIVSEL_FB_1),
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PLL_DIVSEL_REF_0 => (TILE_PLL_DIVSEL_REF_0),
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PLL_DIVSEL_REF_1 => (TILE_PLL_DIVSEL_REF_1),
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--PLL Attributes
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CLKINDC_B_0 => (TRUE),
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CLKRCV_TRST_0 => (TRUE),
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OOB_CLK_DIVIDER_0 => (4),
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PLL_COM_CFG_0 => (x"21680a"),
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PLL_CP_CFG_0 => (x"00"),
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PLL_RXDIVSEL_OUT_0 => (1),
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PLL_SATA_0 => (FALSE),
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PLL_SOURCE_0 => (TILE_PLL_SOURCE_0),
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PLL_TXDIVSEL_OUT_0 => (1),
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PLLLKDET_CFG_0 => ("111"),
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--
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CLKINDC_B_1 => (TRUE),
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CLKRCV_TRST_1 => (TRUE),
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OOB_CLK_DIVIDER_1 => (4),
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PLL_COM_CFG_1 => (x"21680a"),
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PLL_CP_CFG_1 => (x"00"),
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PLL_RXDIVSEL_OUT_1 => (1),
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PLL_SATA_1 => (FALSE),
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PLL_SOURCE_1 => (TILE_PLL_SOURCE_1),
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PLL_TXDIVSEL_OUT_1 => (1),
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PLLLKDET_CFG_1 => ("111"),
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PMA_COM_CFG_EAST => (x"000008000"),
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PMA_COM_CFG_WEST => (x"00000a000"),
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TST_ATTR_0 => (x"00000000"),
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TST_ATTR_1 => (x"00000000"),
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--TX Interface Attributes
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CLK_OUT_GTP_SEL_0 => ("REFCLKPLL0"),
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TX_TDCC_CFG_0 => ("11"),
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|
|
CLK_OUT_GTP_SEL_1 => ("REFCLKPLL1"),
|
| 302 |
|
|
TX_TDCC_CFG_1 => ("11"),
|
| 303 |
|
|
|
| 304 |
|
|
--TX Buffer and Phase Alignment Attributes
|
| 305 |
|
|
PMA_TX_CFG_0 => (x"00082"),
|
| 306 |
|
|
TX_BUFFER_USE_0 => (TRUE),
|
| 307 |
|
|
TX_XCLK_SEL_0 => ("TXOUT"),
|
| 308 |
|
|
TXRX_INVERT_0 => ("011"),
|
| 309 |
|
|
PMA_TX_CFG_1 => (x"00082"),
|
| 310 |
|
|
TX_BUFFER_USE_1 => (TRUE),
|
| 311 |
|
|
TX_XCLK_SEL_1 => ("TXOUT"),
|
| 312 |
|
|
TXRX_INVERT_1 => ("011"),
|
| 313 |
|
|
|
| 314 |
|
|
--TX Driver and OOB signalling Attributes
|
| 315 |
|
|
CM_TRIM_0 => ("00"),
|
| 316 |
|
|
TX_IDLE_DELAY_0 => ("010"),
|
| 317 |
|
|
CM_TRIM_1 => ("00"),
|
| 318 |
|
|
TX_IDLE_DELAY_1 => ("010"),
|
| 319 |
|
|
|
| 320 |
|
|
--TX PIPE/SATA Attributes
|
| 321 |
|
|
COM_BURST_VAL_0 => ("1111"),
|
| 322 |
|
|
COM_BURST_VAL_1 => ("1111"),
|
| 323 |
|
|
|
| 324 |
|
|
--RX Driver,OOB signalling,Coupling and Eq,CDR Attributes
|
| 325 |
|
|
AC_CAP_DIS_0 => (FALSE),
|
| 326 |
|
|
OOBDETECT_THRESHOLD_0 => ("111"),
|
| 327 |
|
|
PMA_CDR_SCAN_0 => (x"6404040"),
|
| 328 |
|
|
PMA_RX_CFG_0 => (x"05ce089"),
|
| 329 |
|
|
PMA_RXSYNC_CFG_0 => (x"00"),
|
| 330 |
|
|
RCV_TERM_GND_0 => (TRUE),
|
| 331 |
|
|
RCV_TERM_VTTRX_0 => (FALSE),
|
| 332 |
|
|
RXEQ_CFG_0 => ("01111011"),
|
| 333 |
|
|
TERMINATION_CTRL_0 => ("10100"),
|
| 334 |
|
|
TERMINATION_OVRD_0 => (FALSE),
|
| 335 |
|
|
TX_DETECT_RX_CFG_0 => (x"1832"),
|
| 336 |
|
|
AC_CAP_DIS_1 => (FALSE),
|
| 337 |
|
|
OOBDETECT_THRESHOLD_1 => ("111"),
|
| 338 |
|
|
PMA_CDR_SCAN_1 => (x"6404040"),
|
| 339 |
|
|
PMA_RX_CFG_1 => (x"05ce089"),
|
| 340 |
|
|
PMA_RXSYNC_CFG_1 => (x"00"),
|
| 341 |
|
|
RCV_TERM_GND_1 => (TRUE),
|
| 342 |
|
|
RCV_TERM_VTTRX_1 => (FALSE),
|
| 343 |
|
|
RXEQ_CFG_1 => ("01111011"),
|
| 344 |
|
|
TERMINATION_CTRL_1 => ("10100"),
|
| 345 |
|
|
TERMINATION_OVRD_1 => (FALSE),
|
| 346 |
|
|
TX_DETECT_RX_CFG_1 => (x"1832"),
|
| 347 |
|
|
|
| 348 |
|
|
--PRBS Detection Attributes
|
| 349 |
|
|
RXPRBSERR_LOOPBACK_0 => ('0'),
|
| 350 |
|
|
RXPRBSERR_LOOPBACK_1 => ('0'),
|
| 351 |
|
|
|
| 352 |
|
|
--Comma Detection and Alignment Attributes
|
| 353 |
|
|
ALIGN_COMMA_WORD_0 => (1),
|
| 354 |
|
|
COMMA_10B_ENABLE_0 => ("1111111111"),
|
| 355 |
|
|
DEC_MCOMMA_DETECT_0 => (TRUE),
|
| 356 |
|
|
DEC_PCOMMA_DETECT_0 => (TRUE),
|
| 357 |
|
|
DEC_VALID_COMMA_ONLY_0 => (TRUE),
|
| 358 |
|
|
MCOMMA_10B_VALUE_0 => ("1010000011"),
|
| 359 |
|
|
MCOMMA_DETECT_0 => (TRUE),
|
| 360 |
|
|
PCOMMA_10B_VALUE_0 => ("0101111100"),
|
| 361 |
|
|
PCOMMA_DETECT_0 => (TRUE),
|
| 362 |
|
|
RX_SLIDE_MODE_0 => ("PCS"),
|
| 363 |
|
|
ALIGN_COMMA_WORD_1 => (1),
|
| 364 |
|
|
COMMA_10B_ENABLE_1 => ("1111111111"),
|
| 365 |
|
|
DEC_MCOMMA_DETECT_1 => (TRUE),
|
| 366 |
|
|
DEC_PCOMMA_DETECT_1 => (TRUE),
|
| 367 |
|
|
DEC_VALID_COMMA_ONLY_1 => (TRUE),
|
| 368 |
|
|
MCOMMA_10B_VALUE_1 => ("1010000011"),
|
| 369 |
|
|
MCOMMA_DETECT_1 => (TRUE),
|
| 370 |
|
|
PCOMMA_10B_VALUE_1 => ("0101111100"),
|
| 371 |
|
|
PCOMMA_DETECT_1 => (TRUE),
|
| 372 |
|
|
RX_SLIDE_MODE_1 => ("PCS"),
|
| 373 |
|
|
|
| 374 |
|
|
--RX Loss-of-sync State Machine Attributes
|
| 375 |
|
|
RX_LOS_INVALID_INCR_0 => (8),
|
| 376 |
|
|
RX_LOS_THRESHOLD_0 => (128),
|
| 377 |
|
|
RX_LOSS_OF_SYNC_FSM_0 => (FALSE),
|
| 378 |
|
|
RX_LOS_INVALID_INCR_1 => (8),
|
| 379 |
|
|
RX_LOS_THRESHOLD_1 => (128),
|
| 380 |
|
|
RX_LOSS_OF_SYNC_FSM_1 => (FALSE),
|
| 381 |
|
|
|
| 382 |
|
|
--RX Elastic Buffer and Phase alignment Attributes
|
| 383 |
|
|
RX_BUFFER_USE_0 => (TRUE),
|
| 384 |
|
|
RX_EN_IDLE_RESET_BUF_0 => (TRUE),
|
| 385 |
|
|
RX_IDLE_HI_CNT_0 => ("1000"),
|
| 386 |
|
|
RX_IDLE_LO_CNT_0 => ("0000"),
|
| 387 |
|
|
RX_XCLK_SEL_0 => ("RXREC"),
|
| 388 |
|
|
RX_BUFFER_USE_1 => (TRUE),
|
| 389 |
|
|
RX_EN_IDLE_RESET_BUF_1 => (TRUE),
|
| 390 |
|
|
RX_IDLE_HI_CNT_1 => ("1000"),
|
| 391 |
|
|
RX_IDLE_LO_CNT_1 => ("0000"),
|
| 392 |
|
|
RX_XCLK_SEL_1 => ("RXREC"),
|
| 393 |
|
|
|
| 394 |
|
|
--Clock Correction Attributes
|
| 395 |
|
|
CLK_COR_ADJ_LEN_0 => (1),
|
| 396 |
|
|
CLK_COR_DET_LEN_0 => (1),
|
| 397 |
|
|
CLK_COR_INSERT_IDLE_FLAG_0 => (FALSE),
|
| 398 |
|
|
CLK_COR_KEEP_IDLE_0 => (FALSE),
|
| 399 |
|
|
CLK_COR_MAX_LAT_0 => (20),
|
| 400 |
|
|
CLK_COR_MIN_LAT_0 => (18),
|
| 401 |
|
|
CLK_COR_PRECEDENCE_0 => (TRUE),
|
| 402 |
|
|
CLK_COR_REPEAT_WAIT_0 => (0),
|
| 403 |
|
|
CLK_COR_SEQ_1_1_0 => ("0100011100"),
|
| 404 |
|
|
CLK_COR_SEQ_1_2_0 => ("0000000000"),
|
| 405 |
|
|
CLK_COR_SEQ_1_3_0 => ("0000000000"),
|
| 406 |
|
|
CLK_COR_SEQ_1_4_0 => ("0000000000"),
|
| 407 |
|
|
CLK_COR_SEQ_1_ENABLE_0 => ("0001"),
|
| 408 |
|
|
CLK_COR_SEQ_2_1_0 => ("0000000000"),
|
| 409 |
|
|
CLK_COR_SEQ_2_2_0 => ("0000000000"),
|
| 410 |
|
|
CLK_COR_SEQ_2_3_0 => ("0000000000"),
|
| 411 |
|
|
CLK_COR_SEQ_2_4_0 => ("0000000000"),
|
| 412 |
|
|
CLK_COR_SEQ_2_ENABLE_0 => ("0000"),
|
| 413 |
|
|
CLK_COR_SEQ_2_USE_0 => (FALSE),
|
| 414 |
|
|
CLK_CORRECT_USE_0 => (TRUE),
|
| 415 |
|
|
RX_DECODE_SEQ_MATCH_0 => (TRUE),
|
| 416 |
|
|
CLK_COR_ADJ_LEN_1 => (1),
|
| 417 |
|
|
CLK_COR_DET_LEN_1 => (1),
|
| 418 |
|
|
CLK_COR_INSERT_IDLE_FLAG_1 => (FALSE),
|
| 419 |
|
|
CLK_COR_KEEP_IDLE_1 => (FALSE),
|
| 420 |
|
|
CLK_COR_MAX_LAT_1 => (20),
|
| 421 |
|
|
CLK_COR_MIN_LAT_1 => (18),
|
| 422 |
|
|
CLK_COR_PRECEDENCE_1 => (TRUE),
|
| 423 |
|
|
CLK_COR_REPEAT_WAIT_1 => (0),
|
| 424 |
|
|
CLK_COR_SEQ_1_1_1 => ("0100011100"),
|
| 425 |
|
|
CLK_COR_SEQ_1_2_1 => ("0000000000"),
|
| 426 |
|
|
CLK_COR_SEQ_1_3_1 => ("0000000000"),
|
| 427 |
|
|
CLK_COR_SEQ_1_4_1 => ("0000000000"),
|
| 428 |
|
|
CLK_COR_SEQ_1_ENABLE_1 => ("0001"),
|
| 429 |
|
|
CLK_COR_SEQ_2_1_1 => ("0000000000"),
|
| 430 |
|
|
CLK_COR_SEQ_2_2_1 => ("0000000000"),
|
| 431 |
|
|
CLK_COR_SEQ_2_3_1 => ("0000000000"),
|
| 432 |
|
|
CLK_COR_SEQ_2_4_1 => ("0000000000"),
|
| 433 |
|
|
CLK_COR_SEQ_2_ENABLE_1 => ("0000"),
|
| 434 |
|
|
CLK_COR_SEQ_2_USE_1 => (FALSE),
|
| 435 |
|
|
CLK_CORRECT_USE_1 => (TRUE),
|
| 436 |
|
|
RX_DECODE_SEQ_MATCH_1 => (TRUE),
|
| 437 |
|
|
|
| 438 |
|
|
--Channel Bonding Attributes
|
| 439 |
|
|
CHAN_BOND_1_MAX_SKEW_0 => (1),
|
| 440 |
|
|
CHAN_BOND_2_MAX_SKEW_0 => (1),
|
| 441 |
|
|
CHAN_BOND_KEEP_ALIGN_0 => (FALSE),
|
| 442 |
|
|
CHAN_BOND_SEQ_1_1_0 => ("0001001010"),
|
| 443 |
|
|
CHAN_BOND_SEQ_1_2_0 => ("0001001010"),
|
| 444 |
|
|
CHAN_BOND_SEQ_1_3_0 => ("0001001010"),
|
| 445 |
|
|
CHAN_BOND_SEQ_1_4_0 => ("0110111100"),
|
| 446 |
|
|
CHAN_BOND_SEQ_1_ENABLE_0 => ("0000"),
|
| 447 |
|
|
CHAN_BOND_SEQ_2_1_0 => ("0100111100"),
|
| 448 |
|
|
CHAN_BOND_SEQ_2_2_0 => ("0100111100"),
|
| 449 |
|
|
CHAN_BOND_SEQ_2_3_0 => ("0110111100"),
|
| 450 |
|
|
CHAN_BOND_SEQ_2_4_0 => ("0100011100"),
|
| 451 |
|
|
CHAN_BOND_SEQ_2_ENABLE_0 => ("0000"),
|
| 452 |
|
|
CHAN_BOND_SEQ_2_USE_0 => (FALSE),
|
| 453 |
|
|
CHAN_BOND_SEQ_LEN_0 => (1),
|
| 454 |
|
|
RX_EN_MODE_RESET_BUF_0 => (TRUE),
|
| 455 |
|
|
CHAN_BOND_1_MAX_SKEW_1 => (1),
|
| 456 |
|
|
CHAN_BOND_2_MAX_SKEW_1 => (1),
|
| 457 |
|
|
CHAN_BOND_KEEP_ALIGN_1 => (FALSE),
|
| 458 |
|
|
CHAN_BOND_SEQ_1_1_1 => ("0001001010"),
|
| 459 |
|
|
CHAN_BOND_SEQ_1_2_1 => ("0001001010"),
|
| 460 |
|
|
CHAN_BOND_SEQ_1_3_1 => ("0001001010"),
|
| 461 |
|
|
CHAN_BOND_SEQ_1_4_1 => ("0110111100"),
|
| 462 |
|
|
CHAN_BOND_SEQ_1_ENABLE_1 => ("0000"),
|
| 463 |
|
|
CHAN_BOND_SEQ_2_1_1 => ("0100111100"),
|
| 464 |
|
|
CHAN_BOND_SEQ_2_2_1 => ("0100111100"),
|
| 465 |
|
|
CHAN_BOND_SEQ_2_3_1 => ("0110111100"),
|
| 466 |
|
|
CHAN_BOND_SEQ_2_4_1 => ("0100011100"),
|
| 467 |
|
|
CHAN_BOND_SEQ_2_ENABLE_1 => ("0000"),
|
| 468 |
|
|
CHAN_BOND_SEQ_2_USE_1 => (FALSE),
|
| 469 |
|
|
CHAN_BOND_SEQ_LEN_1 => (1),
|
| 470 |
|
|
RX_EN_MODE_RESET_BUF_1 => (TRUE),
|
| 471 |
|
|
|
| 472 |
|
|
--RX PCI Express Attributes
|
| 473 |
|
|
CB2_INH_CC_PERIOD_0 => (8),
|
| 474 |
|
|
CDR_PH_ADJ_TIME_0 => ("01010"),
|
| 475 |
|
|
PCI_EXPRESS_MODE_0 => (TRUE),
|
| 476 |
|
|
RX_EN_IDLE_HOLD_CDR_0 => (TRUE),
|
| 477 |
|
|
RX_EN_IDLE_RESET_FR_0 => (TRUE),
|
| 478 |
|
|
RX_EN_IDLE_RESET_PH_0 => (TRUE),
|
| 479 |
|
|
RX_STATUS_FMT_0 => ("PCIE"),
|
| 480 |
|
|
TRANS_TIME_FROM_P2_0 => (x"03c"),
|
| 481 |
|
|
TRANS_TIME_NON_P2_0 => (x"19"),
|
| 482 |
|
|
TRANS_TIME_TO_P2_0 => (x"064"),
|
| 483 |
|
|
CB2_INH_CC_PERIOD_1 => (8),
|
| 484 |
|
|
CDR_PH_ADJ_TIME_1 => ("01010"),
|
| 485 |
|
|
PCI_EXPRESS_MODE_1 => (TRUE),
|
| 486 |
|
|
RX_EN_IDLE_HOLD_CDR_1 => (TRUE),
|
| 487 |
|
|
RX_EN_IDLE_RESET_FR_1 => (TRUE),
|
| 488 |
|
|
RX_EN_IDLE_RESET_PH_1 => (TRUE),
|
| 489 |
|
|
RX_STATUS_FMT_1 => ("PCIE"),
|
| 490 |
|
|
TRANS_TIME_FROM_P2_1 => (x"03c"),
|
| 491 |
|
|
TRANS_TIME_NON_P2_1 => (x"19"),
|
| 492 |
|
|
TRANS_TIME_TO_P2_1 => (x"064"),
|
| 493 |
|
|
|
| 494 |
|
|
--RX SATA Attributes
|
| 495 |
|
|
SATA_BURST_VAL_0 => ("100"),
|
| 496 |
|
|
SATA_IDLE_VAL_0 => ("100"),
|
| 497 |
|
|
SATA_MAX_BURST_0 => (7),
|
| 498 |
|
|
SATA_MAX_INIT_0 => (22),
|
| 499 |
|
|
SATA_MAX_WAKE_0 => (7),
|
| 500 |
|
|
SATA_MIN_BURST_0 => (4),
|
| 501 |
|
|
SATA_MIN_INIT_0 => (12),
|
| 502 |
|
|
SATA_MIN_WAKE_0 => (4),
|
| 503 |
|
|
SATA_BURST_VAL_1 => ("100"),
|
| 504 |
|
|
SATA_IDLE_VAL_1 => ("100"),
|
| 505 |
|
|
SATA_MAX_BURST_1 => (7),
|
| 506 |
|
|
SATA_MAX_INIT_1 => (22),
|
| 507 |
|
|
SATA_MAX_WAKE_1 => (7),
|
| 508 |
|
|
SATA_MIN_BURST_1 => (4),
|
| 509 |
|
|
SATA_MIN_INIT_1 => (12),
|
| 510 |
|
|
SATA_MIN_WAKE_1 => (4)
|
| 511 |
|
|
|
| 512 |
|
|
|
| 513 |
|
|
)
|
| 514 |
|
|
port map
|
| 515 |
|
|
(
|
| 516 |
|
|
------------------------ Loopback and Powerdown Ports ----------------------
|
| 517 |
|
|
LOOPBACK0 => tied_to_ground_vec_i(2 downto 0),
|
| 518 |
|
|
LOOPBACK1 => tied_to_ground_vec_i(2 downto 0),
|
| 519 |
|
|
RXPOWERDOWN0 => RXPOWERDOWN0_IN,
|
| 520 |
|
|
RXPOWERDOWN1 => RXPOWERDOWN1_IN,
|
| 521 |
|
|
TXPOWERDOWN0 => TXPOWERDOWN0_IN,
|
| 522 |
|
|
TXPOWERDOWN1 => TXPOWERDOWN1_IN,
|
| 523 |
|
|
--------------------------------- PLL Ports --------------------------------
|
| 524 |
|
|
CLK00 => CLK00_IN,
|
| 525 |
|
|
CLK01 => CLK01_IN,
|
| 526 |
|
|
CLK10 => tied_to_ground_i,
|
| 527 |
|
|
CLK11 => tied_to_ground_i,
|
| 528 |
|
|
CLKINEAST0 => tied_to_ground_i,
|
| 529 |
|
|
CLKINEAST1 => tied_to_ground_i,
|
| 530 |
|
|
CLKINWEST0 => tied_to_ground_i,
|
| 531 |
|
|
CLKINWEST1 => tied_to_ground_i,
|
| 532 |
|
|
GCLK00 => tied_to_ground_i,
|
| 533 |
|
|
GCLK01 => tied_to_ground_i,
|
| 534 |
|
|
GCLK10 => tied_to_ground_i,
|
| 535 |
|
|
GCLK11 => tied_to_ground_i,
|
| 536 |
|
|
GTPRESET0 => GTPRESET0_IN,
|
| 537 |
|
|
GTPRESET1 => GTPRESET1_IN,
|
| 538 |
|
|
GTPTEST0 => "00010000",
|
| 539 |
|
|
GTPTEST1 => "00010000",
|
| 540 |
|
|
INTDATAWIDTH0 => tied_to_vcc_i,
|
| 541 |
|
|
INTDATAWIDTH1 => tied_to_vcc_i,
|
| 542 |
|
|
PLLCLK00 => tied_to_ground_i,
|
| 543 |
|
|
PLLCLK01 => tied_to_ground_i,
|
| 544 |
|
|
PLLCLK10 => tied_to_ground_i,
|
| 545 |
|
|
PLLCLK11 => tied_to_ground_i,
|
| 546 |
|
|
PLLLKDET0 => PLLLKDET0_OUT,
|
| 547 |
|
|
PLLLKDET1 => PLLLKDET1_OUT,
|
| 548 |
|
|
PLLLKDETEN0 => tied_to_vcc_i,
|
| 549 |
|
|
PLLLKDETEN1 => tied_to_vcc_i,
|
| 550 |
|
|
PLLPOWERDOWN0 => tied_to_ground_i,
|
| 551 |
|
|
PLLPOWERDOWN1 => tied_to_ground_i,
|
| 552 |
|
|
REFCLKOUT0 => open,
|
| 553 |
|
|
REFCLKOUT1 => open,
|
| 554 |
|
|
REFCLKPLL0 => open,
|
| 555 |
|
|
REFCLKPLL1 => open,
|
| 556 |
|
|
REFCLKPWRDNB0 => tied_to_vcc_i,
|
| 557 |
|
|
REFCLKPWRDNB1 => tied_to_vcc_i,
|
| 558 |
|
|
REFSELDYPLL0 => tied_to_ground_vec_i(2 downto 0),
|
| 559 |
|
|
REFSELDYPLL1 => tied_to_ground_vec_i(2 downto 0),
|
| 560 |
|
|
RESETDONE0 => RESETDONE0_OUT,
|
| 561 |
|
|
RESETDONE1 => RESETDONE1_OUT,
|
| 562 |
|
|
TSTCLK0 => tied_to_ground_i,
|
| 563 |
|
|
TSTCLK1 => tied_to_ground_i,
|
| 564 |
|
|
TSTIN0 => tied_to_ground_vec_i(11 downto 0),
|
| 565 |
|
|
TSTIN1 => tied_to_ground_vec_i(11 downto 0),
|
| 566 |
|
|
TSTOUT0 => open,
|
| 567 |
|
|
TSTOUT1 => open,
|
| 568 |
|
|
----------------------- Receive Ports - 8b10b Decoder ----------------------
|
| 569 |
|
|
RXCHARISCOMMA0 => open,
|
| 570 |
|
|
RXCHARISCOMMA1 => open,
|
| 571 |
|
|
RXCHARISK0(3 downto 2) => rxcharisk0_float_i,
|
| 572 |
|
|
RXCHARISK0(1 downto 0) => RXCHARISK0_OUT,
|
| 573 |
|
|
RXCHARISK1(3 downto 2) => rxcharisk1_float_i,
|
| 574 |
|
|
RXCHARISK1(1 downto 0) => RXCHARISK1_OUT,
|
| 575 |
|
|
RXDEC8B10BUSE0 => tied_to_vcc_i,
|
| 576 |
|
|
RXDEC8B10BUSE1 => tied_to_vcc_i,
|
| 577 |
|
|
RXDISPERR0(3 downto 2) => rxdisperr0_float_i,
|
| 578 |
|
|
RXDISPERR0(1 downto 0) => RXDISPERR0_OUT,
|
| 579 |
|
|
RXDISPERR1(3 downto 2) => rxdisperr1_float_i,
|
| 580 |
|
|
RXDISPERR1(1 downto 0) => RXDISPERR1_OUT,
|
| 581 |
|
|
RXNOTINTABLE0(3 downto 2) => rxnotintable0_float_i,
|
| 582 |
|
|
RXNOTINTABLE0(1 downto 0) => RXNOTINTABLE0_OUT,
|
| 583 |
|
|
RXNOTINTABLE1(3 downto 2) => rxnotintable1_float_i,
|
| 584 |
|
|
RXNOTINTABLE1(1 downto 0) => RXNOTINTABLE1_OUT,
|
| 585 |
|
|
RXRUNDISP0 => open,
|
| 586 |
|
|
RXRUNDISP1 => open,
|
| 587 |
|
|
USRCODEERR0 => tied_to_ground_i,
|
| 588 |
|
|
USRCODEERR1 => tied_to_ground_i,
|
| 589 |
|
|
---------------------- Receive Ports - Channel Bonding ---------------------
|
| 590 |
|
|
RXCHANBONDSEQ0 => open,
|
| 591 |
|
|
RXCHANBONDSEQ1 => open,
|
| 592 |
|
|
RXCHANISALIGNED0 => open,
|
| 593 |
|
|
RXCHANISALIGNED1 => open,
|
| 594 |
|
|
RXCHANREALIGN0 => open,
|
| 595 |
|
|
RXCHANREALIGN1 => open,
|
| 596 |
|
|
RXCHBONDI => tied_to_ground_vec_i(2 downto 0),
|
| 597 |
|
|
RXCHBONDMASTER0 => tied_to_ground_i,
|
| 598 |
|
|
RXCHBONDMASTER1 => tied_to_ground_i,
|
| 599 |
|
|
RXCHBONDO => open,
|
| 600 |
|
|
RXCHBONDSLAVE0 => tied_to_ground_i,
|
| 601 |
|
|
RXCHBONDSLAVE1 => tied_to_ground_i,
|
| 602 |
|
|
RXENCHANSYNC0 => tied_to_ground_i,
|
| 603 |
|
|
RXENCHANSYNC1 => tied_to_ground_i,
|
| 604 |
|
|
---------------------- Receive Ports - Clock Correction --------------------
|
| 605 |
|
|
RXCLKCORCNT0 => RXCLKCORCNT0_OUT,
|
| 606 |
|
|
RXCLKCORCNT1 => RXCLKCORCNT1_OUT,
|
| 607 |
|
|
--------------- Receive Ports - Comma Detection and Alignment --------------
|
| 608 |
|
|
RXBYTEISALIGNED0 => open,
|
| 609 |
|
|
RXBYTEISALIGNED1 => open,
|
| 610 |
|
|
RXBYTEREALIGN0 => open,
|
| 611 |
|
|
RXBYTEREALIGN1 => open,
|
| 612 |
|
|
RXCOMMADET0 => open,
|
| 613 |
|
|
RXCOMMADET1 => open,
|
| 614 |
|
|
RXCOMMADETUSE0 => tied_to_vcc_i,
|
| 615 |
|
|
RXCOMMADETUSE1 => tied_to_vcc_i,
|
| 616 |
|
|
RXENMCOMMAALIGN0 => RXENMCOMMAALIGN0_IN,
|
| 617 |
|
|
RXENMCOMMAALIGN1 => RXENMCOMMAALIGN1_IN,
|
| 618 |
|
|
RXENPCOMMAALIGN0 => RXENPCOMMAALIGN0_IN,
|
| 619 |
|
|
RXENPCOMMAALIGN1 => RXENPCOMMAALIGN1_IN,
|
| 620 |
|
|
RXSLIDE0 => tied_to_ground_i,
|
| 621 |
|
|
RXSLIDE1 => tied_to_ground_i,
|
| 622 |
|
|
----------------------- Receive Ports - PRBS Detection ---------------------
|
| 623 |
|
|
PRBSCNTRESET0 => tied_to_ground_i,
|
| 624 |
|
|
PRBSCNTRESET1 => tied_to_ground_i,
|
| 625 |
|
|
RXENPRBSTST0 => tied_to_ground_vec_i(2 downto 0),
|
| 626 |
|
|
RXENPRBSTST1 => tied_to_ground_vec_i(2 downto 0),
|
| 627 |
|
|
RXPRBSERR0 => open,
|
| 628 |
|
|
RXPRBSERR1 => open,
|
| 629 |
|
|
------------------- Receive Ports - RX Data Path interface -----------------
|
| 630 |
|
|
RXDATA0 => rxdata0_i,
|
| 631 |
|
|
RXDATA1 => rxdata1_i,
|
| 632 |
|
|
RXDATAWIDTH0 => "01",
|
| 633 |
|
|
RXDATAWIDTH1 => "01",
|
| 634 |
|
|
RXRECCLK0 => open,
|
| 635 |
|
|
RXRECCLK1 => open,
|
| 636 |
|
|
RXRESET0 => RXRESET0_IN,
|
| 637 |
|
|
RXRESET1 => RXRESET1_IN,
|
| 638 |
|
|
RXUSRCLK0 => RXUSRCLK0_IN,
|
| 639 |
|
|
RXUSRCLK1 => RXUSRCLK1_IN,
|
| 640 |
|
|
RXUSRCLK20 => RXUSRCLK20_IN,
|
| 641 |
|
|
RXUSRCLK21 => RXUSRCLK21_IN,
|
| 642 |
|
|
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
|
| 643 |
|
|
GATERXELECIDLE0 => GATERXELECIDLE0_IN,
|
| 644 |
|
|
GATERXELECIDLE1 => GATERXELECIDLE1_IN,
|
| 645 |
|
|
IGNORESIGDET0 => IGNORESIGDET0_IN,
|
| 646 |
|
|
IGNORESIGDET1 => IGNORESIGDET1_IN,
|
| 647 |
|
|
RCALINEAST => tied_to_ground_vec_i(4 downto 0),
|
| 648 |
|
|
RCALINWEST => tied_to_ground_vec_i(4 downto 0),
|
| 649 |
|
|
RCALOUTEAST => open,
|
| 650 |
|
|
RCALOUTWEST => open,
|
| 651 |
|
|
RXCDRRESET0 => tied_to_ground_i,
|
| 652 |
|
|
RXCDRRESET1 => tied_to_ground_i,
|
| 653 |
|
|
RXELECIDLE0 => RXELECIDLE0_OUT,
|
| 654 |
|
|
RXELECIDLE1 => RXELECIDLE1_OUT,
|
| 655 |
|
|
RXEQMIX0 => "11",
|
| 656 |
|
|
RXEQMIX1 => "11",
|
| 657 |
|
|
RXN0 => RXN0_IN,
|
| 658 |
|
|
RXN1 => RXN1_IN,
|
| 659 |
|
|
RXP0 => RXP0_IN,
|
| 660 |
|
|
RXP1 => RXP1_IN,
|
| 661 |
|
|
----------- Receive Ports - RX Elastic Buffer and Phase Alignment ----------
|
| 662 |
|
|
RXBUFRESET0 => tied_to_ground_i,
|
| 663 |
|
|
RXBUFRESET1 => tied_to_ground_i,
|
| 664 |
|
|
RXBUFSTATUS0 => open,
|
| 665 |
|
|
RXBUFSTATUS1 => open,
|
| 666 |
|
|
RXENPMAPHASEALIGN0 => tied_to_ground_i,
|
| 667 |
|
|
RXENPMAPHASEALIGN1 => tied_to_ground_i,
|
| 668 |
|
|
RXPMASETPHASE0 => tied_to_ground_i,
|
| 669 |
|
|
RXPMASETPHASE1 => tied_to_ground_i,
|
| 670 |
|
|
RXSTATUS0 => RXSTATUS0_OUT,
|
| 671 |
|
|
RXSTATUS1 => RXSTATUS1_OUT,
|
| 672 |
|
|
--------------- Receive Ports - RX Loss-of-sync State Machine --------------
|
| 673 |
|
|
RXLOSSOFSYNC0 => open,
|
| 674 |
|
|
RXLOSSOFSYNC1 => open,
|
| 675 |
|
|
-------------- Receive Ports - RX Pipe Control for PCI Express -------------
|
| 676 |
|
|
PHYSTATUS0 => PHYSTATUS0_OUT,
|
| 677 |
|
|
PHYSTATUS1 => PHYSTATUS1_OUT,
|
| 678 |
|
|
RXVALID0 => RXVALID0_OUT,
|
| 679 |
|
|
RXVALID1 => RXVALID1_OUT,
|
| 680 |
|
|
-------------------- Receive Ports - RX Polarity Control -------------------
|
| 681 |
|
|
RXPOLARITY0 => RXPOLARITY0_IN,
|
| 682 |
|
|
RXPOLARITY1 => RXPOLARITY1_IN,
|
| 683 |
|
|
------------- Shared Ports - Dynamic Reconfiguration Port (DRP) ------------
|
| 684 |
|
|
DADDR => tied_to_ground_vec_i(7 downto 0),
|
| 685 |
|
|
DCLK => tied_to_ground_i,
|
| 686 |
|
|
DEN => tied_to_ground_i,
|
| 687 |
|
|
DI => tied_to_ground_vec_i(15 downto 0),
|
| 688 |
|
|
DRDY => open,
|
| 689 |
|
|
DRPDO => open,
|
| 690 |
|
|
DWE => tied_to_ground_i,
|
| 691 |
|
|
---------------------------- TX/RX Datapath Ports --------------------------
|
| 692 |
|
|
GTPCLKFBEAST => open,
|
| 693 |
|
|
GTPCLKFBSEL0EAST => "10",
|
| 694 |
|
|
GTPCLKFBSEL0WEST => "00",
|
| 695 |
|
|
GTPCLKFBSEL1EAST => "11",
|
| 696 |
|
|
GTPCLKFBSEL1WEST => "01",
|
| 697 |
|
|
GTPCLKFBWEST => open,
|
| 698 |
|
|
GTPCLKOUT0 => GTPCLKOUT0_OUT,
|
| 699 |
|
|
GTPCLKOUT1 => GTPCLKOUT1_OUT,
|
| 700 |
|
|
------------------- Transmit Ports - 8b10b Encoder Control -----------------
|
| 701 |
|
|
TXBYPASS8B10B0 => tied_to_ground_vec_i(3 downto 0),
|
| 702 |
|
|
TXBYPASS8B10B1 => tied_to_ground_vec_i(3 downto 0),
|
| 703 |
|
|
TXCHARDISPMODE0(3 downto 2) => tied_to_ground_vec_i(1 downto 0),
|
| 704 |
|
|
TXCHARDISPMODE0(1 downto 0) => TXCHARDISPMODE0_IN,
|
| 705 |
|
|
TXCHARDISPMODE1(3 downto 2) => tied_to_ground_vec_i(1 downto 0),
|
| 706 |
|
|
TXCHARDISPMODE1(1 downto 0) => TXCHARDISPMODE1_IN,
|
| 707 |
|
|
TXCHARDISPVAL0 => tied_to_ground_vec_i(3 downto 0),
|
| 708 |
|
|
TXCHARDISPVAL1 => tied_to_ground_vec_i(3 downto 0),
|
| 709 |
|
|
TXCHARISK0(3 downto 2) => tied_to_ground_vec_i(1 downto 0),
|
| 710 |
|
|
TXCHARISK0(1 downto 0) => TXCHARISK0_IN,
|
| 711 |
|
|
TXCHARISK1(3 downto 2) => tied_to_ground_vec_i(1 downto 0),
|
| 712 |
|
|
TXCHARISK1(1 downto 0) => TXCHARISK1_IN,
|
| 713 |
|
|
TXENC8B10BUSE0 => tied_to_vcc_i,
|
| 714 |
|
|
TXENC8B10BUSE1 => tied_to_vcc_i,
|
| 715 |
|
|
TXKERR0 => open,
|
| 716 |
|
|
TXKERR1 => open,
|
| 717 |
|
|
TXRUNDISP0 => open,
|
| 718 |
|
|
TXRUNDISP1 => open,
|
| 719 |
|
|
--------------- Transmit Ports - TX Buffer and Phase Alignment -------------
|
| 720 |
|
|
TXBUFSTATUS0 => open,
|
| 721 |
|
|
TXBUFSTATUS1 => open,
|
| 722 |
|
|
TXENPMAPHASEALIGN0 => tied_to_ground_i,
|
| 723 |
|
|
TXENPMAPHASEALIGN1 => tied_to_ground_i,
|
| 724 |
|
|
TXPMASETPHASE0 => tied_to_ground_i,
|
| 725 |
|
|
TXPMASETPHASE1 => tied_to_ground_i,
|
| 726 |
|
|
------------------ Transmit Ports - TX Data Path interface -----------------
|
| 727 |
|
|
TXDATA0 => txdata0_i,
|
| 728 |
|
|
TXDATA1 => txdata1_i,
|
| 729 |
|
|
TXDATAWIDTH0 => "01",
|
| 730 |
|
|
TXDATAWIDTH1 => "01",
|
| 731 |
|
|
TXOUTCLK0 => open,
|
| 732 |
|
|
TXOUTCLK1 => open,
|
| 733 |
|
|
TXRESET0 => tied_to_ground_i,
|
| 734 |
|
|
TXRESET1 => tied_to_ground_i,
|
| 735 |
|
|
TXUSRCLK0 => TXUSRCLK0_IN,
|
| 736 |
|
|
TXUSRCLK1 => TXUSRCLK1_IN,
|
| 737 |
|
|
TXUSRCLK20 => TXUSRCLK20_IN,
|
| 738 |
|
|
TXUSRCLK21 => TXUSRCLK21_IN,
|
| 739 |
|
|
--------------- Transmit Ports - TX Driver and OOB signalling --------------
|
| 740 |
|
|
TXBUFDIFFCTRL0 => "101",
|
| 741 |
|
|
TXBUFDIFFCTRL1 => "101",
|
| 742 |
|
|
TXDIFFCTRL0 => "1001",
|
| 743 |
|
|
TXDIFFCTRL1 => "1001",
|
| 744 |
|
|
TXINHIBIT0 => tied_to_ground_i,
|
| 745 |
|
|
TXINHIBIT1 => tied_to_ground_i,
|
| 746 |
|
|
TXN0 => TXN0_OUT,
|
| 747 |
|
|
TXN1 => TXN1_OUT,
|
| 748 |
|
|
TXP0 => TXP0_OUT,
|
| 749 |
|
|
TXP1 => TXP1_OUT,
|
| 750 |
|
|
TXPREEMPHASIS0 => "000",
|
| 751 |
|
|
TXPREEMPHASIS1 => "000",
|
| 752 |
|
|
--------------------- Transmit Ports - TX PRBS Generator -------------------
|
| 753 |
|
|
TXENPRBSTST0 => tied_to_ground_vec_i(2 downto 0),
|
| 754 |
|
|
TXENPRBSTST1 => tied_to_ground_vec_i(2 downto 0),
|
| 755 |
|
|
TXPRBSFORCEERR0 => tied_to_ground_i,
|
| 756 |
|
|
TXPRBSFORCEERR1 => tied_to_ground_i,
|
| 757 |
|
|
-------------------- Transmit Ports - TX Polarity Control ------------------
|
| 758 |
|
|
TXPOLARITY0 => tied_to_ground_i,
|
| 759 |
|
|
TXPOLARITY1 => tied_to_ground_i,
|
| 760 |
|
|
----------------- Transmit Ports - TX Ports for PCI Express ----------------
|
| 761 |
|
|
TXDETECTRX0 => TXDETECTRX0_IN,
|
| 762 |
|
|
TXDETECTRX1 => TXDETECTRX1_IN,
|
| 763 |
|
|
TXELECIDLE0 => TXELECIDLE0_IN,
|
| 764 |
|
|
TXELECIDLE1 => TXELECIDLE1_IN,
|
| 765 |
|
|
TXPDOWNASYNCH0 => tied_to_ground_i,
|
| 766 |
|
|
TXPDOWNASYNCH1 => tied_to_ground_i,
|
| 767 |
|
|
--------------------- Transmit Ports - TX Ports for SATA -------------------
|
| 768 |
|
|
TXCOMSTART0 => tied_to_ground_i,
|
| 769 |
|
|
TXCOMSTART1 => tied_to_ground_i,
|
| 770 |
|
|
TXCOMTYPE0 => tied_to_ground_i,
|
| 771 |
|
|
TXCOMTYPE1 => tied_to_ground_i
|
| 772 |
|
|
|
| 773 |
|
|
);
|
| 774 |
|
|
|
| 775 |
|
|
end RTL;
|
| 776 |
|
|
|
| 777 |
|
|
|
