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-------------------------------------------------------------------------------
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--
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-- (c) Copyright 2008, 2009 Xilinx, Inc. All rights reserved.
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--
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-- This file contains confidential and proprietary information
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-- of Xilinx, Inc. and is protected under U.S. and
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-- international copyright and other intellectual property
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-- laws.
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--
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-- DISCLAIMER
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-- This disclaimer is not a license and does not grant any
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-- rights to the materials distributed herewith. Except as
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-- otherwise provided in a valid license issued to you by
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-- Xilinx, and to the maximum extent permitted by applicable
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-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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-- (2) Xilinx shall not be liable (whether in contract or tort,
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-- including negligence, or under any other theory of
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-- liability) for any loss or damage of any kind or nature
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-- related to, arising under or in connection with these
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-- materials, including for any direct, or any indirect,
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-- special, incidental, or consequential loss or damage
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-- (including loss of data, profits, goodwill, or any type of
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-- loss or damage suffered as a result of any action brought
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-- by a third party) even if such damage or loss was
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-- reasonably foreseeable or Xilinx had been advised of the
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-- possibility of the same.
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--
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-- CRITICAL APPLICATIONS
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-- Xilinx products are not designed or intended to be fail-
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-- safe, or for use in any application requiring fail-safe
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-- performance, such as life-support or safety devices or
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-- systems, Class III medical devices, nuclear facilities,
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-- applications related to the deployment of airbags, or any
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-- other applications that could lead to death, personal
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-- injury, or severe property or environmental damage
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-- (individually and collectively, "Critical
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-- Applications"). Customer assumes the sole risk and
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-- liability of any use of Xilinx products in Critical
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-- Applications, subject only to applicable laws and
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-- regulations governing limitations on product liability.
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--
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-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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-- PART OF THIS FILE AT ALL TIMES.
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--
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-------------------------------------------------------------------------------
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-- Project : Spartan-6 Integrated Block for PCI Express
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-- File : pcie_bram_top_s6.vhd
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-- Description: BlockRAM top level module for Spartan-6 PCIe Block
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--
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-- Given the selected core configuration, calculate the number of
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-- BRAMs and pipeline stages and instantiate the BRAMS.
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--
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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entity pcie_bram_top_s6 is
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generic (
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DEV_CAP_MAX_PAYLOAD_SUPPORTED : integer := 0;
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VC0_TX_LASTPACKET : integer := 31;
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TLM_TX_OVERHEAD : integer := 20;
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TL_TX_RAM_RADDR_LATENCY : integer := 1;
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TL_TX_RAM_RDATA_LATENCY : integer := 2;
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TL_TX_RAM_WRITE_LATENCY : integer := 1;
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VC0_RX_LIMIT : integer := 16#1FFF#;
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TL_RX_RAM_RADDR_LATENCY : integer := 1;
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TL_RX_RAM_RDATA_LATENCY : integer := 2;
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TL_RX_RAM_WRITE_LATENCY : integer := 1
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);
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port (
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user_clk_i : in std_logic;
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reset_i : in std_logic;
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mim_tx_wen : in std_logic;
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mim_tx_waddr : in std_logic_vector(11 downto 0);
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mim_tx_wdata : in std_logic_vector(35 downto 0);
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mim_tx_ren : in std_logic;
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mim_tx_rce : in std_logic;
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mim_tx_raddr : in std_logic_vector(11 downto 0);
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mim_tx_rdata : out std_logic_vector(35 downto 0);
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mim_rx_wen : in std_logic;
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mim_rx_waddr : in std_logic_vector(11 downto 0);
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mim_rx_wdata : in std_logic_vector(35 downto 0);
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mim_rx_ren : in std_logic;
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mim_rx_rce : in std_logic;
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mim_rx_raddr : in std_logic_vector(11 downto 0);
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mim_rx_rdata : out std_logic_vector(35 downto 0)
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);
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end pcie_bram_top_s6;
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architecture rtl of pcie_bram_top_s6 is
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component pcie_brams_s6
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generic (
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NUM_BRAMS : integer;
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RAM_RADDR_LATENCY : integer;
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RAM_RDATA_LATENCY : integer;
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RAM_WRITE_LATENCY : integer
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);
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port (
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user_clk_i : in std_logic;
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reset_i : in std_logic;
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wen : in std_logic;
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waddr : in std_logic_vector(11 downto 0);
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wdata : in std_logic_vector(35 downto 0);
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ren : in std_logic;
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rce : in std_logic;
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raddr : in std_logic_vector(11 downto 0);
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rdata : out std_logic_vector(35 downto 0)
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);
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end component;
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function CALC_TX_COLS(constant MPS : in integer;
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constant LASTPACKET : in integer;
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constant OVERHEAD : in integer
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) return integer is
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variable MPS_BYTES : integer;
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variable BYTES_TX : integer;
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variable COLS_TX : integer;
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begin
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-- Decode MPS value
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if (MPS = 0) then MPS_BYTES := 128;
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elsif (MPS = 1) then MPS_BYTES := 256;
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else MPS_BYTES := 512; -- MPS = 2
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end if;
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-- Calculate total bytes from MPS, number of packets, and overhead
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BYTES_TX := (LASTPACKET + 1) * (MPS_BYTES + OVERHEAD);
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-- Determine number of BRAM columns from total bytes
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if (BYTES_TX <= 2048) then COLS_TX := 1;
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elsif (BYTES_TX <= 4096) then COLS_TX := 2;
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else COLS_TX := 4; -- BYTES_TX <= 8192
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end if;
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return COLS_TX;
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end function CALC_TX_COLS;
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function CALC_RX_COLS(constant LIMIT : in integer) return integer is
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variable COLS_RX : integer;
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begin
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-- Determine number of BRAM columns from total RAM size
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if (LIMIT <= 512) then COLS_RX := 1;
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elsif (LIMIT <= 1024) then COLS_RX := 2;
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else COLS_RX := 4; -- LIMIT <= 2048
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end if;
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return COLS_RX;
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end function CALC_RX_COLS;
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begin
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pcie_brams_tx : pcie_brams_s6
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generic map(
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NUM_BRAMS => CALC_TX_COLS(DEV_CAP_MAX_PAYLOAD_SUPPORTED, VC0_TX_LASTPACKET, TLM_TX_OVERHEAD),
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RAM_RADDR_LATENCY => TL_TX_RAM_RADDR_LATENCY,
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RAM_RDATA_LATENCY => TL_TX_RAM_RDATA_LATENCY,
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RAM_WRITE_LATENCY => TL_TX_RAM_WRITE_LATENCY
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)
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port map (
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user_clk_i => user_clk_i,
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reset_i => reset_i,
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waddr => mim_tx_waddr,
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wen => mim_tx_wen,
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ren => mim_tx_ren,
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rce => mim_tx_rce,
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wdata => mim_tx_wdata,
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raddr => mim_tx_raddr,
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rdata => mim_tx_rdata
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);
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pcie_brams_rx : pcie_brams_s6
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generic map(
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NUM_BRAMS => CALC_RX_COLS(VC0_RX_LIMIT),
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RAM_RADDR_LATENCY => TL_RX_RAM_RADDR_LATENCY,
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RAM_RDATA_LATENCY => TL_RX_RAM_RDATA_LATENCY,
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RAM_WRITE_LATENCY => TL_RX_RAM_WRITE_LATENCY
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)
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port map (
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user_clk_i => user_clk_i,
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reset_i => reset_i,
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waddr => mim_rx_waddr,
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wen => mim_rx_wen,
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ren => mim_rx_ren,
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rce => mim_rx_rce,
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wdata => mim_rx_wdata,
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raddr => mim_rx_raddr,
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rdata => mim_rx_rdata
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);
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end rtl;
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