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[/] [pcie_ds_dma/] [trunk/] [core/] [ds_dma64/] [pcie_src/] [pcie_core64_m1/] [source_s6/] [pcie_brams_s6.vhd] - Blame information for rev 2

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-------------------------------------------------------------------------------
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--
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-- (c) Copyright 2008, 2009 Xilinx, Inc. All rights reserved.
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--
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-- This file contains confidential and proprietary information
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-- of Xilinx, Inc. and is protected under U.S. and
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-- international copyright and other intellectual property
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-- laws.
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--
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-- DISCLAIMER
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-- This disclaimer is not a license and does not grant any
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-- rights to the materials distributed herewith. Except as
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-- otherwise provided in a valid license issued to you by
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-- Xilinx, and to the maximum extent permitted by applicable
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-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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-- (2) Xilinx shall not be liable (whether in contract or tort,
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-- including negligence, or under any other theory of
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-- liability) for any loss or damage of any kind or nature
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-- related to, arising under or in connection with these
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-- materials, including for any direct, or any indirect,
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-- special, incidental, or consequential loss or damage
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-- (including loss of data, profits, goodwill, or any type of
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-- loss or damage suffered as a result of any action brought
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-- by a third party) even if such damage or loss was
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-- reasonably foreseeable or Xilinx had been advised of the
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-- possibility of the same.
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--
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-- CRITICAL APPLICATIONS
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-- Xilinx products are not designed or intended to be fail-
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-- safe, or for use in any application requiring fail-safe
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-- performance, such as life-support or safety devices or
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-- systems, Class III medical devices, nuclear facilities,
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-- applications related to the deployment of airbags, or any
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-- other applications that could lead to death, personal
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-- injury, or severe property or environmental damage
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-- (individually and collectively, "Critical
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-- Applications"). Customer assumes the sole risk and
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-- liability of any use of Xilinx products in Critical
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-- Applications, subject only to applicable laws and
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-- regulations governing limitations on product liability.
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--
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-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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-- PART OF THIS FILE AT ALL TIMES.
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--
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-------------------------------------------------------------------------------
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-- Project    : Spartan-6 Integrated Block for PCI Express
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-- File       : pcie_brams_s6.vhd
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-- Description: BlockRAM module for Spartan-6 PCIe Block
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--
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--              Arranges and connects brams
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--              Implements address decoding, datapath muxing and
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--              pipeline stages
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--
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-------------------------------------------------------------------------------
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60
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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64
entity pcie_brams_s6 is
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  generic (
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    -- the number of BRAMs to use
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    -- supported values are:
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    -- 1,2,4,9
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    NUM_BRAMS           : integer := 0;
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    -- BRAM read address latency
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    --
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    -- value     meaning
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    -- ====================================================
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    --   0       BRAM read address port sample
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    --   1       BRAM read address port sample and a pipeline stage on the address port
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    RAM_RADDR_LATENCY   : integer := 1;
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    -- BRAM read data latency
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    --
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    -- value     meaning
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    -- ====================================================
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    --   1       no BRAM OREG
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    --   2       use BRAM OREG
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    --   3       use BRAM OREG and a pipeline stage on the data port
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    RAM_RDATA_LATENCY   : integer := 1;
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    -- BRAM write latency
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    -- The BRAM write port is synchronous
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    --
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    -- value     meaning
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    -- ====================================================
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    --   0       BRAM write port sample
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    --   1       BRAM write port sample plus pipeline stage
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    RAM_WRITE_LATENCY   : integer :=  1
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  );
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  port (
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    user_clk_i          : in std_logic;
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    reset_i             : in std_logic;
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    wen                 : in std_logic;
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    waddr               : in std_logic_vector(11 downto 0);
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    wdata               : in std_logic_vector(35 downto 0);
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    ren                 : in std_logic;
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    rce                 : in std_logic;
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    raddr               : in std_logic_vector(11 downto 0);
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    rdata               : out std_logic_vector(35 downto 0)
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  );
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end pcie_brams_s6;
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110
architecture rtl of pcie_brams_s6 is
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  constant TCQ : time := 1 ns;  -- Clock-to-out delay to be modeled
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  -- Turn on the bram output register
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  function CALC_DOB_REG(constant RAM_RDATA_LATENCY : in integer) return integer is
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    variable DOB_REG : integer;
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  begin
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    if   (RAM_RDATA_LATENCY > 1) then DOB_REG := 1;
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    else                              DOB_REG := 0;
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    end if;
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    return DOB_REG;
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  end function CALC_DOB_REG;
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124
  -- Calculate the data width of the individual BRAMs
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  function CALC_WIDTH(constant NUM_BRAMS : in integer) return integer is
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    variable WIDTH : integer;
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  begin
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    if    (NUM_BRAMS = 1) then WIDTH := 36;
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    elsif (NUM_BRAMS = 2) then WIDTH := 18;
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    elsif (NUM_BRAMS = 4) then WIDTH := 9;
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    else                       WIDTH := 4; -- NUM_BRAMS = 9
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    end if;
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    return WIDTH;
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  end function CALC_WIDTH;
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136
  component pcie_bram_s6 is
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  generic (
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    DOB_REG           : integer;
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    WIDTH             : integer
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  );
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  port (
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    user_clk_i : in std_logic;
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    reset_i    : in std_logic;
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    wen_i      : in std_logic;
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    waddr_i    : in std_logic_vector(11 downto 0);
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    wdata_i    : in std_logic_vector(CALC_WIDTH(NUM_BRAMS)-1 downto 0);
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    ren_i      : in std_logic;
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    rce_i      : in std_logic;
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    raddr_i    : in std_logic_vector(11 downto 0);
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    rdata_o    : out std_logic_vector(CALC_WIDTH(NUM_BRAMS)-1 downto 0) --  read data
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  );
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  end component;
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157
  -- Model the delays for RAM write latency
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  signal wen_int   : std_logic;
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  signal waddr_int : std_logic_vector(11 downto 0);
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  signal wdata_int : std_logic_vector(35 downto 0);
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162
  signal wen_dly   : std_logic;
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  signal waddr_dly : std_logic_vector(11 downto 0);
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  signal wdata_dly : std_logic_vector(35 downto 0);
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166
  -- Model the delays for RAM read latency
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  signal ren_int   : std_logic;
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  signal raddr_int : std_logic_vector(11 downto 0);
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  signal rdata_int : std_logic_vector(35 downto 0);
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171
  signal ren_dly   : std_logic;
172
  signal raddr_dly : std_logic_vector(11 downto 0);
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  signal rdata_dly : std_logic_vector(35 downto 0);
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175
begin
176
 
177
  --synthesis translate_off
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  process begin
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    case NUM_BRAMS is
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      when 1 | 2 | 4 | 9 =>
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        null;
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      when others =>
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        report "Error NUM_BRAMS size " & integer'image(NUM_BRAMS) & " is not supported." severity failure;
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    end case; -- case NUM_BRAMS
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    case RAM_RADDR_LATENCY is
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      when 0 | 1 =>
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        null;
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      when others =>
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        report "Error RAM_RADDR_LATENCY size " & integer'image(RAM_RADDR_LATENCY) & " is not supported." severity failure;
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    end case; -- case RAM_RADDR_LATENCY
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    case RAM_RDATA_LATENCY is
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      when 1 | 2 | 3 =>
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        null;
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      when others =>
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        report "Error RAM_RDATA_LATENCY size " & integer'image(RAM_RDATA_LATENCY) & " is not supported." severity failure;
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    end case; -- case RAM_RDATA_LATENCY
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    case RAM_WRITE_LATENCY is
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      when 0 | 1 =>
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        null;
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      when others =>
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        report "Error RAM_WRITE_LATENCY size " & integer'image(RAM_WRITE_LATENCY) & " is not supported." severity failure;
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    end case; -- case RAM_WRITE_LATENCY
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207
    wait;
208
  end process;
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  --synthesis translate_on
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211
  -- 1 stage RAM write pipeline
212
  wr_lat_1 : if(RAM_WRITE_LATENCY = 1) generate
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    process (user_clk_i) begin
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      if (user_clk_i'event and user_clk_i = '1') then
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         if (reset_i = '1') then
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           wen_dly   <= '0' after TCQ;
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           waddr_dly <= (others => '0') after TCQ;
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           wdata_dly <= (others => '0') after TCQ;
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         else
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           wen_dly   <= wen after TCQ;
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           waddr_dly <= waddr after TCQ;
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           wdata_dly <= wdata after TCQ;
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         end if;
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      end if;
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    end process;
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    wen_int <= wen_dly;
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    waddr_int <= waddr_dly;
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    wdata_int <= wdata_dly;
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  end generate wr_lat_1;
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  -- No RAM write pipeline
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  wr_lat_0 : if(RAM_WRITE_LATENCY /= 1) generate
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    wen_int   <= wen;
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    waddr_int <= waddr;
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    wdata_int <= wdata;
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  end generate wr_lat_0;
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  -- 1 stage RAM read addr pipeline
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  raddr_lat_1 : if(RAM_RADDR_LATENCY = 1) generate
242
    process (user_clk_i) begin
243
      if (user_clk_i'event and user_clk_i = '1') then
244
        if (reset_i = '1') then
245
          ren_dly   <= '0' after TCQ;
246
          raddr_dly <= (others => '0') after TCQ;
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        else
248
          ren_dly   <= ren after TCQ;
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          raddr_dly <= raddr after TCQ;
250
        end if;
251
      end if;
252
    end process;
253
 
254
    ren_int <= ren_dly;
255
    raddr_int <= raddr_dly;
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257
  end generate raddr_lat_1;
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  -- No RAM read addr pipeline
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  raddr_lat_0 : if(RAM_RADDR_LATENCY /= 1) generate
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    ren_int   <= ren after TCQ;
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    raddr_int <= raddr after TCQ;
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  end generate raddr_lat_0;
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  -- 3 stages RAM read data pipeline (first is internal to BRAM)
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  rdata_lat_3 : if(RAM_RDATA_LATENCY = 3) generate
267
    process (user_clk_i) begin
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      if (user_clk_i'event and user_clk_i = '1') then
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        if (reset_i = '1') then
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          rdata_dly <= (others => '0') after TCQ;
271
        else
272
          rdata_dly <= rdata_int after TCQ;
273
        end if;
274
      end if;
275
    end process;
276
 
277
    rdata <= rdata_dly;
278
 
279
  end generate rdata_lat_3;
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281
  -- 1 or 2 stages RAM read data pipeline
282
  rdata_lat_1_2 : if(RAM_RDATA_LATENCY /= 3) generate
283
    rdata <= rdata_int;
284
  end generate rdata_lat_1_2;
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286
  -- Instantiate BRAM(s)
287
  brams : for i in 0 to (NUM_BRAMS - 1) generate
288
  begin
289
    ram : pcie_bram_s6
290
    generic map (
291
      DOB_REG => CALC_DOB_REG(RAM_RDATA_LATENCY),
292
      WIDTH   => CALC_WIDTH(NUM_BRAMS)
293
    )
294
    port map (
295
      user_clk_i => user_clk_i,
296
      reset_i    => reset_i,
297
      wen_i      => wen_int,
298
      waddr_i    => waddr_int,
299
      wdata_i    => wdata_int((((i + 1) * CALC_WIDTH(NUM_BRAMS)) - 1) downto (i * CALC_WIDTH(NUM_BRAMS))),
300
      ren_i      => ren_int,
301
      rce_i      => rce,
302
      raddr_i    => raddr_int,
303
      rdata_o    => rdata_int((((i + 1) * CALC_WIDTH(NUM_BRAMS)) - 1) downto (i * CALC_WIDTH(NUM_BRAMS)))
304
    );
305
  end generate brams;
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307
end rtl;
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