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-------------------------------------------------------------------------------
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--
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-- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
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--
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-- This file contains confidential and proprietary information
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-- of Xilinx, Inc. and is protected under U.S. and
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-- international copyright and other intellectual property
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-- laws.
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--
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-- DISCLAIMER
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-- This disclaimer is not a license and does not grant any
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-- rights to the materials distributed herewith. Except as
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-- otherwise provided in a valid license issued to you by
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-- Xilinx, and to the maximum extent permitted by applicable
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-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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-- (2) Xilinx shall not be liable (whether in contract or tort,
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-- including negligence, or under any other theory of
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-- liability) for any loss or damage of any kind or nature
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-- related to, arising under or in connection with these
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-- materials, including for any direct, or any indirect,
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-- special, incidental, or consequential loss or damage
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-- (including loss of data, profits, goodwill, or any type of
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-- loss or damage suffered as a result of any action brought
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-- by a third party) even if such damage or loss was
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-- reasonably foreseeable or Xilinx had been advised of the
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-- possibility of the same.
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--
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-- CRITICAL APPLICATIONS
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-- Xilinx products are not designed or intended to be fail-
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-- safe, or for use in any application requiring fail-safe
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-- performance, such as life-support or safety devices or
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-- systems, Class III medical devices, nuclear facilities,
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-- applications related to the deployment of airbags, or any
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-- other applications that could lead to death, personal
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-- injury, or severe property or environmental damage
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-- (individually and collectively, "Critical
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-- Applications"). Customer assumes the sole risk and
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-- liability of any use of Xilinx products in Critical
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-- Applications, subject only to applicable laws and
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-- regulations governing limitations on product liability.
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--
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-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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-- PART OF THIS FILE AT ALL TIMES.
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--
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-------------------------------------------------------------------------------
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-- Project : Virtex-6 Integrated Block for PCI Express
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-- File : axi_basic_rx.vhd
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-- Version : 2.3
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-- Description:
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-- TRN to AXI RX module. Instantiates pipeline and null generator RX
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-- submodules.
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--
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-- Notes:
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-- Optional notes section.
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--
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-- Hierarchical:
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-- axi_basic_top
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-- axi_basic_rx
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--------------------------------------------------------------------------------
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-- Library Declarations
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--------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_unsigned.all;
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ENTITY axi_basic_rx IS
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GENERIC (
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C_DATA_WIDTH : INTEGER := 128; -- RX/TX interface data width
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C_FAMILY : STRING := "X7"; -- Targeted FPGA family
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C_ROOT_PORT : BOOLEAN := FALSE; -- PCIe block is in root port mode
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C_PM_PRIORITY : BOOLEAN := FALSE; -- Disable TX packet boundary thrtl
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TCQ : INTEGER := 1; -- Clock to Q time
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C_REM_WIDTH : INTEGER := 1; -- trem/rrem width
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C_STRB_WIDTH : INTEGER := 4 -- TSTRB width
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);
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PORT (
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-------------------------------------------------
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-- User Design I/O --
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-------------------------------------------------
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-- AXI RX
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-------------
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M_AXIS_RX_TDATA : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH - 1 DOWNTO 0):=(OTHERS=>'0'); -- RX data to user
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M_AXIS_RX_TVALID : OUT STD_LOGIC :='0'; -- RX data is valid
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M_AXIS_RX_TREADY : IN STD_LOGIC :='0'; -- RX ready for data
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M_AXIS_RX_TSTRB : OUT STD_LOGIC_VECTOR(C_STRB_WIDTH - 1 DOWNTO 0):=(OTHERS=>'0'); -- RX strobe byte enables
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M_AXIS_RX_TLAST : OUT STD_LOGIC :='0'; -- RX data is last
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M_AXIS_RX_TUSER : OUT STD_LOGIC_VECTOR(21 DOWNTO 0) :=(OTHERS=>'0'); -- RX user signals
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-------------------------------------------------
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-- PCIe Block I/O --
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-------------------------------------------------
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-- TRN RX
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-------------
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TRN_RD : IN STD_LOGIC_VECTOR(C_DATA_WIDTH - 1 DOWNTO 0) :=(OTHERS=>'0'); -- RX data from block
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TRN_RSOF : IN STD_LOGIC :='0'; -- RX start of packet
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TRN_REOF : IN STD_LOGIC :='0'; -- RX end of packet
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TRN_RSRC_RDY : IN STD_LOGIC :='0'; -- RX source ready
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TRN_RDST_RDY : OUT STD_LOGIC :='0'; -- RX destination ready
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TRN_RSRC_DSC : IN STD_LOGIC :='0'; -- RX source discontinue
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TRN_RREM : IN STD_LOGIC_VECTOR(C_REM_WIDTH - 1 DOWNTO 0) :=(OTHERS=>'0'); -- RX remainder
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TRN_RERRFWD : IN STD_LOGIC :='0'; -- RX error forward
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TRN_RBAR_HIT : IN STD_LOGIC_VECTOR(6 DOWNTO 0) :=(OTHERS=>'0'); -- RX BAR hit
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TRN_RECRC_ERR : IN STD_LOGIC :='0'; -- RX ECRC error
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-- System
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-------------
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NP_COUNTER : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) :=(OTHERS=>'0'); -- Non-posted counter
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USER_CLK : IN STD_LOGIC :='0'; -- user clock from block
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USER_RST : IN STD_LOGIC :='0' -- user reset from block
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);
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END axi_basic_rx;
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-------------------------------------------------
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-- RX Data Pipeline --
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-------------------------------------------------
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ARCHITECTURE TRANS OF axi_basic_rx IS
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SIGNAL null_rx_tvalid : STD_LOGIC;
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SIGNAL null_rx_tlast : STD_LOGIC;
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SIGNAL null_rx_tstrb : STD_LOGIC_VECTOR(C_STRB_WIDTH - 1 DOWNTO 0);
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SIGNAL null_rdst_rdy : STD_LOGIC;
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SIGNAL null_is_eof : STD_LOGIC_VECTOR(4 DOWNTO 0);
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-- Declare intermediate signals for referenced outputs
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SIGNAL m_axis_rx_tdata_xhdl0 : STD_LOGIC_VECTOR(C_DATA_WIDTH - 1 DOWNTO 0);
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SIGNAL m_axis_rx_tvalid_xhdl4 : STD_LOGIC;
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SIGNAL m_axis_rx_tstrb_xhdl2 : STD_LOGIC_VECTOR(C_STRB_WIDTH - 1 DOWNTO 0);
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SIGNAL m_axis_rx_tlast_xhdl1 : STD_LOGIC;
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SIGNAL m_axis_rx_tuser_xhdl3 : STD_LOGIC_VECTOR(21 DOWNTO 0);
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SIGNAL trn_rdst_rdy_xhdl6 : STD_LOGIC;
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SIGNAL np_counter_xhdl5 : STD_LOGIC_VECTOR(2 DOWNTO 0);
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COMPONENT axi_basic_rx_null_gen IS
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GENERIC (
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C_DATA_WIDTH : INTEGER := 128;
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TCQ : INTEGER := 1;
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C_STRB_WIDTH : INTEGER := 4
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);
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PORT (
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M_AXIS_RX_TDATA : IN STD_LOGIC_VECTOR(C_DATA_WIDTH - 1 DOWNTO 0) := (OTHERS=>'0');
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M_AXIS_RX_TVALID : IN STD_LOGIC := '0';
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M_AXIS_RX_TREADY : IN STD_LOGIC := '0';
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M_AXIS_RX_TLAST : IN STD_LOGIC := '0';
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M_AXIS_RX_TUSER : IN STD_LOGIC_VECTOR(21 DOWNTO 0) := (OTHERS=>'0');
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NULL_RX_TVALID : OUT STD_LOGIC := '0';
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NULL_RX_TLAST : OUT STD_LOGIC := '0';
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NULL_RX_TSTRB : OUT STD_LOGIC_VECTOR(C_STRB_WIDTH - 1 DOWNTO 0) := (OTHERS=>'0');
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NULL_RDST_RDY : OUT STD_LOGIC := '0';
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NULL_IS_EOF : OUT STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS=>'0');
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USER_CLK : IN STD_LOGIC := '0';
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USER_RST : IN STD_LOGIC := '0'
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);
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END COMPONENT axi_basic_rx_null_gen;
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-------------------------------------------------
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-- RX Data Pipeline --
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-------------------------------------------------
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COMPONENT axi_basic_rx_pipeline IS
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GENERIC (
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C_DATA_WIDTH : INTEGER := 128;
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C_FAMILY : STRING := "X7";
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TCQ : INTEGER := 1;
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C_REM_WIDTH : INTEGER := 1;
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C_STRB_WIDTH : INTEGER := 4
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);
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PORT (
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M_AXIS_RX_TDATA : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH - 1 DOWNTO 0) := (OTHERS=>'0');
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M_AXIS_RX_TVALID : OUT STD_LOGIC := '0';
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M_AXIS_RX_TREADY : IN STD_LOGIC := '0';
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M_AXIS_RX_TSTRB : OUT STD_LOGIC_VECTOR(C_STRB_WIDTH - 1 DOWNTO 0) := (OTHERS=>'0');
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M_AXIS_RX_TLAST : OUT STD_LOGIC := '0';
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M_AXIS_RX_TUSER : OUT STD_LOGIC_VECTOR(21 DOWNTO 0) := (OTHERS=>'0');
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TRN_RD : IN STD_LOGIC_VECTOR(C_DATA_WIDTH - 1 DOWNTO 0) := (OTHERS=>'0');
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TRN_RSOF : IN STD_LOGIC := '0';
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TRN_REOF : IN STD_LOGIC := '0';
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TRN_RSRC_RDY : IN STD_LOGIC := '0';
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TRN_RDST_RDY : OUT STD_LOGIC := '0';
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TRN_RSRC_DSC : IN STD_LOGIC := '0';
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TRN_RREM : IN STD_LOGIC_VECTOR(C_REM_WIDTH - 1 DOWNTO 0) := (OTHERS=>'0');
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TRN_RERRFWD : IN STD_LOGIC := '0';
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TRN_RBAR_HIT : IN STD_LOGIC_VECTOR(6 DOWNTO 0) := (OTHERS=>'0');
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TRN_RECRC_ERR : IN STD_LOGIC := '0';
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NULL_RX_TVALID : IN STD_LOGIC := '0';
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NULL_RX_TLAST : IN STD_LOGIC := '0';
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NULL_RX_TSTRB : IN STD_LOGIC_VECTOR(C_STRB_WIDTH - 1 DOWNTO 0) := (OTHERS=>'0') ;
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NULL_RDST_RDY : IN STD_LOGIC := '0';
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NULL_IS_EOF : IN STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS=>'0');
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NP_COUNTER : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) :=(OTHERS=>'0');
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USER_CLK : IN STD_LOGIC :='0';
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USER_RST : IN STD_LOGIC :='0'
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);
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END COMPONENT axi_basic_rx_pipeline;
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BEGIN
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-- Drive referenced outputs
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M_AXIS_RX_TDATA <= m_axis_rx_tdata_xhdl0;
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M_AXIS_RX_TVALID <= m_axis_rx_tvalid_xhdl4;
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M_AXIS_RX_TSTRB <= m_axis_rx_tstrb_xhdl2;
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M_AXIS_RX_TLAST <= m_axis_rx_tlast_xhdl1;
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M_AXIS_RX_TUSER <= m_axis_rx_tuser_xhdl3;
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TRN_RDST_RDY <= trn_rdst_rdy_xhdl6;
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NP_COUNTER <= np_counter_xhdl5;
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rx_pipeline_inst : axi_basic_rx_pipeline
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GENERIC MAP (
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C_DATA_WIDTH => C_DATA_WIDTH,
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C_FAMILY => C_FAMILY,
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TCQ => TCQ,
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C_REM_WIDTH => C_REM_WIDTH,
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C_STRB_WIDTH => C_STRB_WIDTH
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)
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PORT MAP (
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----------------------
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-- Outgoing AXI TX
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----------------------
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M_AXIS_RX_TDATA => m_axis_rx_tdata_xhdl0,
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M_AXIS_RX_TVALID => m_axis_rx_tvalid_xhdl4,
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M_AXIS_RX_TREADY => M_AXIS_RX_TREADY,
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M_AXIS_RX_TSTRB => m_axis_rx_tstrb_xhdl2,
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M_AXIS_RX_TLAST => m_axis_rx_tlast_xhdl1,
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M_AXIS_RX_TUSER => m_axis_rx_tuser_xhdl3,
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----------------------
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-- Incoming TRN RX
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----------------------
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TRN_RD => TRN_RD,
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TRN_RSOF => TRN_RSOF,
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TRN_REOF => TRN_REOF,
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TRN_RSRC_RDY => TRN_RSRC_RDY,
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TRN_RDST_RDY => trn_rdst_rdy_xhdl6,
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TRN_RSRC_DSC => TRN_RSRC_DSC,
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TRN_RREM => TRN_RREM,
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TRN_RERRFWD => TRN_RERRFWD,
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TRN_RBAR_HIT => TRN_RBAR_HIT,
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TRN_RECRC_ERR => TRN_RECRC_ERR,
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----------------------
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-- Null Inputs
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----------------------
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NULL_RX_TVALID => null_rx_tvalid,
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NULL_RX_TLAST => null_rx_tlast,
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NULL_RX_TSTRB => null_rx_tstrb,
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NULL_RDST_RDY => null_rdst_rdy,
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NULL_IS_EOF => null_is_eof,
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----------------------
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-- System
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----------------------
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NP_COUNTER => np_counter_xhdl5,
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USER_CLK => USER_CLK,
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USER_RST => USER_RST
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);
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rx_null_gen_inst : axi_basic_rx_null_gen
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GENERIC MAP (
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C_DATA_WIDTH => C_DATA_WIDTH,
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TCQ => TCQ,
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C_STRB_WIDTH => C_STRB_WIDTH
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)
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PORT MAP (
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----------------------
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-- Inputs
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----------------------
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M_AXIS_RX_TDATA => m_axis_rx_tdata_xhdl0,
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M_AXIS_RX_TVALID => m_axis_rx_tvalid_xhdl4,
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M_AXIS_RX_TREADY => M_AXIS_RX_TREADY,
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M_AXIS_RX_TLAST => m_axis_rx_tlast_xhdl1,
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M_AXIS_RX_TUSER => m_axis_rx_tuser_xhdl3,
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----------------------
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-- Null Outputs
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----------------------
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NULL_RX_TVALID => null_rx_tvalid,
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NULL_RX_TLAST => null_rx_tlast,
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NULL_RX_TSTRB => null_rx_tstrb,
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NULL_RDST_RDY => null_rdst_rdy,
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NULL_IS_EOF => null_is_eof,
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----------------------
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-- System
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----------------------
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USER_CLK => USER_CLK,
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USER_RST => USER_RST
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);
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|
305 |
|
|
END TRANS;
|