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-------------------------------------------------------------------------------
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--
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-- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
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--
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-- This file contains confidential and proprietary information
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-- of Xilinx, Inc. and is protected under U.S. and
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-- international copyright and other intellectual property
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-- laws.
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--
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-- DISCLAIMER
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-- This disclaimer is not a license and does not grant any
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-- rights to the materials distributed herewith. Except as
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-- otherwise provided in a valid license issued to you by
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-- Xilinx, and to the maximum extent permitted by applicable
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-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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-- (2) Xilinx shall not be liable (whether in contract or tort,
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-- including negligence, or under any other theory of
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-- liability) for any loss or damage of any kind or nature
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-- related to, arising under or in connection with these
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-- materials, including for any direct, or any indirect,
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-- special, incidental, or consequential loss or damage
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-- reasonably foreseeable or Xilinx had been advised of the
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-- possibility of the same.
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--
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-- CRITICAL APPLICATIONS
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-- Xilinx products are not designed or intended to be fail-
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-- safe, or for use in any application requiring fail-safe
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-- performance, such as life-support or safety devices or
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-- systems, Class III medical devices, nuclear facilities,
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-- applications related to the deployment of airbags, or any
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-- other applications that could lead to death, personal
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-- injury, or severe property or environmental damage
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-- (individually and collectively, "Critical
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-- Applications"). Customer assumes the sole risk and
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-- liability of any use of Xilinx products in Critical
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-- Applications, subject only to applicable laws and
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-- regulations governing limitations on product liability.
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--
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-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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-- PART OF THIS FILE AT ALL TIMES.
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--
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-------------------------------------------------------------------------------
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-- Project : Virtex-6 Integrated Block for PCI Express
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-- File : axi_basic_rx_null_gen.vhd
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-- Version : 2.3
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--
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-- Description:
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-- TRN to AXI RX null generator. Generates null packets for use in discontinue situations.
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--
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-- Notes:
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-- Optional notes section.
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--
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-- Hierarchical:
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-- axi_basic_top
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-- axi_basic_rx
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-- axi_basic_rx_null_gen
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--------------------------------------------------------------------------------
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-- Library Declarations
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--------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_unsigned.all;
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ENTITY axi_basic_rx_null_gen IS
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GENERIC (
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C_DATA_WIDTH : INTEGER := 128; -- RX/TX interface data width
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TCQ : INTEGER := 1; -- Clock to Q time
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C_STRB_WIDTH : INTEGER := 4 --TSTRB width
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);
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PORT (
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-- AXI RX
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M_AXIS_RX_TDATA : IN STD_LOGIC_VECTOR(C_DATA_WIDTH - 1 DOWNTO 0) :=(OTHERS=>'0'); -- RX data to user
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M_AXIS_RX_TVALID : IN STD_LOGIC :='0'; -- RX data is valid
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M_AXIS_RX_TREADY : IN STD_LOGIC :='0'; -- RX ready for data
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M_AXIS_RX_TLAST : IN STD_LOGIC :='0'; -- RX data is last
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M_AXIS_RX_TUSER : IN STD_LOGIC_VECTOR(21 DOWNTO 0) :=(OTHERS=>'0'); -- RX user signals
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-- Null Inputs
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NULL_RX_TVALID : OUT STD_LOGIC ; -- NULL generated tvalid
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NULL_RX_TLAST : OUT STD_LOGIC ; -- NULL generated tlast
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NULL_RX_TSTRB : OUT STD_LOGIC_VECTOR(C_STRB_WIDTH - 1 DOWNTO 0); -- NULL generated tstrb
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NULL_RDST_RDY : OUT STD_LOGIC ; -- NULL generated rdst_rdy
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NULL_IS_EOF : OUT STD_LOGIC_VECTOR(4 DOWNTO 0) ; -- NULL generated is_eof
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-- System
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USER_CLK : IN STD_LOGIC :='0';
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USER_RST : IN STD_LOGIC :='0'
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);
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END axi_basic_rx_null_gen;
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------------------------------------------------------------------------------//
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-- NULL packet gnereator state machine //
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-- This state machine shadows the TRN RX interface, tracking each packet as //
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-- it's passed to the AXI user. When a disountine is detected, the rx data //
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-- pipeline switches to a NULL packet and clocks that out instead. It does so //
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-- by asserting null_mux_sel, which the rx pipeline uses to mux in NULL vals. //
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------------------------------------------------------------------------------//
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ARCHITECTURE TRANS OF axi_basic_rx_null_gen IS
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-- INTERFACE_WIDTH_DWORDS = (C_DATA_WIDTH == 128) ? 11'd4 : (C_DATA_WIDTH == 64) ? 11'd2 : 11'd1;
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function if_wdt_dw (
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constant wdt : integer)
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return integer is
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variable dw : integer := 1;
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begin -- if_wdt_dw
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if (wdt = 128) then
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dw := 4;
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elsif (wdt = 64) then
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dw := 2;
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else
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dw := 1;
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end if;
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return dw;
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end if_wdt_dw;
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constant INTERFACE_WIDTH_DWORDS : integer := if_wdt_dw(C_DATA_WIDTH);
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constant IDLE : std_logic := '0';
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constant IN_PACKET : std_logic := '1';
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-- Signals for tracking a packet on the AXI interface
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SIGNAL reg_pkt_len_counter : STD_LOGIC_VECTOR(11 DOWNTO 0);
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SIGNAL pkt_len_counter : STD_LOGIC_VECTOR(11 DOWNTO 0);
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SIGNAL pkt_len_counter_dec : STD_LOGIC_VECTOR(11 DOWNTO 0);
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SIGNAL pkt_done : STD_LOGIC;
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SIGNAL new_pkt_len : STD_LOGIC_VECTOR(11 DOWNTO 0);
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SIGNAL payload_len : STD_LOGIC_VECTOR(9 DOWNTO 0);
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SIGNAL payload_len_tmp : STD_LOGIC_VECTOR(9 DOWNTO 0) := (others => '0');
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SIGNAL packet_fmt : STD_LOGIC_VECTOR(1 DOWNTO 0);
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SIGNAL packet_td : STD_LOGIC;
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SIGNAL packet_overhead : STD_LOGIC_VECTOR(3 DOWNTO 0);
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-- X-HDL generated signals`
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SIGNAL xhdl2 : STD_LOGIC_VECTOR(2 DOWNTO 0);
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SIGNAL reg_is_eof : STD_LOGIC_VECTOR(4 DOWNTO 0);
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SIGNAL xhdl5 : STD_LOGIC_VECTOR(1 DOWNTO 0);
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SIGNAL xhdl7 : STD_LOGIC_VECTOR(1 DOWNTO 0);
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--State machine variables and states
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SIGNAL next_state : STD_LOGIC;
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SIGNAL cur_state : STD_LOGIC;
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-- Declare intermediate signals for referenced outputs
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SIGNAL null_rx_tlast_xhdl0 : STD_LOGIC;
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-- Misc.
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SIGNAL eof_tstrb : STD_LOGIC_VECTOR(C_STRB_WIDTH - 1 DOWNTO 0);
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SIGNAL straddle_sof : STD_LOGIC;
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SIGNAL eof : STD_LOGIC;
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BEGIN
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-- Create signals to detect sof and eof situations. These signals vary depending
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-- on the data width.
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eof <= M_AXIS_RX_TUSER(21);
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SOF_EOF_128 : IF (C_DATA_WIDTH = 128) GENERATE
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straddle_sof <= '1' WHEN (M_AXIS_RX_TUSER(14 DOWNTO 13) = "11") ELSE '0';
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END GENERATE;
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SOF_EOF_64_32 : IF (C_DATA_WIDTH /= 128) GENERATE
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straddle_sof <= '0';
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END GENERATE;
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------------------------------------------------------------------------------//
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-- Calculate the length of the packet being presented on the RX interface. To //
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-- do so, we need the relevent packet fields that impact total packet length. //
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-- These are: //
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-- - Header length: obtained from bit 1 of FMT field in 1st DWORD of header //
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-- - Payload length: obtained from LENGTH field in 1st DWORD of header //
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-- - TLP digist: obtained from TD field in 1st DWORD of header //
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-- - Current data: the number of bytes that have already been presented //
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-- on the data interface //
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-- //
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-- packet length = header + payload + tlp digest - # of DWORDS already //
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-- transmitted //
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-- //
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-- packet_overhead is where we calculate everything except payload. //
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------------------------------------------------------------------------------//
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-- Drive referenced outputs
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NULL_RX_TLAST <= null_rx_tlast_xhdl0;
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XHDL1 : IF (C_DATA_WIDTH = 128) GENERATE
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packet_fmt <= M_AXIS_RX_TDATA(94 DOWNTO 93) WHEN ((straddle_sof) = '1') ELSE M_AXIS_RX_TDATA(30 DOWNTO 29);
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packet_td <= M_AXIS_RX_TDATA(79) WHEN (straddle_sof = '1') ELSE M_AXIS_RX_TDATA(15);
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payload_len_tmp <= M_AXIS_RX_TDATA(73 DOWNTO 64) WHEN (straddle_sof = '1') ELSE M_AXIS_RX_TDATA(9 DOWNTO 0);
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payload_len <= payload_len_tmp WHEN ((packet_fmt(1)) = '1') ELSE (others => '0');
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xhdl2 <= packet_fmt(0) & packet_td & straddle_sof;
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-- In 128-bit mode, the amount of data currently on the interface
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-- depends on whether we're straddling or not. If so, 2 DWORDs have been
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-- seen. If not, 4 DWORDs.
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PROCESS (xhdl2)
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BEGIN
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CASE xhdl2 IS
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WHEN "000" =>
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packet_overhead <= "0011" + "0000" - "0100";
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WHEN "001" =>
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packet_overhead <= "0011" + "0000" - "0010";
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WHEN "010" =>
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packet_overhead <= "0011" + "0001" - "0100";
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WHEN "011" =>
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packet_overhead <= "0011" + "0001" - "0010";
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WHEN "100" =>
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packet_overhead <= "0100" + "0000" - "0100";
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WHEN "101" =>
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packet_overhead <= "0100" + "0000" - "0010";
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WHEN "110" =>
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packet_overhead <= "0100" + "0001" - "0100";
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WHEN "111" =>
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packet_overhead <= "0100" + "0001" - "0010";
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WHEN OTHERS =>
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packet_overhead <= "0000" + "0000" - "0000";
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END CASE;
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END PROCESS;
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END GENERATE;
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XHDL4 : IF (C_DATA_WIDTH = 64) GENERATE
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packet_fmt <= M_AXIS_RX_TDATA(30 DOWNTO 29);
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packet_td <= M_AXIS_RX_TDATA(15);
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payload_len <= M_AXIS_RX_TDATA(9 DOWNTO 0) WHEN ((packet_fmt(1)) = '1') ELSE "0000000000";
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xhdl5 <= packet_fmt(0) & packet_td;
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-- 64-bit mode: no straddling, so always 2 DWORDs
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PROCESS (packet_fmt, packet_td,xhdl5)
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BEGIN
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CASE xhdl5 IS
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-- Header + TD - Data currently on interface
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WHEN "00" =>
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packet_overhead <= "0011" + "0000" - "0010";
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WHEN "01" =>
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packet_overhead <= "0011" + "0001" - "0010";
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WHEN "10" =>
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packet_overhead <= "0100" + "0000" - "0010";
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WHEN "11" =>
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packet_overhead <= "0100" + "0001" - "0010";
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WHEN OTHERS =>
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packet_overhead <= "0000" + "0000" - "0000";
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END CASE;
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END PROCESS;
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END GENERATE;
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XHDL6 : IF (C_DATA_WIDTH = 32) GENERATE
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packet_fmt <= M_AXIS_RX_TDATA(30 DOWNTO 29);
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packet_td <= M_AXIS_RX_TDATA(15);
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payload_len <= M_AXIS_RX_TDATA(9 DOWNTO 0) WHEN ((packet_fmt(1)) = '1') ELSE "0000000000";
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xhdl7 <= packet_fmt(0) & packet_td;
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-- 32-bit mode: no straddling, so always 1 DWORD
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PROCESS (packet_fmt, packet_td,xhdl7)
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BEGIN
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CASE xhdl7 IS
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WHEN "00" =>
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packet_overhead <= "0011" + "0000" - "0001";
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WHEN "01" =>
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packet_overhead <= "0011" + "0001" - "0001";
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WHEN "10" =>
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packet_overhead <= "0100" + "0000" - "0001";
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WHEN "11" =>
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packet_overhead <= "0100" + "0001" - "0001";
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WHEN OTHERS =>
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packet_overhead <= "0000" + "0000" - "0000";
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END CASE;
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END PROCESS;
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END GENERATE;
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--END GENERATE;
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-- Now calculate actual packet length, adding the packet overhead and the
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-- payload length. This is signed math, so sign-extend packet_overhead.
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-- NOTE: a payload length of zero means 1024 DW in the PCIe spec, but this behavior isn't supported in our block.
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new_pkt_len <= (packet_overhead(3) & packet_overhead(3) & packet_overhead(3) & packet_overhead(3) & packet_overhead(3) & packet_overhead(3) & packet_overhead(3) & packet_overhead(3) & packet_overhead(3) & packet_overhead(2 DOWNTO 0)) + ("00" & payload_len);
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-- Math signals needed in the state machine below. These are seperate wires to
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-- help ensure synthesis tools are smart about optimizing them.
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pkt_len_counter_dec <= reg_pkt_len_counter - INTERFACE_WIDTH_DWORDS;
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pkt_done <= '1' WHEN (reg_pkt_len_counter <= INTERFACE_WIDTH_DWORDS) ELSE '0';
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PROCESS (cur_state, M_AXIS_RX_TVALID, M_AXIS_RX_TREADY, eof, new_pkt_len, reg_pkt_len_counter, pkt_len_counter_dec)
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BEGIN
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CASE cur_state IS
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-- IDLE state: the interface is IDLE and we're waiting for a packet to
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-- start. If a packet starts, move to state IN_PACKET and begin tracking it as long as it's NOT
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-- a signle cycle packet (indicated by assertion of eof at packet start)
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WHEN IDLE =>
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IF ((M_AXIS_RX_TVALID = '1') and (M_AXIS_RX_TREADY = '1') and (eof = '0')) THEN next_state <= IN_PACKET;
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ELSE
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next_state <= IDLE;
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END IF;
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pkt_len_counter <= new_pkt_len;
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-- IN_PACKET: a multi -cycle packet is in progress and we're tracking it. We are
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-- in lock-step with the AXI interface decrementing our packet length
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-- tracking reg, and waiting for the packet to finish.
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305 |
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-- If packet finished and a new one starts, this is a straddle situation.
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306 |
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-- Next state is IN_PACKET (128-bit only).
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307 |
|
|
-- If the current packet is done, next state is IDLE.
|
308 |
|
|
-- Otherwise, next state is IN_PACKET.
|
309 |
|
|
WHEN IN_PACKET =>
|
310 |
|
|
-- Straddle packet
|
311 |
|
|
IF ((C_DATA_WIDTH = 128) AND straddle_sof = '1' AND M_AXIS_RX_TVALID = '1') THEN
|
312 |
|
|
pkt_len_counter <= new_pkt_len;
|
313 |
|
|
next_state <= IN_PACKET;
|
314 |
|
|
-- Current packet finished
|
315 |
|
|
ELSIF (M_AXIS_RX_TREADY = '1' AND pkt_done = '1') THEN
|
316 |
|
|
pkt_len_counter <= new_pkt_len;
|
317 |
|
|
next_state <= IDLE ;
|
318 |
|
|
|
319 |
|
|
ELSE
|
320 |
|
|
IF (M_AXIS_RX_TREADY = '1') THEN
|
321 |
|
|
-- Packet in progress
|
322 |
|
|
pkt_len_counter <= pkt_len_counter_dec;
|
323 |
|
|
ELSE
|
324 |
|
|
-- Throttled
|
325 |
|
|
pkt_len_counter <= reg_pkt_len_counter;
|
326 |
|
|
END IF;
|
327 |
|
|
|
328 |
|
|
next_state <= IN_PACKET;
|
329 |
|
|
END IF;
|
330 |
|
|
WHEN OTHERS =>
|
331 |
|
|
pkt_len_counter <= reg_pkt_len_counter;
|
332 |
|
|
next_state <= IDLE ;
|
333 |
|
|
END CASE;
|
334 |
|
|
END PROCESS;
|
335 |
|
|
|
336 |
|
|
--Synchronous NULL packet generator state machine logic
|
337 |
|
|
PROCESS (USER_CLK)
|
338 |
|
|
BEGIN
|
339 |
|
|
IF (USER_CLK'EVENT AND USER_CLK = '1') THEN
|
340 |
|
|
IF (USER_RST = '1') THEN
|
341 |
|
|
cur_state <= IDLE AFTER (TCQ)*1 ps;
|
342 |
|
|
reg_pkt_len_counter <= (others => '0') AFTER (TCQ)*1 ps;
|
343 |
|
|
ELSE
|
344 |
|
|
cur_state <= next_state AFTER (TCQ)*1 ps;
|
345 |
|
|
reg_pkt_len_counter <= pkt_len_counter AFTER (TCQ)*1 ps;
|
346 |
|
|
END IF;
|
347 |
|
|
END IF;
|
348 |
|
|
END PROCESS;
|
349 |
|
|
|
350 |
|
|
--Generate TSTRB/is_eof for an end-of-packet situation.
|
351 |
|
|
XHDL8 : IF (C_DATA_WIDTH = 128) GENERATE
|
352 |
|
|
-- Assign null_is_eof depending on how many DWORDs are left in the packet.
|
353 |
|
|
PROCESS (pkt_len_counter)
|
354 |
|
|
BEGIN
|
355 |
|
|
CASE pkt_len_counter IS
|
356 |
|
|
WHEN "000000000001" =>
|
357 |
|
|
null_is_eof <= "10011";
|
358 |
|
|
WHEN "000000000010" =>
|
359 |
|
|
null_is_eof <= "10111";
|
360 |
|
|
WHEN "000000000011" =>
|
361 |
|
|
null_is_eof <= "11011";
|
362 |
|
|
WHEN "000000000100" =>
|
363 |
|
|
null_is_eof <= "11111";
|
364 |
|
|
WHEN OTHERS =>
|
365 |
|
|
null_is_eof <= "00011";
|
366 |
|
|
END CASE;
|
367 |
|
|
END PROCESS;
|
368 |
|
|
|
369 |
|
|
--TSTRB not used in 128-bit interface
|
370 |
|
|
eof_tstrb <= (others => '0') ; --'0' & '0' & '0' & '0';
|
371 |
|
|
END GENERATE;
|
372 |
|
|
|
373 |
|
|
XHDL9 : IF (NOT(C_DATA_WIDTH = 128)) GENERATE
|
374 |
|
|
XHDL10 : IF (C_DATA_WIDTH = 64) GENERATE
|
375 |
|
|
-- Assign null_is_eof depending on how many DWORDs are left in the packet.
|
376 |
|
|
PROCESS (pkt_len_counter)
|
377 |
|
|
BEGIN
|
378 |
|
|
CASE pkt_len_counter IS
|
379 |
|
|
WHEN "000000000001" =>
|
380 |
|
|
null_is_eof <= "10011";
|
381 |
|
|
WHEN "000000000010" =>
|
382 |
|
|
null_is_eof <= "10111";
|
383 |
|
|
WHEN OTHERS =>
|
384 |
|
|
null_is_eof <= "00011";
|
385 |
|
|
END CASE;
|
386 |
|
|
END PROCESS;
|
387 |
|
|
|
388 |
|
|
-- Assign TSTRB to 0xFF or 0x0F depending on how many DWORDs are left in the current packet.
|
389 |
|
|
eof_tstrb <= X"FF" WHEN (pkt_len_counter = "000000000010") ELSE X"0F";
|
390 |
|
|
END GENERATE;
|
391 |
|
|
|
392 |
|
|
XHDL11 : IF (NOT(C_DATA_WIDTH = 64)) GENERATE
|
393 |
|
|
PROCESS (pkt_len_counter)
|
394 |
|
|
BEGIN
|
395 |
|
|
--is_eof is either on or off in 32-bit interface
|
396 |
|
|
IF (pkt_len_counter = "000000000001") THEN
|
397 |
|
|
null_is_eof <= "10011";
|
398 |
|
|
ELSE
|
399 |
|
|
null_is_eof <= "10011";
|
400 |
|
|
END IF;
|
401 |
|
|
END PROCESS;
|
402 |
|
|
|
403 |
|
|
--The entire DWORD is always valid in 32-bit mode, so TSTRB is always 0xF
|
404 |
|
|
eof_tstrb <= "1111";
|
405 |
|
|
END GENERATE;
|
406 |
|
|
END GENERATE;
|
407 |
|
|
|
408 |
|
|
--Finally, use everything we've generated to calculate our NULL outputs
|
409 |
|
|
NULL_RX_TVALID <= '1';
|
410 |
|
|
null_rx_tlast_xhdl0 <= '1' WHEN (pkt_len_counter <= INTERFACE_WIDTH_DWORDS) ELSE '0' ;
|
411 |
|
|
NULL_RX_TSTRB <= eof_tstrb WHEN (null_rx_tlast_xhdl0 = '1') ELSE (others => '1');
|
412 |
|
|
NULL_RDST_RDY <= null_rx_tlast_xhdl0 ;
|
413 |
|
|
END TRANS;
|
414 |
|
|
|
415 |
|
|
|