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[/] [pcie_ds_dma/] [trunk/] [core/] [ds_dma64/] [pcie_src/] [pcie_core64_m1/] [source_virtex6/] [axi_basic_top.vhd] - Blame information for rev 2

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-------------------------------------------------------------------------------
2
--
3
-- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
4
--
5
-- This file contains confidential and proprietary information
6
-- of Xilinx, Inc. and is protected under U.S. and
7
-- international copyright and other intellectual property
8
-- laws.
9
--
10
-- DISCLAIMER
11
-- This disclaimer is not a license and does not grant any
12
-- rights to the materials distributed herewith. Except as
13
-- otherwise provided in a valid license issued to you by
14
-- Xilinx, and to the maximum extent permitted by applicable
15
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
16
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
17
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
18
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
19
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
20
-- (2) Xilinx shall not be liable (whether in contract or tort,
21
-- including negligence, or under any other theory of
22
-- liability) for any loss or damage of any kind or nature
23
-- related to, arising under or in connection with these
24
-- materials, including for any direct, or any indirect,
25
-- special, incidental, or consequential loss or damage
26
-- (including loss of data, profits, goodwill, or any type of
27
-- loss or damage suffered as a result of any action brought
28
-- by a third party) even if such damage or loss was
29
-- reasonably foreseeable or Xilinx had been advised of the
30
-- possibility of the same.
31
--
32
-- CRITICAL APPLICATIONS
33
-- Xilinx products are not designed or intended to be fail-
34
-- safe, or for use in any application requiring fail-safe
35
-- performance, such as life-support or safety devices or
36
-- systems, Class III medical devices, nuclear facilities,
37
-- applications related to the deployment of airbags, or any
38
-- other applications that could lead to death, personal
39
-- injury, or severe property or environmental damage
40
-- (individually and collectively, "Critical
41
-- Applications"). Customer assumes the sole risk and
42
-- liability of any use of Xilinx products in Critical
43
-- Applications, subject only to applicable laws and
44
-- regulations governing limitations on product liability.
45
--
46
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
47
-- PART OF THIS FILE AT ALL TIMES.
48
--
49
-------------------------------------------------------------------------------
50
-- Project    : Virtex-6 Integrated Block for PCI Express
51
-- File       : axi_basic_top.vhd
52
-- Version    : 2.3
53
--
54
-- Description:
55
--  TRN/AXI4-S Bridge top level module. Instantiates RX and TX modules.
56
--
57
--  Notes:
58
--  Optional notes section.
59
--
60
--  Hierarchical:
61
--    axi_basic_top
62
--------------------------------------------------------------------------------
63
-- Library Declarations
64
--------------------------------------------------------------------------------
65
 
66
LIBRARY ieee;
67
   USE ieee.std_logic_1164.all;
68
   USE ieee.std_logic_unsigned.all;
69
 
70
 
71
ENTITY axi_basic_top IS
72
   GENERIC (
73
      C_DATA_WIDTH              : INTEGER := 128;     -- RX/TX interface data width
74
      C_FAMILY                  : STRING := "X7";    -- Targeted FPGA family
75
      C_ROOT_PORT               : BOOLEAN := FALSE; -- PCIe block is in root port mode
76
      C_PM_PRIORITY             : BOOLEAN := FALSE; -- Disable TX packet boundary thrtl
77
      TCQ                       : INTEGER := 1;      -- Clock to Q time
78
 
79
      C_REM_WIDTH               : INTEGER := 1;      -- trem/rrem width
80
      C_STRB_WIDTH              : INTEGER := 4       -- TSTRB width
81
   );
82
   PORT (
83
      -----------------------------------------------
84
      -- User Design I/O
85
      -----------------------------------------------
86
 
87
      -- AXI TX
88
      -------------
89
      s_axis_tx_tdata         : IN STD_LOGIC_VECTOR(C_DATA_WIDTH - 1 DOWNTO 0) := (OTHERS=>'0');
90
      s_axis_tx_tvalid        : IN STD_LOGIC                                   := '0';
91
      s_axis_tx_tready        : OUT STD_LOGIC                                  := '0';
92
      s_axis_tx_tstrb         : IN STD_LOGIC_VECTOR(C_STRB_WIDTH - 1 DOWNTO 0) := (OTHERS=>'0');
93
      s_axis_tx_tlast         : IN STD_LOGIC                                   := '0';
94
      s_axis_tx_tuser         : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS=>'0');
95
 
96
      -- AXI RX
97
      -------------
98
      m_axis_rx_tdata         : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH - 1 DOWNTO 0) := (OTHERS=>'0');
99
      m_axis_rx_tvalid        : OUT STD_LOGIC                                   := '0';
100
      m_axis_rx_tready        : IN STD_LOGIC                                    := '0';
101
      m_axis_rx_tstrb         : OUT STD_LOGIC_VECTOR(C_STRB_WIDTH - 1 DOWNTO 0) := (OTHERS=>'0');
102
      m_axis_rx_tlast         : OUT STD_LOGIC                                   := '0';
103
      m_axis_rx_tuser         : OUT STD_LOGIC_VECTOR(21 DOWNTO 0) := (OTHERS=>'0');
104
 
105
      -- User Misc.
106
      -------------
107
      user_turnoff_ok         : IN STD_LOGIC                                   := '0';
108
      user_tcfg_gnt           : IN STD_LOGIC                                   := '0';
109
 
110
      -----------------------------------------------
111
      -- PCIe Block I/O
112
      -----------------------------------------------
113
 
114
      -- TRN TX
115
      -------------
116
      trn_td                  : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH - 1 DOWNTO 0) := (OTHERS=>'0');
117
      trn_tsof                : OUT STD_LOGIC                                   := '0';
118
      trn_teof                : OUT STD_LOGIC                                   := '0';
119
      trn_tsrc_rdy            : OUT STD_LOGIC                                   := '0';
120
      trn_tdst_rdy            : IN STD_LOGIC                                    := '0';
121
      trn_tsrc_dsc            : OUT STD_LOGIC                                   := '0';
122
      trn_trem                : OUT STD_LOGIC_VECTOR(C_REM_WIDTH - 1 DOWNTO 0)  := (OTHERS=>'0');
123
      trn_terrfwd             : OUT STD_LOGIC                                   := '0';
124
      trn_tstr                : OUT STD_LOGIC                                   := '0';
125
      trn_tbuf_av             : IN STD_LOGIC_VECTOR(5 DOWNTO 0)                 := (OTHERS=>'0');
126
      trn_tecrc_gen           : OUT STD_LOGIC                                   := '0';
127
 
128
      -- TRN RX
129
      -------------
130
      trn_rd                  : IN STD_LOGIC_VECTOR(C_DATA_WIDTH - 1 DOWNTO 0) := (OTHERS=>'0');
131
      trn_rsof                : IN STD_LOGIC                                   := '0';
132
      trn_reof                : IN STD_LOGIC                                   := '0';
133
      trn_rsrc_rdy            : IN STD_LOGIC                                   := '0';
134
      trn_rdst_rdy            : OUT STD_LOGIC                                  := '0';
135
      trn_rsrc_dsc            : IN STD_LOGIC                                   := '0';
136
      trn_rrem                : IN STD_LOGIC_VECTOR(C_REM_WIDTH - 1 DOWNTO 0)  := (OTHERS=>'0');
137
      trn_rerrfwd             : IN STD_LOGIC                                   := '0';
138
      trn_rbar_hit            : IN STD_LOGIC_VECTOR(6 DOWNTO 0)                := (OTHERS=>'0');
139
      trn_recrc_err           : IN STD_LOGIC                                   := '0';
140
 
141
      -- TRN Misc.
142
      -------------
143
      trn_tcfg_req            : IN STD_LOGIC                                   := '0';
144
      trn_tcfg_gnt            : OUT STD_LOGIC                                  := '0';
145
      trn_lnk_up              : IN STD_LOGIC                                   := '0';
146
 
147
      -- 7 Series/Virtex6 PM
148
      -------------
149
      cfg_pcie_link_state     : IN STD_LOGIC_VECTOR(2 DOWNTO 0)                := (OTHERS=>'0');
150
 
151
      -- Virtex6 PM
152
      -------------
153
      cfg_pm_send_pme_to      : IN STD_LOGIC                                   := '0';
154
      cfg_pmcsr_powerstate    : IN STD_LOGIC_VECTOR(1 DOWNTO 0)                := (OTHERS=>'0');
155
      trn_rdllp_data          : IN STD_LOGIC_VECTOR(31 DOWNTO 0)               := (OTHERS=>'0');
156
      trn_rdllp_src_rdy       : IN STD_LOGIC                                   := '0';
157
 
158
      -- Virtex6/Spartan6 PM
159
      -------------
160
      cfg_to_turnoff          : IN STD_LOGIC                                   := '0';
161
      cfg_turnoff_ok          : OUT STD_LOGIC                                  := '0';
162
 
163
      np_counter              : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)               := (OTHERS=>'0');
164
      user_clk                : IN STD_LOGIC                                   := '0';
165
      user_rst                : IN STD_LOGIC                                   := '0'
166
   );
167
END axi_basic_top;
168
 
169
 
170
-----------------------------------------------
171
-- RX Data Pipeline
172
-----------------------------------------------
173
 
174
ARCHITECTURE trans OF axi_basic_top IS
175
   COMPONENT axi_basic_rx IS
176
      GENERIC (
177
         C_DATA_WIDTH              : INTEGER := 128;
178
         C_FAMILY                  : STRING := "X7";
179
         C_ROOT_PORT               : BOOLEAN := FALSE;
180
         C_PM_PRIORITY             : BOOLEAN := FALSE;
181
         TCQ                       : INTEGER := 1;
182
         C_REM_WIDTH               : INTEGER := 1;
183
         C_STRB_WIDTH              : INTEGER := 4
184
      );
185
      PORT (
186
 
187
         -- Outgoing AXI TX
188
         -------------
189
         M_AXIS_RX_TDATA         : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH - 1 DOWNTO 0) := (OTHERS=>'0');
190
         M_AXIS_RX_TVALID        : OUT STD_LOGIC                                   := '0';
191
         M_AXIS_RX_TREADY        : IN STD_LOGIC                                    := '0';
192
         M_AXIS_RX_TSTRB         : OUT STD_LOGIC_VECTOR(C_STRB_WIDTH - 1 DOWNTO 0) := (OTHERS=>'0');
193
         M_AXIS_RX_TLAST         : OUT STD_LOGIC                                   := '0';
194
         M_AXIS_RX_TUSER         : OUT STD_LOGIC_VECTOR(21 DOWNTO 0) := (OTHERS=>'0');
195
 
196
         -- Incoming TRN RX
197
        -------------
198
         TRN_RD                  : IN STD_LOGIC_VECTOR(C_DATA_WIDTH - 1 DOWNTO 0) := (OTHERS=>'0');
199
         TRN_RSOF                : IN STD_LOGIC                                   := '0';
200
         TRN_REOF                : IN STD_LOGIC                                   := '0';
201
         TRN_RSRC_RDY            : IN STD_LOGIC                                   := '0';
202
         TRN_RDST_RDY            : OUT STD_LOGIC                                  := '0';
203
         TRN_RSRC_DSC            : IN STD_LOGIC                                   := '0';
204
         TRN_RREM                : IN STD_LOGIC_VECTOR(C_REM_WIDTH - 1 DOWNTO 0)  := (OTHERS=>'0');
205
         TRN_RERRFWD             : IN STD_LOGIC                                   := '0';
206
         TRN_RBAR_HIT            : IN STD_LOGIC_VECTOR(6 DOWNTO 0)                := (OTHERS=>'0');
207
         TRN_RECRC_ERR           : IN STD_LOGIC                                   := '0';
208
 
209
         -- System
210
         -------------
211
         NP_COUNTER              : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)               := (OTHERS=>'0');
212
         USER_CLK                : IN STD_LOGIC                                   := '0';
213
         USER_RST                : IN STD_LOGIC                                   := '0'
214
      );
215
   END COMPONENT;
216
 
217
    -----------------------------------------------
218
    -- TX Data Pipeline
219
    -----------------------------------------------
220
   COMPONENT axi_basic_tx IS
221
   GENERIC (
222
      C_DATA_WIDTH            : INTEGER := 128;
223
      C_FAMILY                : STRING := "X7";
224
      C_ROOT_PORT             : BOOLEAN := FALSE;
225
      C_PM_PRIORITY           : BOOLEAN := FALSE;
226
      TCQ                     : INTEGER := 1;
227
 
228
      C_REM_WIDTH               : INTEGER :=  1;
229
      C_STRB_WIDTH              : INTEGER :=  4
230
   );
231
   PORT (
232
      -- Incoming AXI RX
233
      -------------
234
      S_AXIS_TX_TDATA         : IN STD_LOGIC_VECTOR(C_DATA_WIDTH - 1 DOWNTO 0) := (OTHERS=>'0');
235
      S_AXIS_TX_TVALID        : IN STD_LOGIC                                   := '0';
236
      S_AXIS_TX_TREADY        : OUT STD_LOGIC                                  := '0';
237
      S_AXIS_TX_TSTRB         : IN STD_LOGIC_VECTOR(C_STRB_WIDTH - 1 DOWNTO 0) := (OTHERS=>'0');
238
      S_AXIS_TX_TLAST         : IN STD_LOGIC                                   := '0';
239
      S_AXIS_TX_TUSER         : IN STD_LOGIC_VECTOR(3 DOWNTO 0)                := (OTHERS=>'0');
240
 
241
      -- User Misc.
242
      -------------
243
      USER_TURNOFF_OK         : IN STD_LOGIC                                   := '0';
244
      USER_TCFG_GNT           : IN STD_LOGIC                                   := '0';
245
 
246
      -- Outgoing TRN TX
247
      -------------
248
      TRN_TD                  : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH - 1 DOWNTO 0) := (OTHERS=>'0');
249
      TRN_TSOF                : OUT STD_LOGIC                                   := '0';
250
      TRN_TEOF                : OUT STD_LOGIC                                   := '0';
251
      TRN_TSRC_RDY            : OUT STD_LOGIC                                   := '0';
252
      TRN_TDST_RDY            : IN STD_LOGIC                                    := '0';
253
      TRN_TSRC_DSC            : OUT STD_LOGIC;
254
      TRN_TREM                : OUT STD_LOGIC_VECTOR(C_REM_WIDTH - 1 DOWNTO 0) := (OTHERS=>'0');
255
      TRN_TERRFWD             : OUT STD_LOGIC                                   := '0';
256
      TRN_TSTR                : OUT STD_LOGIC                                   := '0';
257
      TRN_TBUF_AV             : IN STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS=>'0');
258
      TRN_TECRC_GEN           : OUT STD_LOGIC                                   := '0';
259
 
260
      -- TRN Misc.
261
      -------------
262
      TRN_TCFG_REQ            : IN STD_LOGIC                                   := '0';
263
      TRN_TCFG_GNT            : OUT STD_LOGIC                                  := '0';
264
      TRN_LNK_UP              : IN STD_LOGIC                                   := '0';
265
 
266
      -- 7 Series/Virtex6 PM
267
      -------------
268
      CFG_PCIE_LINK_STATE     : IN STD_LOGIC_VECTOR(2 DOWNTO 0)                := (OTHERS=>'0');
269
 
270
      -- Virtex6 PM
271
      -------------
272
      CFG_PM_SEND_PME_TO      : IN STD_LOGIC                                   := '0';
273
      CFG_PMCSR_POWERSTATE    : IN STD_LOGIC_VECTOR(1 DOWNTO 0)                := (OTHERS=>'0');
274
      TRN_RDLLP_DATA          : IN STD_LOGIC_VECTOR(31 DOWNTO 0)               := (OTHERS=>'0');
275
      TRN_RDLLP_SRC_RDY       : IN STD_LOGIC;
276
 
277
      -- Spartan6 PM
278
      -------------
279
      CFG_TO_TURNOFF          : IN STD_LOGIC                                    := '0';
280
      CFG_TURNOFF_OK          : OUT STD_LOGIC                                   := '0';
281
 
282
      -- System
283
      -------------
284
      USER_CLK                : IN STD_LOGIC                                    := '0';
285
      USER_RST                : IN STD_LOGIC                                    := '0'
286
   );
287
END COMPONENT axi_basic_tx;
288
 
289
 
290
BEGIN
291
 
292
   rx_inst : axi_basic_rx
293
      GENERIC MAP (
294
         C_DATA_WIDTH  => C_DATA_WIDTH,
295
         TCQ           => TCQ,
296
         C_FAMILY      => C_FAMILY,
297
         C_REM_WIDTH   => C_REM_WIDTH,
298
         C_STRB_WIDTH  => C_STRB_WIDTH
299
      )
300
      PORT MAP (
301
 
302
         M_AXIS_RX_TDATA   => m_axis_rx_tdata,
303
         M_AXIS_RX_TVALID  => m_axis_rx_tvalid,
304
         M_AXIS_RX_TREADY  => m_axis_rx_tready,
305
         M_AXIS_RX_TSTRB   => m_axis_rx_tstrb,
306
         M_AXIS_RX_TLAST   => m_axis_rx_tlast,
307
         M_AXIS_RX_TUSER   => m_axis_rx_tuser,
308
 
309
         TRN_RD            => trn_rd,
310
         TRN_RSOF          => trn_rsof,
311
         TRN_REOF          => trn_reof,
312
         TRN_RSRC_RDY      => trn_rsrc_rdy,
313
         TRN_RDST_RDY      => trn_rdst_rdy,
314
         TRN_RSRC_DSC      => trn_rsrc_dsc,
315
         TRN_RREM          => trn_rrem,
316
         TRN_RERRFWD       => trn_rerrfwd,
317
         TRN_RBAR_HIT      => trn_rbar_hit,
318
         TRN_RECRC_ERR     => trn_recrc_err,
319
 
320
         NP_COUNTER        => np_counter,
321
         USER_CLK          => user_clk,
322
         USER_RST          => user_rst
323
      );
324
 
325
   tx_inst : axi_basic_tx
326
      GENERIC MAP (
327
         C_DATA_WIDTH      => C_DATA_WIDTH,
328
         C_FAMILY          => C_FAMILY,
329
         C_ROOT_PORT       => C_ROOT_PORT,
330
         C_PM_PRIORITY     => C_PM_PRIORITY,
331
         TCQ               => TCQ,
332
         C_REM_WIDTH       => C_REM_WIDTH,
333
         C_STRB_WIDTH      => C_STRB_WIDTH
334
      )
335
      PORT MAP (
336
 
337
         S_AXIS_TX_TDATA       => s_axis_tx_tdata,
338
         S_AXIS_TX_TVALID      => s_axis_tx_tvalid,
339
         S_AXIS_TX_TREADY      => s_axis_tx_tready,
340
         S_AXIS_TX_TSTRB       => s_axis_tx_tstrb,
341
         S_AXIS_TX_TLAST       => s_axis_tx_tlast,
342
         S_AXIS_TX_TUSER       => s_axis_tx_tuser,
343
 
344
         USER_TURNOFF_OK       => user_turnoff_ok,
345
         USER_TCFG_GNT         => user_tcfg_gnt,
346
 
347
         TRN_TD                => trn_td,
348
         TRN_TSOF              => trn_tsof,
349
         TRN_TEOF              => trn_teof,
350
         TRN_TSRC_RDY          => trn_tsrc_rdy,
351
         TRN_TDST_RDY          => trn_tdst_rdy,
352
         TRN_TSRC_DSC          => trn_tsrc_dsc,
353
         TRN_TREM              => trn_trem,
354
         TRN_TERRFWD           => trn_terrfwd,
355
         TRN_TSTR              => trn_tstr,
356
         TRN_TBUF_AV           => trn_tbuf_av,
357
         TRN_TECRC_GEN         => trn_tecrc_gen,
358
 
359
         TRN_TCFG_REQ          => trn_tcfg_req,
360
         TRN_TCFG_GNT          => trn_tcfg_gnt,
361
         TRN_LNK_UP            => trn_lnk_up,
362
 
363
         CFG_PCIE_LINK_STATE   => cfg_pcie_link_state,
364
 
365
         CFG_PM_SEND_PME_TO    => cfg_pm_send_pme_to,
366
         CFG_PMCSR_POWERSTATe  => cfg_pmcsr_powerstate,
367
         TRN_RDLLP_DATA        => trn_rdllp_data,
368
         TRN_RDLLP_SRC_RDY     => trn_rdllp_src_rdy,
369
 
370
         CFG_TO_TURNOFF        => cfg_to_turnoff,
371
         CFG_TURNOFF_OK        => cfg_turnoff_ok,
372
 
373
         USER_CLK              => user_clk,
374
         USER_RST              => user_rst
375
      );
376
 
377
END trans;
378
 
379
 

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