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-------------------------------------------------------------------------------
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--
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-- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
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--
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-- This file contains confidential and proprietary information
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-- of Xilinx, Inc. and is protected under U.S. and
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-- international copyright and other intellectual property
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-- laws.
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--
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-- DISCLAIMER
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-- This disclaimer is not a license and does not grant any
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-- rights to the materials distributed herewith. Except as
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-- otherwise provided in a valid license issued to you by
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-- Xilinx, and to the maximum extent permitted by applicable
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-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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-- (2) Xilinx shall not be liable (whether in contract or tort,
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-- including negligence, or under any other theory of
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-- liability) for any loss or damage of any kind or nature
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-- related to, arising under or in connection with these
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-- materials, including for any direct, or any indirect,
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-- special, incidental, or consequential loss or damage
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-- (including loss of data, profits, goodwill, or any type of
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-- loss or damage suffered as a result of any action brought
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-- by a third party) even if such damage or loss was
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-- reasonably foreseeable or Xilinx had been advised of the
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-- possibility of the same.
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--
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-- CRITICAL APPLICATIONS
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-- Xilinx products are not designed or intended to be fail-
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-- safe, or for use in any application requiring fail-safe
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-- performance, such as life-support or safety devices or
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-- systems, Class III medical devices, nuclear facilities,
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-- applications related to the deployment of airbags, or any
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-- other applications that could lead to death, personal
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-- injury, or severe property or environmental damage
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-- (individually and collectively, "Critical
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-- Applications"). Customer assumes the sole risk and
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-- liability of any use of Xilinx products in Critical
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-- Applications, subject only to applicable laws and
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-- regulations governing limitations on product liability.
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--
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-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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-- PART OF THIS FILE AT ALL TIMES.
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--
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-------------------------------------------------------------------------------
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-- Project : Virtex-6 Integrated Block for PCI Express
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-- File : axi_basic_top.vhd
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-- Version : 2.3
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--
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-- Description:
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-- TRN/AXI4-S Bridge top level module. Instantiates RX and TX modules.
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--
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-- Notes:
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-- Optional notes section.
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--
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-- Hierarchical:
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-- axi_basic_top
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--------------------------------------------------------------------------------
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-- Library Declarations
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--------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_unsigned.all;
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ENTITY axi_basic_top IS
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GENERIC (
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C_DATA_WIDTH : INTEGER := 128; -- RX/TX interface data width
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C_FAMILY : STRING := "X7"; -- Targeted FPGA family
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C_ROOT_PORT : BOOLEAN := FALSE; -- PCIe block is in root port mode
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C_PM_PRIORITY : BOOLEAN := FALSE; -- Disable TX packet boundary thrtl
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TCQ : INTEGER := 1; -- Clock to Q time
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C_REM_WIDTH : INTEGER := 1; -- trem/rrem width
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C_STRB_WIDTH : INTEGER := 4 -- TSTRB width
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);
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PORT (
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-----------------------------------------------
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-- User Design I/O
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-----------------------------------------------
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-- AXI TX
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-------------
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s_axis_tx_tdata : IN STD_LOGIC_VECTOR(C_DATA_WIDTH - 1 DOWNTO 0) := (OTHERS=>'0');
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s_axis_tx_tvalid : IN STD_LOGIC := '0';
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s_axis_tx_tready : OUT STD_LOGIC := '0';
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s_axis_tx_tstrb : IN STD_LOGIC_VECTOR(C_STRB_WIDTH - 1 DOWNTO 0) := (OTHERS=>'0');
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s_axis_tx_tlast : IN STD_LOGIC := '0';
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s_axis_tx_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS=>'0');
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-- AXI RX
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-------------
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m_axis_rx_tdata : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH - 1 DOWNTO 0) := (OTHERS=>'0');
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m_axis_rx_tvalid : OUT STD_LOGIC := '0';
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m_axis_rx_tready : IN STD_LOGIC := '0';
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m_axis_rx_tstrb : OUT STD_LOGIC_VECTOR(C_STRB_WIDTH - 1 DOWNTO 0) := (OTHERS=>'0');
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m_axis_rx_tlast : OUT STD_LOGIC := '0';
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m_axis_rx_tuser : OUT STD_LOGIC_VECTOR(21 DOWNTO 0) := (OTHERS=>'0');
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-- User Misc.
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-------------
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user_turnoff_ok : IN STD_LOGIC := '0';
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user_tcfg_gnt : IN STD_LOGIC := '0';
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-----------------------------------------------
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-- PCIe Block I/O
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-----------------------------------------------
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-- TRN TX
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-------------
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trn_td : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH - 1 DOWNTO 0) := (OTHERS=>'0');
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trn_tsof : OUT STD_LOGIC := '0';
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trn_teof : OUT STD_LOGIC := '0';
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trn_tsrc_rdy : OUT STD_LOGIC := '0';
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trn_tdst_rdy : IN STD_LOGIC := '0';
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trn_tsrc_dsc : OUT STD_LOGIC := '0';
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trn_trem : OUT STD_LOGIC_VECTOR(C_REM_WIDTH - 1 DOWNTO 0) := (OTHERS=>'0');
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trn_terrfwd : OUT STD_LOGIC := '0';
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trn_tstr : OUT STD_LOGIC := '0';
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trn_tbuf_av : IN STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS=>'0');
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trn_tecrc_gen : OUT STD_LOGIC := '0';
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-- TRN RX
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-------------
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trn_rd : IN STD_LOGIC_VECTOR(C_DATA_WIDTH - 1 DOWNTO 0) := (OTHERS=>'0');
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trn_rsof : IN STD_LOGIC := '0';
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trn_reof : IN STD_LOGIC := '0';
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trn_rsrc_rdy : IN STD_LOGIC := '0';
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trn_rdst_rdy : OUT STD_LOGIC := '0';
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trn_rsrc_dsc : IN STD_LOGIC := '0';
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trn_rrem : IN STD_LOGIC_VECTOR(C_REM_WIDTH - 1 DOWNTO 0) := (OTHERS=>'0');
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trn_rerrfwd : IN STD_LOGIC := '0';
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trn_rbar_hit : IN STD_LOGIC_VECTOR(6 DOWNTO 0) := (OTHERS=>'0');
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trn_recrc_err : IN STD_LOGIC := '0';
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-- TRN Misc.
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-------------
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trn_tcfg_req : IN STD_LOGIC := '0';
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trn_tcfg_gnt : OUT STD_LOGIC := '0';
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trn_lnk_up : IN STD_LOGIC := '0';
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-- 7 Series/Virtex6 PM
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-------------
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cfg_pcie_link_state : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS=>'0');
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-- Virtex6 PM
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-------------
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cfg_pm_send_pme_to : IN STD_LOGIC := '0';
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cfg_pmcsr_powerstate : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS=>'0');
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trn_rdllp_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS=>'0');
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trn_rdllp_src_rdy : IN STD_LOGIC := '0';
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-- Virtex6/Spartan6 PM
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-------------
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cfg_to_turnoff : IN STD_LOGIC := '0';
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cfg_turnoff_ok : OUT STD_LOGIC := '0';
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np_counter : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS=>'0');
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user_clk : IN STD_LOGIC := '0';
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user_rst : IN STD_LOGIC := '0'
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);
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END axi_basic_top;
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-----------------------------------------------
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-- RX Data Pipeline
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-----------------------------------------------
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ARCHITECTURE trans OF axi_basic_top IS
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COMPONENT axi_basic_rx IS
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GENERIC (
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C_DATA_WIDTH : INTEGER := 128;
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C_FAMILY : STRING := "X7";
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C_ROOT_PORT : BOOLEAN := FALSE;
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C_PM_PRIORITY : BOOLEAN := FALSE;
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TCQ : INTEGER := 1;
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C_REM_WIDTH : INTEGER := 1;
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C_STRB_WIDTH : INTEGER := 4
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);
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PORT (
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-- Outgoing AXI TX
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-------------
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M_AXIS_RX_TDATA : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH - 1 DOWNTO 0) := (OTHERS=>'0');
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M_AXIS_RX_TVALID : OUT STD_LOGIC := '0';
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M_AXIS_RX_TREADY : IN STD_LOGIC := '0';
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M_AXIS_RX_TSTRB : OUT STD_LOGIC_VECTOR(C_STRB_WIDTH - 1 DOWNTO 0) := (OTHERS=>'0');
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M_AXIS_RX_TLAST : OUT STD_LOGIC := '0';
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M_AXIS_RX_TUSER : OUT STD_LOGIC_VECTOR(21 DOWNTO 0) := (OTHERS=>'0');
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-- Incoming TRN RX
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-------------
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TRN_RD : IN STD_LOGIC_VECTOR(C_DATA_WIDTH - 1 DOWNTO 0) := (OTHERS=>'0');
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TRN_RSOF : IN STD_LOGIC := '0';
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TRN_REOF : IN STD_LOGIC := '0';
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TRN_RSRC_RDY : IN STD_LOGIC := '0';
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TRN_RDST_RDY : OUT STD_LOGIC := '0';
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TRN_RSRC_DSC : IN STD_LOGIC := '0';
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TRN_RREM : IN STD_LOGIC_VECTOR(C_REM_WIDTH - 1 DOWNTO 0) := (OTHERS=>'0');
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TRN_RERRFWD : IN STD_LOGIC := '0';
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TRN_RBAR_HIT : IN STD_LOGIC_VECTOR(6 DOWNTO 0) := (OTHERS=>'0');
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TRN_RECRC_ERR : IN STD_LOGIC := '0';
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-- System
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-------------
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NP_COUNTER : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS=>'0');
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USER_CLK : IN STD_LOGIC := '0';
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USER_RST : IN STD_LOGIC := '0'
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);
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END COMPONENT;
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-----------------------------------------------
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-- TX Data Pipeline
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-----------------------------------------------
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COMPONENT axi_basic_tx IS
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GENERIC (
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C_DATA_WIDTH : INTEGER := 128;
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C_FAMILY : STRING := "X7";
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C_ROOT_PORT : BOOLEAN := FALSE;
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C_PM_PRIORITY : BOOLEAN := FALSE;
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TCQ : INTEGER := 1;
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C_REM_WIDTH : INTEGER := 1;
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C_STRB_WIDTH : INTEGER := 4
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);
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PORT (
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-- Incoming AXI RX
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-------------
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S_AXIS_TX_TDATA : IN STD_LOGIC_VECTOR(C_DATA_WIDTH - 1 DOWNTO 0) := (OTHERS=>'0');
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S_AXIS_TX_TVALID : IN STD_LOGIC := '0';
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S_AXIS_TX_TREADY : OUT STD_LOGIC := '0';
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S_AXIS_TX_TSTRB : IN STD_LOGIC_VECTOR(C_STRB_WIDTH - 1 DOWNTO 0) := (OTHERS=>'0');
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S_AXIS_TX_TLAST : IN STD_LOGIC := '0';
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S_AXIS_TX_TUSER : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS=>'0');
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-- User Misc.
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-------------
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USER_TURNOFF_OK : IN STD_LOGIC := '0';
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USER_TCFG_GNT : IN STD_LOGIC := '0';
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-- Outgoing TRN TX
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-------------
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TRN_TD : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH - 1 DOWNTO 0) := (OTHERS=>'0');
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TRN_TSOF : OUT STD_LOGIC := '0';
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TRN_TEOF : OUT STD_LOGIC := '0';
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TRN_TSRC_RDY : OUT STD_LOGIC := '0';
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TRN_TDST_RDY : IN STD_LOGIC := '0';
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TRN_TSRC_DSC : OUT STD_LOGIC;
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TRN_TREM : OUT STD_LOGIC_VECTOR(C_REM_WIDTH - 1 DOWNTO 0) := (OTHERS=>'0');
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TRN_TERRFWD : OUT STD_LOGIC := '0';
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TRN_TSTR : OUT STD_LOGIC := '0';
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TRN_TBUF_AV : IN STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS=>'0');
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TRN_TECRC_GEN : OUT STD_LOGIC := '0';
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-- TRN Misc.
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-------------
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TRN_TCFG_REQ : IN STD_LOGIC := '0';
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TRN_TCFG_GNT : OUT STD_LOGIC := '0';
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TRN_LNK_UP : IN STD_LOGIC := '0';
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-- 7 Series/Virtex6 PM
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-------------
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CFG_PCIE_LINK_STATE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS=>'0');
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-- Virtex6 PM
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-------------
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CFG_PM_SEND_PME_TO : IN STD_LOGIC := '0';
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CFG_PMCSR_POWERSTATE : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS=>'0');
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TRN_RDLLP_DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS=>'0');
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TRN_RDLLP_SRC_RDY : IN STD_LOGIC;
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-- Spartan6 PM
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-------------
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CFG_TO_TURNOFF : IN STD_LOGIC := '0';
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CFG_TURNOFF_OK : OUT STD_LOGIC := '0';
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-- System
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-------------
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USER_CLK : IN STD_LOGIC := '0';
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USER_RST : IN STD_LOGIC := '0'
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);
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END COMPONENT axi_basic_tx;
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BEGIN
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rx_inst : axi_basic_rx
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GENERIC MAP (
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C_DATA_WIDTH => C_DATA_WIDTH,
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TCQ => TCQ,
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C_FAMILY => C_FAMILY,
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C_REM_WIDTH => C_REM_WIDTH,
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C_STRB_WIDTH => C_STRB_WIDTH
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)
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PORT MAP (
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M_AXIS_RX_TDATA => m_axis_rx_tdata,
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M_AXIS_RX_TVALID => m_axis_rx_tvalid,
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M_AXIS_RX_TREADY => m_axis_rx_tready,
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M_AXIS_RX_TSTRB => m_axis_rx_tstrb,
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|
M_AXIS_RX_TLAST => m_axis_rx_tlast,
|
307 |
|
|
M_AXIS_RX_TUSER => m_axis_rx_tuser,
|
308 |
|
|
|
309 |
|
|
TRN_RD => trn_rd,
|
310 |
|
|
TRN_RSOF => trn_rsof,
|
311 |
|
|
TRN_REOF => trn_reof,
|
312 |
|
|
TRN_RSRC_RDY => trn_rsrc_rdy,
|
313 |
|
|
TRN_RDST_RDY => trn_rdst_rdy,
|
314 |
|
|
TRN_RSRC_DSC => trn_rsrc_dsc,
|
315 |
|
|
TRN_RREM => trn_rrem,
|
316 |
|
|
TRN_RERRFWD => trn_rerrfwd,
|
317 |
|
|
TRN_RBAR_HIT => trn_rbar_hit,
|
318 |
|
|
TRN_RECRC_ERR => trn_recrc_err,
|
319 |
|
|
|
320 |
|
|
NP_COUNTER => np_counter,
|
321 |
|
|
USER_CLK => user_clk,
|
322 |
|
|
USER_RST => user_rst
|
323 |
|
|
);
|
324 |
|
|
|
325 |
|
|
tx_inst : axi_basic_tx
|
326 |
|
|
GENERIC MAP (
|
327 |
|
|
C_DATA_WIDTH => C_DATA_WIDTH,
|
328 |
|
|
C_FAMILY => C_FAMILY,
|
329 |
|
|
C_ROOT_PORT => C_ROOT_PORT,
|
330 |
|
|
C_PM_PRIORITY => C_PM_PRIORITY,
|
331 |
|
|
TCQ => TCQ,
|
332 |
|
|
C_REM_WIDTH => C_REM_WIDTH,
|
333 |
|
|
C_STRB_WIDTH => C_STRB_WIDTH
|
334 |
|
|
)
|
335 |
|
|
PORT MAP (
|
336 |
|
|
|
337 |
|
|
S_AXIS_TX_TDATA => s_axis_tx_tdata,
|
338 |
|
|
S_AXIS_TX_TVALID => s_axis_tx_tvalid,
|
339 |
|
|
S_AXIS_TX_TREADY => s_axis_tx_tready,
|
340 |
|
|
S_AXIS_TX_TSTRB => s_axis_tx_tstrb,
|
341 |
|
|
S_AXIS_TX_TLAST => s_axis_tx_tlast,
|
342 |
|
|
S_AXIS_TX_TUSER => s_axis_tx_tuser,
|
343 |
|
|
|
344 |
|
|
USER_TURNOFF_OK => user_turnoff_ok,
|
345 |
|
|
USER_TCFG_GNT => user_tcfg_gnt,
|
346 |
|
|
|
347 |
|
|
TRN_TD => trn_td,
|
348 |
|
|
TRN_TSOF => trn_tsof,
|
349 |
|
|
TRN_TEOF => trn_teof,
|
350 |
|
|
TRN_TSRC_RDY => trn_tsrc_rdy,
|
351 |
|
|
TRN_TDST_RDY => trn_tdst_rdy,
|
352 |
|
|
TRN_TSRC_DSC => trn_tsrc_dsc,
|
353 |
|
|
TRN_TREM => trn_trem,
|
354 |
|
|
TRN_TERRFWD => trn_terrfwd,
|
355 |
|
|
TRN_TSTR => trn_tstr,
|
356 |
|
|
TRN_TBUF_AV => trn_tbuf_av,
|
357 |
|
|
TRN_TECRC_GEN => trn_tecrc_gen,
|
358 |
|
|
|
359 |
|
|
TRN_TCFG_REQ => trn_tcfg_req,
|
360 |
|
|
TRN_TCFG_GNT => trn_tcfg_gnt,
|
361 |
|
|
TRN_LNK_UP => trn_lnk_up,
|
362 |
|
|
|
363 |
|
|
CFG_PCIE_LINK_STATE => cfg_pcie_link_state,
|
364 |
|
|
|
365 |
|
|
CFG_PM_SEND_PME_TO => cfg_pm_send_pme_to,
|
366 |
|
|
CFG_PMCSR_POWERSTATe => cfg_pmcsr_powerstate,
|
367 |
|
|
TRN_RDLLP_DATA => trn_rdllp_data,
|
368 |
|
|
TRN_RDLLP_SRC_RDY => trn_rdllp_src_rdy,
|
369 |
|
|
|
370 |
|
|
CFG_TO_TURNOFF => cfg_to_turnoff,
|
371 |
|
|
CFG_TURNOFF_OK => cfg_turnoff_ok,
|
372 |
|
|
|
373 |
|
|
USER_CLK => user_clk,
|
374 |
|
|
USER_RST => user_rst
|
375 |
|
|
);
|
376 |
|
|
|
377 |
|
|
END trans;
|
378 |
|
|
|
379 |
|
|
|