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-------------------------------------------------------------------------------
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--
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-- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
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--
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-- This file contains confidential and proprietary information
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-- of Xilinx, Inc. and is protected under U.S. and
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-- international copyright and other intellectual property
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-- laws.
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--
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-- DISCLAIMER
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-- This disclaimer is not a license and does not grant any
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-- rights to the materials distributed herewith. Except as
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-- otherwise provided in a valid license issued to you by
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-- Xilinx, and to the maximum extent permitted by applicable
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-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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-- (2) Xilinx shall not be liable (whether in contract or tort,
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-- including negligence, or under any other theory of
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-- liability) for any loss or damage of any kind or nature
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-- related to, arising under or in connection with these
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-- materials, including for any direct, or any indirect,
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-- reasonably foreseeable or Xilinx had been advised of the
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-- possibility of the same.
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--
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-- CRITICAL APPLICATIONS
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-- Xilinx products are not designed or intended to be fail-
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-- safe, or for use in any application requiring fail-safe
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-- performance, such as life-support or safety devices or
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-- systems, Class III medical devices, nuclear facilities,
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-- applications related to the deployment of airbags, or any
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-- other applications that could lead to death, personal
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-- injury, or severe property or environmental damage
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-- (individually and collectively, "Critical
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-- Applications"). Customer assumes the sole risk and
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-- liability of any use of Xilinx products in Critical
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-- Applications, subject only to applicable laws and
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-- regulations governing limitations on product liability.
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--
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-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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-- PART OF THIS FILE AT ALL TIMES.
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--
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-------------------------------------------------------------------------------
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-- Project : Virtex-6 Integrated Block for PCI Express
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-- File : axi_basic_tx.vhd
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-- Version : 2.3
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--
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-- Description:
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--AXI to TRN TX module. Instantiates pipeline and throttle control TX
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-- submodules.
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--
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-- Notes:
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-- Optional notes section.
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--
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-- Hierarchical:
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-- axi_basic_top
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-- axi_basic_tx
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--
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--------------------------------------------------------------------------------
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-- Library Declarations
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--------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_unsigned.all;
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ENTITY axi_basic_tx IS
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GENERIC (
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C_DATA_WIDTH : INTEGER := 128; -- RX/TX interface data width
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C_FAMILY : STRING := "X7"; -- Targeted FPGA family
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C_ROOT_PORT : BOOLEAN := FALSE; -- PCIe block is in root port mode
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C_PM_PRIORITY : BOOLEAN := FALSE; -- Disable TX packet boundary thrtl
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TCQ : INTEGER := 1; -- Clock to Q time
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C_REM_WIDTH : INTEGER := 1; -- trem/rrem width
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C_STRB_WIDTH : INTEGER := 4 -- TSTRB width
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);
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PORT (
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-----------------------------------------------
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-- User Design I/O
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-----------------------------------------------
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-- AXI TX
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-------------
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S_AXIS_TX_TDATA : IN STD_LOGIC_VECTOR(C_DATA_WIDTH - 1 DOWNTO 0);
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S_AXIS_TX_TVALID : IN STD_LOGIC;
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S_AXIS_TX_TREADY : OUT STD_LOGIC;
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S_AXIS_TX_TSTRB : IN STD_LOGIC_VECTOR(C_STRB_WIDTH - 1 DOWNTO 0);
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S_AXIS_TX_TLAST : IN STD_LOGIC;
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S_AXIS_TX_TUSER : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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-- User Misc.
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-------------
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USER_TURNOFF_OK : IN STD_LOGIC;
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USER_TCFG_GNT : IN STD_LOGIC;
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-----------------------------------------------
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-- PCIe Block I/O
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-----------------------------------------------
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-- TRN TX
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-------------
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TRN_TD : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH - 1 DOWNTO 0);
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TRN_TSOF : OUT STD_LOGIC;
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TRN_TEOF : OUT STD_LOGIC;
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TRN_TSRC_RDY : OUT STD_LOGIC;
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TRN_TDST_RDY : IN STD_LOGIC;
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TRN_TSRC_DSC : OUT STD_LOGIC;
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TRN_TREM : OUT STD_LOGIC_VECTOR(C_REM_WIDTH - 1 DOWNTO 0);
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TRN_TERRFWD : OUT STD_LOGIC;
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TRN_TSTR : OUT STD_LOGIC;
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TRN_TBUF_AV : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
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TRN_TECRC_GEN : OUT STD_LOGIC;
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-- TRN Misc.
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-----------
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TRN_TCFG_REQ : IN STD_LOGIC;
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TRN_TCFG_GNT : OUT STD_LOGIC;
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TRN_LNK_UP : IN STD_LOGIC;
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-- 7 Series/Virtex6 PM
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-----------
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CFG_PCIE_LINK_STATE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
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-- Virtex6 PM
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-----------
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CFG_PM_SEND_PME_TO : IN STD_LOGIC;
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CFG_PMCSR_POWERSTATE : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
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TRN_RDLLP_DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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TRN_RDLLP_SRC_RDY : IN STD_LOGIC;
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-- Virtex6/Spartan6 PM
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-----------
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CFG_TO_TURNOFF : IN STD_LOGIC;
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CFG_TURNOFF_OK : OUT STD_LOGIC;
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-- System
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-----------
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USER_CLK : IN STD_LOGIC;
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USER_RST : IN STD_LOGIC
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);
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END axi_basic_tx;
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ARCHITECTURE trans OF axi_basic_tx IS
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SIGNAL tready_thrtl : STD_LOGIC;
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-- Declare intermediate signals for referenced outputs
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SIGNAL s_axis_tx_tready_xhdl1 : STD_LOGIC;
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SIGNAL trn_td_xhdl3 : STD_LOGIC_VECTOR(C_DATA_WIDTH - 1 DOWNTO 0);
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SIGNAL trn_tsof_xhdl8 : STD_LOGIC;
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SIGNAL trn_teof_xhdl5 : STD_LOGIC;
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SIGNAL trn_tsrc_rdy_xhdl10 : STD_LOGIC;
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SIGNAL trn_tsrc_dsc_xhdl9 : STD_LOGIC;
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SIGNAL trn_trem_xhdl7 : STD_LOGIC_VECTOR(C_REM_WIDTH - 1 DOWNTO 0);
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SIGNAL trn_terrfwd_xhdl6 : STD_LOGIC;
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SIGNAL trn_tstr_xhdl11 : STD_LOGIC;
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SIGNAL trn_tecrc_gen_xhdl4 : STD_LOGIC;
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SIGNAL trn_tcfg_gnt_xhdl2 : STD_LOGIC;
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SIGNAL cfg_turnoff_ok_xhdl0 : STD_LOGIC;
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COMPONENT axi_basic_tx_thrtl_ctl IS
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GENERIC (
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C_DATA_WIDTH : INTEGER := 128;
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C_FAMILY : STRING := "X7";
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C_ROOT_PORT : BOOLEAN := FALSE;
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TCQ : INTEGER := 1
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);
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PORT (
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S_AXIS_TX_TDATA : IN STD_LOGIC_VECTOR(C_DATA_WIDTH - 1 DOWNTO 0);
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S_AXIS_TX_TVALID : IN STD_LOGIC;
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S_AXIS_TX_TUSER : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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S_AXIS_TX_TLAST : IN STD_LOGIC;
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USER_TURNOFF_OK : IN STD_LOGIC;
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USER_TCFG_GNT : IN STD_LOGIC;
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TRN_TBUF_AV : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
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TRN_TDST_RDY : IN STD_LOGIC;
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TRN_TCFG_REQ : IN STD_LOGIC;
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TRN_TCFG_GNT : OUT STD_LOGIC;
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TRN_LNK_UP : IN STD_LOGIC;
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CFG_PCIE_LINK_STATE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
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CFG_PM_SEND_PME_TO : IN STD_LOGIC;
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CFG_PMCSR_POWERSTATE : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
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TRN_RDLLP_DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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TRN_RDLLP_SRC_RDY : IN STD_LOGIC;
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CFG_TO_TURNOFF : IN STD_LOGIC;
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CFG_TURNOFF_OK : OUT STD_LOGIC;
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TREADY_THRTL : OUT STD_LOGIC;
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USER_CLK : IN STD_LOGIC;
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USER_RST : IN STD_LOGIC
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);
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END COMPONENT axi_basic_tx_thrtl_ctl;
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-----------------------------------------------
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-- TX Data Pipeline
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-----------------------------------------------
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COMPONENT axi_basic_tx_pipeline IS
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GENERIC (
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C_DATA_WIDTH : INTEGER := 128;
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C_PM_PRIORITY : BOOLEAN := FALSE;
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TCQ : INTEGER := 1;
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C_REM_WIDTH : INTEGER := 1;
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C_STRB_WIDTH : INTEGER := 8
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);
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PORT (
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-- Incoming AXI RX
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-------------
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S_AXIS_TX_TDATA : IN STD_LOGIC_VECTOR(C_DATA_WIDTH - 1 DOWNTO 0);
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S_AXIS_TX_TVALID : IN STD_LOGIC;
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S_AXIS_TX_TREADY : OUT STD_LOGIC;
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S_AXIS_TX_TSTRB : IN STD_LOGIC_VECTOR(C_STRB_WIDTH - 1 DOWNTO 0);
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S_AXIS_TX_TLAST : IN STD_LOGIC;
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S_AXIS_TX_TUSER : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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-- Outgoing TRN TX
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-------------
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TRN_TD : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH - 1 DOWNTO 0);
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TRN_TSOF : OUT STD_LOGIC;
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TRN_TEOF : OUT STD_LOGIC;
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TRN_TSRC_RDY : OUT STD_LOGIC;
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TRN_TDST_RDY : IN STD_LOGIC;
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TRN_TSRC_DSC : OUT STD_LOGIC;
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TRN_TREM : OUT STD_LOGIC_VECTOR(C_REM_WIDTH - 1 DOWNTO 0);
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TRN_TERRFWD : OUT STD_LOGIC;
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TRN_TSTR : OUT STD_LOGIC;
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TRN_TECRC_GEN : OUT STD_LOGIC;
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TRN_LNK_UP : IN STD_LOGIC;
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-- System
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-------------
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TREADY_THRTL : IN STD_LOGIC;
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USER_CLK : IN STD_LOGIC;
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USER_RST : IN STD_LOGIC
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);
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END COMPONENT axi_basic_tx_pipeline;
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BEGIN
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-- Drive referenced outputs
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S_AXIS_TX_TREADY <= s_axis_tx_tready_xhdl1;
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TRN_TD <= trn_td_xhdl3;
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TRN_TSOF <= trn_tsof_xhdl8;
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TRN_TEOF <= trn_teof_xhdl5;
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TRN_TSRC_RDY <= trn_tsrc_rdy_xhdl10;
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TRN_TSRC_DSC <= trn_tsrc_dsc_xhdl9;
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TRN_TREM <= trn_trem_xhdl7;
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TRN_TERRFWD <= trn_terrfwd_xhdl6;
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TRN_TSTR <= trn_tstr_xhdl11;
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TRN_TECRC_GEN <= trn_tecrc_gen_xhdl4;
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TRN_TCFG_GNT <= trn_tcfg_gnt_xhdl2;
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CFG_TURNOFF_OK <= cfg_turnoff_ok_xhdl0;
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tx_pipeline_inst : axi_basic_tx_pipeline
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GENERIC MAP (
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C_DATA_WIDTH => C_DATA_WIDTH,
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C_PM_PRIORITY => C_PM_PRIORITY,
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TCQ => TCQ,
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C_REM_WIDTH => C_REM_WIDTH,
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C_STRB_WIDTH => C_STRB_WIDTH
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)
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PORT MAP (
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S_AXIS_TX_TDATA => S_AXIS_TX_TDATA,
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S_AXIS_TX_TREADY => s_axis_tx_tready_xhdl1,
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S_AXIS_TX_TVALID => S_AXIS_TX_TVALID,
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S_AXIS_TX_TSTRB => S_AXIS_TX_TSTRB,
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S_AXIS_TX_TLAST => S_AXIS_TX_TLAST,
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S_AXIS_TX_TUSER => S_AXIS_TX_TUSER,
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TRN_TD => trn_td_xhdl3,
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TRN_TSOF => trn_tsof_xhdl8,
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TRN_TEOF => trn_teof_xhdl5,
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TRN_TSRC_RDY => trn_tsrc_rdy_xhdl10,
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TRN_TDST_RDY => TRN_TDST_RDY,
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TRN_TSRC_DSC => trn_tsrc_dsc_xhdl9,
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TRN_TREM => trn_trem_xhdl7,
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TRN_TERRFWD => trn_terrfwd_xhdl6,
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TRN_TSTR => trn_tstr_xhdl11,
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TRN_TECRC_GEN => trn_tecrc_gen_xhdl4,
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TRN_LNK_UP => trn_lnk_up,
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TREADY_THRTL => TREADY_THRTL,
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USER_CLK => USER_CLK,
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USER_RST => USER_RST
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);
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-------------------------------------------------
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-- TX Throttle Controller
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-------------------------------------------------
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xhdl12 : IF (NOT(C_PM_PRIORITY)) GENERATE
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tx_thrl_ctl_inst : axi_basic_tx_thrtl_ctl
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GENERIC MAP (
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C_DATA_WIDTH => C_DATA_WIDTH,
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C_FAMILY => C_FAMILY,
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C_ROOT_PORT => C_ROOT_PORT,
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TCQ => TCQ
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)
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PORT MAP (
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-- Outgoing AXI TX
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311 |
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-------------
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S_AXIS_TX_TDATA => S_AXIS_TX_TDATA,
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S_AXIS_TX_TVALID => S_AXIS_TX_TVALID,
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314 |
|
|
S_AXIS_TX_TUSER => S_AXIS_TX_TUSER,
|
315 |
|
|
S_AXIS_TX_TLAST => S_AXIS_TX_TLAST,
|
316 |
|
|
|
317 |
|
|
-- User Misc.
|
318 |
|
|
-------------
|
319 |
|
|
USER_TURNOFF_OK => USER_TURNOFF_OK,
|
320 |
|
|
USER_TCFG_GNT => USER_TCFG_GNT,
|
321 |
|
|
|
322 |
|
|
-- Incoming TRN RX
|
323 |
|
|
-------------
|
324 |
|
|
TRN_TBUF_AV => TRN_TBUF_AV,
|
325 |
|
|
TRN_TDST_RDY => TRN_TDST_RDY,
|
326 |
|
|
|
327 |
|
|
-- TRN Misc.
|
328 |
|
|
-------------
|
329 |
|
|
TRN_TCFG_REQ => TRN_TCFG_REQ,
|
330 |
|
|
TRN_TCFG_GNT => trn_tcfg_gnt_xhdl2,
|
331 |
|
|
TRN_LNK_UP => trn_lnk_up,
|
332 |
|
|
|
333 |
|
|
-- 7 Seriesq/Virtex6 PM
|
334 |
|
|
-------------
|
335 |
|
|
CFG_PCIE_LINK_STATE => CFG_PCIE_LINK_STATE,
|
336 |
|
|
|
337 |
|
|
-- Virtex6 PM
|
338 |
|
|
-------------
|
339 |
|
|
CFG_PM_SEND_PME_TO => CFG_PM_SEND_PME_TO,
|
340 |
|
|
CFG_PMCSR_POWERSTATE => CFG_PMCSR_POWERSTATE,
|
341 |
|
|
TRN_RDLLP_DATA => TRN_RDLLP_DATA,
|
342 |
|
|
TRN_RDLLP_SRC_RDY => TRN_RDLLP_SRC_RDY,
|
343 |
|
|
|
344 |
|
|
-- Spartan6 PM
|
345 |
|
|
-------------
|
346 |
|
|
CFG_TO_TURNOFF => CFG_TO_TURNOFF,
|
347 |
|
|
CFG_TURNOFF_OK => cfg_turnoff_ok_xhdl0,
|
348 |
|
|
|
349 |
|
|
-- System
|
350 |
|
|
-------------
|
351 |
|
|
TREADY_THRTL => TREADY_THRTL,
|
352 |
|
|
USER_CLK => USER_CLK,
|
353 |
|
|
USER_RST => USER_RST
|
354 |
|
|
);
|
355 |
|
|
END GENERATE;
|
356 |
|
|
xhdl13 : IF (C_PM_PRIORITY) GENERATE
|
357 |
|
|
TREADY_THRTL <= '0';
|
358 |
|
|
cfg_turnoff_ok_xhdl0 <= USER_TURNOFF_OK;
|
359 |
|
|
trn_tcfg_gnt_xhdl2 <= USER_TCFG_GNT;
|
360 |
|
|
END GENERATE;
|
361 |
|
|
END trans;
|