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[/] [pcie_ds_dma/] [trunk/] [core/] [ds_dma64/] [pcie_src/] [pcie_core64_m1/] [source_virtex6/] [cl_v6pcie_m1.vhd] - Blame information for rev 2

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-------------------------------------------------------------------------------
2
--
3
-- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
4
--
5
-- This file contains confidential and proprietary information
6
-- of Xilinx, Inc. and is protected under U.S. and
7
-- international copyright and other intellectual property
8
-- laws.
9
--
10
-- DISCLAIMER
11
-- This disclaimer is not a license and does not grant any
12
-- rights to the materials distributed herewith. Except as
13
-- otherwise provided in a valid license issued to you by
14
-- Xilinx, and to the maximum extent permitted by applicable
15
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
16
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
17
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
18
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
19
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
20
-- (2) Xilinx shall not be liable (whether in contract or tort,
21
-- including negligence, or under any other theory of
22
-- liability) for any loss or damage of any kind or nature
23
-- related to, arising under or in connection with these
24
-- materials, including for any direct, or any indirect,
25
-- special, incidental, or consequential loss or damage
26
-- (including loss of data, profits, goodwill, or any type of
27
-- loss or damage suffered as a result of any action brought
28
-- by a third party) even if such damage or loss was
29
-- reasonably foreseeable or Xilinx had been advised of the
30
-- possibility of the same.
31
--
32
-- CRITICAL APPLICATIONS
33
-- Xilinx products are not designed or intended to be fail-
34
-- safe, or for use in any application requiring fail-safe
35
-- performance, such as life-support or safety devices or
36
-- systems, Class III medical devices, nuclear facilities,
37
-- applications related to the deployment of airbags, or any
38
-- other applications that could lead to death, personal
39
-- injury, or severe property or environmental damage
40
-- (individually and collectively, "Critical
41
-- Applications"). Customer assumes the sole risk and
42
-- liability of any use of Xilinx products in Critical
43
-- Applications, subject only to applicable laws and
44
-- regulations governing limitations on product liability.
45
--
46
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
47
-- PART OF THIS FILE AT ALL TIMES.
48
--
49
-------------------------------------------------------------------------------
50
-- Project    : Virtex-6 Integrated Block for PCI Express
51
-- File       : cl_v6pcie_m1.vhd
52
-- Version    : 2.3
53
-- Description: Virtex6 solution wrapper : Endpoint for PCI Express
54
--
55
--
56
--
57
--------------------------------------------------------------------------------
58
 
59
library ieee;
60
   use ieee.std_logic_1164.all;
61
   use ieee.std_logic_unsigned.all;
62
 
63
library unisim;
64
use unisim.vcomponents.all;
65
 
66
entity cl_v6pcie_m1 is
67
   generic (
68
   PCIE_DRP_ENABLE                              : boolean := FALSE;
69
   ALLOW_X8_GEN2                                : boolean := FALSE;
70
   BAR0                                         : bit_vector := X"FFE00000";
71
   BAR1                                         : bit_vector := X"FFE00000";
72
   BAR2                                         : bit_vector := X"00000000";
73
   BAR3                                         : bit_vector := X"00000000";
74
   BAR4                                         : bit_vector := X"00000000";
75
   BAR5                                         : bit_vector := X"00000000";
76
 
77
   CARDBUS_CIS_POINTER                          : bit_vector := X"00000000";
78
   CLASS_CODE                                   : bit_vector := X"FFFFFF";
79
   CMD_INTX_IMPLEMENTED                         : boolean    := TRUE;
80
   CPL_TIMEOUT_DISABLE_SUPPORTED                : boolean    := FALSE;
81
   CPL_TIMEOUT_RANGES_SUPPORTED                 : bit_vector := X"2";
82
 
83
   DEV_CAP_ENDPOINT_L0S_LATENCY                 : integer    := 0;
84
   DEV_CAP_ENDPOINT_L1_LATENCY                  : integer    := 7;
85
   DEV_CAP_EXT_TAG_SUPPORTED                    : boolean    := FALSE;
86
   DEV_CAP_MAX_PAYLOAD_SUPPORTED                : integer    := 1;
87
   DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT            : integer    := 0;
88
   DEVICE_ID                                    : bit_vector := X"5507";
89
 
90
   DISABLE_LANE_REVERSAL                        : boolean    := TRUE;
91
   DISABLE_SCRAMBLING                           : boolean    := FALSE;
92
   DSN_BASE_PTR                                 : bit_vector := X"0";
93
   DSN_CAP_NEXTPTR                              : bit_vector := X"000";
94
   DSN_CAP_ON                                   : boolean    := FALSE;
95
 
96
   ENABLE_MSG_ROUTE                             : bit_vector := "00000000000";
97
   ENABLE_RX_TD_ECRC_TRIM                       : boolean    := TRUE;
98
   EXPANSION_ROM                                : bit_vector := X"00000000";
99
   EXT_CFG_CAP_PTR                              : bit_vector := X"3F";
100
   EXT_CFG_XP_CAP_PTR                           : bit_vector := X"3FF";
101
   HEADER_TYPE                                  : bit_vector := X"00";
102
   INTERRUPT_PIN                                : bit_vector := X"1";
103
 
104
   LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP       : boolean    := FALSE;
105
   LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP     : boolean    := FALSE;
106
   LINK_CAP_MAX_LINK_SPEED                      : bit_vector := X"2";
107
   LINK_CAP_MAX_LINK_WIDTH                      : bit_vector := X"04";
108
   LINK_CAP_MAX_LINK_WIDTH_int                  : integer    := 4;
109
   LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE         : boolean    := FALSE;
110
 
111
   LINK_CTRL2_DEEMPHASIS                        : boolean    := FALSE;
112
   LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE       : boolean    := FALSE;
113
   LINK_CTRL2_TARGET_LINK_SPEED                 : bit_vector := X"2";
114
   LINK_STATUS_SLOT_CLOCK_CONFIG                : boolean    := TRUE;
115
 
116
   LL_ACK_TIMEOUT                               : bit_vector := X"0000";
117
   LL_ACK_TIMEOUT_EN                            : boolean    := FALSE;
118
   LL_ACK_TIMEOUT_FUNC                          : integer    := 0;
119
   LL_REPLAY_TIMEOUT                            : bit_vector := X"0026";
120
   LL_REPLAY_TIMEOUT_EN                         : boolean    := TRUE;
121
   LL_REPLAY_TIMEOUT_FUNC                       : integer    := 1;
122
 
123
   LTSSM_MAX_LINK_WIDTH                         : bit_vector := X"04";
124
   MSI_CAP_MULTIMSGCAP                          : integer    := 0;
125
   MSI_CAP_MULTIMSG_EXTENSION                   : integer    := 0;
126
   MSI_CAP_ON                                   : boolean    := FALSE;
127
   MSI_CAP_PER_VECTOR_MASKING_CAPABLE           : boolean    := FALSE;
128
   MSI_CAP_64_BIT_ADDR_CAPABLE                  : boolean    := TRUE;
129
 
130
   MSIX_CAP_ON                                  : boolean    := FALSE;
131
   MSIX_CAP_PBA_BIR                             : integer    := 0;
132
   MSIX_CAP_PBA_OFFSET                          : bit_vector := X"0";
133
   MSIX_CAP_TABLE_BIR                           : integer    := 0;
134
   MSIX_CAP_TABLE_OFFSET                        : bit_vector := X"0";
135
   MSIX_CAP_TABLE_SIZE                          : bit_vector := X"000";
136
 
137
   PCIE_CAP_DEVICE_PORT_TYPE                    : bit_vector := X"0";
138
   PCIE_CAP_INT_MSG_NUM                         : bit_vector := X"1";
139
   PCIE_CAP_NEXTPTR                             : bit_vector := X"00";
140
   PIPE_PIPELINE_STAGES                         : integer    := 0;                -- 0 - 0 stages; 1 - 1 stage; 2 - 2 stages
141
 
142
   PM_CAP_DSI                                   : boolean    := FALSE;
143
   PM_CAP_D1SUPPORT                             : boolean    := FALSE;
144
   PM_CAP_D2SUPPORT                             : boolean    := FALSE;
145
   PM_CAP_NEXTPTR                               : bit_vector := X"60";
146
   PM_CAP_PMESUPPORT                            : bit_vector := X"0F";
147
   PM_CSR_NOSOFTRST                             : boolean    := TRUE;
148
 
149
   PM_DATA_SCALE0                               : bit_vector := X"0";
150
   PM_DATA_SCALE1                               : bit_vector := X"0";
151
   PM_DATA_SCALE2                               : bit_vector := X"0";
152
   PM_DATA_SCALE3                               : bit_vector := X"0";
153
   PM_DATA_SCALE4                               : bit_vector := X"0";
154
   PM_DATA_SCALE5                               : bit_vector := X"0";
155
   PM_DATA_SCALE6                               : bit_vector := X"0";
156
   PM_DATA_SCALE7                               : bit_vector := X"0";
157
 
158
   PM_DATA0                                     : bit_vector := X"00";
159
   PM_DATA1                                     : bit_vector := X"00";
160
   PM_DATA2                                     : bit_vector := X"00";
161
   PM_DATA3                                     : bit_vector := X"00";
162
   PM_DATA4                                     : bit_vector := X"00";
163
   PM_DATA5                                     : bit_vector := X"00";
164
   PM_DATA6                                     : bit_vector := X"00";
165
   PM_DATA7                                     : bit_vector := X"00";
166
 
167
   REF_CLK_FREQ                                 : integer    := 0;                        -- 0 - 100 MHz; 1 - 125 MHz; 2 - 250 MHz
168
   REVISION_ID                                  : bit_vector := X"20";
169
   SPARE_BIT0                                   : integer    := 0;
170
   SUBSYSTEM_ID                                 : bit_vector := X"0002";
171
   SUBSYSTEM_VENDOR_ID                          : bit_vector := X"4953";
172
 
173
   TL_RX_RAM_RADDR_LATENCY                      : integer    := 0;
174
   TL_RX_RAM_RDATA_LATENCY                      : integer    := 2;
175
   TL_RX_RAM_WRITE_LATENCY                      : integer    := 0;
176
   TL_TX_RAM_RADDR_LATENCY                      : integer    := 0;
177
   TL_TX_RAM_RDATA_LATENCY                      : integer    := 2;
178
   TL_TX_RAM_WRITE_LATENCY                      : integer    := 0;
179
 
180
   UPCONFIG_CAPABLE                             : boolean    := TRUE;
181
   USER_CLK_FREQ                                : integer    := 3;
182
   VC_BASE_PTR                                  : bit_vector := X"0";
183
   VC_CAP_NEXTPTR                               : bit_vector := X"000";
184
   VC_CAP_ON                                    : boolean    := FALSE;
185
   VC_CAP_REJECT_SNOOP_TRANSACTIONS             : boolean    := FALSE;
186
 
187
   VC0_CPL_INFINITE                             : boolean    := TRUE;
188
   VC0_RX_RAM_LIMIT                             : bit_vector := X"3FF";
189
   VC0_TOTAL_CREDITS_CD                         : integer    := 378;
190
   VC0_TOTAL_CREDITS_CH                         : integer    := 36;
191
   VC0_TOTAL_CREDITS_NPH                        : integer    := 12;
192
   VC0_TOTAL_CREDITS_PD                         : integer    := 32;
193
   VC0_TOTAL_CREDITS_PH                         : integer    := 32;
194
   VC0_TX_LASTPACKET                            : integer    := 28;
195
 
196
   VENDOR_ID                                    : bit_vector := X"4953";
197
   VSEC_BASE_PTR                                : bit_vector := X"0";
198
   VSEC_CAP_NEXTPTR                             : bit_vector := X"000";
199
   VSEC_CAP_ON                                  : boolean    := FALSE;
200
 
201
   AER_BASE_PTR                                 : bit_vector := X"128";
202
   AER_CAP_ECRC_CHECK_CAPABLE                   : boolean    := FALSE;
203
   AER_CAP_ECRC_GEN_CAPABLE                     : boolean    := FALSE;
204
   AER_CAP_ID                                   : bit_vector := X"0001";
205
   AER_CAP_INT_MSG_NUM_MSI                      : bit_vector := X"0a";
206
   AER_CAP_INT_MSG_NUM_MSIX                     : bit_vector := X"15";
207
   AER_CAP_NEXTPTR                              : bit_vector := X"160";
208
   AER_CAP_ON                                   : boolean    := FALSE;
209
   AER_CAP_PERMIT_ROOTERR_UPDATE                : boolean    := TRUE;
210
   AER_CAP_VERSION                              : bit_vector := X"1";
211
 
212
   CAPABILITIES_PTR                             : bit_vector := X"40";
213
   CRM_MODULE_RSTS                              : bit_vector := X"00";
214
   DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE          : boolean    := TRUE;
215
   DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE          : boolean    := TRUE;
216
   DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE         : boolean    := FALSE;
217
   DEV_CAP_ROLE_BASED_ERROR                     : boolean    := TRUE;
218
   DEV_CAP_RSVD_14_12                           : integer    := 0;
219
   DEV_CAP_RSVD_17_16                           : integer    := 0;
220
   DEV_CAP_RSVD_31_29                           : integer    := 0;
221
   DEV_CONTROL_AUX_POWER_SUPPORTED              : boolean    := FALSE;
222
 
223
   DISABLE_ASPM_L1_TIMER                        : boolean    := FALSE;
224
   DISABLE_BAR_FILTERING                        : boolean    := FALSE;
225
   DISABLE_ID_CHECK                             : boolean    := FALSE;
226
   DISABLE_RX_TC_FILTER                         : boolean    := FALSE;
227
   DNSTREAM_LINK_NUM                            : bit_vector := X"00";
228
 
229
   DSN_CAP_ID                                   : bit_vector := X"0003";
230
   DSN_CAP_VERSION                              : bit_vector := X"1";
231
   ENTER_RVRY_EI_L0                             : boolean    := TRUE;
232
   INFER_EI                                     : bit_vector := X"0c";
233
   IS_SWITCH                                    : boolean    := FALSE;
234
 
235
   LAST_CONFIG_DWORD                            : bit_vector := X"3FF";
236
   LINK_CAP_ASPM_SUPPORT                        : integer    := 1;
237
   LINK_CAP_CLOCK_POWER_MANAGEMENT              : boolean    := FALSE;
238
   LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1        : integer    := 7;
239
   LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2        : integer    := 7;
240
   LINK_CAP_L0S_EXIT_LATENCY_GEN1               : integer    := 7;
241
   LINK_CAP_L0S_EXIT_LATENCY_GEN2               : integer    := 7;
242
   LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1         : integer    := 7;
243
   LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2         : integer    := 7;
244
   LINK_CAP_L1_EXIT_LATENCY_GEN1                : integer    := 7;
245
   LINK_CAP_L1_EXIT_LATENCY_GEN2                : integer    := 7;
246
   LINK_CAP_RSVD_23_22                          : integer    := 0;
247
   LINK_CONTROL_RCB                             : integer    := 0;
248
 
249
   MSI_BASE_PTR                                 : bit_vector := X"48";
250
   MSI_CAP_ID                                   : bit_vector := X"05";
251
   MSI_CAP_NEXTPTR                              : bit_vector := X"60";
252
   MSIX_BASE_PTR                                : bit_vector := X"9c";
253
   MSIX_CAP_ID                                  : bit_vector := X"11";
254
   MSIX_CAP_NEXTPTR                             : bit_vector := X"00";
255
   N_FTS_COMCLK_GEN1                            : integer    := 255;
256
   N_FTS_COMCLK_GEN2                            : integer    := 254;
257
   N_FTS_GEN1                                   : integer    := 255;
258
   N_FTS_GEN2                                   : integer    := 255;
259
 
260
   PCIE_BASE_PTR                                : bit_vector := X"60";
261
   PCIE_CAP_CAPABILITY_ID                       : bit_vector := X"10";
262
   PCIE_CAP_CAPABILITY_VERSION                  : bit_vector := X"2";
263
   PCIE_CAP_ON                                  : boolean    := TRUE;
264
   PCIE_CAP_RSVD_15_14                          : integer    := 0;
265
   PCIE_CAP_SLOT_IMPLEMENTED                    : boolean    := FALSE;
266
   PCIE_REVISION                                : integer    := 2;
267
   PGL0_LANE                                    : integer    := 0;
268
   PGL1_LANE                                    : integer    := 1;
269
   PGL2_LANE                                    : integer    := 2;
270
   PGL3_LANE                                    : integer    := 3;
271
   PGL4_LANE                                    : integer    := 4;
272
   PGL5_LANE                                    : integer    := 5;
273
   PGL6_LANE                                    : integer    := 6;
274
   PGL7_LANE                                    : integer    := 7;
275
   PL_AUTO_CONFIG                               : integer    := 0;
276
   PL_FAST_TRAIN                                : boolean    := FALSE;
277
 
278
   PM_BASE_PTR                                  : bit_vector := X"40";
279
   PM_CAP_AUXCURRENT                            : integer    := 0;
280
   PM_CAP_ID                                    : bit_vector := X"01";
281
   PM_CAP_ON                                    : boolean    := TRUE;
282
   PM_CAP_PME_CLOCK                             : boolean    := FALSE;
283
   PM_CAP_RSVD_04                               : integer    := 0;
284
   PM_CAP_VERSION                               : integer    := 3;
285
   PM_CSR_BPCCEN                                : boolean    := FALSE;
286
   PM_CSR_B2B3                                  : boolean    := FALSE;
287
 
288
   RECRC_CHK                                    : integer    := 0;
289
   RECRC_CHK_TRIM                               : boolean    := FALSE;
290
   ROOT_CAP_CRS_SW_VISIBILITY                   : boolean    := FALSE;
291
   SELECT_DLL_IF                                : boolean    := FALSE;
292
   SLOT_CAP_ATT_BUTTON_PRESENT                  : boolean    := FALSE;
293
   SLOT_CAP_ATT_INDICATOR_PRESENT               : boolean    := FALSE;
294
   SLOT_CAP_ELEC_INTERLOCK_PRESENT              : boolean    := FALSE;
295
   SLOT_CAP_HOTPLUG_CAPABLE                     : boolean    := FALSE;
296
   SLOT_CAP_HOTPLUG_SURPRISE                    : boolean    := FALSE;
297
   SLOT_CAP_MRL_SENSOR_PRESENT                  : boolean    := FALSE;
298
   SLOT_CAP_NO_CMD_COMPLETED_SUPPORT            : boolean    := FALSE;
299
   SLOT_CAP_PHYSICAL_SLOT_NUM                   : bit_vector := X"0000";
300
   SLOT_CAP_POWER_CONTROLLER_PRESENT            : boolean    := FALSE;
301
   SLOT_CAP_POWER_INDICATOR_PRESENT             : boolean    := FALSE;
302
   SLOT_CAP_SLOT_POWER_LIMIT_SCALE              : integer    := 0;
303
   SLOT_CAP_SLOT_POWER_LIMIT_VALUE              : bit_vector := X"00";
304
   SPARE_BIT1                                   : integer    := 0;
305
   SPARE_BIT2                                   : integer    := 0;
306
   SPARE_BIT3                                   : integer    := 0;
307
   SPARE_BIT4                                   : integer    := 0;
308
   SPARE_BIT5                                   : integer    := 0;
309
   SPARE_BIT6                                   : integer    := 0;
310
   SPARE_BIT7                                   : integer    := 0;
311
   SPARE_BIT8                                   : integer    := 0;
312
   SPARE_BYTE0                                  : bit_vector := X"00";
313
   SPARE_BYTE1                                  : bit_vector := X"00";
314
   SPARE_BYTE2                                  : bit_vector := X"00";
315
   SPARE_BYTE3                                  : bit_vector := X"00";
316
   SPARE_WORD0                                  : bit_vector := X"00000000";
317
   SPARE_WORD1                                  : bit_vector := X"00000000";
318
   SPARE_WORD2                                  : bit_vector := X"00000000";
319
   SPARE_WORD3                                  : bit_vector := X"00000000";
320
 
321
   TL_RBYPASS                                   : boolean    := FALSE;
322
   TL_TFC_DISABLE                               : boolean    := FALSE;
323
   TL_TX_CHECKS_DISABLE                         : boolean    := FALSE;
324
   EXIT_LOOPBACK_ON_EI                          : boolean    := TRUE;
325
   UPSTREAM_FACING                              : boolean    := TRUE;
326
   UR_INV_REQ                                   : boolean    := TRUE;
327
 
328
   VC_CAP_ID                                    : bit_vector := X"0002";
329
   VC_CAP_VERSION                               : bit_vector := X"1";
330
   VSEC_CAP_HDR_ID                              : bit_vector := X"1234";
331
   VSEC_CAP_HDR_LENGTH                          : bit_vector := X"018";
332
   VSEC_CAP_HDR_REVISION                        : bit_vector := X"1";
333
   VSEC_CAP_ID                                  : bit_vector := X"000b";
334
   VSEC_CAP_IS_LINK_VISIBLE                     : boolean    := TRUE;
335
   VSEC_CAP_VERSION                             : bit_vector := X"1"
336
      );
337
   port (
338
      ---------------------------------------------------------
339
      -- 1. PCI Express (pci_exp) Interface
340
      ---------------------------------------------------------
341
 
342
      -- Tx
343
      pci_exp_txp                               : out std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);
344
      pci_exp_txn                               : out std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);
345
 
346
      -- Rx
347
      pci_exp_rxp                               : in std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);
348
      pci_exp_rxn                               : in std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);
349
 
350
      ---------------------------------------------------------
351
      -- 2. Transaction (TRN) Interface
352
      ---------------------------------------------------------
353
 
354
      -- Common
355
      user_clk_out                              : out std_logic;
356
      user_reset_out                            : out std_logic;
357
      user_lnk_up                               : out std_logic;
358
 
359
      -- Tx
360
      tx_buf_av                                 : out std_logic_vector(5 downto 0);
361
      tx_cfg_req                                : out std_logic;
362
      tx_err_drop                               : out std_logic;
363
 
364
--      s_axis_tx_tready                          : out std_logic;
365
--      s_axis_tx_tdata                           : in std_logic_vector(63 downto 0);
366
--      s_axis_tx_tstrb                           : in std_logic_vector(7 downto 0);
367
--      s_axis_tx_tuser                           : in std_logic_vector(3 downto 0);
368
--      s_axis_tx_tlast                           : in std_logic;
369
--      s_axis_tx_tvalid                          : in std_logic;
370
 
371
      tx_cfg_gnt                                : in std_logic;
372
 
373
      -- Rx
374
--      m_axis_rx_tdata                           : out std_logic_vector(63 downto 0);
375
--      m_axis_rx_tstrb                           : out std_logic_vector(7 downto 0);
376
--      m_axis_rx_tlast                           : out std_logic;
377
--      m_axis_rx_tvalid                          : out std_logic;
378
--      m_axis_rx_tuser                           : out std_logic_vector(21 downto 0);
379
--      m_axis_rx_tready                          : in std_logic;
380
      rx_np_ok                                  : in std_logic;
381
 
382
 
383
      -- TRN TX
384
      -------------
385
      trn_td                  : in STD_LOGIC_VECTOR( 63 DOWNTO 0) := (OTHERS=>'0');
386
      trn_tsof                : in STD_LOGIC                                   := '0';
387
      trn_teof                : in STD_LOGIC                                   := '0';
388
      trn_tsrc_rdy            : in STD_LOGIC                                   := '0';
389
      trn_tdst_rdy            : out STD_LOGIC                                    := '0';
390
      trn_tsrc_dsc            : in STD_LOGIC                                   := '0';
391
      trn_trem                : in STD_LOGIC_VECTOR( 0 DOWNTO 0)  := (OTHERS=>'0');
392
      trn_terrfwd             : in STD_LOGIC                                   := '0';
393
      trn_tstr                : in STD_LOGIC                                   := '0';
394
      trn_tbuf_av             : out STD_LOGIC_VECTOR(5 DOWNTO 0)                 := (OTHERS=>'0');
395
      trn_tecrc_gen           : in STD_LOGIC                                   := '0';
396
 
397
      -- TRN RX
398
      -------------
399
      trn_rd                  : out STD_LOGIC_VECTOR( 63 DOWNTO 0) := (OTHERS=>'0');
400
      trn_rsof                : out STD_LOGIC                                   := '0';
401
      trn_reof                : out STD_LOGIC                                   := '0';
402
      trn_rsrc_rdy            : out STD_LOGIC                                   := '0';
403
      trn_rdst_rdy            : in STD_LOGIC                                  := '0';
404
      trn_rsrc_dsc            : out STD_LOGIC                                   := '0';
405
      trn_rrem                : out STD_LOGIC_VECTOR( 0 DOWNTO 0)  := (OTHERS=>'0');
406
      trn_rerrfwd             : out STD_LOGIC                                   := '0';
407
      trn_rbar_hit            : out STD_LOGIC_VECTOR(6 DOWNTO 0)                := (OTHERS=>'0');
408
      trn_recrc_err           : out STD_LOGIC                                   := '0';
409
 
410
 
411
      -- Flow Control
412
      fc_cpld                                   : out std_logic_vector(11 downto 0);
413
      fc_cplh                                   : out std_logic_vector(7 downto 0);
414
      fc_npd                                    : out std_logic_vector(11 downto 0);
415
      fc_nph                                    : out std_logic_vector(7 downto 0);
416
      fc_pd                                     : out std_logic_vector(11 downto 0);
417
      fc_ph                                     : out std_logic_vector(7 downto 0);
418
      fc_sel                                    : in std_logic_vector(2 downto 0);
419
 
420
      ---------------------------------------------------------
421
      -- 3. Configuration (CFG) Interface
422
      ---------------------------------------------------------
423
 
424
      cfg_do                                    : out std_logic_vector(31 downto 0);
425
      cfg_rd_wr_done                            : out std_logic;
426
      cfg_di                                    : in std_logic_vector(31 downto 0);
427
      cfg_byte_en                               : in std_logic_vector(3 downto 0);
428
      cfg_dwaddr                                : in std_logic_vector(9 downto 0);
429
      cfg_wr_en                                 : in std_logic;
430
      cfg_rd_en                                 : in std_logic;
431
 
432
      cfg_err_cor                               : in std_logic;
433
      cfg_err_ur                                : in std_logic;
434
      cfg_err_ecrc                              : in std_logic;
435
      cfg_err_cpl_timeout                       : in std_logic;
436
      cfg_err_cpl_abort                         : in std_logic;
437
      cfg_err_cpl_unexpect                      : in std_logic;
438
      cfg_err_posted                            : in std_logic;
439
      cfg_err_locked                            : in std_logic;
440
      cfg_err_tlp_cpl_header                    : in std_logic_vector(47 downto 0);
441
      cfg_err_cpl_rdy                           : out std_logic;
442
      cfg_interrupt                             : in std_logic;
443
      cfg_interrupt_rdy                         : out std_logic;
444
      cfg_interrupt_assert                      : in std_logic;
445
      cfg_interrupt_di                          : in std_logic_vector(7 downto 0);
446
      cfg_interrupt_do                          : out std_logic_vector(7 downto 0);
447
      cfg_interrupt_mmenable                    : out std_logic_vector(2 downto 0);
448
      cfg_interrupt_msienable                   : out std_logic;
449
      cfg_interrupt_msixenable                  : out std_logic;
450
      cfg_interrupt_msixfm                      : out std_logic;
451
      cfg_turnoff_ok                            : in std_logic;
452
      cfg_to_turnoff                            : out std_logic;
453
      cfg_trn_pending                           : in std_logic;
454
      cfg_pm_wake                               : in std_logic;
455
      cfg_bus_number                            : out std_logic_vector(7 downto 0);
456
      cfg_device_number                         : out std_logic_vector(4 downto 0);
457
      cfg_function_number                       : out std_logic_vector(2 downto 0);
458
      cfg_status                                : out std_logic_vector(15 downto 0);
459
      cfg_command                               : out std_logic_vector(15 downto 0);
460
      cfg_dstatus                               : out std_logic_vector(15 downto 0);
461
      cfg_dcommand                              : out std_logic_vector(15 downto 0);
462
      cfg_lstatus                               : out std_logic_vector(15 downto 0);
463
      cfg_lcommand                              : out std_logic_vector(15 downto 0);
464
      cfg_dcommand2                             : out std_logic_vector(15 downto 0);
465
      cfg_pcie_link_state                       : out std_logic_vector(2 downto 0);
466
      cfg_dsn                                   : in std_logic_vector(63 downto 0);
467
      cfg_pmcsr_pme_en                          : out std_logic;
468
      cfg_pmcsr_pme_status                      : out std_logic;
469
      cfg_pmcsr_powerstate                      : out std_logic_vector(1 downto 0);
470
 
471
      ---------------------------------------------------------
472
      -- 4. Physical Layer Control and Status (PL) Interface
473
      ---------------------------------------------------------
474
 
475
      pl_initial_link_width                     : out std_logic_vector(2 downto 0);
476
      pl_lane_reversal_mode                     : out std_logic_vector(1 downto 0);
477
      pl_link_gen2_capable                      : out std_logic;
478
      pl_link_partner_gen2_supported            : out std_logic;
479
      pl_link_upcfg_capable                     : out std_logic;
480
      pl_ltssm_state                            : out std_logic_vector(5 downto 0);
481
      pl_received_hot_rst                       : out std_logic;
482
      pl_sel_link_rate                          : out std_logic;
483
      pl_sel_link_width                         : out std_logic_vector(1 downto 0);
484
      pl_directed_link_auton                    : in std_logic;
485
      pl_directed_link_change                   : in std_logic_vector(1 downto 0);
486
      pl_directed_link_speed                    : in std_logic;
487
      pl_directed_link_width                    : in std_logic_vector(1 downto 0);
488
      pl_upstream_prefer_deemph                 : in std_logic;
489
 
490
      ---------------------------------------------------------
491
      -- 5. System  (SYS) Interface
492
      ---------------------------------------------------------
493
 
494
      sys_clk                                   : in std_logic;
495
      sys_reset                                 : in std_logic
496
   );
497
end cl_v6pcie_m1;
498
 
499
architecture v6_pcie of cl_v6pcie_m1 is
500
 
501
   attribute CORE_GENERATION_INFO : string;
502
   attribute CORE_GENERATION_INFO of v6_pcie : ARCHITECTURE is
503
     "cl_v6pcie_m1,v6_pcie_v2_3,{LINK_CAP_MAX_LINK_SPEED=2,LINK_CAP_MAX_LINK_WIDTH=04,PCIE_CAP_DEVICE_PORT_TYPE=0000,DEV_CAP_MAX_PAYLOAD_SUPPORTED=1,USER_CLK_FREQ=3,REF_CLK_FREQ=0,MSI_CAP_ON=FALSE,MSI_CAP_MULTIMSGCAP=0,MSI_CAP_MULTIMSG_EXTENSION=0,MSIX_CAP_ON=FALSE,TL_TX_RAM_RADDR_LATENCY=0,TL_TX_RAM_RDATA_LATENCY=2,TL_RX_RAM_RADDR_LATENCY=0,TL_RX_RAM_RDATA_LATENCY=2,TL_RX_RAM_WRITE_LATENCY=0,VC0_TX_LASTPACKET=28,VC0_RX_RAM_LIMIT=3FF,VC0_TOTAL_CREDITS_PH=32,VC0_TOTAL_CREDITS_PD=32,VC0_TOTAL_CREDITS_NPH=12,VC0_TOTAL_CREDITS_CH=36,VC0_TOTAL_CREDITS_CD=378,VC0_CPL_INFINITE=TRUE,DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT=0,DEV_CAP_EXT_TAG_SUPPORTED=FALSE,LINK_STATUS_SLOT_CLOCK_CONFIG=TRUE,ENABLE_RX_TD_ECRC_TRIM=TRUE,DISABLE_LANE_REVERSAL=TRUE,DISABLE_SCRAMBLING=FALSE,DSN_CAP_ON=FALSE,PIPE_PIPELINE_STAGES=0,REVISION_ID=20,VC_CAP_ON=FALSE}";
504
 
505
   component axi_basic_top
506
   generic (
507
      C_DATA_WIDTH              : integer := 32;     -- rx/tx interface data width
508
      C_FAMILY                  : string  := "x7";    -- targeted fpga family
509
      C_ROOT_PORT               : BOOLEAN := FALSE; -- pcie block is in root port mode
510
      C_PM_PRIORITY             : BOOLEAN := FALSE; -- disable tx packet boundary thrtl
511
      TCQ                       : integer := 1;      -- clock to q time
512
 
513
      C_REM_WIDTH               : integer := 1;      -- trem/rrem width
514
      C_STRB_WIDTH              : integer := 4       -- tstrb width
515
   );
516
   port (
517
      -----------------------------------------------
518
      -- user design I/O
519
      -----------------------------------------------
520
 
521
      -- AXI TX
522
      -------------
523
      s_axis_tx_tdata         : in std_logic_vector(C_DATA_WIDTH - 1 downto 0) := (others=>'0');
524
      s_axis_tx_tvalid        : in std_logic                                   := '0';
525
      s_axis_tx_tready        : out std_logic                                  := '0';
526
      s_axis_tx_tstrb         : in std_logic_vector(C_STRB_WIDTH - 1 downto 0) := (others=>'0');
527
      s_axis_tx_tlast         : in std_logic                                   := '0';
528
      s_axis_tx_tuser         : in std_logic_vector(3 downto 0) := (others=>'0');
529
 
530
      -- AXI RX
531
      -------------
532
      m_axis_rx_tdata         : out std_logic_vector(C_DATA_WIDTH - 1 downto 0) := (others=>'0');
533
      m_axis_rx_tvalid        : out std_logic                                   := '0';
534
      m_axis_rx_tready        : in std_logic                                    := '0';
535
      m_axis_rx_tstrb         : out std_logic_vector(C_STRB_WIDTH - 1 downto 0) := (others=>'0');
536
      m_axis_rx_tlast         : out std_logic                                   := '0';
537
      m_axis_rx_tuser         : out std_logic_vector(21 downto 0) := (others=>'0');
538
 
539
      -- user misc.
540
      -------------
541
      user_turnoff_ok         : in std_logic                                   := '0';
542
      user_tcfg_gnt           : in std_logic                                   := '0';
543
 
544
      -----------------------------------------------
545
      -- PCIe block I/O
546
      -----------------------------------------------
547
 
548
      -- TRN TX
549
      -------------
550
      trn_td                  : out std_logic_vector(C_DATA_WIDTH - 1 downto 0) := (others=>'0');
551
      trn_tsof                : out std_logic                                   := '0';
552
      trn_teof                : out std_logic                                   := '0';
553
      trn_tsrc_rdy            : out std_logic                                   := '0';
554
      trn_tdst_rdy            : in std_logic                                    := '0';
555
      trn_tsrc_dsc            : out std_logic                                   := '0';
556
      trn_trem                : out std_logic_vector(C_REM_WIDTH - 1 downto 0)  := (others=>'0');
557
      trn_terrfwd             : out std_logic                                   := '0';
558
      trn_tstr                : out std_logic                                   := '0';
559
      trn_tbuf_av             : in std_logic_vector(5 downto 0)                 := (others=>'0');
560
      trn_tecrc_gen           : out std_logic                                   := '0';
561
 
562
      -- TRN RX
563
      -------------
564
      trn_rd                  : in std_logic_vector(C_DATA_WIDTH - 1 downto 0) := (others=>'0');
565
      trn_rsof                : in std_logic                                   := '0';
566
      trn_reof                : in std_logic                                   := '0';
567
      trn_rsrc_rdy            : in std_logic                                   := '0';
568
      trn_rdst_rdy            : out std_logic                                  := '0';
569
      trn_rsrc_dsc            : in std_logic                                   := '0';
570
      trn_rrem                : in std_logic_vector(C_REM_WIDTH - 1 downto 0)  := (others=>'0');
571
      trn_rerrfwd             : in std_logic                                   := '0';
572
      trn_rbar_hit            : in std_logic_vector(6 downto 0)                := (others=>'0');
573
      trn_recrc_err           : in std_logic                                   := '0';
574
 
575
      -- TRN misc.
576
      -------------
577
      trn_tcfg_req            : in std_logic                                   := '0';
578
      trn_tcfg_gnt            : out std_logic                                  := '0';
579
      trn_lnk_up              : in std_logic                                   := '0';
580
 
581
      -- 7 series/Virtex6 PM
582
      -------------
583
      cfg_pcie_link_state     : in std_logic_vector(2 downto 0)                := (others=>'0');
584
 
585
      -- Virtex6 PM
586
      -------------
587
      cfg_pm_send_pme_to      : in std_logic                                   := '0';
588
      cfg_pmcsr_powerstate    : in std_logic_vector(1 downto 0)                := (others=>'0');
589
      trn_rdllp_data          : in std_logic_vector(31 downto 0)               := (others=>'0');
590
      trn_rdllp_src_rdy       : in std_logic                                   := '0';
591
 
592
      -- Virtex6/Spartan6 PM
593
      -------------
594
      cfg_to_turnoff          : in std_logic                                   := '0';
595
      cfg_turnoff_ok          : out std_logic                                  := '0';
596
 
597
      np_counter              : out std_logic_vector(2 downto 0)               := (others=>'0');
598
      user_clk                : in std_logic                                   := '0';
599
      user_rst                : in std_logic                                   := '0'
600
   );
601
   end component;
602
 
603
  component pcie_reset_delay_v6
604
    generic (
605
      PL_FAST_TRAIN : boolean;
606
      REF_CLK_FREQ  : integer);
607
    port (
608
      ref_clk             : in  std_logic;
609
      sys_reset_n         : in  std_logic;
610
      delayed_sys_reset_n : out std_logic);
611
  end component;
612
 
613
  component pcie_clocking_v6
614
    generic (
615
      CAP_LINK_WIDTH : integer;
616
      CAP_LINK_SPEED : integer;
617
      REF_CLK_FREQ   : integer;
618
      USER_CLK_FREQ  : integer);
619
    port (
620
      sys_clk       : in  std_logic;
621
      gt_pll_lock   : in  std_logic;
622
      sel_lnk_rate  : in  std_logic;
623
      sel_lnk_width : in  std_logic_vector(1 downto 0);
624
      sys_clk_bufg  : out std_logic;
625
      pipe_clk      : out std_logic;
626
      user_clk      : out std_logic;
627
      block_clk     : out std_logic;
628
      drp_clk       : out std_logic;
629
      clock_locked  : out std_logic);
630
  end component;
631
 
632
  component pcie_2_0_v6
633
    generic (
634
      REF_CLK_FREQ                             : integer;
635
      PIPE_PIPELINE_STAGES                     : integer;
636
      LINK_CAP_MAX_LINK_WIDTH_int              : integer;
637
      AER_BASE_PTR                             : bit_vector;
638
      AER_CAP_ECRC_CHECK_CAPABLE               : boolean;
639
      AER_CAP_ECRC_GEN_CAPABLE                 : boolean;
640
      AER_CAP_ID                               : bit_vector;
641
      AER_CAP_INT_MSG_NUM_MSI                  : bit_vector;
642
      AER_CAP_INT_MSG_NUM_MSIX                 : bit_vector;
643
      AER_CAP_NEXTPTR                          : bit_vector;
644
      AER_CAP_ON                               : boolean;
645
      AER_CAP_PERMIT_ROOTERR_UPDATE            : boolean;
646
      AER_CAP_VERSION                          : bit_vector;
647
      ALLOW_X8_GEN2                            : boolean;
648
      BAR0                                     : bit_vector;
649
      BAR1                                     : bit_vector;
650
      BAR2                                     : bit_vector;
651
      BAR3                                     : bit_vector;
652
      BAR4                                     : bit_vector;
653
      BAR5                                     : bit_vector;
654
      CAPABILITIES_PTR                         : bit_vector;
655
      CARDBUS_CIS_POINTER                      : bit_vector;
656
      CLASS_CODE                               : bit_vector;
657
      CMD_INTX_IMPLEMENTED                     : boolean;
658
      CPL_TIMEOUT_DISABLE_SUPPORTED            : boolean;
659
      CPL_TIMEOUT_RANGES_SUPPORTED             : bit_vector;
660
      CRM_MODULE_RSTS                          : bit_vector;
661
      DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE      : boolean;
662
      DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE      : boolean;
663
      DEV_CAP_ENDPOINT_L0S_LATENCY             : integer;
664
      DEV_CAP_ENDPOINT_L1_LATENCY              : integer;
665
      DEV_CAP_EXT_TAG_SUPPORTED                : boolean;
666
      DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE     : boolean;
667
      DEV_CAP_MAX_PAYLOAD_SUPPORTED            : integer;
668
      DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT        : integer;
669
      DEV_CAP_ROLE_BASED_ERROR                 : boolean;
670
      DEV_CAP_RSVD_14_12                       : integer;
671
      DEV_CAP_RSVD_17_16                       : integer;
672
      DEV_CAP_RSVD_31_29                       : integer;
673
      DEV_CONTROL_AUX_POWER_SUPPORTED          : boolean;
674
      DEVICE_ID                                : bit_vector;
675
      DISABLE_ASPM_L1_TIMER                    : boolean;
676
      DISABLE_BAR_FILTERING                    : boolean;
677
      DISABLE_ID_CHECK                         : boolean;
678
      DISABLE_LANE_REVERSAL                    : boolean;
679
      DISABLE_RX_TC_FILTER                     : boolean;
680
      DISABLE_SCRAMBLING                       : boolean;
681
      DNSTREAM_LINK_NUM                        : bit_vector;
682
      DSN_BASE_PTR                             : bit_vector;
683
      DSN_CAP_ID                               : bit_vector;
684
      DSN_CAP_NEXTPTR                          : bit_vector;
685
      DSN_CAP_ON                               : boolean;
686
      DSN_CAP_VERSION                          : bit_vector;
687
      ENABLE_MSG_ROUTE                         : bit_vector;
688
      ENABLE_RX_TD_ECRC_TRIM                   : boolean;
689
      ENTER_RVRY_EI_L0                         : boolean;
690
      EXPANSION_ROM                            : bit_vector;
691
      EXT_CFG_CAP_PTR                          : bit_vector;
692
      EXT_CFG_XP_CAP_PTR                       : bit_vector;
693
      HEADER_TYPE                              : bit_vector;
694
      INFER_EI                                 : bit_vector;
695
      INTERRUPT_PIN                            : bit_vector;
696
      IS_SWITCH                                : boolean;
697
      LAST_CONFIG_DWORD                        : bit_vector;
698
      LINK_CAP_ASPM_SUPPORT                    : integer;
699
      LINK_CAP_CLOCK_POWER_MANAGEMENT          : boolean;
700
      LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP   : boolean;
701
      LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1    : integer;
702
      LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2    : integer;
703
      LINK_CAP_L0S_EXIT_LATENCY_GEN1           : integer;
704
      LINK_CAP_L0S_EXIT_LATENCY_GEN2           : integer;
705
      LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1     : integer;
706
      LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2     : integer;
707
      LINK_CAP_L1_EXIT_LATENCY_GEN1            : integer;
708
      LINK_CAP_L1_EXIT_LATENCY_GEN2            : integer;
709
      LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP : boolean;
710
      LINK_CAP_MAX_LINK_SPEED                  : bit_vector;
711
      LINK_CAP_MAX_LINK_WIDTH                  : bit_vector;
712
      LINK_CAP_RSVD_23_22                      : integer;
713
      LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE     : boolean;
714
      LINK_CONTROL_RCB                         : integer;
715
      LINK_CTRL2_DEEMPHASIS                    : boolean;
716
      LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE   : boolean;
717
      LINK_CTRL2_TARGET_LINK_SPEED             : bit_vector;
718
      LINK_STATUS_SLOT_CLOCK_CONFIG            : boolean;
719
      LL_ACK_TIMEOUT                           : bit_vector;
720
      LL_ACK_TIMEOUT_EN                        : boolean;
721
      LL_ACK_TIMEOUT_FUNC                      : integer;
722
      LL_REPLAY_TIMEOUT                        : bit_vector;
723
      LL_REPLAY_TIMEOUT_EN                     : boolean;
724
      LL_REPLAY_TIMEOUT_FUNC                   : integer;
725
      LTSSM_MAX_LINK_WIDTH                     : bit_vector;
726
      MSI_BASE_PTR                             : bit_vector;
727
      MSI_CAP_ID                               : bit_vector;
728
      MSI_CAP_MULTIMSGCAP                      : integer;
729
      MSI_CAP_MULTIMSG_EXTENSION               : integer;
730
      MSI_CAP_NEXTPTR                          : bit_vector;
731
      MSI_CAP_ON                               : boolean;
732
      MSI_CAP_PER_VECTOR_MASKING_CAPABLE       : boolean;
733
      MSI_CAP_64_BIT_ADDR_CAPABLE              : boolean;
734
      MSIX_BASE_PTR                            : bit_vector;
735
      MSIX_CAP_ID                              : bit_vector;
736
      MSIX_CAP_NEXTPTR                         : bit_vector;
737
      MSIX_CAP_ON                              : boolean;
738
      MSIX_CAP_PBA_BIR                         : integer;
739
      MSIX_CAP_PBA_OFFSET                      : bit_vector;
740
      MSIX_CAP_TABLE_BIR                       : integer;
741
      MSIX_CAP_TABLE_OFFSET                    : bit_vector;
742
      MSIX_CAP_TABLE_SIZE                      : bit_vector;
743
      N_FTS_COMCLK_GEN1                        : integer;
744
      N_FTS_COMCLK_GEN2                        : integer;
745
      N_FTS_GEN1                               : integer;
746
      N_FTS_GEN2                               : integer;
747
      PCIE_BASE_PTR                            : bit_vector;
748
      PCIE_CAP_CAPABILITY_ID                   : bit_vector;
749
      PCIE_CAP_CAPABILITY_VERSION              : bit_vector;
750
      PCIE_CAP_DEVICE_PORT_TYPE                : bit_vector;
751
      PCIE_CAP_INT_MSG_NUM                     : bit_vector;
752
      PCIE_CAP_NEXTPTR                         : bit_vector;
753
      PCIE_CAP_ON                              : boolean;
754
      PCIE_CAP_RSVD_15_14                      : integer;
755
      PCIE_CAP_SLOT_IMPLEMENTED                : boolean;
756
      PCIE_REVISION                            : integer;
757
      PGL0_LANE                                : integer;
758
      PGL1_LANE                                : integer;
759
      PGL2_LANE                                : integer;
760
      PGL3_LANE                                : integer;
761
      PGL4_LANE                                : integer;
762
      PGL5_LANE                                : integer;
763
      PGL6_LANE                                : integer;
764
      PGL7_LANE                                : integer;
765
      PL_AUTO_CONFIG                           : integer;
766
      PL_FAST_TRAIN                            : boolean;
767
      PM_BASE_PTR                              : bit_vector;
768
      PM_CAP_AUXCURRENT                        : integer;
769
      PM_CAP_DSI                               : boolean;
770
      PM_CAP_D1SUPPORT                         : boolean;
771
      PM_CAP_D2SUPPORT                         : boolean;
772
      PM_CAP_ID                                : bit_vector;
773
      PM_CAP_NEXTPTR                           : bit_vector;
774
      PM_CAP_ON                                : boolean;
775
      PM_CAP_PME_CLOCK                         : boolean;
776
      PM_CAP_PMESUPPORT                        : bit_vector;
777
      PM_CAP_RSVD_04                           : integer;
778
      PM_CAP_VERSION                           : integer;
779
      PM_CSR_BPCCEN                            : boolean;
780
      PM_CSR_B2B3                              : boolean;
781
      PM_CSR_NOSOFTRST                         : boolean;
782
      PM_DATA0                                 : bit_vector;
783
      PM_DATA1                                 : bit_vector;
784
      PM_DATA2                                 : bit_vector;
785
      PM_DATA3                                 : bit_vector;
786
      PM_DATA4                                 : bit_vector;
787
      PM_DATA5                                 : bit_vector;
788
      PM_DATA6                                 : bit_vector;
789
      PM_DATA7                                 : bit_vector;
790
      PM_DATA_SCALE0                           : bit_vector;
791
      PM_DATA_SCALE1                           : bit_vector;
792
      PM_DATA_SCALE2                           : bit_vector;
793
      PM_DATA_SCALE3                           : bit_vector;
794
      PM_DATA_SCALE4                           : bit_vector;
795
      PM_DATA_SCALE5                           : bit_vector;
796
      PM_DATA_SCALE6                           : bit_vector;
797
      PM_DATA_SCALE7                           : bit_vector;
798
      RECRC_CHK                                : integer;
799
      RECRC_CHK_TRIM                           : boolean;
800
      REVISION_ID                              : bit_vector;
801
      ROOT_CAP_CRS_SW_VISIBILITY               : boolean;
802
      SELECT_DLL_IF                            : boolean;
803
      SLOT_CAP_ATT_BUTTON_PRESENT              : boolean;
804
      SLOT_CAP_ATT_INDICATOR_PRESENT           : boolean;
805
      SLOT_CAP_ELEC_INTERLOCK_PRESENT          : boolean;
806
      SLOT_CAP_HOTPLUG_CAPABLE                 : boolean;
807
      SLOT_CAP_HOTPLUG_SURPRISE                : boolean;
808
      SLOT_CAP_MRL_SENSOR_PRESENT              : boolean;
809
      SLOT_CAP_NO_CMD_COMPLETED_SUPPORT        : boolean;
810
      SLOT_CAP_PHYSICAL_SLOT_NUM               : bit_vector;
811
      SLOT_CAP_POWER_CONTROLLER_PRESENT        : boolean;
812
      SLOT_CAP_POWER_INDICATOR_PRESENT         : boolean;
813
      SLOT_CAP_SLOT_POWER_LIMIT_SCALE          : integer;
814
      SLOT_CAP_SLOT_POWER_LIMIT_VALUE          : bit_vector;
815
      SPARE_BIT0                               : integer;
816
      SPARE_BIT1                               : integer;
817
      SPARE_BIT2                               : integer;
818
      SPARE_BIT3                               : integer;
819
      SPARE_BIT4                               : integer;
820
      SPARE_BIT5                               : integer;
821
      SPARE_BIT6                               : integer;
822
      SPARE_BIT7                               : integer;
823
      SPARE_BIT8                               : integer;
824
      SPARE_BYTE0                              : bit_vector;
825
      SPARE_BYTE1                              : bit_vector;
826
      SPARE_BYTE2                              : bit_vector;
827
      SPARE_BYTE3                              : bit_vector;
828
      SPARE_WORD0                              : bit_vector;
829
      SPARE_WORD1                              : bit_vector;
830
      SPARE_WORD2                              : bit_vector;
831
      SPARE_WORD3                              : bit_vector;
832
      SUBSYSTEM_ID                             : bit_vector;
833
      SUBSYSTEM_VENDOR_ID                      : bit_vector;
834
      TL_RBYPASS                               : boolean;
835
      TL_RX_RAM_RADDR_LATENCY                  : integer;
836
      TL_RX_RAM_RDATA_LATENCY                  : integer;
837
      TL_RX_RAM_WRITE_LATENCY                  : integer;
838
      TL_TFC_DISABLE                           : boolean;
839
      TL_TX_CHECKS_DISABLE                     : boolean;
840
      TL_TX_RAM_RADDR_LATENCY                  : integer;
841
      TL_TX_RAM_RDATA_LATENCY                  : integer;
842
      TL_TX_RAM_WRITE_LATENCY                  : integer;
843
      UPCONFIG_CAPABLE                         : boolean;
844
      UPSTREAM_FACING                          : boolean;
845
      UR_INV_REQ                               : boolean;
846
      USER_CLK_FREQ                            : integer;
847
      EXIT_LOOPBACK_ON_EI                      : boolean;
848
      VC_BASE_PTR                              : bit_vector;
849
      VC_CAP_ID                                : bit_vector;
850
      VC_CAP_NEXTPTR                           : bit_vector;
851
      VC_CAP_ON                                : boolean;
852
      VC_CAP_REJECT_SNOOP_TRANSACTIONS         : boolean;
853
      VC_CAP_VERSION                           : bit_vector;
854
      VC0_CPL_INFINITE                         : boolean;
855
      VC0_RX_RAM_LIMIT                         : bit_vector;
856
      VC0_TOTAL_CREDITS_CD                     : integer;
857
      VC0_TOTAL_CREDITS_CH                     : integer;
858
      VC0_TOTAL_CREDITS_NPH                    : integer;
859
      VC0_TOTAL_CREDITS_PD                     : integer;
860
      VC0_TOTAL_CREDITS_PH                     : integer;
861
      VC0_TX_LASTPACKET                        : integer;
862
      VENDOR_ID                                : bit_vector;
863
      VSEC_BASE_PTR                            : bit_vector;
864
      VSEC_CAP_HDR_ID                          : bit_vector;
865
      VSEC_CAP_HDR_LENGTH                      : bit_vector;
866
      VSEC_CAP_HDR_REVISION                    : bit_vector;
867
      VSEC_CAP_ID                              : bit_vector;
868
      VSEC_CAP_IS_LINK_VISIBLE                 : boolean;
869
      VSEC_CAP_NEXTPTR                         : bit_vector;
870
      VSEC_CAP_ON                              : boolean;
871
      VSEC_CAP_VERSION                         : bit_vector);
872
    port (
873
      PCIEXPRXN                           : in  std_logic_vector(3 downto 0);
874
      PCIEXPRXP                           : in  std_logic_vector(3 downto 0);
875
      PCIEXPTXN                           : out std_logic_vector(3 downto 0);
876
      PCIEXPTXP                           : out std_logic_vector(3 downto 0);
877
      SYSCLK                              : in  std_logic;
878
      FUNDRSTN                            : in  std_logic;
879
      TRNLNKUPN                           : out std_logic;
880
      PHYRDYN                             : out std_logic;
881
      USERRSTN                            : out std_logic;
882
      RECEIVEDFUNCLVLRSTN                 : out std_logic;
883
      LNKCLKEN                            : out std_logic;
884
      SYSRSTN                             : in  std_logic;
885
      PLRSTN                              : in  std_logic;
886
      DLRSTN                              : in  std_logic;
887
      TLRSTN                              : in  std_logic;
888
      FUNCLVLRSTN                         : in  std_logic;
889
      CMRSTN                              : in  std_logic;
890
      CMSTICKYRSTN                        : in  std_logic;
891
      TRNRBARHITN                         : out std_logic_vector(6 downto 0);
892
      TRNRD                               : out std_logic_vector(63 downto 0);
893
      TRNRECRCERRN                        : out std_logic;
894
      TRNREOFN                            : out std_logic;
895
      TRNRERRFWDN                         : out std_logic;
896
      TRNRREMN                            : out std_logic;
897
      TRNRSOFN                            : out std_logic;
898
      TRNRSRCDSCN                         : out std_logic;
899
      TRNRSRCRDYN                         : out std_logic;
900
      TRNRDSTRDYN                         : in  std_logic;
901
      TRNRNPOKN                           : in  std_logic;
902
      TRNRDLLPDATA                        : out std_logic_vector(31 downto 0);
903
      TRNRDLLPSRCRDYN                     : out std_logic;
904
      TRNTBUFAV                           : out std_logic_vector(5 downto 0);
905
      TRNTCFGREQN                         : out std_logic;
906
      TRNTDLLPDSTRDYN                     : out std_logic;
907
      TRNTDSTRDYN                         : out std_logic;
908
      TRNTERRDROPN                        : out std_logic;
909
      TRNTCFGGNTN                         : in  std_logic;
910
      TRNTD                               : in  std_logic_vector(63 downto 0);
911
      TRNTDLLPDATA                        : in  std_logic_vector(31 downto 0);
912
      TRNTDLLPSRCRDYN                     : in  std_logic;
913
      TRNTECRCGENN                        : in  std_logic;
914
      TRNTEOFN                            : in  std_logic;
915
      TRNTERRFWDN                         : in  std_logic;
916
      TRNTREMN                            : in  std_logic;
917
      TRNTSOFN                            : in  std_logic;
918
      TRNTSRCDSCN                         : in  std_logic;
919
      TRNTSRCRDYN                         : in  std_logic;
920
      TRNTSTRN                            : in  std_logic;
921
      TRNFCCPLD                           : out std_logic_vector(11 downto 0);
922
      TRNFCCPLH                           : out std_logic_vector(7 downto 0);
923
      TRNFCNPD                            : out std_logic_vector(11 downto 0);
924
      TRNFCNPH                            : out std_logic_vector(7 downto 0);
925
      TRNFCPD                             : out std_logic_vector(11 downto 0);
926
      TRNFCPH                             : out std_logic_vector(7 downto 0);
927
      TRNFCSEL                            : in  std_logic_vector(2 downto 0);
928
      CFGAERECRCCHECKEN                   : out std_logic;
929
      CFGAERECRCGENEN                     : out std_logic;
930
      CFGCOMMANDBUSMASTERENABLE           : out std_logic;
931
      CFGCOMMANDINTERRUPTDISABLE          : out std_logic;
932
      CFGCOMMANDIOENABLE                  : out std_logic;
933
      CFGCOMMANDMEMENABLE                 : out std_logic;
934
      CFGCOMMANDSERREN                    : out std_logic;
935
      CFGDEVCONTROLAUXPOWEREN             : out std_logic;
936
      CFGDEVCONTROLCORRERRREPORTINGEN     : out std_logic;
937
      CFGDEVCONTROLENABLERO               : out std_logic;
938
      CFGDEVCONTROLEXTTAGEN               : out std_logic;
939
      CFGDEVCONTROLFATALERRREPORTINGEN    : out std_logic;
940
      CFGDEVCONTROLMAXPAYLOAD             : out std_logic_vector(2 downto 0);
941
      CFGDEVCONTROLMAXREADREQ             : out std_logic_vector(2 downto 0);
942
      CFGDEVCONTROLNONFATALREPORTINGEN    : out std_logic;
943
      CFGDEVCONTROLNOSNOOPEN              : out std_logic;
944
      CFGDEVCONTROLPHANTOMEN              : out std_logic;
945
      CFGDEVCONTROLURERRREPORTINGEN       : out std_logic;
946
      CFGDEVCONTROL2CPLTIMEOUTDIS         : out std_logic;
947
      CFGDEVCONTROL2CPLTIMEOUTVAL         : out std_logic_vector(3 downto 0);
948
      CFGDEVSTATUSCORRERRDETECTED         : out std_logic;
949
      CFGDEVSTATUSFATALERRDETECTED        : out std_logic;
950
      CFGDEVSTATUSNONFATALERRDETECTED     : out std_logic;
951
      CFGDEVSTATUSURDETECTED              : out std_logic;
952
      CFGDO                               : out std_logic_vector(31 downto 0);
953
      CFGERRAERHEADERLOGSETN              : out std_logic;
954
      CFGERRCPLRDYN                       : out std_logic;
955
      CFGINTERRUPTDO                      : out std_logic_vector(7 downto 0);
956
      CFGINTERRUPTMMENABLE                : out std_logic_vector(2 downto 0);
957
      CFGINTERRUPTMSIENABLE               : out std_logic;
958
      CFGINTERRUPTMSIXENABLE              : out std_logic;
959
      CFGINTERRUPTMSIXFM                  : out std_logic;
960
      CFGINTERRUPTRDYN                    : out std_logic;
961
      CFGLINKCONTROLRCB                   : out std_logic;
962
      CFGLINKCONTROLASPMCONTROL           : out std_logic_vector(1 downto 0);
963
      CFGLINKCONTROLAUTOBANDWIDTHINTEN    : out std_logic;
964
      CFGLINKCONTROLBANDWIDTHINTEN        : out std_logic;
965
      CFGLINKCONTROLCLOCKPMEN             : out std_logic;
966
      CFGLINKCONTROLCOMMONCLOCK           : out std_logic;
967
      CFGLINKCONTROLEXTENDEDSYNC          : out std_logic;
968
      CFGLINKCONTROLHWAUTOWIDTHDIS        : out std_logic;
969
      CFGLINKCONTROLLINKDISABLE           : out std_logic;
970
      CFGLINKCONTROLRETRAINLINK           : out std_logic;
971
      CFGLINKSTATUSAUTOBANDWIDTHSTATUS    : out std_logic;
972
      CFGLINKSTATUSBANDWITHSTATUS         : out std_logic;
973
      CFGLINKSTATUSCURRENTSPEED           : out std_logic_vector(1 downto 0);
974
      CFGLINKSTATUSDLLACTIVE              : out std_logic;
975
      CFGLINKSTATUSLINKTRAINING           : out std_logic;
976
      CFGLINKSTATUSNEGOTIATEDWIDTH        : out std_logic_vector(3 downto 0);
977
      CFGMSGDATA                          : out std_logic_vector(15 downto 0);
978
      CFGMSGRECEIVED                      : out std_logic;
979
      CFGMSGRECEIVEDASSERTINTA            : out std_logic;
980
      CFGMSGRECEIVEDASSERTINTB            : out std_logic;
981
      CFGMSGRECEIVEDASSERTINTC            : out std_logic;
982
      CFGMSGRECEIVEDASSERTINTD            : out std_logic;
983
      CFGMSGRECEIVEDDEASSERTINTA          : out std_logic;
984
      CFGMSGRECEIVEDDEASSERTINTB          : out std_logic;
985
      CFGMSGRECEIVEDDEASSERTINTC          : out std_logic;
986
      CFGMSGRECEIVEDDEASSERTINTD          : out std_logic;
987
      CFGMSGRECEIVEDERRCOR                : out std_logic;
988
      CFGMSGRECEIVEDERRFATAL              : out std_logic;
989
      CFGMSGRECEIVEDERRNONFATAL           : out std_logic;
990
      CFGMSGRECEIVEDPMASNAK               : out std_logic;
991
      CFGMSGRECEIVEDPMETO                 : out std_logic;
992
      CFGMSGRECEIVEDPMETOACK              : out std_logic;
993
      CFGMSGRECEIVEDPMPME                 : out std_logic;
994
      CFGMSGRECEIVEDSETSLOTPOWERLIMIT     : out std_logic;
995
      CFGMSGRECEIVEDUNLOCK                : out std_logic;
996
      CFGPCIELINKSTATE                    : out std_logic_vector(2 downto 0);
997
      CFGPMCSRPMEEN                       : out std_logic;
998
      CFGPMCSRPMESTATUS                   : out std_logic;
999
      CFGPMCSRPOWERSTATE                  : out std_logic_vector(1 downto 0);
1000
      CFGPMRCVASREQL1N                    : out std_logic;
1001
      CFGPMRCVENTERL1N                    : out std_logic;
1002
      CFGPMRCVENTERL23N                   : out std_logic;
1003
      CFGPMRCVREQACKN                     : out std_logic;
1004
      CFGRDWRDONEN                        : out std_logic;
1005
      CFGSLOTCONTROLELECTROMECHILCTLPULSE : out std_logic;
1006
      CFGTRANSACTION                      : out std_logic;
1007
      CFGTRANSACTIONADDR                  : out std_logic_vector(6 downto 0);
1008
      CFGTRANSACTIONTYPE                  : out std_logic;
1009
      CFGVCTCVCMAP                        : out std_logic_vector(6 downto 0);
1010
      CFGBYTEENN                          : in  std_logic_vector(3 downto 0);
1011
      CFGDI                               : in  std_logic_vector(31 downto 0);
1012
      CFGDSBUSNUMBER                      : in  std_logic_vector(7 downto 0);
1013
      CFGDSDEVICENUMBER                   : in  std_logic_vector(4 downto 0);
1014
      CFGDSFUNCTIONNUMBER                 : in  std_logic_vector(2 downto 0);
1015
      CFGDSN                              : in  std_logic_vector(63 downto 0);
1016
      CFGDWADDR                           : in  std_logic_vector(9 downto 0);
1017
      CFGERRACSN                          : in  std_logic;
1018
      CFGERRAERHEADERLOG                  : in  std_logic_vector(127 downto 0);
1019
      CFGERRCORN                          : in  std_logic;
1020
      CFGERRCPLABORTN                     : in  std_logic;
1021
      CFGERRCPLTIMEOUTN                   : in  std_logic;
1022
      CFGERRCPLUNEXPECTN                  : in  std_logic;
1023
      CFGERRECRCN                         : in  std_logic;
1024
      CFGERRLOCKEDN                       : in  std_logic;
1025
      CFGERRPOSTEDN                       : in  std_logic;
1026
      CFGERRTLPCPLHEADER                  : in  std_logic_vector(47 downto 0);
1027
      CFGERRURN                           : in  std_logic;
1028
      CFGINTERRUPTASSERTN                 : in  std_logic;
1029
      CFGINTERRUPTDI                      : in  std_logic_vector(7 downto 0);
1030
      CFGINTERRUPTN                       : in  std_logic;
1031
      CFGPMDIRECTASPML1N                  : in  std_logic;
1032
      CFGPMSENDPMACKN                     : in  std_logic;
1033
      CFGPMSENDPMETON                     : in  std_logic;
1034
      CFGPMSENDPMNAKN                     : in  std_logic;
1035
      CFGPMTURNOFFOKN                     : in  std_logic;
1036
      CFGPMWAKEN                          : in  std_logic;
1037
      CFGPORTNUMBER                       : in  std_logic_vector(7 downto 0);
1038
      CFGRDENN                            : in  std_logic;
1039
      CFGTRNPENDINGN                      : in  std_logic;
1040
      CFGWRENN                            : in  std_logic;
1041
      CFGWRREADONLYN                      : in  std_logic;
1042
      CFGWRRW1CASRWN                      : in  std_logic;
1043
      PLINITIALLINKWIDTH                  : out std_logic_vector(2 downto 0);
1044
      PLLANEREVERSALMODE                  : out std_logic_vector(1 downto 0);
1045
      PLLINKGEN2CAP                       : out std_logic;
1046
      PLLINKPARTNERGEN2SUPPORTED          : out std_logic;
1047
      PLLINKUPCFGCAP                      : out std_logic;
1048
      PLLTSSMSTATE                        : out std_logic_vector(5 downto 0);
1049
      PLPHYLNKUPN                         : out std_logic;
1050
      PLRECEIVEDHOTRST                    : out std_logic;
1051
      PLRXPMSTATE                         : out std_logic_vector(1 downto 0);
1052
      PLSELLNKRATE                        : out std_logic;
1053
      PLSELLNKWIDTH                       : out std_logic_vector(1 downto 0);
1054
      PLTXPMSTATE                         : out std_logic_vector(2 downto 0);
1055
      PLDIRECTEDLINKAUTON                 : in  std_logic;
1056
      PLDIRECTEDLINKCHANGE                : in  std_logic_vector(1 downto 0);
1057
      PLDIRECTEDLINKSPEED                 : in  std_logic;
1058
      PLDIRECTEDLINKWIDTH                 : in  std_logic_vector(1 downto 0);
1059
      PLDOWNSTREAMDEEMPHSOURCE            : in  std_logic;
1060
      PLUPSTREAMPREFERDEEMPH              : in  std_logic;
1061
      PLTRANSMITHOTRST                    : in  std_logic;
1062
      DBGSCLRA                            : out std_logic;
1063
      DBGSCLRB                            : out std_logic;
1064
      DBGSCLRC                            : out std_logic;
1065
      DBGSCLRD                            : out std_logic;
1066
      DBGSCLRE                            : out std_logic;
1067
      DBGSCLRF                            : out std_logic;
1068
      DBGSCLRG                            : out std_logic;
1069
      DBGSCLRH                            : out std_logic;
1070
      DBGSCLRI                            : out std_logic;
1071
      DBGSCLRJ                            : out std_logic;
1072
      DBGSCLRK                            : out std_logic;
1073
      DBGVECA                             : out std_logic_vector(63 downto 0);
1074
      DBGVECB                             : out std_logic_vector(63 downto 0);
1075
      DBGVECC                             : out std_logic_vector(11 downto 0);
1076
      PLDBGVEC                            : out std_logic_vector(11 downto 0);
1077
      DBGMODE                             : in  std_logic_vector(1 downto 0);
1078
      DBGSUBMODE                          : in  std_logic;
1079
      PLDBGMODE                           : in  std_logic_vector(2 downto 0);
1080
      PCIEDRPDO                           : out std_logic_vector(15 downto 0);
1081
      PCIEDRPDRDY                         : out std_logic;
1082
      PCIEDRPCLK                          : in  std_logic;
1083
      PCIEDRPDADDR                        : in  std_logic_vector(8 downto 0);
1084
      PCIEDRPDEN                          : in  std_logic;
1085
      PCIEDRPDI                           : in  std_logic_vector(15 downto 0);
1086
      PCIEDRPDWE                          : in  std_logic;
1087
      GTPLLLOCK                           : out std_logic;
1088
      PIPECLK                             : in  std_logic;
1089
      USERCLK                             : in  std_logic;
1090
      DRPCLK                              : in  std_logic;
1091
      CLOCKLOCKED                         : in  std_logic;
1092
      TxOutClk                            : out std_logic);
1093
   end component;
1094
 
1095
   function to_integer (
1096
      val_in    : bit_vector) return integer is
1097
 
1098
      constant vctr   : bit_vector(val_in'high-val_in'low downto 0) := val_in;
1099
      variable ret    : integer := 0;
1100
   begin
1101
      for index in vctr'range loop
1102
         if (vctr(index) = '1') then
1103
            ret := ret + (2**index);
1104
         end if;
1105
      end loop;
1106
      return(ret);
1107
   end to_integer;
1108
 
1109
   function to_stdlogic (
1110
      in_val      : in boolean) return std_logic is
1111
   begin
1112
      if (in_val) then
1113
         return('1');
1114
      else
1115
         return('0');
1116
      end if;
1117
   end to_stdlogic;
1118
 
1119
   function pad_gen (
1120
      in_vec   : bit_vector;
1121
      op_len   : integer)
1122
      return bit_vector is
1123
      variable ret : bit_vector(op_len-1 downto 0) := (others => '0');
1124
      constant len : integer := in_vec'length;  -- length of input vector
1125
   begin  -- pad_gen
1126
      for i in 0 to op_len-1 loop
1127
         if (i < len) then
1128
            ret(i) := in_vec(len-i-1);
1129
         else
1130
            ret(i) := '0';
1131
         end if;
1132
      end loop;  -- i
1133
      return ret;
1134
   end pad_gen;
1135
 
1136
   constant LINK_CAP_MAX_LINK_SPEED_int : integer := to_integer(LINK_CAP_MAX_LINK_SPEED);
1137
 
1138
   signal rx_func_level_reset_n                       : std_logic;
1139
   signal cfg_msg_received                            : std_logic;
1140
   signal cfg_msg_received_pme_to                     : std_logic;
1141
 
1142
   signal cfg_cmd_bme                                 : std_logic;
1143
   signal cfg_cmd_intdis                              : std_logic;
1144
   signal cfg_cmd_io_en                               : std_logic;
1145
   signal cfg_cmd_mem_en                              : std_logic;
1146
   signal cfg_cmd_serr_en                             : std_logic;
1147
   signal cfg_dev_control_aux_power_en                : std_logic;
1148
   signal cfg_dev_control_corr_err_reporting_en       : std_logic;
1149
   signal cfg_dev_control_enable_relaxed_order        : std_logic;
1150
   signal cfg_dev_control_ext_tag_en                  : std_logic;
1151
   signal cfg_dev_control_fatal_err_reporting_en      : std_logic;
1152
   signal cfg_dev_control_maxpayload                  : std_logic_vector(2 downto 0);
1153
   signal cfg_dev_control_max_read_req                : std_logic_vector(2 downto 0);
1154
   signal cfg_dev_control_non_fatal_reporting_en      : std_logic;
1155
   signal cfg_dev_control_nosnoop_en                  : std_logic;
1156
   signal cfg_dev_control_phantom_en                  : std_logic;
1157
   signal cfg_dev_control_ur_err_reporting_en         : std_logic;
1158
   signal cfg_dev_control2_cpltimeout_dis             : std_logic;
1159
   signal cfg_dev_control2_cpltimeout_val             : std_logic_vector(3 downto 0);
1160
   signal cfg_dev_status_corr_err_detected            : std_logic;
1161
   signal cfg_dev_status_fatal_err_detected           : std_logic;
1162
   signal cfg_dev_status_nonfatal_err_detected        : std_logic;
1163
   signal cfg_dev_status_ur_detected                  : std_logic;
1164
   signal cfg_link_control_auto_bandwidth_int_en      : std_logic;
1165
   signal cfg_link_control_bandwidth_int_en           : std_logic;
1166
   signal cfg_link_control_hw_auto_width_dis          : std_logic;
1167
   signal cfg_link_control_clock_pm_en                : std_logic;
1168
   signal cfg_link_control_extended_sync              : std_logic;
1169
   signal cfg_link_control_common_clock               : std_logic;
1170
   signal cfg_link_control_retrain_link               : std_logic;
1171
   signal cfg_link_control_linkdisable                : std_logic;
1172
   signal cfg_link_control_rcb                        : std_logic;
1173
   signal cfg_link_control_aspm_control               : std_logic_vector(1 downto 0);
1174
   signal cfg_link_status_autobandwidth_status        : std_logic;
1175
   signal cfg_link_status_bandwidth_status            : std_logic;
1176
   signal cfg_link_status_dll_active                  : std_logic;
1177
   signal cfg_link_status_link_training               : std_logic;
1178
   signal cfg_link_status_negotiated_link_width       : std_logic_vector(3 downto 0);
1179
   signal cfg_link_status_current_speed               : std_logic_vector(1 downto 0);
1180
   signal cfg_msg_data                                : std_logic_vector(15 downto 0);
1181
 
1182
   signal sys_reset_n                                 : std_logic;
1183
   signal sys_reset_n_d                               : std_logic;
1184
   signal phy_rdy_n                                   : std_logic;
1185
 
1186
   signal TxOutClk                                    : std_logic;
1187
   signal TxOutClk_bufg                               : std_logic;
1188
 
1189
   signal cfg_bus_number_d                            : std_logic_vector(7 downto 0);
1190
   signal cfg_device_number_d                         : std_logic_vector(4 downto 0);
1191
   signal cfg_function_number_d                       : std_logic_vector(2 downto 0);
1192
 
1193
   signal trn_rdllp_data                              : std_logic_vector(31 downto 0);
1194
   signal trn_rdllp_src_rdy_n                         : std_logic;
1195
   signal trn_rdllp_src_rdy                           : std_logic;
1196
 
1197
   -- assigns to outputs
1198
 
1199
   signal gt_pll_lock                                 : std_logic;
1200
 
1201
   signal pipe_clk                                    : std_logic;
1202
   signal user_clk                                    : std_logic;
1203
   signal clock_locked                                : std_logic;
1204
   signal phy_rdy                                     : std_logic;
1205
 
1206
   signal drp_clk                                     : std_logic;
1207
 
1208
   signal trn_reset_n_d                               : std_logic;
1209
   signal sys_reset_d                                 : std_logic;
1210
   signal trn_reset_n                                 : std_logic;
1211
   signal trn_reset_n_int1                            : std_logic;
1212
   signal trn_reset_n_1_d                             : std_logic;
1213
   signal trn_lnk_up_n                                : std_logic;
1214
   signal trn_lnk_up_n_1                              : std_logic;
1215
   signal user_reset_out_int                          : std_logic;
1216
   signal user_lnk_up_int                             : std_logic;
1217
   signal user_lnk_up_d                               : std_logic;
1218
   signal tx_cfg_req_int                              : std_logic;
1219
   signal cfg_pcie_link_state_int                     : std_logic_vector(2 downto 0);
1220
   signal cfg_pmcsr_powerstate_int                    : std_logic_vector(1 downto 0);
1221
   signal cfg_to_turnoff_int                          : std_logic;
1222
 
1223
   -- Declare intermediate signals for referenced outputs
1224
   signal trn_tcfg_req_n                              : std_logic;
1225
   signal trn_tcfg_gnt_n                              : std_logic;
1226
   signal trn_tcfg_gnt                                : std_logic;
1227
   signal trn_terr_drop_n                             : std_logic;
1228
   signal trn_rdst_rdy_n                              : std_logic;
1229
   signal trn_rnp_ok_n                                : std_logic;
1230
   signal trn_tdst_rdy_n                              : std_logic;
1231
--   signal trn_tdst_rdy                                : std_logic;
1232
--   signal trn_rd                                      : std_logic_vector(63 downto 0);
1233
   signal trn_rrem_n                                  : std_logic;
1234
--   signal trn_rrem                                    : std_logic_vector(0 downto 0);
1235
--   signal trn_td                                      : std_logic_vector(63 downto 0);
1236
   signal trn_trem_n                                  : std_logic;
1237
--   signal trn_trem                                    : std_logic_vector(0 downto 0);
1238
   signal trn_rsof_n                                  : std_logic;
1239
   signal trn_reof_n                                  : std_logic;
1240
   signal trn_rsrc_rdy_n                              : std_logic;
1241
   signal trn_rsrc_dsc_n                              : std_logic;
1242
   signal trn_rerrfwd_n                               : std_logic;
1243
   signal trn_rbar_hit_n                              : std_logic_vector(6 downto 0);
1244
   signal trn_recrc_err_n                             : std_logic;
1245
--   signal trn_rsof                                    : std_logic;
1246
--   signal trn_reof                                    : std_logic;
1247
--   signal trn_rsrc_rdy                                : std_logic;
1248
--   signal trn_rdst_rdy                                : std_logic;
1249
--   signal trn_rsrc_dsc                                : std_logic;
1250
--   signal trn_rerrfwd                                 : std_logic;
1251
--   signal trn_rbar_hit                                : std_logic_vector(6 downto 0);
1252
--   signal trn_recrc_err                               : std_logic;
1253
   signal trn_tsof_n                                  : std_logic;
1254
   signal trn_teof_n                                  : std_logic;
1255
   signal trn_tsrc_rdy_n                              : std_logic;
1256
   signal trn_tsrc_dsc_n                              : std_logic;
1257
   signal trn_terrfwd_n                               : std_logic;
1258
   signal trn_tstr_n                                  : std_logic;
1259
--   signal trn_tecrc_gen                               : std_logic;
1260
--   signal trn_tsof                                    : std_logic;
1261
--   signal trn_teof                                    : std_logic;
1262
--   signal trn_tsrc_rdy                                : std_logic;
1263
--   signal trn_tsrc_dsc                                : std_logic;
1264
--   signal trn_terrfwd                                 : std_logic;
1265
--   signal trn_tstr                                    : std_logic;
1266
   signal cfg_rd_wr_done_n                            : std_logic;
1267
   signal cfg_err_cpl_rdy_n                           : std_logic;
1268
   signal cfg_interrupt_rdy_n                         : std_logic;
1269
   signal cfg_byte_en_n                               : std_logic_vector(3 downto 0);
1270
   signal cfg_err_cor_n                               : std_logic;
1271
   signal cfg_err_cpl_abort_n                         : std_logic;
1272
   signal cfg_err_cpl_timeout_n                       : std_logic;
1273
   signal cfg_err_cpl_unexpect_n                      : std_logic;
1274
   signal cfg_err_ecrc_n                              : std_logic;
1275
   signal cfg_err_locked_n                            : std_logic;
1276
   signal cfg_err_posted_n                            : std_logic;
1277
   signal cfg_err_ur_n                                : std_logic;
1278
   signal cfg_interrupt_assert_n                      : std_logic;
1279
   signal cfg_interrupt_n                             : std_logic;
1280
   signal cfg_turnoff_ok_n                            : std_logic;
1281
   signal cfg_turnoff_ok_axi                          : std_logic;
1282
   signal cfg_pm_wake_n                               : std_logic;
1283
   signal cfg_rd_en_n                                 : std_logic;
1284
   signal cfg_trn_pending_n                           : std_logic;
1285
   signal cfg_wr_en_n                                 : std_logic;
1286
   signal tx_buf_av_int                               : std_logic_vector(5 downto 0);
1287
 
1288
   signal pl_sel_link_rate_int                        : std_logic;
1289
   signal pl_sel_link_width_int                       : std_logic_vector(1 downto 0);
1290
 
1291
   signal LINK_STATUS_SLOT_CLOCK_CONFIG_lstatus       : std_logic;
1292
 
1293
begin
1294
   -- Drive referenced outputs
1295
   user_clk_out           <= user_clk;
1296
   user_reset_out         <= user_reset_out_int;
1297
   user_lnk_up            <= user_lnk_up_int;
1298
   pl_sel_link_rate       <= pl_sel_link_rate_int;
1299
   pl_sel_link_width      <= pl_sel_link_width_int;
1300
   tx_buf_av              <= tx_buf_av_int;
1301
   tx_cfg_req_int         <= not(trn_tcfg_req_n);
1302
   tx_cfg_req             <= tx_cfg_req_int;
1303
   cfg_pcie_link_state    <= cfg_pcie_link_state_int;
1304
   cfg_pmcsr_powerstate   <= cfg_pmcsr_powerstate_int;
1305
   cfg_to_turnoff_int     <= cfg_msg_received_pme_to;
1306
   cfg_to_turnoff         <= cfg_to_turnoff_int;
1307
 
1308
   -- Invert outputs
1309
   tx_err_drop            <= not(trn_terr_drop_n);
1310
   cfg_rd_wr_done         <= not(cfg_rd_wr_done_n);
1311
   cfg_err_cpl_rdy        <= not(cfg_err_cpl_rdy_n);
1312
   cfg_interrupt_rdy      <= not(cfg_interrupt_rdy_n);
1313
   trn_tdst_rdy           <= not(trn_tdst_rdy_n);
1314
   trn_rsof               <= not(trn_rsof_n);
1315
   trn_reof               <= not(trn_reof_n);
1316
   trn_rrem(0)            <= not(trn_rrem_n);
1317
   trn_rsrc_rdy           <= not(trn_rsrc_rdy_n);
1318
   trn_rsrc_dsc           <= not(trn_rsrc_dsc_n);
1319
   trn_rerrfwd            <= not(trn_rerrfwd_n);
1320
   trn_rbar_hit           <= not(trn_rbar_hit_n);
1321
   trn_recrc_err          <= not(trn_recrc_err_n);
1322
   trn_rdllp_src_rdy      <= not(trn_rdllp_src_rdy_n);
1323
 
1324
   -- Invert inputs
1325
   cfg_byte_en_n          <= not(cfg_byte_en);
1326
   cfg_err_cor_n          <= not(cfg_err_cor);
1327
   cfg_err_cpl_abort_n    <= not(cfg_err_cpl_abort);
1328
   cfg_err_cpl_timeout_n  <= not(cfg_err_cpl_timeout);
1329
   cfg_err_cpl_unexpect_n <= not(cfg_err_cpl_unexpect);
1330
   cfg_err_ecrc_n         <= not(cfg_err_ecrc);
1331
   cfg_err_locked_n       <= not(cfg_err_locked);
1332
   cfg_err_posted_n       <= not(cfg_err_posted);
1333
   cfg_err_ur_n           <= not(cfg_err_ur);
1334
   cfg_interrupt_assert_n <= not(cfg_interrupt_assert);
1335
   cfg_interrupt_n        <= not(cfg_interrupt);
1336
   cfg_turnoff_ok_n       <= not(cfg_turnoff_ok_axi);
1337
   cfg_pm_wake_n          <= not(cfg_pm_wake);
1338
   cfg_rd_en_n            <= not(cfg_rd_en);
1339
   cfg_trn_pending_n      <= not(cfg_trn_pending);
1340
   cfg_wr_en_n            <= not(cfg_wr_en);
1341
   trn_tcfg_gnt_n         <= not(trn_tcfg_gnt);
1342
   trn_rdst_rdy_n         <= not(trn_rdst_rdy);
1343
   trn_rnp_ok_n           <= not(rx_np_ok);
1344
   trn_tsof_n             <= not(trn_tsof);
1345
   trn_teof_n             <= not(trn_teof);
1346
   trn_tsrc_rdy_n         <= not(trn_tsrc_rdy);
1347
   trn_tsrc_dsc_n         <= not(trn_tsrc_dsc);
1348
   trn_terrfwd_n          <= not(trn_terrfwd);
1349
   trn_trem_n             <= not(trn_trem(0));
1350
   trn_tstr_n             <= not(trn_tstr);
1351
 
1352
   LINK_STATUS_SLOT_CLOCK_CONFIG_lstatus <= '1' when (LINK_STATUS_SLOT_CLOCK_CONFIG) else '0';
1353
 
1354
   -- Calculated/concatenated oututs
1355
   cfg_status             <= "0000000000000000";
1356
   cfg_command            <= ("00000" &
1357
                              cfg_cmd_intdis &
1358
                              '0' &
1359
                              cfg_cmd_serr_en &
1360
                              "00000" &
1361
                              cfg_cmd_bme &
1362
                              cfg_cmd_mem_en &
1363
                              cfg_cmd_io_en);
1364
   cfg_dstatus            <= ("0000000000" &
1365
                              not(cfg_trn_pending_n) &
1366
                              '0' &
1367
                              cfg_dev_status_ur_detected &
1368
                              cfg_dev_status_fatal_err_detected &
1369
                              cfg_dev_status_nonfatal_err_detected &
1370
                              cfg_dev_status_corr_err_detected);
1371
   cfg_dcommand           <= ('0' &
1372
                              cfg_dev_control_max_read_req &
1373
                              cfg_dev_control_nosnoop_en &
1374
                              cfg_dev_control_aux_power_en &
1375
                              cfg_dev_control_phantom_en &
1376
                              cfg_dev_control_ext_tag_en &
1377
                              cfg_dev_control_maxpayload &
1378
                              cfg_dev_control_enable_relaxed_order &
1379
                              cfg_dev_control_ur_err_reporting_en &
1380
                              cfg_dev_control_fatal_err_reporting_en &
1381
                              cfg_dev_control_non_fatal_reporting_en &
1382
                              cfg_dev_control_corr_err_reporting_en);
1383
   cfg_lstatus            <= (cfg_link_status_autobandwidth_status &
1384
                              cfg_link_status_bandwidth_status &
1385
                              cfg_link_status_dll_active &
1386
                              LINK_STATUS_SLOT_CLOCK_CONFIG_lstatus &
1387
                              cfg_link_status_link_training &
1388
                              '0' &
1389
                              "00" &
1390
                              cfg_link_status_negotiated_link_width &
1391
                              "00" &
1392
                              cfg_link_status_current_speed);
1393
   cfg_lcommand           <= ("0000" &
1394
                              cfg_link_control_auto_bandwidth_int_en &
1395
                              cfg_link_control_bandwidth_int_en &
1396
                              cfg_link_control_hw_auto_width_dis &
1397
                              cfg_link_control_clock_pm_en &
1398
                              cfg_link_control_extended_sync &
1399
                              cfg_link_control_common_clock &
1400
                              cfg_link_control_retrain_link &
1401
                              cfg_link_control_linkdisable &
1402
                              cfg_link_control_rcb &
1403
                              '0' &
1404
                              cfg_link_control_aspm_control);
1405
   cfg_bus_number         <= cfg_bus_number_d;
1406
   cfg_device_number      <= cfg_device_number_d;
1407
   cfg_function_number    <= cfg_function_number_d;
1408
   cfg_dcommand2          <= ("00000000000" &
1409
                              cfg_dev_control2_cpltimeout_dis &
1410
                              cfg_dev_control2_cpltimeout_val);
1411
 
1412
   -- Capture Bus/Device/Function number
1413
 
1414
   process (user_clk)
1415
   begin
1416
      if (rising_edge(user_clk)) then
1417
         if (user_lnk_up_int = '0') then
1418
            cfg_bus_number_d       <= "00000000";
1419
            cfg_device_number_d    <= "00000";
1420
            cfg_function_number_d  <= "000";
1421
         elsif (cfg_msg_received = '0') then
1422
            cfg_bus_number_d       <= cfg_msg_data(15 downto 8);
1423
            cfg_device_number_d    <= cfg_msg_data(7 downto 3);
1424
            cfg_function_number_d  <= cfg_msg_data(2 downto 0);
1425
         end if;
1426
      end if;
1427
   end process;
1428
 
1429
   -- Generate user_lnk_up
1430
 
1431
   user_lnk_up_int_i : FDCP
1432
      generic map (
1433
         INIT  => '0'
1434
      )
1435
      port map (
1436
         Q    => user_lnk_up_int,
1437
         D    => user_lnk_up_d,
1438
         C    => user_clk,
1439
         CLR  => '0',
1440
         PRE  => '0'
1441
      );
1442
 
1443
   user_lnk_up_d <= not(trn_lnk_up_n_1);
1444
 
1445
   trn_lnk_up_n_1_i : FDCP
1446
      generic map (
1447
         INIT  => '1'
1448
      )
1449
      port map (
1450
         Q    => trn_lnk_up_n_1,
1451
         D    => trn_lnk_up_n,
1452
         C    => user_clk,
1453
         CLR  => '0',
1454
         PRE  => '0'
1455
      );
1456
 
1457
 
1458
   -- Generate user_reset_out
1459
 
1460
   trn_reset_n_d <= not(trn_reset_n_int1 and not(phy_rdy_n));
1461
   sys_reset_d   <= not(sys_reset_n_d);
1462
 
1463
   trn_reset_n_i : FDCP
1464
      generic map (
1465
         INIT  => '1'
1466
      )
1467
      port map (
1468
         Q    => user_reset_out_int,
1469
         D    => trn_reset_n_d,
1470
         C    => user_clk,
1471
         CLR  => sys_reset_d,
1472
         PRE  => '0'
1473
      );
1474
 
1475
 
1476
   trn_reset_n_1_d <= trn_reset_n and not(phy_rdy_n);
1477
   trn_reset_n_int_i : FDCP
1478
      generic map (
1479
         INIT  => '0'
1480
      )
1481
      port map (
1482
         Q    => trn_reset_n_int1,
1483
         D    => trn_reset_n_1_d,
1484
         C    => user_clk,
1485
         CLR  => sys_reset_d,
1486
         PRE  => '0'
1487
      );
1488
 
1489
 
1490
   ---------------------------------------------------------
1491
   -- AXI Basic Bridge
1492
   -- Converts between TRN and AXI
1493
   ---------------------------------------------------------
1494
 
1495
   axi_basic_top_i : axi_basic_top
1496
      generic map (
1497
         C_DATA_WIDTH     => 64,           -- RX/TX interface data width
1498
         C_REM_WIDTH      => 1,            -- trem/rrem width
1499
         C_STRB_WIDTH     => 8,            -- tstrb width
1500
         TCQ              => 1,            -- Clock to Q time
1501
 
1502
         C_FAMILY         => "V6",         -- Targeted FPGA family
1503
         C_ROOT_PORT      => FALSE,      -- PCIe block is in root port mode
1504
         C_PM_PRIORITY    => FALSE       -- Disable TX packet boundary thrtl
1505
      )
1506
      port map (
1507
         -------------------------------------------------
1508
         -- User Design I/O                             --
1509
         -------------------------------------------------
1510
 
1511
         -- AXI TX
1512
         -------------
1513
         s_axis_tx_tdata          => (others=>'0'),          --  input
1514
         s_axis_tx_tvalid         => '0',         --  input
1515
         --s_axis_tx_tready         => s_axis_tx_tready,         --  output
1516
         s_axis_tx_tstrb          => (others=>'0'),          --  input
1517
         s_axis_tx_tlast          => '0',          --  input
1518
         s_axis_tx_tuser          => (others=>'0'),          --  input
1519
 
1520
         -- AXI RX
1521
         -------------
1522
         --m_axis_rx_tdata          => m_axis_rx_tdata,          --  output
1523
         --m_axis_rx_tvalid         => m_axis_rx_tvalid,         --  output
1524
         m_axis_rx_tready         => '0',         --  input
1525
         --m_axis_rx_tstrb          => m_axis_rx_tstrb,          --  output
1526
         --m_axis_rx_tlast          => m_axis_rx_tlast,          --  output
1527
         --m_axis_rx_tuser          => m_axis_rx_tuser,          --  output
1528
 
1529
         -- User Misc.
1530
         -------------
1531
         user_turnoff_ok          => cfg_turnoff_ok,           --  input
1532
         user_tcfg_gnt            => tx_cfg_gnt,               --  input
1533
 
1534
         -------------------------------------------------
1535
         -- PCIe Block I/O                              --
1536
         -------------------------------------------------
1537
 
1538
         -- TRN TX
1539
         -------------
1540
         --trn_td                   => trn_td,                   --  output
1541
         --trn_tsof                 => trn_tsof,                 --  output
1542
         --trn_teof                 => trn_teof,                 --  output
1543
         --trn_tsrc_rdy             => trn_tsrc_rdy,             --  output
1544
         trn_tdst_rdy             => '0',             --  input
1545
         --trn_tsrc_dsc             => trn_tsrc_dsc,             --  output
1546
         --trn_trem                 => trn_trem,                 --  output
1547
         --trn_terrfwd              => trn_terrfwd,              --  output
1548
         --trn_tstr                 => trn_tstr,                 --  output
1549
         trn_tbuf_av              => tx_buf_av_int,            --  input
1550
         --trn_tecrc_gen            => trn_tecrc_gen,            --  output
1551
 
1552
         -- TRN RX
1553
         -------------
1554
         trn_rd                   => (others=>'0'),                   --  input
1555
         trn_rsof                 => '1',                 --  input
1556
         trn_reof                 => '1',                 --  input
1557
         trn_rsrc_rdy             => '1',             --  input
1558
         --trn_rdst_rdy             => trn_rdst_rdy,             --  output
1559
         trn_rsrc_dsc             => '1',             --  input
1560
         trn_rrem                 => "1",                 --  input
1561
         trn_rerrfwd              => '0',              --  input
1562
         trn_rbar_hit             => (others=>'0'),             --  input
1563
         trn_recrc_err            => '0',            --  input
1564
 
1565
         -- TRN Misc.
1566
         -------------
1567
         trn_tcfg_req             => tx_cfg_req_int,           --  input
1568
         trn_tcfg_gnt             => trn_tcfg_gnt,             --  output
1569
         trn_lnk_up               => user_lnk_up_int,          --  input
1570
 
1571
         -- Artix/Kintex/Virtex PM
1572
         -------------
1573
         cfg_pcie_link_state      => cfg_pcie_link_state_int,  --  input
1574
 
1575
         -- Virtex6 PM
1576
         -------------
1577
         cfg_pm_send_pme_to       => '0',                      --  input  NOT USED FOR EP
1578
         cfg_pmcsr_powerstate     => cfg_pmcsr_powerstate_int, --  input
1579
         trn_rdllp_data           => trn_rdllp_data,           --  input
1580
         trn_rdllp_src_rdy        => trn_rdllp_src_rdy,        --  input
1581
 
1582
         -- Power Mgmt for S6/V6
1583
         -------------
1584
         cfg_to_turnoff           => cfg_to_turnoff_int,       --  input
1585
         cfg_turnoff_ok           => cfg_turnoff_ok_axi,       --  output
1586
 
1587
         -- System
1588
         -------------
1589
         user_clk                 => user_clk,                 --  input
1590
         user_rst                 => user_reset_out_int,       --  input
1591
         np_counter               => open                      --  output
1592
   );
1593
 
1594
 
1595
 
1596
--cfg_turnoff_ok_axi <= '0';                      
1597
--trn_tcfg_gnt <='0';
1598
--   ---------------------------------------------------------
1599
   -- PCI Express Reset Delay Module
1600
   ---------------------------------------------------------
1601
 
1602
   sys_reset_n <= not(sys_reset);
1603
 
1604
   pcie_reset_delay_i : pcie_reset_delay_v6
1605
      generic map (
1606
         PL_FAST_TRAIN  => PL_FAST_TRAIN,
1607
         REF_CLK_FREQ   => REF_CLK_FREQ
1608
      )
1609
      port map (
1610
         ref_clk              => TxOutClk_bufg,
1611
         sys_reset_n          => sys_reset_n,
1612
         delayed_sys_reset_n  => sys_reset_n_d
1613
      );
1614
 
1615
 
1616
   ---------------------------------------------------------
1617
   -- PCI Express Clocking Module
1618
   ---------------------------------------------------------
1619
 
1620
   pcie_clocking_i : pcie_clocking_v6
1621
      generic map (
1622
         CAP_LINK_WIDTH  => LINK_CAP_MAX_LINK_WIDTH_int,
1623
         CAP_LINK_SPEED  => LINK_CAP_MAX_LINK_SPEED_int,
1624
         REF_CLK_FREQ    => REF_CLK_FREQ,
1625
         USER_CLK_FREQ   => USER_CLK_FREQ
1626
      )
1627
      port map (
1628
         sys_clk        => TxOutClk,
1629
         gt_pll_lock    => gt_pll_lock,
1630
         sel_lnk_rate   => pl_sel_link_rate_int,
1631
         sel_lnk_width  => pl_sel_link_width_int,
1632
         sys_clk_bufg   => TxOutClk_bufg,
1633
         pipe_clk       => pipe_clk,
1634
         user_clk       => user_clk,
1635
         block_clk      => open,
1636
         drp_clk        => drp_clk,
1637
         clock_locked   => clock_locked
1638
      );
1639
 
1640
 
1641
   phy_rdy <= not(phy_rdy_n);
1642
 
1643
   ---------------------------------------------------------
1644
   -- Virtex6 PCI Express Block Module
1645
   ---------------------------------------------------------
1646
 
1647
   pcie_2_0_i : pcie_2_0_v6
1648
      generic map (
1649
         REF_CLK_FREQ                              => REF_CLK_FREQ,
1650
         PIPE_PIPELINE_STAGES                      => PIPE_PIPELINE_STAGES,
1651
         LINK_CAP_MAX_LINK_WIDTH_int               => LINK_CAP_MAX_LINK_WIDTH_int,
1652
         AER_BASE_PTR                              => AER_BASE_PTR,
1653
         AER_CAP_ECRC_CHECK_CAPABLE                => AER_CAP_ECRC_CHECK_CAPABLE,
1654
         AER_CAP_ECRC_GEN_CAPABLE                  => AER_CAP_ECRC_GEN_CAPABLE,
1655
         AER_CAP_ID                                => AER_CAP_ID,
1656
         AER_CAP_INT_MSG_NUM_MSI                   => AER_CAP_INT_MSG_NUM_MSI,
1657
         AER_CAP_INT_MSG_NUM_MSIX                  => AER_CAP_INT_MSG_NUM_MSIX,
1658
         AER_CAP_NEXTPTR                           => AER_CAP_NEXTPTR,
1659
         AER_CAP_ON                                => AER_CAP_ON,
1660
         AER_CAP_PERMIT_ROOTERR_UPDATE             => AER_CAP_PERMIT_ROOTERR_UPDATE,
1661
         AER_CAP_VERSION                           => AER_CAP_VERSION,
1662
         ALLOW_X8_GEN2                             => ALLOW_X8_GEN2,
1663
         BAR0                                      => pad_gen(BAR0, 32),
1664
         BAR1                                      => pad_gen(BAR1, 32),
1665
         BAR2                                      => pad_gen(BAR2, 32),
1666
         BAR3                                      => pad_gen(BAR3, 32),
1667
         BAR4                                      => pad_gen(BAR4, 32),
1668
         BAR5                                      => pad_gen(BAR5, 32),
1669
         CAPABILITIES_PTR                          => CAPABILITIES_PTR,
1670
         CARDBUS_CIS_POINTER                       => pad_gen(CARDBUS_CIS_POINTER, 32),
1671
         CLASS_CODE                                => pad_gen(CLASS_CODE, 24),
1672
         CMD_INTX_IMPLEMENTED                      => CMD_INTX_IMPLEMENTED,
1673
         CPL_TIMEOUT_DISABLE_SUPPORTED             => CPL_TIMEOUT_DISABLE_SUPPORTED,
1674
         CPL_TIMEOUT_RANGES_SUPPORTED              => pad_gen(CPL_TIMEOUT_RANGES_SUPPORTED, 4),
1675
         CRM_MODULE_RSTS                           => CRM_MODULE_RSTS,
1676
         DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE       => DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE,
1677
         DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE       => DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE,
1678
         DEV_CAP_ENDPOINT_L0S_LATENCY              => DEV_CAP_ENDPOINT_L0S_LATENCY,
1679
         DEV_CAP_ENDPOINT_L1_LATENCY               => DEV_CAP_ENDPOINT_L1_LATENCY,
1680
         DEV_CAP_EXT_TAG_SUPPORTED                 => DEV_CAP_EXT_TAG_SUPPORTED,
1681
         DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE      => DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE,
1682
         DEV_CAP_MAX_PAYLOAD_SUPPORTED             => DEV_CAP_MAX_PAYLOAD_SUPPORTED,
1683
         DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT         => DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT,
1684
         DEV_CAP_ROLE_BASED_ERROR                  => DEV_CAP_ROLE_BASED_ERROR,
1685
         DEV_CAP_RSVD_14_12                        => DEV_CAP_RSVD_14_12,
1686
         DEV_CAP_RSVD_17_16                        => DEV_CAP_RSVD_17_16,
1687
         DEV_CAP_RSVD_31_29                        => DEV_CAP_RSVD_31_29,
1688
         DEV_CONTROL_AUX_POWER_SUPPORTED           => DEV_CONTROL_AUX_POWER_SUPPORTED,
1689
         DEVICE_ID                                 => pad_gen(DEVICE_ID, 16),
1690
         DISABLE_ASPM_L1_TIMER                     => DISABLE_ASPM_L1_TIMER,
1691
         DISABLE_BAR_FILTERING                     => DISABLE_BAR_FILTERING,
1692
         DISABLE_ID_CHECK                          => DISABLE_ID_CHECK,
1693
         DISABLE_LANE_REVERSAL                     => DISABLE_LANE_REVERSAL,
1694
         DISABLE_RX_TC_FILTER                      => DISABLE_RX_TC_FILTER,
1695
         DISABLE_SCRAMBLING                        => DISABLE_SCRAMBLING,
1696
         DNSTREAM_LINK_NUM                         => DNSTREAM_LINK_NUM,
1697
         DSN_BASE_PTR                              => pad_gen(DSN_BASE_PTR, 12),
1698
         DSN_CAP_ID                                => DSN_CAP_ID,
1699
         DSN_CAP_NEXTPTR                           => pad_gen(DSN_CAP_NEXTPTR, 12),
1700
         DSN_CAP_ON                                => DSN_CAP_ON,
1701
         DSN_CAP_VERSION                           => DSN_CAP_VERSION,
1702
         ENABLE_MSG_ROUTE                          => pad_gen(ENABLE_MSG_ROUTE, 11),
1703
         ENABLE_RX_TD_ECRC_TRIM                    => ENABLE_RX_TD_ECRC_TRIM,
1704
         ENTER_RVRY_EI_L0                          => ENTER_RVRY_EI_L0,
1705
         EXPANSION_ROM                             => pad_gen(EXPANSION_ROM, 32),
1706
         EXT_CFG_CAP_PTR                           => EXT_CFG_CAP_PTR,
1707
         EXT_CFG_XP_CAP_PTR                        => pad_gen(EXT_CFG_XP_CAP_PTR, 10),
1708
         HEADER_TYPE                               => pad_gen(HEADER_TYPE, 8),
1709
         INFER_EI                                  => INFER_EI,
1710
         INTERRUPT_PIN                             => pad_gen(INTERRUPT_PIN, 8),
1711
         IS_SWITCH                                 => IS_SWITCH,
1712
         LAST_CONFIG_DWORD                         => LAST_CONFIG_DWORD,
1713
         LINK_CAP_ASPM_SUPPORT                     => LINK_CAP_ASPM_SUPPORT,
1714
         LINK_CAP_CLOCK_POWER_MANAGEMENT           => LINK_CAP_CLOCK_POWER_MANAGEMENT,
1715
         LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP    => LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP,
1716
         LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP  => LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP,
1717
         LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1     => LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1,
1718
         LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2     => LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2,
1719
         LINK_CAP_L0S_EXIT_LATENCY_GEN1            => LINK_CAP_L0S_EXIT_LATENCY_GEN1,
1720
         LINK_CAP_L0S_EXIT_LATENCY_GEN2            => LINK_CAP_L0S_EXIT_LATENCY_GEN2,
1721
         LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1      => LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1,
1722
         LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2      => LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2,
1723
         LINK_CAP_L1_EXIT_LATENCY_GEN1             => LINK_CAP_L1_EXIT_LATENCY_GEN1,
1724
         LINK_CAP_L1_EXIT_LATENCY_GEN2             => LINK_CAP_L1_EXIT_LATENCY_GEN2,
1725
         LINK_CAP_MAX_LINK_SPEED                   => pad_gen(LINK_CAP_MAX_LINK_SPEED, 4),
1726
         LINK_CAP_MAX_LINK_WIDTH                   => pad_gen(LINK_CAP_MAX_LINK_WIDTH, 6),
1727
         LINK_CAP_RSVD_23_22                       => LINK_CAP_RSVD_23_22,
1728
         LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE      => LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE,
1729
         LINK_CONTROL_RCB                          => LINK_CONTROL_RCB,
1730
         LINK_CTRL2_DEEMPHASIS                     => LINK_CTRL2_DEEMPHASIS,
1731
         LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE    => LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE,
1732
         LINK_CTRL2_TARGET_LINK_SPEED              => pad_gen(LINK_CTRL2_TARGET_LINK_SPEED, 4),
1733
         LINK_STATUS_SLOT_CLOCK_CONFIG             => LINK_STATUS_SLOT_CLOCK_CONFIG,
1734
         LL_ACK_TIMEOUT                            => pad_gen(LL_ACK_TIMEOUT, 15),
1735
         LL_ACK_TIMEOUT_EN                         => LL_ACK_TIMEOUT_EN,
1736
         LL_ACK_TIMEOUT_FUNC                       => LL_ACK_TIMEOUT_FUNC,
1737
         LL_REPLAY_TIMEOUT                         => pad_gen(LL_REPLAY_TIMEOUT, 15),
1738
         LL_REPLAY_TIMEOUT_EN                      => LL_REPLAY_TIMEOUT_EN,
1739
         LL_REPLAY_TIMEOUT_FUNC                    => LL_REPLAY_TIMEOUT_FUNC,
1740
         LTSSM_MAX_LINK_WIDTH                      => pad_gen(LTSSM_MAX_LINK_WIDTH, 6),
1741
         MSI_BASE_PTR                              => MSI_BASE_PTR,
1742
         MSI_CAP_ID                                => MSI_CAP_ID,
1743
         MSI_CAP_MULTIMSGCAP                       => MSI_CAP_MULTIMSGCAP,
1744
         MSI_CAP_MULTIMSG_EXTENSION                => MSI_CAP_MULTIMSG_EXTENSION,
1745
         MSI_CAP_NEXTPTR                           => MSI_CAP_NEXTPTR,
1746
         MSI_CAP_ON                                => MSI_CAP_ON,
1747
         MSI_CAP_PER_VECTOR_MASKING_CAPABLE        => MSI_CAP_PER_VECTOR_MASKING_CAPABLE,
1748
         MSI_CAP_64_BIT_ADDR_CAPABLE               => MSI_CAP_64_BIT_ADDR_CAPABLE,
1749
         MSIX_BASE_PTR                             => MSIX_BASE_PTR,
1750
         MSIX_CAP_ID                               => MSIX_CAP_ID,
1751
         MSIX_CAP_NEXTPTR                          => MSIX_CAP_NEXTPTR,
1752
         MSIX_CAP_ON                               => MSIX_CAP_ON,
1753
         MSIX_CAP_PBA_BIR                          => MSIX_CAP_PBA_BIR,
1754
         MSIX_CAP_PBA_OFFSET                       => pad_gen(MSIX_CAP_PBA_OFFSET, 29),
1755
         MSIX_CAP_TABLE_BIR                        => MSIX_CAP_TABLE_BIR,
1756
         MSIX_CAP_TABLE_OFFSET                     => pad_gen(MSIX_CAP_TABLE_OFFSET, 29),
1757
         MSIX_CAP_TABLE_SIZE                       => pad_gen(MSIX_CAP_TABLE_SIZE, 11),
1758
         N_FTS_COMCLK_GEN1                         => N_FTS_COMCLK_GEN1,
1759
         N_FTS_COMCLK_GEN2                         => N_FTS_COMCLK_GEN2,
1760
         N_FTS_GEN1                                => N_FTS_GEN1,
1761
         N_FTS_GEN2                                => N_FTS_GEN2,
1762
         PCIE_BASE_PTR                             => PCIE_BASE_PTR,
1763
         PCIE_CAP_CAPABILITY_ID                    => PCIE_CAP_CAPABILITY_ID,
1764
         PCIE_CAP_CAPABILITY_VERSION               => PCIE_CAP_CAPABILITY_VERSION,
1765
         PCIE_CAP_DEVICE_PORT_TYPE                 => pad_gen(PCIE_CAP_DEVICE_PORT_TYPE, 4),
1766
         PCIE_CAP_INT_MSG_NUM                      => pad_gen(PCIE_CAP_INT_MSG_NUM, 5),
1767
         PCIE_CAP_NEXTPTR                          => pad_gen(PCIE_CAP_NEXTPTR, 8),
1768
         PCIE_CAP_ON                               => PCIE_CAP_ON,
1769
         PCIE_CAP_RSVD_15_14                       => PCIE_CAP_RSVD_15_14,
1770
         PCIE_CAP_SLOT_IMPLEMENTED                 => PCIE_CAP_SLOT_IMPLEMENTED,
1771
         PCIE_REVISION                             => PCIE_REVISION,
1772
         PGL0_LANE                                 => PGL0_LANE,
1773
         PGL1_LANE                                 => PGL1_LANE,
1774
         PGL2_LANE                                 => PGL2_LANE,
1775
         PGL3_LANE                                 => PGL3_LANE,
1776
         PGL4_LANE                                 => PGL4_LANE,
1777
         PGL5_LANE                                 => PGL5_LANE,
1778
         PGL6_LANE                                 => PGL6_LANE,
1779
         PGL7_LANE                                 => PGL7_LANE,
1780
         PL_AUTO_CONFIG                            => PL_AUTO_CONFIG,
1781
         PL_FAST_TRAIN                             => PL_FAST_TRAIN,
1782
         PM_BASE_PTR                               => PM_BASE_PTR,
1783
         PM_CAP_AUXCURRENT                         => PM_CAP_AUXCURRENT,
1784
         PM_CAP_DSI                                => PM_CAP_DSI,
1785
         PM_CAP_D1SUPPORT                          => PM_CAP_D1SUPPORT,
1786
         PM_CAP_D2SUPPORT                          => PM_CAP_D2SUPPORT,
1787
         PM_CAP_ID                                 => PM_CAP_ID,
1788
         PM_CAP_NEXTPTR                            => PM_CAP_NEXTPTR,
1789
         PM_CAP_ON                                 => PM_CAP_ON,
1790
         PM_CAP_PME_CLOCK                          => PM_CAP_PME_CLOCK,
1791
         PM_CAP_PMESUPPORT                         => pad_gen(PM_CAP_PMESUPPORT, 5),
1792
         PM_CAP_RSVD_04                            => PM_CAP_RSVD_04,
1793
         PM_CAP_VERSION                            => PM_CAP_VERSION,
1794
         PM_CSR_BPCCEN                             => PM_CSR_BPCCEN,
1795
         PM_CSR_B2B3                               => PM_CSR_B2B3,
1796
         PM_CSR_NOSOFTRST                          => PM_CSR_NOSOFTRST,
1797
         PM_DATA_SCALE0                            => pad_gen(PM_DATA_SCALE0, 2),
1798
         PM_DATA_SCALE1                            => pad_gen(PM_DATA_SCALE1, 2),
1799
         PM_DATA_SCALE2                            => pad_gen(PM_DATA_SCALE2, 2),
1800
         PM_DATA_SCALE3                            => pad_gen(PM_DATA_SCALE3, 2),
1801
         PM_DATA_SCALE4                            => pad_gen(PM_DATA_SCALE4, 2),
1802
         PM_DATA_SCALE5                            => pad_gen(PM_DATA_SCALE5, 2),
1803
         PM_DATA_SCALE6                            => pad_gen(PM_DATA_SCALE6, 2),
1804
         PM_DATA_SCALE7                            => pad_gen(PM_DATA_SCALE7, 2),
1805
         PM_DATA0                                  => pad_gen(PM_DATA0, 8),
1806
         PM_DATA1                                  => pad_gen(PM_DATA1, 8),
1807
         PM_DATA2                                  => pad_gen(PM_DATA2, 8),
1808
         PM_DATA3                                  => pad_gen(PM_DATA3, 8),
1809
         PM_DATA4                                  => pad_gen(PM_DATA4, 8),
1810
         PM_DATA5                                  => pad_gen(PM_DATA5, 8),
1811
         PM_DATA6                                  => pad_gen(PM_DATA6, 8),
1812
         PM_DATA7                                  => pad_gen(PM_DATA7, 8),
1813
         RECRC_CHK                                 => RECRC_CHK,
1814
         RECRC_CHK_TRIM                            => RECRC_CHK_TRIM,
1815
         REVISION_ID                               => pad_gen(REVISION_ID, 8),
1816
         ROOT_CAP_CRS_SW_VISIBILITY                => ROOT_CAP_CRS_SW_VISIBILITY,
1817
         SELECT_DLL_IF                             => SELECT_DLL_IF,
1818
         SLOT_CAP_ATT_BUTTON_PRESENT               => SLOT_CAP_ATT_BUTTON_PRESENT,
1819
         SLOT_CAP_ATT_INDICATOR_PRESENT            => SLOT_CAP_ATT_INDICATOR_PRESENT,
1820
         SLOT_CAP_ELEC_INTERLOCK_PRESENT           => SLOT_CAP_ELEC_INTERLOCK_PRESENT,
1821
         SLOT_CAP_HOTPLUG_CAPABLE                  => SLOT_CAP_HOTPLUG_CAPABLE,
1822
         SLOT_CAP_HOTPLUG_SURPRISE                 => SLOT_CAP_HOTPLUG_SURPRISE,
1823
         SLOT_CAP_MRL_SENSOR_PRESENT               => SLOT_CAP_MRL_SENSOR_PRESENT,
1824
         SLOT_CAP_NO_CMD_COMPLETED_SUPPORT         => SLOT_CAP_NO_CMD_COMPLETED_SUPPORT,
1825
         SLOT_CAP_PHYSICAL_SLOT_NUM                => SLOT_CAP_PHYSICAL_SLOT_NUM,
1826
         SLOT_CAP_POWER_CONTROLLER_PRESENT         => SLOT_CAP_POWER_CONTROLLER_PRESENT,
1827
         SLOT_CAP_POWER_INDICATOR_PRESENT          => SLOT_CAP_POWER_INDICATOR_PRESENT,
1828
         SLOT_CAP_SLOT_POWER_LIMIT_SCALE           => SLOT_CAP_SLOT_POWER_LIMIT_SCALE,
1829
         SLOT_CAP_SLOT_POWER_LIMIT_VALUE           => SLOT_CAP_SLOT_POWER_LIMIT_VALUE,
1830
         SPARE_BIT0                                => SPARE_BIT0,
1831
         SPARE_BIT1                                => SPARE_BIT1,
1832
         SPARE_BIT2                                => SPARE_BIT2,
1833
         SPARE_BIT3                                => SPARE_BIT3,
1834
         SPARE_BIT4                                => SPARE_BIT4,
1835
         SPARE_BIT5                                => SPARE_BIT5,
1836
         SPARE_BIT6                                => SPARE_BIT6,
1837
         SPARE_BIT7                                => SPARE_BIT7,
1838
         SPARE_BIT8                                => SPARE_BIT8,
1839
         SPARE_BYTE0                               => SPARE_BYTE0,
1840
         SPARE_BYTE1                               => SPARE_BYTE1,
1841
         SPARE_BYTE2                               => SPARE_BYTE2,
1842
         SPARE_BYTE3                               => SPARE_BYTE3,
1843
         SPARE_WORD0                               => SPARE_WORD0,
1844
         SPARE_WORD1                               => SPARE_WORD1,
1845
         SPARE_WORD2                               => SPARE_WORD2,
1846
         SPARE_WORD3                               => SPARE_WORD3,
1847
         SUBSYSTEM_ID                              => pad_gen(SUBSYSTEM_ID, 16),
1848
         SUBSYSTEM_VENDOR_ID                       => pad_gen(SUBSYSTEM_VENDOR_ID, 16),
1849
         TL_RBYPASS                                => TL_RBYPASS,
1850
         TL_RX_RAM_RADDR_LATENCY                   => TL_RX_RAM_RADDR_LATENCY,
1851
         TL_RX_RAM_RDATA_LATENCY                   => TL_RX_RAM_RDATA_LATENCY,
1852
         TL_RX_RAM_WRITE_LATENCY                   => TL_RX_RAM_WRITE_LATENCY,
1853
         TL_TFC_DISABLE                            => TL_TFC_DISABLE,
1854
         TL_TX_CHECKS_DISABLE                      => TL_TX_CHECKS_DISABLE,
1855
         TL_TX_RAM_RADDR_LATENCY                   => TL_TX_RAM_RADDR_LATENCY,
1856
         TL_TX_RAM_RDATA_LATENCY                   => TL_TX_RAM_RDATA_LATENCY,
1857
         TL_TX_RAM_WRITE_LATENCY                   => TL_TX_RAM_WRITE_LATENCY,
1858
         UPCONFIG_CAPABLE                          => UPCONFIG_CAPABLE,
1859
         UPSTREAM_FACING                           => UPSTREAM_FACING,
1860
         EXIT_LOOPBACK_ON_EI                       => EXIT_LOOPBACK_ON_EI,
1861
         UR_INV_REQ                                => UR_INV_REQ,
1862
         USER_CLK_FREQ                             => USER_CLK_FREQ,
1863
         VC_BASE_PTR                               => pad_gen(VC_BASE_PTR, 12),
1864
         VC_CAP_ID                                 => VC_CAP_ID,
1865
         VC_CAP_NEXTPTR                            => pad_gen(VC_CAP_NEXTPTR, 12),
1866
         VC_CAP_ON                                 => VC_CAP_ON,
1867
         VC_CAP_REJECT_SNOOP_TRANSACTIONS          => VC_CAP_REJECT_SNOOP_TRANSACTIONS,
1868
         VC_CAP_VERSION                            => VC_CAP_VERSION,
1869
         VC0_CPL_INFINITE                          => VC0_CPL_INFINITE,
1870
         VC0_RX_RAM_LIMIT                          => pad_gen(VC0_RX_RAM_LIMIT, 13),
1871
         VC0_TOTAL_CREDITS_CD                      => VC0_TOTAL_CREDITS_CD,
1872
         VC0_TOTAL_CREDITS_CH                      => VC0_TOTAL_CREDITS_CH,
1873
         VC0_TOTAL_CREDITS_NPH                     => VC0_TOTAL_CREDITS_NPH,
1874
         VC0_TOTAL_CREDITS_PD                      => VC0_TOTAL_CREDITS_PD,
1875
         VC0_TOTAL_CREDITS_PH                      => VC0_TOTAL_CREDITS_PH,
1876
         VC0_TX_LASTPACKET                         => VC0_TX_LASTPACKET,
1877
         VENDOR_ID                                 => pad_gen(VENDOR_ID, 16),
1878
         VSEC_BASE_PTR                             => pad_gen(VSEC_BASE_PTR, 12),
1879
         VSEC_CAP_HDR_ID                           => VSEC_CAP_HDR_ID,
1880
         VSEC_CAP_HDR_LENGTH                       => VSEC_CAP_HDR_LENGTH,
1881
         VSEC_CAP_HDR_REVISION                     => VSEC_CAP_HDR_REVISION,
1882
         VSEC_CAP_ID                               => VSEC_CAP_ID,
1883
         VSEC_CAP_IS_LINK_VISIBLE                  => VSEC_CAP_IS_LINK_VISIBLE,
1884
         VSEC_CAP_NEXTPTR                          => pad_gen(VSEC_CAP_NEXTPTR, 12),
1885
         VSEC_CAP_ON                               => VSEC_CAP_ON,
1886
         VSEC_CAP_VERSION                          => VSEC_CAP_VERSION
1887
      )
1888
      port map (
1889
         PCIEXPRXN                            => pci_exp_rxn,
1890
         PCIEXPRXP                            => pci_exp_rxp,
1891
         PCIEXPTXN                            => pci_exp_txn,
1892
         PCIEXPTXP                            => pci_exp_txp,
1893
         SYSCLK                               => sys_clk,
1894
         TRNLNKUPN                            => trn_lnk_up_n,
1895
         FUNDRSTN                             => sys_reset_n_d,
1896
         PHYRDYN                              => phy_rdy_n,
1897
         LNKCLKEN                             => open,
1898
         USERRSTN                             => trn_reset_n,
1899
         RECEIVEDFUNCLVLRSTN                  => rx_func_level_reset_n,
1900
         SYSRSTN                              => phy_rdy,
1901
         PLRSTN                               => '1',
1902
         DLRSTN                               => '1',
1903
         TLRSTN                               => '1',
1904
         FUNCLVLRSTN                          => '1',
1905
         CMRSTN                               => '1',
1906
         CMSTICKYRSTN                         => '1',
1907
 
1908
         TRNRBARHITN                          => trn_rbar_hit_n,
1909
         TRNRD                                => trn_rd,
1910
         TRNRECRCERRN                         => trn_recrc_err_n,
1911
         TRNREOFN                             => trn_reof_n,
1912
         TRNRERRFWDN                          => trn_rerrfwd_n,
1913
         TRNRREMN                             => trn_rrem_n,
1914
         TRNRSOFN                             => trn_rsof_n,
1915
         TRNRSRCDSCN                          => trn_rsrc_dsc_n,
1916
         TRNRSRCRDYN                          => trn_rsrc_rdy_n,
1917
         TRNRDSTRDYN                          => trn_rdst_rdy_n,
1918
         TRNRNPOKN                            => trn_rnp_ok_n,
1919
         TRNRDLLPDATA                         => trn_rdllp_data,
1920
         TRNRDLLPSRCRDYN                      => trn_rdllp_src_rdy_n,
1921
 
1922
         TRNTBUFAV                            => tx_buf_av_int,
1923
         TRNTCFGREQN                          => trn_tcfg_req_n,
1924
         TRNTDLLPDSTRDYN                      => open,
1925
         TRNTDSTRDYN                          => trn_tdst_rdy_n,
1926
         TRNTERRDROPN                         => trn_terr_drop_n,
1927
         TRNTCFGGNTN                          => trn_tcfg_gnt_n,
1928
         TRNTD                                => trn_td,
1929
         TRNTDLLPDATA                         => (others => '0'),
1930
         TRNTDLLPSRCRDYN                      => '1',
1931
         TRNTECRCGENN                         => '1',
1932
         TRNTEOFN                             => trn_teof_n,
1933
         TRNTERRFWDN                          => trn_terrfwd_n,
1934
         TRNTREMN                             => trn_trem_n,
1935
         TRNTSOFN                             => trn_tsof_n,
1936
         TRNTSRCDSCN                          => trn_tsrc_dsc_n,
1937
         TRNTSRCRDYN                          => trn_tsrc_rdy_n,
1938
         TRNTSTRN                             => trn_tstr_n,
1939
         TRNFCCPLD                            => fc_cpld,
1940
         TRNFCCPLH                            => fc_cplh,
1941
         TRNFCNPD                             => fc_npd,
1942
         TRNFCNPH                             => fc_nph,
1943
         TRNFCPD                              => fc_pd,
1944
         TRNFCPH                              => fc_ph,
1945
         TRNFCSEL                             => fc_sel,
1946
         CFGAERECRCCHECKEN                    => open,
1947
         CFGAERECRCGENEN                      => open,
1948
         CFGCOMMANDBUSMASTERENABLE            => cfg_cmd_bme,
1949
         CFGCOMMANDINTERRUPTDISABLE           => cfg_cmd_intdis,
1950
         CFGCOMMANDIOENABLE                   => cfg_cmd_io_en,
1951
         CFGCOMMANDMEMENABLE                  => cfg_cmd_mem_en,
1952
         CFGCOMMANDSERREN                     => cfg_cmd_serr_en,
1953
         CFGDEVCONTROLAUXPOWEREN              => cfg_dev_control_aux_power_en,
1954
         CFGDEVCONTROLCORRERRREPORTINGEN      => cfg_dev_control_corr_err_reporting_en,
1955
         CFGDEVCONTROLENABLERO                => cfg_dev_control_enable_relaxed_order,
1956
         CFGDEVCONTROLEXTTAGEN                => cfg_dev_control_ext_tag_en,
1957
         CFGDEVCONTROLFATALERRREPORTINGEN     => cfg_dev_control_fatal_err_reporting_en,
1958
         CFGDEVCONTROLMAXPAYLOAD              => cfg_dev_control_maxpayload,
1959
         CFGDEVCONTROLMAXREADREQ              => cfg_dev_control_max_read_req,
1960
         CFGDEVCONTROLNONFATALREPORTINGEN     => cfg_dev_control_non_fatal_reporting_en,
1961
         CFGDEVCONTROLNOSNOOPEN               => cfg_dev_control_nosnoop_en,
1962
         CFGDEVCONTROLPHANTOMEN               => cfg_dev_control_phantom_en,
1963
         CFGDEVCONTROLURERRREPORTINGEN        => cfg_dev_control_ur_err_reporting_en,
1964
         CFGDEVCONTROL2CPLTIMEOUTDIS          => cfg_dev_control2_cpltimeout_dis,
1965
         CFGDEVCONTROL2CPLTIMEOUTVAL          => cfg_dev_control2_cpltimeout_val,
1966
         CFGDEVSTATUSCORRERRDETECTED          => cfg_dev_status_corr_err_detected,
1967
         CFGDEVSTATUSFATALERRDETECTED         => cfg_dev_status_fatal_err_detected,
1968
         CFGDEVSTATUSNONFATALERRDETECTED      => cfg_dev_status_nonfatal_err_detected,
1969
         CFGDEVSTATUSURDETECTED               => cfg_dev_status_ur_detected,
1970
         CFGDO                                => cfg_do,
1971
         CFGERRAERHEADERLOGSETN               => open,
1972
         CFGERRCPLRDYN                        => cfg_err_cpl_rdy_n,
1973
         CFGINTERRUPTDO                       => cfg_interrupt_do,
1974
         CFGINTERRUPTMMENABLE                 => cfg_interrupt_mmenable,
1975
         CFGINTERRUPTMSIENABLE                => cfg_interrupt_msienable,
1976
         CFGINTERRUPTMSIXENABLE               => cfg_interrupt_msixenable,
1977
         CFGINTERRUPTMSIXFM                   => cfg_interrupt_msixfm,
1978
         CFGINTERRUPTRDYN                     => cfg_interrupt_rdy_n,
1979
         CFGLINKCONTROLRCB                    => cfg_link_control_rcb,
1980
         CFGLINKCONTROLASPMCONTROL            => cfg_link_control_aspm_control,
1981
         CFGLINKCONTROLAUTOBANDWIDTHINTEN     => cfg_link_control_auto_bandwidth_int_en,
1982
         CFGLINKCONTROLBANDWIDTHINTEN         => cfg_link_control_bandwidth_int_en,
1983
         CFGLINKCONTROLCLOCKPMEN              => cfg_link_control_clock_pm_en,
1984
         CFGLINKCONTROLCOMMONCLOCK            => cfg_link_control_common_clock,
1985
         CFGLINKCONTROLEXTENDEDSYNC           => cfg_link_control_extended_sync,
1986
         CFGLINKCONTROLHWAUTOWIDTHDIS         => cfg_link_control_hw_auto_width_dis,
1987
         CFGLINKCONTROLLINKDISABLE            => cfg_link_control_linkdisable,
1988
         CFGLINKCONTROLRETRAINLINK            => cfg_link_control_retrain_link,
1989
         CFGLINKSTATUSAUTOBANDWIDTHSTATUS     => cfg_link_status_autobandwidth_status,
1990
         CFGLINKSTATUSBANDWITHSTATUS          => cfg_link_status_bandwidth_status,
1991
         CFGLINKSTATUSCURRENTSPEED            => cfg_link_status_current_speed,
1992
         CFGLINKSTATUSDLLACTIVE               => cfg_link_status_dll_active,
1993
         CFGLINKSTATUSLINKTRAINING            => cfg_link_status_link_training,
1994
         CFGLINKSTATUSNEGOTIATEDWIDTH         => cfg_link_status_negotiated_link_width,
1995
         CFGMSGDATA                           => cfg_msg_data,
1996
         CFGMSGRECEIVED                       => cfg_msg_received,
1997
         CFGMSGRECEIVEDASSERTINTA             => open,
1998
         CFGMSGRECEIVEDASSERTINTB             => open,
1999
         CFGMSGRECEIVEDASSERTINTC             => open,
2000
         CFGMSGRECEIVEDASSERTINTD             => open,
2001
         CFGMSGRECEIVEDDEASSERTINTA           => open,
2002
         CFGMSGRECEIVEDDEASSERTINTB           => open,
2003
         CFGMSGRECEIVEDDEASSERTINTC           => open,
2004
         CFGMSGRECEIVEDDEASSERTINTD           => open,
2005
         CFGMSGRECEIVEDERRCOR                 => open,
2006
         CFGMSGRECEIVEDERRFATAL               => open,
2007
         CFGMSGRECEIVEDERRNONFATAL            => open,
2008
         CFGMSGRECEIVEDPMASNAK                => open,
2009
         CFGMSGRECEIVEDPMETO                  => cfg_msg_received_pme_to,
2010
         CFGMSGRECEIVEDPMETOACK               => open,
2011
         CFGMSGRECEIVEDPMPME                  => open,
2012
         CFGMSGRECEIVEDSETSLOTPOWERLIMIT      => open,
2013
         CFGMSGRECEIVEDUNLOCK                 => open,
2014
         CFGPCIELINKSTATE                     => cfg_pcie_link_state_int,
2015
         CFGPMCSRPMEEN                        => cfg_pmcsr_pme_en,
2016
         CFGPMCSRPMESTATUS                    => cfg_pmcsr_pme_status,
2017
         CFGPMCSRPOWERSTATE                   => cfg_pmcsr_powerstate_int,
2018
         CFGPMRCVASREQL1N                     => open,
2019
         CFGPMRCVENTERL1N                     => open,
2020
         CFGPMRCVENTERL23N                    => open,
2021
         CFGPMRCVREQACKN                      => open,
2022
         CFGRDWRDONEN                         => cfg_rd_wr_done_n,
2023
         CFGSLOTCONTROLELECTROMECHILCTLPULSE  => open,
2024
         CFGTRANSACTION                       => open,
2025
         CFGTRANSACTIONADDR                   => open,
2026
         CFGTRANSACTIONTYPE                   => open,
2027
         CFGVCTCVCMAP                         => open,
2028
         CFGBYTEENN                           => cfg_byte_en_n,
2029
         CFGDI                                => cfg_di,
2030
         CFGDSBUSNUMBER                       => "00000000",
2031
         CFGDSDEVICENUMBER                    => "00000",
2032
         CFGDSFUNCTIONNUMBER                  => "000",
2033
         CFGDSN                               => cfg_dsn,
2034
         CFGDWADDR                            => cfg_dwaddr,
2035
         CFGERRACSN                           => '1',
2036
         CFGERRAERHEADERLOG                   => (others => '0'),
2037
         CFGERRCORN                           => cfg_err_cor_n,
2038
         CFGERRCPLABORTN                      => cfg_err_cpl_abort_n,
2039
         CFGERRCPLTIMEOUTN                    => cfg_err_cpl_timeout_n,
2040
         CFGERRCPLUNEXPECTN                   => cfg_err_cpl_unexpect_n,
2041
         CFGERRECRCN                          => cfg_err_ecrc_n,
2042
         CFGERRLOCKEDN                        => cfg_err_locked_n,
2043
         CFGERRPOSTEDN                        => cfg_err_posted_n,
2044
         CFGERRTLPCPLHEADER                   => cfg_err_tlp_cpl_header,
2045
         CFGERRURN                            => cfg_err_ur_n,
2046
         CFGINTERRUPTASSERTN                  => cfg_interrupt_assert_n,
2047
         CFGINTERRUPTDI                       => cfg_interrupt_di,
2048
         CFGINTERRUPTN                        => cfg_interrupt_n,
2049
         CFGPMDIRECTASPML1N                   => '1',
2050
         CFGPMSENDPMACKN                      => '1',
2051
         CFGPMSENDPMETON                      => '1',
2052
         CFGPMSENDPMNAKN                      => '1',
2053
         CFGPMTURNOFFOKN                      => cfg_turnoff_ok_n,
2054
         CFGPMWAKEN                           => cfg_pm_wake_n,
2055
         CFGPORTNUMBER                        => "00000000",
2056
         CFGRDENN                             => cfg_rd_en_n,
2057
         CFGTRNPENDINGN                       => cfg_trn_pending_n,
2058
         CFGWRENN                             => cfg_wr_en_n,
2059
         CFGWRREADONLYN                       => '1',
2060
         CFGWRRW1CASRWN                       => '1',
2061
 
2062
         PLINITIALLINKWIDTH                   => pl_initial_link_width,
2063
         PLLANEREVERSALMODE                   => pl_lane_reversal_mode,
2064
         PLLINKGEN2CAP                        => pl_link_gen2_capable,
2065
         PLLINKPARTNERGEN2SUPPORTED           => pl_link_partner_gen2_supported,
2066
         PLLINKUPCFGCAP                       => pl_link_upcfg_capable,
2067
         PLLTSSMSTATE                         => pl_ltssm_state,
2068
         PLPHYLNKUPN                          => open,                                 -- Debug
2069
         PLRECEIVEDHOTRST                     => pl_received_hot_rst,
2070
         PLRXPMSTATE                          => open,                                 -- Debug
2071
         PLSELLNKRATE                         => pl_sel_link_rate_int,
2072
         PLSELLNKWIDTH                        => pl_sel_link_width_int,
2073
         PLTXPMSTATE                          => open,                                 -- Debug
2074
         PLDIRECTEDLINKAUTON                  => pl_directed_link_auton,
2075
         PLDIRECTEDLINKCHANGE                 => pl_directed_link_change,
2076
         PLDIRECTEDLINKSPEED                  => pl_directed_link_speed,
2077
         PLDIRECTEDLINKWIDTH                  => pl_directed_link_width,
2078
         PLDOWNSTREAMDEEMPHSOURCE             => '1',
2079
         PLUPSTREAMPREFERDEEMPH               => pl_upstream_prefer_deemph,
2080
         PLTRANSMITHOTRST                     => '0',
2081
 
2082
         DBGSCLRA                             => open,
2083
         DBGSCLRB                             => open,
2084
         DBGSCLRC                             => open,
2085
         DBGSCLRD                             => open,
2086
         DBGSCLRE                             => open,
2087
         DBGSCLRF                             => open,
2088
         DBGSCLRG                             => open,
2089
         DBGSCLRH                             => open,
2090
         DBGSCLRI                             => open,
2091
         DBGSCLRJ                             => open,
2092
         DBGSCLRK                             => open,
2093
         DBGVECA                              => open,
2094
         DBGVECB                              => open,
2095
         DBGVECC                              => open,
2096
         PLDBGVEC                             => open,
2097
         DBGMODE                              => "00",
2098
         DBGSUBMODE                           => '0',
2099
         PLDBGMODE                            => "000",
2100
 
2101
         PCIEDRPDO                            => open,
2102
         PCIEDRPDRDY                          => open,
2103
         PCIEDRPCLK                           => '0',
2104
         PCIEDRPDADDR                         => "000000000",
2105
         PCIEDRPDEN                           => '0',
2106
         PCIEDRPDI                            => X"0000",
2107
         PCIEDRPDWE                           => '0',
2108
 
2109
         GTPLLLOCK                            => gt_pll_lock,
2110
         PIPECLK                              => pipe_clk,
2111
         USERCLK                              => user_clk,
2112
         DRPCLK                               => drp_clk,
2113
         CLOCKLOCKED                          => clock_locked,
2114
         TxOutClk                             => TxOutClk
2115
      );
2116
 
2117
end v6_pcie;
2118
 

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