Subversion Repositories pcie_ds_dma

-------------------------------------------------------------------------------

--

-- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.

--

-- This file contains confidential and proprietary information

-- of Xilinx, Inc. and is protected under U.S. and

-- international copyright and other intellectual property

-- laws.

--

-- DISCLAIMER

-- This disclaimer is not a license and does not grant any

-- rights to the materials distributed herewith. Except as

-- otherwise provided in a valid license issued to you by

-- Xilinx, and to the maximum extent permitted by applicable

-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND

-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES

-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING

-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-

-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and

-- (2) Xilinx shall not be liable (whether in contract or tort,

-- including negligence, or under any other theory of

-- liability) for any loss or damage of any kind or nature

-- related to, arising under or in connection with these

-- materials, including for any direct, or any indirect,

-- special, incidental, or consequential loss or damage

-- (including loss of data, profits, goodwill, or any type of

-- loss or damage suffered as a result of any action brought

-- by a third party) even if such damage or loss was

-- reasonably foreseeable or Xilinx had been advised of the

-- possibility of the same.

--

-- CRITICAL APPLICATIONS

-- Xilinx products are not designed or intended to be fail-

-- safe, or for use in any application requiring fail-safe

-- performance, such as life-support or safety devices or

-- systems, Class III medical devices, nuclear facilities,

-- applications related to the deployment of airbags, or any

-- other applications that could lead to death, personal

-- injury, or severe property or environmental damage

-- (individually and collectively, "Critical

-- Applications"). Customer assumes the sole risk and

-- liability of any use of Xilinx products in Critical

-- Applications, subject only to applicable laws and

-- regulations governing limitations on product liability.

--

-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS

-- PART OF THIS FILE AT ALL TIMES.

--

-------------------------------------------------------------------------------

-- Project    : Virtex-6 Integrated Block for PCI Express

-- File       : cl_v6pcie_x4.vhd

-- Version    : 2.3

-- Description: Virtex6 solution wrapper : Endpoint for PCI Express

--

--

--

--------------------------------------------------------------------------------

library ieee;

   use ieee.std_logic_1164.all;

   use ieee.std_logic_unsigned.all;

library unisim;

use unisim.vcomponents.all;

entity cl_v6pcie_x4 is

   generic (

   PCIE_DRP_ENABLE                              : boolean := FALSE;

   ALLOW_X8_GEN2                                : boolean := FALSE;

   BAR0                                         : bit_vector := X"FFE00000";

   BAR1                                         : bit_vector := X"FFE00000";

   BAR2                                         : bit_vector := X"00000000";

   BAR3                                         : bit_vector := X"00000000";

   BAR4                                         : bit_vector := X"00000000";

   BAR5                                         : bit_vector := X"00000000";

   CARDBUS_CIS_POINTER                          : bit_vector := X"00000000";

   CLASS_CODE                                   : bit_vector := X"FFFFFF";

   CMD_INTX_IMPLEMENTED                         : boolean    := TRUE;

   CPL_TIMEOUT_DISABLE_SUPPORTED                : boolean    := FALSE;

   CPL_TIMEOUT_RANGES_SUPPORTED                 : bit_vector := X"2";

   DEV_CAP_ENDPOINT_L0S_LATENCY                 : integer    := 0;

   DEV_CAP_ENDPOINT_L1_LATENCY                  : integer    := 7;

   DEV_CAP_EXT_TAG_SUPPORTED                    : boolean    := FALSE;

   DEV_CAP_MAX_PAYLOAD_SUPPORTED                : integer    := 1;

   DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT            : integer    := 0;

   DEVICE_ID                                    : bit_vector := X"5507";

   DISABLE_LANE_REVERSAL                        : boolean    := FALSE;

   DISABLE_SCRAMBLING                           : boolean    := FALSE;

   DSN_BASE_PTR                                 : bit_vector := X"0";

   DSN_CAP_NEXTPTR                              : bit_vector := X"000";

   DSN_CAP_ON                                   : boolean    := FALSE;

   ENABLE_MSG_ROUTE                             : bit_vector := "00000000000";

   ENABLE_RX_TD_ECRC_TRIM                       : boolean    := TRUE;

   EXPANSION_ROM                                : bit_vector := X"00000000";

   EXT_CFG_CAP_PTR                              : bit_vector := X"3F";

   EXT_CFG_XP_CAP_PTR                           : bit_vector := X"3FF";

   HEADER_TYPE                                  : bit_vector := X"00";

   INTERRUPT_PIN                                : bit_vector := X"1";

   LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP       : boolean    := FALSE;

   LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP     : boolean    := FALSE;

   LINK_CAP_MAX_LINK_SPEED                      : bit_vector := X"2";

   LINK_CAP_MAX_LINK_WIDTH                      : bit_vector := X"04";

   LINK_CAP_MAX_LINK_WIDTH_int                  : integer    := 4;

   LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE         : boolean    := FALSE;

   LINK_CTRL2_DEEMPHASIS                        : boolean    := FALSE;

   LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE       : boolean    := FALSE;

   LINK_CTRL2_TARGET_LINK_SPEED                 : bit_vector := X"2";

   LINK_STATUS_SLOT_CLOCK_CONFIG                : boolean    := TRUE;

   LL_ACK_TIMEOUT                               : bit_vector := X"0000";

   LL_ACK_TIMEOUT_EN                            : boolean    := FALSE;

   LL_ACK_TIMEOUT_FUNC                          : integer    := 0;

   LL_REPLAY_TIMEOUT                            : bit_vector := X"0026";

   LL_REPLAY_TIMEOUT_EN                         : boolean    := TRUE;

   LL_REPLAY_TIMEOUT_FUNC                       : integer    := 1;

   LTSSM_MAX_LINK_WIDTH                         : bit_vector := X"04";

   MSI_CAP_MULTIMSGCAP                          : integer    := 0;

   MSI_CAP_MULTIMSG_EXTENSION                   : integer    := 0;

   MSI_CAP_ON                                   : boolean    := FALSE;

   MSI_CAP_PER_VECTOR_MASKING_CAPABLE           : boolean    := FALSE;

   MSI_CAP_64_BIT_ADDR_CAPABLE                  : boolean    := TRUE;

   MSIX_CAP_ON                                  : boolean    := FALSE;

   MSIX_CAP_PBA_BIR                             : integer    := 0;

   MSIX_CAP_PBA_OFFSET                          : bit_vector := X"0";

   MSIX_CAP_TABLE_BIR                           : integer    := 0;

   MSIX_CAP_TABLE_OFFSET                        : bit_vector := X"0";

   MSIX_CAP_TABLE_SIZE                          : bit_vector := X"000";

   PCIE_CAP_DEVICE_PORT_TYPE                    : bit_vector := X"0";

   PCIE_CAP_INT_MSG_NUM                         : bit_vector := X"1";

   PCIE_CAP_NEXTPTR                             : bit_vector := X"00";

   PIPE_PIPELINE_STAGES                         : integer    := 0;                -- 0 - 0 stages; 1 - 1 stage; 2 - 2 stages

   PM_CAP_DSI                                   : boolean    := FALSE;

   PM_CAP_D1SUPPORT                             : boolean    := FALSE;

   PM_CAP_D2SUPPORT                             : boolean    := FALSE;

   PM_CAP_NEXTPTR                               : bit_vector := X"60";

   PM_CAP_PMESUPPORT                            : bit_vector := X"0F";

   PM_CSR_NOSOFTRST                             : boolean    := TRUE;

   PM_DATA_SCALE0                               : bit_vector := X"0";

   PM_DATA_SCALE1                               : bit_vector := X"0";

   PM_DATA_SCALE2                               : bit_vector := X"0";

   PM_DATA_SCALE3                               : bit_vector := X"0";

   PM_DATA_SCALE4                               : bit_vector := X"0";

   PM_DATA_SCALE5                               : bit_vector := X"0";

   PM_DATA_SCALE6                               : bit_vector := X"0";

   PM_DATA_SCALE7                               : bit_vector := X"0";

   PM_DATA0                                     : bit_vector := X"00";

   PM_DATA1                                     : bit_vector := X"00";

   PM_DATA2                                     : bit_vector := X"00";

   PM_DATA3                                     : bit_vector := X"00";

   PM_DATA4                                     : bit_vector := X"00";

   PM_DATA5                                     : bit_vector := X"00";

   PM_DATA6                                     : bit_vector := X"00";

   PM_DATA7                                     : bit_vector := X"00";

   REF_CLK_FREQ                                 : integer    := 0;                        -- 0 - 100 MHz; 1 - 125 MHz; 2 - 250 MHz

   REVISION_ID                                  : bit_vector := X"20";

   SPARE_BIT0                                   : integer    := 0;

   SUBSYSTEM_ID                                 : bit_vector := X"0002";

   SUBSYSTEM_VENDOR_ID                          : bit_vector := X"4953";

   TL_RX_RAM_RADDR_LATENCY                      : integer    := 0;

   TL_RX_RAM_RDATA_LATENCY                      : integer    := 2;

   TL_RX_RAM_WRITE_LATENCY                      : integer    := 0;

   TL_TX_RAM_RADDR_LATENCY                      : integer    := 0;

   TL_TX_RAM_RDATA_LATENCY                      : integer    := 2;

   TL_TX_RAM_WRITE_LATENCY                      : integer    := 0;

   UPCONFIG_CAPABLE                             : boolean    := TRUE;

   USER_CLK_FREQ                                : integer    := 3;

   VC_BASE_PTR                                  : bit_vector := X"0";

   VC_CAP_NEXTPTR                               : bit_vector := X"000";

   VC_CAP_ON                                    : boolean    := FALSE;

   VC_CAP_REJECT_SNOOP_TRANSACTIONS             : boolean    := FALSE;

   VC0_CPL_INFINITE                             : boolean    := TRUE;

   VC0_RX_RAM_LIMIT                             : bit_vector := X"3FF";

   VC0_TOTAL_CREDITS_CD                         : integer    := 378;

   VC0_TOTAL_CREDITS_CH                         : integer    := 36;

   VC0_TOTAL_CREDITS_NPH                        : integer    := 12;

   VC0_TOTAL_CREDITS_PD                         : integer    := 32;

   VC0_TOTAL_CREDITS_PH                         : integer    := 32;

   VC0_TX_LASTPACKET                            : integer    := 28;

   VENDOR_ID                                    : bit_vector := X"4953";

   VSEC_BASE_PTR                                : bit_vector := X"0";

   VSEC_CAP_NEXTPTR                             : bit_vector := X"000";

   VSEC_CAP_ON                                  : boolean    := FALSE;

   AER_BASE_PTR                                 : bit_vector := X"128";

   AER_CAP_ECRC_CHECK_CAPABLE                   : boolean    := FALSE;

   AER_CAP_ECRC_GEN_CAPABLE                     : boolean    := FALSE;

   AER_CAP_ID                                   : bit_vector := X"0001";

   AER_CAP_INT_MSG_NUM_MSI                      : bit_vector := X"0a";

   AER_CAP_INT_MSG_NUM_MSIX                     : bit_vector := X"15";

   AER_CAP_NEXTPTR                              : bit_vector := X"160";

   AER_CAP_ON                                   : boolean    := FALSE;

   AER_CAP_PERMIT_ROOTERR_UPDATE                : boolean    := TRUE;

   AER_CAP_VERSION                              : bit_vector := X"1";

   CAPABILITIES_PTR                             : bit_vector := X"40";

   CRM_MODULE_RSTS                              : bit_vector := X"00";

   DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE          : boolean    := TRUE;

   DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE          : boolean    := TRUE;

   DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE         : boolean    := FALSE;

   DEV_CAP_ROLE_BASED_ERROR                     : boolean    := TRUE;

   DEV_CAP_RSVD_14_12                           : integer    := 0;

   DEV_CAP_RSVD_17_16                           : integer    := 0;

   DEV_CAP_RSVD_31_29                           : integer    := 0;

   DEV_CONTROL_AUX_POWER_SUPPORTED              : boolean    := FALSE;

   DISABLE_ASPM_L1_TIMER                        : boolean    := FALSE;

   DISABLE_BAR_FILTERING                        : boolean    := FALSE;

   DISABLE_ID_CHECK                             : boolean    := FALSE;

   DISABLE_RX_TC_FILTER                         : boolean    := FALSE;

   DNSTREAM_LINK_NUM                            : bit_vector := X"00";

   DSN_CAP_ID                                   : bit_vector := X"0003";

   DSN_CAP_VERSION                              : bit_vector := X"1";

   ENTER_RVRY_EI_L0                             : boolean    := TRUE;

   INFER_EI                                     : bit_vector := X"0c";

   IS_SWITCH                                    : boolean    := FALSE;

   LAST_CONFIG_DWORD                            : bit_vector := X"3FF";

   LINK_CAP_ASPM_SUPPORT                        : integer    := 1;

   LINK_CAP_CLOCK_POWER_MANAGEMENT              : boolean    := FALSE;

   LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1        : integer    := 7;

   LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2        : integer    := 7;

   LINK_CAP_L0S_EXIT_LATENCY_GEN1               : integer    := 7;

   LINK_CAP_L0S_EXIT_LATENCY_GEN2               : integer    := 7;

   LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1         : integer    := 7;

   LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2         : integer    := 7;

   LINK_CAP_L1_EXIT_LATENCY_GEN1                : integer    := 7;

   LINK_CAP_L1_EXIT_LATENCY_GEN2                : integer    := 7;

   LINK_CAP_RSVD_23_22                          : integer    := 0;

   LINK_CONTROL_RCB                             : integer    := 0;

   MSI_BASE_PTR                                 : bit_vector := X"48";

   MSI_CAP_ID                                   : bit_vector := X"05";

   MSI_CAP_NEXTPTR                              : bit_vector := X"60";

   MSIX_BASE_PTR                                : bit_vector := X"9c";

   MSIX_CAP_ID                                  : bit_vector := X"11";

   MSIX_CAP_NEXTPTR                             : bit_vector := X"00";

   N_FTS_COMCLK_GEN1                            : integer    := 255;

   N_FTS_COMCLK_GEN2                            : integer    := 254;

   N_FTS_GEN1                                   : integer    := 255;

   N_FTS_GEN2                                   : integer    := 255;

   PCIE_BASE_PTR                                : bit_vector := X"60";

   PCIE_CAP_CAPABILITY_ID                       : bit_vector := X"10";

   PCIE_CAP_CAPABILITY_VERSION                  : bit_vector := X"2";

   PCIE_CAP_ON                                  : boolean    := TRUE;

   PCIE_CAP_RSVD_15_14                          : integer    := 0;

   PCIE_CAP_SLOT_IMPLEMENTED                    : boolean    := FALSE;

   PCIE_REVISION                                : integer    := 2;

   PGL0_LANE                                    : integer    := 0;

   PGL1_LANE                                    : integer    := 1;

   PGL2_LANE                                    : integer    := 2;

   PGL3_LANE                                    : integer    := 3;

   PGL4_LANE                                    : integer    := 4;

   PGL5_LANE                                    : integer    := 5;

   PGL6_LANE                                    : integer    := 6;

   PGL7_LANE                                    : integer    := 7;

   PL_AUTO_CONFIG                               : integer    := 0;

   PL_FAST_TRAIN                                : boolean    := FALSE;

   PM_BASE_PTR                                  : bit_vector := X"40";

   PM_CAP_AUXCURRENT                            : integer    := 0;

   PM_CAP_ID                                    : bit_vector := X"01";

   PM_CAP_ON                                    : boolean    := TRUE;

   PM_CAP_PME_CLOCK                             : boolean    := FALSE;

   PM_CAP_RSVD_04                               : integer    := 0;

   PM_CAP_VERSION                               : integer    := 3;

   PM_CSR_BPCCEN                                : boolean    := FALSE;

   PM_CSR_B2B3                                  : boolean    := FALSE;

   RECRC_CHK                                    : integer    := 0;

   RECRC_CHK_TRIM                               : boolean    := FALSE;

   ROOT_CAP_CRS_SW_VISIBILITY                   : boolean    := FALSE;

   SELECT_DLL_IF                                : boolean    := FALSE;

   SLOT_CAP_ATT_BUTTON_PRESENT                  : boolean    := FALSE;

   SLOT_CAP_ATT_INDICATOR_PRESENT               : boolean    := FALSE;

   SLOT_CAP_ELEC_INTERLOCK_PRESENT              : boolean    := FALSE;

   SLOT_CAP_HOTPLUG_CAPABLE                     : boolean    := FALSE;

   SLOT_CAP_HOTPLUG_SURPRISE                    : boolean    := FALSE;

   SLOT_CAP_MRL_SENSOR_PRESENT                  : boolean    := FALSE;

   SLOT_CAP_NO_CMD_COMPLETED_SUPPORT            : boolean    := FALSE;

   SLOT_CAP_PHYSICAL_SLOT_NUM                   : bit_vector := X"0000";

   SLOT_CAP_POWER_CONTROLLER_PRESENT            : boolean    := FALSE;

   SLOT_CAP_POWER_INDICATOR_PRESENT             : boolean    := FALSE;

   SLOT_CAP_SLOT_POWER_LIMIT_SCALE              : integer    := 0;

   SLOT_CAP_SLOT_POWER_LIMIT_VALUE              : bit_vector := X"00";

   SPARE_BIT1                                   : integer    := 0;

   SPARE_BIT2                                   : integer    := 0;

   SPARE_BIT3                                   : integer    := 0;

   SPARE_BIT4                                   : integer    := 0;

   SPARE_BIT5                                   : integer    := 0;

   SPARE_BIT6                                   : integer    := 0;

   SPARE_BIT7                                   : integer    := 0;

   SPARE_BIT8                                   : integer    := 0;

   SPARE_BYTE0                                  : bit_vector := X"00";

   SPARE_BYTE1                                  : bit_vector := X"00";

   SPARE_BYTE2                                  : bit_vector := X"00";

   SPARE_BYTE3                                  : bit_vector := X"00";

   SPARE_WORD0                                  : bit_vector := X"00000000";

   SPARE_WORD1                                  : bit_vector := X"00000000";

   SPARE_WORD2                                  : bit_vector := X"00000000";

   SPARE_WORD3                                  : bit_vector := X"00000000";

   TL_RBYPASS                                   : boolean    := FALSE;

   TL_TFC_DISABLE                               : boolean    := FALSE;

   TL_TX_CHECKS_DISABLE                         : boolean    := FALSE;

   EXIT_LOOPBACK_ON_EI                          : boolean    := TRUE;

   UPSTREAM_FACING                              : boolean    := TRUE;

   UR_INV_REQ                                   : boolean    := TRUE;

   VC_CAP_ID                                    : bit_vector := X"0002";

   VC_CAP_VERSION                               : bit_vector := X"1";

   VSEC_CAP_HDR_ID                              : bit_vector := X"1234";

   VSEC_CAP_HDR_LENGTH                          : bit_vector := X"018";

   VSEC_CAP_HDR_REVISION                        : bit_vector := X"1";

   VSEC_CAP_ID                                  : bit_vector := X"000b";

   VSEC_CAP_IS_LINK_VISIBLE                     : boolean    := TRUE;

   VSEC_CAP_VERSION                             : bit_vector := X"1"

      );

   port (

      ---------------------------------------------------------

      -- 1. PCI Express (pci_exp) Interface

      ---------------------------------------------------------

      -- Tx

      pci_exp_txp                               : out std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);

      pci_exp_txn                               : out std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);

      -- Rx

      pci_exp_rxp                               : in std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);

      pci_exp_rxn                               : in std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);

      ---------------------------------------------------------

      -- 2. Transaction (TRN) Interface

      ---------------------------------------------------------

      -- Common

      user_clk_out                              : out std_logic;

      user_reset_out                            : out std_logic;

      user_lnk_up                               : out std_logic;

      -- Tx

      tx_buf_av                                 : out std_logic_vector(5 downto 0);

      tx_cfg_req                                : out std_logic;

      tx_err_drop                               : out std_logic;

      s_axis_tx_tready                          : out std_logic;

      s_axis_tx_tdata                           : in std_logic_vector(63 downto 0);

      s_axis_tx_tstrb                           : in std_logic_vector(7 downto 0);

      s_axis_tx_tuser                           : in std_logic_vector(3 downto 0);

      s_axis_tx_tlast                           : in std_logic;

      s_axis_tx_tvalid                          : in std_logic;

      tx_cfg_gnt                                : in std_logic;

      -- Rx

      m_axis_rx_tdata                           : out std_logic_vector(63 downto 0);

      m_axis_rx_tstrb                           : out std_logic_vector(7 downto 0);

      m_axis_rx_tlast                           : out std_logic;

      m_axis_rx_tvalid                          : out std_logic;

      m_axis_rx_tuser                           : out std_logic_vector(21 downto 0);

      m_axis_rx_tready                          : in std_logic;

      rx_np_ok                                  : in std_logic;

      -- Flow Control

      fc_cpld                                   : out std_logic_vector(11 downto 0);

      fc_cplh                                   : out std_logic_vector(7 downto 0);

      fc_npd                                    : out std_logic_vector(11 downto 0);

      fc_nph                                    : out std_logic_vector(7 downto 0);

      fc_pd                                     : out std_logic_vector(11 downto 0);

      fc_ph                                     : out std_logic_vector(7 downto 0);

      fc_sel                                    : in std_logic_vector(2 downto 0);

      ---------------------------------------------------------

      -- 3. Configuration (CFG) Interface

      ---------------------------------------------------------

      cfg_do                                    : out std_logic_vector(31 downto 0);

      cfg_rd_wr_done                            : out std_logic;

      cfg_di                                    : in std_logic_vector(31 downto 0);

      cfg_byte_en                               : in std_logic_vector(3 downto 0);

      cfg_dwaddr                                : in std_logic_vector(9 downto 0);

      cfg_wr_en                                 : in std_logic;

      cfg_rd_en                                 : in std_logic;

      cfg_err_cor                               : in std_logic;

      cfg_err_ur                                : in std_logic;

      cfg_err_ecrc                              : in std_logic;

      cfg_err_cpl_timeout                       : in std_logic;

      cfg_err_cpl_abort                         : in std_logic;

      cfg_err_cpl_unexpect                      : in std_logic;

      cfg_err_posted                            : in std_logic;

      cfg_err_locked                            : in std_logic;

      cfg_err_tlp_cpl_header                    : in std_logic_vector(47 downto 0);

      cfg_err_cpl_rdy                           : out std_logic;

      cfg_interrupt                             : in std_logic;

      cfg_interrupt_rdy                         : out std_logic;

      cfg_interrupt_assert                      : in std_logic;

      cfg_interrupt_di                          : in std_logic_vector(7 downto 0);

      cfg_interrupt_do                          : out std_logic_vector(7 downto 0);

      cfg_interrupt_mmenable                    : out std_logic_vector(2 downto 0);

      cfg_interrupt_msienable                   : out std_logic;

      cfg_interrupt_msixenable                  : out std_logic;

      cfg_interrupt_msixfm                      : out std_logic;

      cfg_turnoff_ok                            : in std_logic;

      cfg_to_turnoff                            : out std_logic;

      cfg_trn_pending                           : in std_logic;

      cfg_pm_wake                               : in std_logic;

      cfg_bus_number                            : out std_logic_vector(7 downto 0);

      cfg_device_number                         : out std_logic_vector(4 downto 0);

      cfg_function_number                       : out std_logic_vector(2 downto 0);

      cfg_status                                : out std_logic_vector(15 downto 0);

      cfg_command                               : out std_logic_vector(15 downto 0);

      cfg_dstatus                               : out std_logic_vector(15 downto 0);

      cfg_dcommand                              : out std_logic_vector(15 downto 0);

      cfg_lstatus                               : out std_logic_vector(15 downto 0);

      cfg_lcommand                              : out std_logic_vector(15 downto 0);

      cfg_dcommand2                             : out std_logic_vector(15 downto 0);

      cfg_pcie_link_state                       : out std_logic_vector(2 downto 0);

      cfg_dsn                                   : in std_logic_vector(63 downto 0);

      cfg_pmcsr_pme_en                          : out std_logic;

      cfg_pmcsr_pme_status                      : out std_logic;

      cfg_pmcsr_powerstate                      : out std_logic_vector(1 downto 0);

      ---------------------------------------------------------

      -- 4. Physical Layer Control and Status (PL) Interface

      ---------------------------------------------------------

      pl_initial_link_width                     : out std_logic_vector(2 downto 0);

      pl_lane_reversal_mode                     : out std_logic_vector(1 downto 0);

      pl_link_gen2_capable                      : out std_logic;

      pl_link_partner_gen2_supported            : out std_logic;

      pl_link_upcfg_capable                     : out std_logic;

      pl_ltssm_state                            : out std_logic_vector(5 downto 0);

      pl_received_hot_rst                       : out std_logic;

      pl_sel_link_rate                          : out std_logic;

      pl_sel_link_width                         : out std_logic_vector(1 downto 0);

      pl_directed_link_auton                    : in std_logic;

      pl_directed_link_change                   : in std_logic_vector(1 downto 0);

      pl_directed_link_speed                    : in std_logic;

      pl_directed_link_width                    : in std_logic_vector(1 downto 0);

      pl_upstream_prefer_deemph                 : in std_logic;

      ---------------------------------------------------------

      -- 5. System  (SYS) Interface

      ---------------------------------------------------------

      sys_clk                                   : in std_logic;

      sys_reset                                 : in std_logic

   );

end cl_v6pcie_x4;

architecture v6_pcie of cl_v6pcie_x4 is

   attribute CORE_GENERATION_INFO : string;

   attribute CORE_GENERATION_INFO of v6_pcie : ARCHITECTURE is

     "cl_v6pcie_x4,v6_pcie_v2_3,{LINK_CAP_MAX_LINK_SPEED=2,LINK_CAP_MAX_LINK_WIDTH=04,PCIE_CAP_DEVICE_PORT_TYPE=0000,DEV_CAP_MAX_PAYLOAD_SUPPORTED=1,USER_CLK_FREQ=3,REF_CLK_FREQ=0,MSI_CAP_ON=FALSE,MSI_CAP_MULTIMSGCAP=0,MSI_CAP_MULTIMSG_EXTENSION=0,MSIX_CAP_ON=FALSE,TL_TX_RAM_RADDR_LATENCY=0,TL_TX_RAM_RDATA_LATENCY=2,TL_RX_RAM_RADDR_LATENCY=0,TL_RX_RAM_RDATA_LATENCY=2,TL_RX_RAM_WRITE_LATENCY=0,VC0_TX_LASTPACKET=28,VC0_RX_RAM_LIMIT=3FF,VC0_TOTAL_CREDITS_PH=32,VC0_TOTAL_CREDITS_PD=32,VC0_TOTAL_CREDITS_NPH=12,VC0_TOTAL_CREDITS_CH=36,VC0_TOTAL_CREDITS_CD=378,VC0_CPL_INFINITE=TRUE,DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT=0,DEV_CAP_EXT_TAG_SUPPORTED=FALSE,LINK_STATUS_SLOT_CLOCK_CONFIG=TRUE,ENABLE_RX_TD_ECRC_TRIM=TRUE,DISABLE_LANE_REVERSAL=TRUE,DISABLE_SCRAMBLING=FALSE,DSN_CAP_ON=FALSE,PIPE_PIPELINE_STAGES=0,REVISION_ID=20,VC_CAP_ON=FALSE}";

   component axi_basic_top

   generic (

      C_DATA_WIDTH              : integer := 32;     -- rx/tx interface data width

      C_FAMILY                  : string  := "x7";    -- targeted fpga family

      C_ROOT_PORT               : BOOLEAN := FALSE; -- pcie block is in root port mode

      C_PM_PRIORITY             : BOOLEAN := FALSE; -- disable tx packet boundary thrtl

      TCQ                       : integer := 1;      -- clock to q time

      C_REM_WIDTH               : integer := 1;      -- trem/rrem width

      C_STRB_WIDTH              : integer := 4       -- tstrb width

   );

   port (

      -----------------------------------------------

      -- user design I/O

      -----------------------------------------------

      -- AXI TX

      -------------

      s_axis_tx_tdata         : in std_logic_vector(C_DATA_WIDTH - 1 downto 0) := (others=>'0');

      s_axis_tx_tvalid        : in std_logic                                   := '0';

      s_axis_tx_tready        : out std_logic                                  := '0';

      s_axis_tx_tstrb         : in std_logic_vector(C_STRB_WIDTH - 1 downto 0) := (others=>'0');

      s_axis_tx_tlast         : in std_logic                                   := '0';

      s_axis_tx_tuser         : in std_logic_vector(3 downto 0) := (others=>'0');

      -- AXI RX

      -------------

      m_axis_rx_tdata         : out std_logic_vector(C_DATA_WIDTH - 1 downto 0) := (others=>'0');

      m_axis_rx_tvalid        : out std_logic                                   := '0';

      m_axis_rx_tready        : in std_logic                                    := '0';

      m_axis_rx_tstrb         : out std_logic_vector(C_STRB_WIDTH - 1 downto 0) := (others=>'0');

      m_axis_rx_tlast         : out std_logic                                   := '0';

      m_axis_rx_tuser         : out std_logic_vector(21 downto 0) := (others=>'0');

      -- user misc.

      -------------

      user_turnoff_ok         : in std_logic                                   := '0';

      user_tcfg_gnt           : in std_logic                                   := '0';

      -----------------------------------------------

      -- PCIe block I/O

      -----------------------------------------------

      -- TRN TX

      -------------

      trn_td                  : out std_logic_vector(C_DATA_WIDTH - 1 downto 0) := (others=>'0');

      trn_tsof                : out std_logic                                   := '0';

      trn_teof                : out std_logic                                   := '0';

      trn_tsrc_rdy            : out std_logic                                   := '0';

      trn_tdst_rdy            : in std_logic                                    := '0';

      trn_tsrc_dsc            : out std_logic                                   := '0';

      trn_trem                : out std_logic_vector(C_REM_WIDTH - 1 downto 0)  := (others=>'0');

      trn_terrfwd             : out std_logic                                   := '0';

      trn_tstr                : out std_logic                                   := '0';

      trn_tbuf_av             : in std_logic_vector(5 downto 0)                 := (others=>'0');

      trn_tecrc_gen           : out std_logic                                   := '0';

      -- TRN RX

      -------------

      trn_rd                  : in std_logic_vector(C_DATA_WIDTH - 1 downto 0) := (others=>'0');

      trn_rsof                : in std_logic                                   := '0';

      trn_reof                : in std_logic                                   := '0';

      trn_rsrc_rdy            : in std_logic                                   := '0';

      trn_rdst_rdy            : out std_logic                                  := '0';

      trn_rsrc_dsc            : in std_logic                                   := '0';

      trn_rrem                : in std_logic_vector(C_REM_WIDTH - 1 downto 0)  := (others=>'0');

      trn_rerrfwd             : in std_logic                                   := '0';

      trn_rbar_hit            : in std_logic_vector(6 downto 0)                := (others=>'0');

      trn_recrc_err           : in std_logic                                   := '0';

      -- TRN misc.

      -------------

      trn_tcfg_req            : in std_logic                                   := '0';

      trn_tcfg_gnt            : out std_logic                                  := '0';

      trn_lnk_up              : in std_logic                                   := '0';

      -- 7 series/Virtex6 PM

      -------------

      cfg_pcie_link_state     : in std_logic_vector(2 downto 0)                := (others=>'0');

      -- Virtex6 PM

      -------------

      cfg_pm_send_pme_to      : in std_logic                                   := '0';

      cfg_pmcsr_powerstate    : in std_logic_vector(1 downto 0)                := (others=>'0');

      trn_rdllp_data          : in std_logic_vector(31 downto 0)               := (others=>'0');

      trn_rdllp_src_rdy       : in std_logic                                   := '0';

      -- Virtex6/Spartan6 PM

      -------------

      cfg_to_turnoff          : in std_logic                                   := '0';

      cfg_turnoff_ok          : out std_logic                                  := '0';

      np_counter              : out std_logic_vector(2 downto 0)               := (others=>'0');

      user_clk                : in std_logic                                   := '0';

      user_rst                : in std_logic                                   := '0'

   );

   end component;

  component pcie_reset_delay_v6

    generic (

      PL_FAST_TRAIN : boolean;

      REF_CLK_FREQ  : integer);

    port (

      ref_clk             : in  std_logic;

      sys_reset_n         : in  std_logic;

      delayed_sys_reset_n : out std_logic);

  end component;

  component pcie_clocking_v6

    generic (

      CAP_LINK_WIDTH : integer;

      CAP_LINK_SPEED : integer;

      REF_CLK_FREQ   : integer;

      USER_CLK_FREQ  : integer);

    port (

      sys_clk       : in  std_logic;

      gt_pll_lock   : in  std_logic;

      sel_lnk_rate  : in  std_logic;

      sel_lnk_width : in  std_logic_vector(1 downto 0);