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[/] [pcie_ds_dma/] [trunk/] [core/] [ds_dma64/] [pcie_src/] [pcie_core64_m1/] [source_virtex6/] [cl_v6pcie_x4.vhd] - Blame information for rev 2

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-------------------------------------------------------------------------------
2
--
3
-- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
4
--
5
-- This file contains confidential and proprietary information
6
-- of Xilinx, Inc. and is protected under U.S. and
7
-- international copyright and other intellectual property
8
-- laws.
9
--
10
-- DISCLAIMER
11
-- This disclaimer is not a license and does not grant any
12
-- rights to the materials distributed herewith. Except as
13
-- otherwise provided in a valid license issued to you by
14
-- Xilinx, and to the maximum extent permitted by applicable
15
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
16
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
17
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
18
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
19
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
20
-- (2) Xilinx shall not be liable (whether in contract or tort,
21
-- including negligence, or under any other theory of
22
-- liability) for any loss or damage of any kind or nature
23
-- related to, arising under or in connection with these
24
-- materials, including for any direct, or any indirect,
25
-- special, incidental, or consequential loss or damage
26
-- (including loss of data, profits, goodwill, or any type of
27
-- loss or damage suffered as a result of any action brought
28
-- by a third party) even if such damage or loss was
29
-- reasonably foreseeable or Xilinx had been advised of the
30
-- possibility of the same.
31
--
32
-- CRITICAL APPLICATIONS
33
-- Xilinx products are not designed or intended to be fail-
34
-- safe, or for use in any application requiring fail-safe
35
-- performance, such as life-support or safety devices or
36
-- systems, Class III medical devices, nuclear facilities,
37
-- applications related to the deployment of airbags, or any
38
-- other applications that could lead to death, personal
39
-- injury, or severe property or environmental damage
40
-- (individually and collectively, "Critical
41
-- Applications"). Customer assumes the sole risk and
42
-- liability of any use of Xilinx products in Critical
43
-- Applications, subject only to applicable laws and
44
-- regulations governing limitations on product liability.
45
--
46
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
47
-- PART OF THIS FILE AT ALL TIMES.
48
--
49
-------------------------------------------------------------------------------
50
-- Project    : Virtex-6 Integrated Block for PCI Express
51
-- File       : cl_v6pcie_x4.vhd
52
-- Version    : 2.3
53
-- Description: Virtex6 solution wrapper : Endpoint for PCI Express
54
--
55
--
56
--
57
--------------------------------------------------------------------------------
58
 
59
library ieee;
60
   use ieee.std_logic_1164.all;
61
   use ieee.std_logic_unsigned.all;
62
 
63
library unisim;
64
use unisim.vcomponents.all;
65
 
66
entity cl_v6pcie_x4 is
67
   generic (
68
   PCIE_DRP_ENABLE                              : boolean := FALSE;
69
   ALLOW_X8_GEN2                                : boolean := FALSE;
70
   BAR0                                         : bit_vector := X"FFE00000";
71
   BAR1                                         : bit_vector := X"FFE00000";
72
   BAR2                                         : bit_vector := X"00000000";
73
   BAR3                                         : bit_vector := X"00000000";
74
   BAR4                                         : bit_vector := X"00000000";
75
   BAR5                                         : bit_vector := X"00000000";
76
 
77
   CARDBUS_CIS_POINTER                          : bit_vector := X"00000000";
78
   CLASS_CODE                                   : bit_vector := X"FFFFFF";
79
   CMD_INTX_IMPLEMENTED                         : boolean    := TRUE;
80
   CPL_TIMEOUT_DISABLE_SUPPORTED                : boolean    := FALSE;
81
   CPL_TIMEOUT_RANGES_SUPPORTED                 : bit_vector := X"2";
82
 
83
   DEV_CAP_ENDPOINT_L0S_LATENCY                 : integer    := 0;
84
   DEV_CAP_ENDPOINT_L1_LATENCY                  : integer    := 7;
85
   DEV_CAP_EXT_TAG_SUPPORTED                    : boolean    := FALSE;
86
   DEV_CAP_MAX_PAYLOAD_SUPPORTED                : integer    := 1;
87
   DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT            : integer    := 0;
88
   DEVICE_ID                                    : bit_vector := X"5507";
89
 
90
   DISABLE_LANE_REVERSAL                        : boolean    := FALSE;
91
   DISABLE_SCRAMBLING                           : boolean    := FALSE;
92
   DSN_BASE_PTR                                 : bit_vector := X"0";
93
   DSN_CAP_NEXTPTR                              : bit_vector := X"000";
94
   DSN_CAP_ON                                   : boolean    := FALSE;
95
 
96
   ENABLE_MSG_ROUTE                             : bit_vector := "00000000000";
97
   ENABLE_RX_TD_ECRC_TRIM                       : boolean    := TRUE;
98
   EXPANSION_ROM                                : bit_vector := X"00000000";
99
   EXT_CFG_CAP_PTR                              : bit_vector := X"3F";
100
   EXT_CFG_XP_CAP_PTR                           : bit_vector := X"3FF";
101
   HEADER_TYPE                                  : bit_vector := X"00";
102
   INTERRUPT_PIN                                : bit_vector := X"1";
103
 
104
   LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP       : boolean    := FALSE;
105
   LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP     : boolean    := FALSE;
106
   LINK_CAP_MAX_LINK_SPEED                      : bit_vector := X"2";
107
   LINK_CAP_MAX_LINK_WIDTH                      : bit_vector := X"04";
108
   LINK_CAP_MAX_LINK_WIDTH_int                  : integer    := 4;
109
   LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE         : boolean    := FALSE;
110
 
111
   LINK_CTRL2_DEEMPHASIS                        : boolean    := FALSE;
112
   LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE       : boolean    := FALSE;
113
   LINK_CTRL2_TARGET_LINK_SPEED                 : bit_vector := X"2";
114
   LINK_STATUS_SLOT_CLOCK_CONFIG                : boolean    := TRUE;
115
 
116
   LL_ACK_TIMEOUT                               : bit_vector := X"0000";
117
   LL_ACK_TIMEOUT_EN                            : boolean    := FALSE;
118
   LL_ACK_TIMEOUT_FUNC                          : integer    := 0;
119
   LL_REPLAY_TIMEOUT                            : bit_vector := X"0026";
120
   LL_REPLAY_TIMEOUT_EN                         : boolean    := TRUE;
121
   LL_REPLAY_TIMEOUT_FUNC                       : integer    := 1;
122
 
123
   LTSSM_MAX_LINK_WIDTH                         : bit_vector := X"04";
124
   MSI_CAP_MULTIMSGCAP                          : integer    := 0;
125
   MSI_CAP_MULTIMSG_EXTENSION                   : integer    := 0;
126
   MSI_CAP_ON                                   : boolean    := FALSE;
127
   MSI_CAP_PER_VECTOR_MASKING_CAPABLE           : boolean    := FALSE;
128
   MSI_CAP_64_BIT_ADDR_CAPABLE                  : boolean    := TRUE;
129
 
130
   MSIX_CAP_ON                                  : boolean    := FALSE;
131
   MSIX_CAP_PBA_BIR                             : integer    := 0;
132
   MSIX_CAP_PBA_OFFSET                          : bit_vector := X"0";
133
   MSIX_CAP_TABLE_BIR                           : integer    := 0;
134
   MSIX_CAP_TABLE_OFFSET                        : bit_vector := X"0";
135
   MSIX_CAP_TABLE_SIZE                          : bit_vector := X"000";
136
 
137
   PCIE_CAP_DEVICE_PORT_TYPE                    : bit_vector := X"0";
138
   PCIE_CAP_INT_MSG_NUM                         : bit_vector := X"1";
139
   PCIE_CAP_NEXTPTR                             : bit_vector := X"00";
140
   PIPE_PIPELINE_STAGES                         : integer    := 0;                -- 0 - 0 stages; 1 - 1 stage; 2 - 2 stages
141
 
142
   PM_CAP_DSI                                   : boolean    := FALSE;
143
   PM_CAP_D1SUPPORT                             : boolean    := FALSE;
144
   PM_CAP_D2SUPPORT                             : boolean    := FALSE;
145
   PM_CAP_NEXTPTR                               : bit_vector := X"60";
146
   PM_CAP_PMESUPPORT                            : bit_vector := X"0F";
147
   PM_CSR_NOSOFTRST                             : boolean    := TRUE;
148
 
149
   PM_DATA_SCALE0                               : bit_vector := X"0";
150
   PM_DATA_SCALE1                               : bit_vector := X"0";
151
   PM_DATA_SCALE2                               : bit_vector := X"0";
152
   PM_DATA_SCALE3                               : bit_vector := X"0";
153
   PM_DATA_SCALE4                               : bit_vector := X"0";
154
   PM_DATA_SCALE5                               : bit_vector := X"0";
155
   PM_DATA_SCALE6                               : bit_vector := X"0";
156
   PM_DATA_SCALE7                               : bit_vector := X"0";
157
 
158
   PM_DATA0                                     : bit_vector := X"00";
159
   PM_DATA1                                     : bit_vector := X"00";
160
   PM_DATA2                                     : bit_vector := X"00";
161
   PM_DATA3                                     : bit_vector := X"00";
162
   PM_DATA4                                     : bit_vector := X"00";
163
   PM_DATA5                                     : bit_vector := X"00";
164
   PM_DATA6                                     : bit_vector := X"00";
165
   PM_DATA7                                     : bit_vector := X"00";
166
 
167
   REF_CLK_FREQ                                 : integer    := 0;                        -- 0 - 100 MHz; 1 - 125 MHz; 2 - 250 MHz
168
   REVISION_ID                                  : bit_vector := X"20";
169
   SPARE_BIT0                                   : integer    := 0;
170
   SUBSYSTEM_ID                                 : bit_vector := X"0002";
171
   SUBSYSTEM_VENDOR_ID                          : bit_vector := X"4953";
172
 
173
   TL_RX_RAM_RADDR_LATENCY                      : integer    := 0;
174
   TL_RX_RAM_RDATA_LATENCY                      : integer    := 2;
175
   TL_RX_RAM_WRITE_LATENCY                      : integer    := 0;
176
   TL_TX_RAM_RADDR_LATENCY                      : integer    := 0;
177
   TL_TX_RAM_RDATA_LATENCY                      : integer    := 2;
178
   TL_TX_RAM_WRITE_LATENCY                      : integer    := 0;
179
 
180
   UPCONFIG_CAPABLE                             : boolean    := TRUE;
181
   USER_CLK_FREQ                                : integer    := 3;
182
   VC_BASE_PTR                                  : bit_vector := X"0";
183
   VC_CAP_NEXTPTR                               : bit_vector := X"000";
184
   VC_CAP_ON                                    : boolean    := FALSE;
185
   VC_CAP_REJECT_SNOOP_TRANSACTIONS             : boolean    := FALSE;
186
 
187
   VC0_CPL_INFINITE                             : boolean    := TRUE;
188
   VC0_RX_RAM_LIMIT                             : bit_vector := X"3FF";
189
   VC0_TOTAL_CREDITS_CD                         : integer    := 378;
190
   VC0_TOTAL_CREDITS_CH                         : integer    := 36;
191
   VC0_TOTAL_CREDITS_NPH                        : integer    := 12;
192
   VC0_TOTAL_CREDITS_PD                         : integer    := 32;
193
   VC0_TOTAL_CREDITS_PH                         : integer    := 32;
194
   VC0_TX_LASTPACKET                            : integer    := 28;
195
 
196
   VENDOR_ID                                    : bit_vector := X"4953";
197
   VSEC_BASE_PTR                                : bit_vector := X"0";
198
   VSEC_CAP_NEXTPTR                             : bit_vector := X"000";
199
   VSEC_CAP_ON                                  : boolean    := FALSE;
200
 
201
   AER_BASE_PTR                                 : bit_vector := X"128";
202
   AER_CAP_ECRC_CHECK_CAPABLE                   : boolean    := FALSE;
203
   AER_CAP_ECRC_GEN_CAPABLE                     : boolean    := FALSE;
204
   AER_CAP_ID                                   : bit_vector := X"0001";
205
   AER_CAP_INT_MSG_NUM_MSI                      : bit_vector := X"0a";
206
   AER_CAP_INT_MSG_NUM_MSIX                     : bit_vector := X"15";
207
   AER_CAP_NEXTPTR                              : bit_vector := X"160";
208
   AER_CAP_ON                                   : boolean    := FALSE;
209
   AER_CAP_PERMIT_ROOTERR_UPDATE                : boolean    := TRUE;
210
   AER_CAP_VERSION                              : bit_vector := X"1";
211
 
212
   CAPABILITIES_PTR                             : bit_vector := X"40";
213
   CRM_MODULE_RSTS                              : bit_vector := X"00";
214
   DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE          : boolean    := TRUE;
215
   DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE          : boolean    := TRUE;
216
   DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE         : boolean    := FALSE;
217
   DEV_CAP_ROLE_BASED_ERROR                     : boolean    := TRUE;
218
   DEV_CAP_RSVD_14_12                           : integer    := 0;
219
   DEV_CAP_RSVD_17_16                           : integer    := 0;
220
   DEV_CAP_RSVD_31_29                           : integer    := 0;
221
   DEV_CONTROL_AUX_POWER_SUPPORTED              : boolean    := FALSE;
222
 
223
   DISABLE_ASPM_L1_TIMER                        : boolean    := FALSE;
224
   DISABLE_BAR_FILTERING                        : boolean    := FALSE;
225
   DISABLE_ID_CHECK                             : boolean    := FALSE;
226
   DISABLE_RX_TC_FILTER                         : boolean    := FALSE;
227
   DNSTREAM_LINK_NUM                            : bit_vector := X"00";
228
 
229
   DSN_CAP_ID                                   : bit_vector := X"0003";
230
   DSN_CAP_VERSION                              : bit_vector := X"1";
231
   ENTER_RVRY_EI_L0                             : boolean    := TRUE;
232
   INFER_EI                                     : bit_vector := X"0c";
233
   IS_SWITCH                                    : boolean    := FALSE;
234
 
235
   LAST_CONFIG_DWORD                            : bit_vector := X"3FF";
236
   LINK_CAP_ASPM_SUPPORT                        : integer    := 1;
237
   LINK_CAP_CLOCK_POWER_MANAGEMENT              : boolean    := FALSE;
238
   LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1        : integer    := 7;
239
   LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2        : integer    := 7;
240
   LINK_CAP_L0S_EXIT_LATENCY_GEN1               : integer    := 7;
241
   LINK_CAP_L0S_EXIT_LATENCY_GEN2               : integer    := 7;
242
   LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1         : integer    := 7;
243
   LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2         : integer    := 7;
244
   LINK_CAP_L1_EXIT_LATENCY_GEN1                : integer    := 7;
245
   LINK_CAP_L1_EXIT_LATENCY_GEN2                : integer    := 7;
246
   LINK_CAP_RSVD_23_22                          : integer    := 0;
247
   LINK_CONTROL_RCB                             : integer    := 0;
248
 
249
   MSI_BASE_PTR                                 : bit_vector := X"48";
250
   MSI_CAP_ID                                   : bit_vector := X"05";
251
   MSI_CAP_NEXTPTR                              : bit_vector := X"60";
252
   MSIX_BASE_PTR                                : bit_vector := X"9c";
253
   MSIX_CAP_ID                                  : bit_vector := X"11";
254
   MSIX_CAP_NEXTPTR                             : bit_vector := X"00";
255
   N_FTS_COMCLK_GEN1                            : integer    := 255;
256
   N_FTS_COMCLK_GEN2                            : integer    := 254;
257
   N_FTS_GEN1                                   : integer    := 255;
258
   N_FTS_GEN2                                   : integer    := 255;
259
 
260
   PCIE_BASE_PTR                                : bit_vector := X"60";
261
   PCIE_CAP_CAPABILITY_ID                       : bit_vector := X"10";
262
   PCIE_CAP_CAPABILITY_VERSION                  : bit_vector := X"2";
263
   PCIE_CAP_ON                                  : boolean    := TRUE;
264
   PCIE_CAP_RSVD_15_14                          : integer    := 0;
265
   PCIE_CAP_SLOT_IMPLEMENTED                    : boolean    := FALSE;
266
   PCIE_REVISION                                : integer    := 2;
267
   PGL0_LANE                                    : integer    := 0;
268
   PGL1_LANE                                    : integer    := 1;
269
   PGL2_LANE                                    : integer    := 2;
270
   PGL3_LANE                                    : integer    := 3;
271
   PGL4_LANE                                    : integer    := 4;
272
   PGL5_LANE                                    : integer    := 5;
273
   PGL6_LANE                                    : integer    := 6;
274
   PGL7_LANE                                    : integer    := 7;
275
   PL_AUTO_CONFIG                               : integer    := 0;
276
   PL_FAST_TRAIN                                : boolean    := FALSE;
277
 
278
   PM_BASE_PTR                                  : bit_vector := X"40";
279
   PM_CAP_AUXCURRENT                            : integer    := 0;
280
   PM_CAP_ID                                    : bit_vector := X"01";
281
   PM_CAP_ON                                    : boolean    := TRUE;
282
   PM_CAP_PME_CLOCK                             : boolean    := FALSE;
283
   PM_CAP_RSVD_04                               : integer    := 0;
284
   PM_CAP_VERSION                               : integer    := 3;
285
   PM_CSR_BPCCEN                                : boolean    := FALSE;
286
   PM_CSR_B2B3                                  : boolean    := FALSE;
287
 
288
   RECRC_CHK                                    : integer    := 0;
289
   RECRC_CHK_TRIM                               : boolean    := FALSE;
290
   ROOT_CAP_CRS_SW_VISIBILITY                   : boolean    := FALSE;
291
   SELECT_DLL_IF                                : boolean    := FALSE;
292
   SLOT_CAP_ATT_BUTTON_PRESENT                  : boolean    := FALSE;
293
   SLOT_CAP_ATT_INDICATOR_PRESENT               : boolean    := FALSE;
294
   SLOT_CAP_ELEC_INTERLOCK_PRESENT              : boolean    := FALSE;
295
   SLOT_CAP_HOTPLUG_CAPABLE                     : boolean    := FALSE;
296
   SLOT_CAP_HOTPLUG_SURPRISE                    : boolean    := FALSE;
297
   SLOT_CAP_MRL_SENSOR_PRESENT                  : boolean    := FALSE;
298
   SLOT_CAP_NO_CMD_COMPLETED_SUPPORT            : boolean    := FALSE;
299
   SLOT_CAP_PHYSICAL_SLOT_NUM                   : bit_vector := X"0000";
300
   SLOT_CAP_POWER_CONTROLLER_PRESENT            : boolean    := FALSE;
301
   SLOT_CAP_POWER_INDICATOR_PRESENT             : boolean    := FALSE;
302
   SLOT_CAP_SLOT_POWER_LIMIT_SCALE              : integer    := 0;
303
   SLOT_CAP_SLOT_POWER_LIMIT_VALUE              : bit_vector := X"00";
304
   SPARE_BIT1                                   : integer    := 0;
305
   SPARE_BIT2                                   : integer    := 0;
306
   SPARE_BIT3                                   : integer    := 0;
307
   SPARE_BIT4                                   : integer    := 0;
308
   SPARE_BIT5                                   : integer    := 0;
309
   SPARE_BIT6                                   : integer    := 0;
310
   SPARE_BIT7                                   : integer    := 0;
311
   SPARE_BIT8                                   : integer    := 0;
312
   SPARE_BYTE0                                  : bit_vector := X"00";
313
   SPARE_BYTE1                                  : bit_vector := X"00";
314
   SPARE_BYTE2                                  : bit_vector := X"00";
315
   SPARE_BYTE3                                  : bit_vector := X"00";
316
   SPARE_WORD0                                  : bit_vector := X"00000000";
317
   SPARE_WORD1                                  : bit_vector := X"00000000";
318
   SPARE_WORD2                                  : bit_vector := X"00000000";
319
   SPARE_WORD3                                  : bit_vector := X"00000000";
320
 
321
   TL_RBYPASS                                   : boolean    := FALSE;
322
   TL_TFC_DISABLE                               : boolean    := FALSE;
323
   TL_TX_CHECKS_DISABLE                         : boolean    := FALSE;
324
   EXIT_LOOPBACK_ON_EI                          : boolean    := TRUE;
325
   UPSTREAM_FACING                              : boolean    := TRUE;
326
   UR_INV_REQ                                   : boolean    := TRUE;
327
 
328
   VC_CAP_ID                                    : bit_vector := X"0002";
329
   VC_CAP_VERSION                               : bit_vector := X"1";
330
   VSEC_CAP_HDR_ID                              : bit_vector := X"1234";
331
   VSEC_CAP_HDR_LENGTH                          : bit_vector := X"018";
332
   VSEC_CAP_HDR_REVISION                        : bit_vector := X"1";
333
   VSEC_CAP_ID                                  : bit_vector := X"000b";
334
   VSEC_CAP_IS_LINK_VISIBLE                     : boolean    := TRUE;
335
   VSEC_CAP_VERSION                             : bit_vector := X"1"
336
      );
337
   port (
338
      ---------------------------------------------------------
339
      -- 1. PCI Express (pci_exp) Interface
340
      ---------------------------------------------------------
341
 
342
      -- Tx
343
      pci_exp_txp                               : out std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);
344
      pci_exp_txn                               : out std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);
345
 
346
      -- Rx
347
      pci_exp_rxp                               : in std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);
348
      pci_exp_rxn                               : in std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);
349
 
350
      ---------------------------------------------------------
351
      -- 2. Transaction (TRN) Interface
352
      ---------------------------------------------------------
353
 
354
      -- Common
355
      user_clk_out                              : out std_logic;
356
      user_reset_out                            : out std_logic;
357
      user_lnk_up                               : out std_logic;
358
 
359
      -- Tx
360
      tx_buf_av                                 : out std_logic_vector(5 downto 0);
361
      tx_cfg_req                                : out std_logic;
362
      tx_err_drop                               : out std_logic;
363
 
364
      s_axis_tx_tready                          : out std_logic;
365
      s_axis_tx_tdata                           : in std_logic_vector(63 downto 0);
366
      s_axis_tx_tstrb                           : in std_logic_vector(7 downto 0);
367
      s_axis_tx_tuser                           : in std_logic_vector(3 downto 0);
368
      s_axis_tx_tlast                           : in std_logic;
369
      s_axis_tx_tvalid                          : in std_logic;
370
 
371
      tx_cfg_gnt                                : in std_logic;
372
 
373
      -- Rx
374
      m_axis_rx_tdata                           : out std_logic_vector(63 downto 0);
375
      m_axis_rx_tstrb                           : out std_logic_vector(7 downto 0);
376
      m_axis_rx_tlast                           : out std_logic;
377
      m_axis_rx_tvalid                          : out std_logic;
378
      m_axis_rx_tuser                           : out std_logic_vector(21 downto 0);
379
      m_axis_rx_tready                          : in std_logic;
380
      rx_np_ok                                  : in std_logic;
381
 
382
      -- Flow Control
383
      fc_cpld                                   : out std_logic_vector(11 downto 0);
384
      fc_cplh                                   : out std_logic_vector(7 downto 0);
385
      fc_npd                                    : out std_logic_vector(11 downto 0);
386
      fc_nph                                    : out std_logic_vector(7 downto 0);
387
      fc_pd                                     : out std_logic_vector(11 downto 0);
388
      fc_ph                                     : out std_logic_vector(7 downto 0);
389
      fc_sel                                    : in std_logic_vector(2 downto 0);
390
 
391
      ---------------------------------------------------------
392
      -- 3. Configuration (CFG) Interface
393
      ---------------------------------------------------------
394
 
395
      cfg_do                                    : out std_logic_vector(31 downto 0);
396
      cfg_rd_wr_done                            : out std_logic;
397
      cfg_di                                    : in std_logic_vector(31 downto 0);
398
      cfg_byte_en                               : in std_logic_vector(3 downto 0);
399
      cfg_dwaddr                                : in std_logic_vector(9 downto 0);
400
      cfg_wr_en                                 : in std_logic;
401
      cfg_rd_en                                 : in std_logic;
402
 
403
      cfg_err_cor                               : in std_logic;
404
      cfg_err_ur                                : in std_logic;
405
      cfg_err_ecrc                              : in std_logic;
406
      cfg_err_cpl_timeout                       : in std_logic;
407
      cfg_err_cpl_abort                         : in std_logic;
408
      cfg_err_cpl_unexpect                      : in std_logic;
409
      cfg_err_posted                            : in std_logic;
410
      cfg_err_locked                            : in std_logic;
411
      cfg_err_tlp_cpl_header                    : in std_logic_vector(47 downto 0);
412
      cfg_err_cpl_rdy                           : out std_logic;
413
      cfg_interrupt                             : in std_logic;
414
      cfg_interrupt_rdy                         : out std_logic;
415
      cfg_interrupt_assert                      : in std_logic;
416
      cfg_interrupt_di                          : in std_logic_vector(7 downto 0);
417
      cfg_interrupt_do                          : out std_logic_vector(7 downto 0);
418
      cfg_interrupt_mmenable                    : out std_logic_vector(2 downto 0);
419
      cfg_interrupt_msienable                   : out std_logic;
420
      cfg_interrupt_msixenable                  : out std_logic;
421
      cfg_interrupt_msixfm                      : out std_logic;
422
      cfg_turnoff_ok                            : in std_logic;
423
      cfg_to_turnoff                            : out std_logic;
424
      cfg_trn_pending                           : in std_logic;
425
      cfg_pm_wake                               : in std_logic;
426
      cfg_bus_number                            : out std_logic_vector(7 downto 0);
427
      cfg_device_number                         : out std_logic_vector(4 downto 0);
428
      cfg_function_number                       : out std_logic_vector(2 downto 0);
429
      cfg_status                                : out std_logic_vector(15 downto 0);
430
      cfg_command                               : out std_logic_vector(15 downto 0);
431
      cfg_dstatus                               : out std_logic_vector(15 downto 0);
432
      cfg_dcommand                              : out std_logic_vector(15 downto 0);
433
      cfg_lstatus                               : out std_logic_vector(15 downto 0);
434
      cfg_lcommand                              : out std_logic_vector(15 downto 0);
435
      cfg_dcommand2                             : out std_logic_vector(15 downto 0);
436
      cfg_pcie_link_state                       : out std_logic_vector(2 downto 0);
437
      cfg_dsn                                   : in std_logic_vector(63 downto 0);
438
      cfg_pmcsr_pme_en                          : out std_logic;
439
      cfg_pmcsr_pme_status                      : out std_logic;
440
      cfg_pmcsr_powerstate                      : out std_logic_vector(1 downto 0);
441
 
442
      ---------------------------------------------------------
443
      -- 4. Physical Layer Control and Status (PL) Interface
444
      ---------------------------------------------------------
445
 
446
      pl_initial_link_width                     : out std_logic_vector(2 downto 0);
447
      pl_lane_reversal_mode                     : out std_logic_vector(1 downto 0);
448
      pl_link_gen2_capable                      : out std_logic;
449
      pl_link_partner_gen2_supported            : out std_logic;
450
      pl_link_upcfg_capable                     : out std_logic;
451
      pl_ltssm_state                            : out std_logic_vector(5 downto 0);
452
      pl_received_hot_rst                       : out std_logic;
453
      pl_sel_link_rate                          : out std_logic;
454
      pl_sel_link_width                         : out std_logic_vector(1 downto 0);
455
      pl_directed_link_auton                    : in std_logic;
456
      pl_directed_link_change                   : in std_logic_vector(1 downto 0);
457
      pl_directed_link_speed                    : in std_logic;
458
      pl_directed_link_width                    : in std_logic_vector(1 downto 0);
459
      pl_upstream_prefer_deemph                 : in std_logic;
460
 
461
      ---------------------------------------------------------
462
      -- 5. System  (SYS) Interface
463
      ---------------------------------------------------------
464
 
465
      sys_clk                                   : in std_logic;
466
      sys_reset                                 : in std_logic
467
   );
468
end cl_v6pcie_x4;
469
 
470
architecture v6_pcie of cl_v6pcie_x4 is
471
 
472
   attribute CORE_GENERATION_INFO : string;
473
   attribute CORE_GENERATION_INFO of v6_pcie : ARCHITECTURE is
474
     "cl_v6pcie_x4,v6_pcie_v2_3,{LINK_CAP_MAX_LINK_SPEED=2,LINK_CAP_MAX_LINK_WIDTH=04,PCIE_CAP_DEVICE_PORT_TYPE=0000,DEV_CAP_MAX_PAYLOAD_SUPPORTED=1,USER_CLK_FREQ=3,REF_CLK_FREQ=0,MSI_CAP_ON=FALSE,MSI_CAP_MULTIMSGCAP=0,MSI_CAP_MULTIMSG_EXTENSION=0,MSIX_CAP_ON=FALSE,TL_TX_RAM_RADDR_LATENCY=0,TL_TX_RAM_RDATA_LATENCY=2,TL_RX_RAM_RADDR_LATENCY=0,TL_RX_RAM_RDATA_LATENCY=2,TL_RX_RAM_WRITE_LATENCY=0,VC0_TX_LASTPACKET=28,VC0_RX_RAM_LIMIT=3FF,VC0_TOTAL_CREDITS_PH=32,VC0_TOTAL_CREDITS_PD=32,VC0_TOTAL_CREDITS_NPH=12,VC0_TOTAL_CREDITS_CH=36,VC0_TOTAL_CREDITS_CD=378,VC0_CPL_INFINITE=TRUE,DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT=0,DEV_CAP_EXT_TAG_SUPPORTED=FALSE,LINK_STATUS_SLOT_CLOCK_CONFIG=TRUE,ENABLE_RX_TD_ECRC_TRIM=TRUE,DISABLE_LANE_REVERSAL=TRUE,DISABLE_SCRAMBLING=FALSE,DSN_CAP_ON=FALSE,PIPE_PIPELINE_STAGES=0,REVISION_ID=20,VC_CAP_ON=FALSE}";
475
 
476
   component axi_basic_top
477
   generic (
478
      C_DATA_WIDTH              : integer := 32;     -- rx/tx interface data width
479
      C_FAMILY                  : string  := "x7";    -- targeted fpga family
480
      C_ROOT_PORT               : BOOLEAN := FALSE; -- pcie block is in root port mode
481
      C_PM_PRIORITY             : BOOLEAN := FALSE; -- disable tx packet boundary thrtl
482
      TCQ                       : integer := 1;      -- clock to q time
483
 
484
      C_REM_WIDTH               : integer := 1;      -- trem/rrem width
485
      C_STRB_WIDTH              : integer := 4       -- tstrb width
486
   );
487
   port (
488
      -----------------------------------------------
489
      -- user design I/O
490
      -----------------------------------------------
491
 
492
      -- AXI TX
493
      -------------
494
      s_axis_tx_tdata         : in std_logic_vector(C_DATA_WIDTH - 1 downto 0) := (others=>'0');
495
      s_axis_tx_tvalid        : in std_logic                                   := '0';
496
      s_axis_tx_tready        : out std_logic                                  := '0';
497
      s_axis_tx_tstrb         : in std_logic_vector(C_STRB_WIDTH - 1 downto 0) := (others=>'0');
498
      s_axis_tx_tlast         : in std_logic                                   := '0';
499
      s_axis_tx_tuser         : in std_logic_vector(3 downto 0) := (others=>'0');
500
 
501
      -- AXI RX
502
      -------------
503
      m_axis_rx_tdata         : out std_logic_vector(C_DATA_WIDTH - 1 downto 0) := (others=>'0');
504
      m_axis_rx_tvalid        : out std_logic                                   := '0';
505
      m_axis_rx_tready        : in std_logic                                    := '0';
506
      m_axis_rx_tstrb         : out std_logic_vector(C_STRB_WIDTH - 1 downto 0) := (others=>'0');
507
      m_axis_rx_tlast         : out std_logic                                   := '0';
508
      m_axis_rx_tuser         : out std_logic_vector(21 downto 0) := (others=>'0');
509
 
510
      -- user misc.
511
      -------------
512
      user_turnoff_ok         : in std_logic                                   := '0';
513
      user_tcfg_gnt           : in std_logic                                   := '0';
514
 
515
      -----------------------------------------------
516
      -- PCIe block I/O
517
      -----------------------------------------------
518
 
519
      -- TRN TX
520
      -------------
521
      trn_td                  : out std_logic_vector(C_DATA_WIDTH - 1 downto 0) := (others=>'0');
522
      trn_tsof                : out std_logic                                   := '0';
523
      trn_teof                : out std_logic                                   := '0';
524
      trn_tsrc_rdy            : out std_logic                                   := '0';
525
      trn_tdst_rdy            : in std_logic                                    := '0';
526
      trn_tsrc_dsc            : out std_logic                                   := '0';
527
      trn_trem                : out std_logic_vector(C_REM_WIDTH - 1 downto 0)  := (others=>'0');
528
      trn_terrfwd             : out std_logic                                   := '0';
529
      trn_tstr                : out std_logic                                   := '0';
530
      trn_tbuf_av             : in std_logic_vector(5 downto 0)                 := (others=>'0');
531
      trn_tecrc_gen           : out std_logic                                   := '0';
532
 
533
      -- TRN RX
534
      -------------
535
      trn_rd                  : in std_logic_vector(C_DATA_WIDTH - 1 downto 0) := (others=>'0');
536
      trn_rsof                : in std_logic                                   := '0';
537
      trn_reof                : in std_logic                                   := '0';
538
      trn_rsrc_rdy            : in std_logic                                   := '0';
539
      trn_rdst_rdy            : out std_logic                                  := '0';
540
      trn_rsrc_dsc            : in std_logic                                   := '0';
541
      trn_rrem                : in std_logic_vector(C_REM_WIDTH - 1 downto 0)  := (others=>'0');
542
      trn_rerrfwd             : in std_logic                                   := '0';
543
      trn_rbar_hit            : in std_logic_vector(6 downto 0)                := (others=>'0');
544
      trn_recrc_err           : in std_logic                                   := '0';
545
 
546
      -- TRN misc.
547
      -------------
548
      trn_tcfg_req            : in std_logic                                   := '0';
549
      trn_tcfg_gnt            : out std_logic                                  := '0';
550
      trn_lnk_up              : in std_logic                                   := '0';
551
 
552
      -- 7 series/Virtex6 PM
553
      -------------
554
      cfg_pcie_link_state     : in std_logic_vector(2 downto 0)                := (others=>'0');
555
 
556
      -- Virtex6 PM
557
      -------------
558
      cfg_pm_send_pme_to      : in std_logic                                   := '0';
559
      cfg_pmcsr_powerstate    : in std_logic_vector(1 downto 0)                := (others=>'0');
560
      trn_rdllp_data          : in std_logic_vector(31 downto 0)               := (others=>'0');
561
      trn_rdllp_src_rdy       : in std_logic                                   := '0';
562
 
563
      -- Virtex6/Spartan6 PM
564
      -------------
565
      cfg_to_turnoff          : in std_logic                                   := '0';
566
      cfg_turnoff_ok          : out std_logic                                  := '0';
567
 
568
      np_counter              : out std_logic_vector(2 downto 0)               := (others=>'0');
569
      user_clk                : in std_logic                                   := '0';
570
      user_rst                : in std_logic                                   := '0'
571
   );
572
   end component;
573
 
574
  component pcie_reset_delay_v6
575
    generic (
576
      PL_FAST_TRAIN : boolean;
577
      REF_CLK_FREQ  : integer);
578
    port (
579
      ref_clk             : in  std_logic;
580
      sys_reset_n         : in  std_logic;
581
      delayed_sys_reset_n : out std_logic);
582
  end component;
583
 
584
  component pcie_clocking_v6
585
    generic (
586
      CAP_LINK_WIDTH : integer;
587
      CAP_LINK_SPEED : integer;
588
      REF_CLK_FREQ   : integer;
589
      USER_CLK_FREQ  : integer);
590
    port (
591
      sys_clk       : in  std_logic;
592
      gt_pll_lock   : in  std_logic;
593
      sel_lnk_rate  : in  std_logic;
594
      sel_lnk_width : in  std_logic_vector(1 downto 0);
595
      sys_clk_bufg  : out std_logic;
596
      pipe_clk      : out std_logic;
597
      user_clk      : out std_logic;
598
      block_clk     : out std_logic;
599
      drp_clk       : out std_logic;
600
      clock_locked  : out std_logic);
601
  end component;
602
 
603
  component pcie_2_0_v6
604
    generic (
605
      REF_CLK_FREQ                             : integer;
606
      PIPE_PIPELINE_STAGES                     : integer;
607
      LINK_CAP_MAX_LINK_WIDTH_int              : integer;
608
      AER_BASE_PTR                             : bit_vector;
609
      AER_CAP_ECRC_CHECK_CAPABLE               : boolean;
610
      AER_CAP_ECRC_GEN_CAPABLE                 : boolean;
611
      AER_CAP_ID                               : bit_vector;
612
      AER_CAP_INT_MSG_NUM_MSI                  : bit_vector;
613
      AER_CAP_INT_MSG_NUM_MSIX                 : bit_vector;
614
      AER_CAP_NEXTPTR                          : bit_vector;
615
      AER_CAP_ON                               : boolean;
616
      AER_CAP_PERMIT_ROOTERR_UPDATE            : boolean;
617
      AER_CAP_VERSION                          : bit_vector;
618
      ALLOW_X8_GEN2                            : boolean;
619
      BAR0                                     : bit_vector;
620
      BAR1                                     : bit_vector;
621
      BAR2                                     : bit_vector;
622
      BAR3                                     : bit_vector;
623
      BAR4                                     : bit_vector;
624
      BAR5                                     : bit_vector;
625
      CAPABILITIES_PTR                         : bit_vector;
626
      CARDBUS_CIS_POINTER                      : bit_vector;
627
      CLASS_CODE                               : bit_vector;
628
      CMD_INTX_IMPLEMENTED                     : boolean;
629
      CPL_TIMEOUT_DISABLE_SUPPORTED            : boolean;
630
      CPL_TIMEOUT_RANGES_SUPPORTED             : bit_vector;
631
      CRM_MODULE_RSTS                          : bit_vector;
632
      DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE      : boolean;
633
      DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE      : boolean;
634
      DEV_CAP_ENDPOINT_L0S_LATENCY             : integer;
635
      DEV_CAP_ENDPOINT_L1_LATENCY              : integer;
636
      DEV_CAP_EXT_TAG_SUPPORTED                : boolean;
637
      DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE     : boolean;
638
      DEV_CAP_MAX_PAYLOAD_SUPPORTED            : integer;
639
      DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT        : integer;
640
      DEV_CAP_ROLE_BASED_ERROR                 : boolean;
641
      DEV_CAP_RSVD_14_12                       : integer;
642
      DEV_CAP_RSVD_17_16                       : integer;
643
      DEV_CAP_RSVD_31_29                       : integer;
644
      DEV_CONTROL_AUX_POWER_SUPPORTED          : boolean;
645
      DEVICE_ID                                : bit_vector;
646
      DISABLE_ASPM_L1_TIMER                    : boolean;
647
      DISABLE_BAR_FILTERING                    : boolean;
648
      DISABLE_ID_CHECK                         : boolean;
649
      DISABLE_LANE_REVERSAL                    : boolean;
650
      DISABLE_RX_TC_FILTER                     : boolean;
651
      DISABLE_SCRAMBLING                       : boolean;
652
      DNSTREAM_LINK_NUM                        : bit_vector;
653
      DSN_BASE_PTR                             : bit_vector;
654
      DSN_CAP_ID                               : bit_vector;
655
      DSN_CAP_NEXTPTR                          : bit_vector;
656
      DSN_CAP_ON                               : boolean;
657
      DSN_CAP_VERSION                          : bit_vector;
658
      ENABLE_MSG_ROUTE                         : bit_vector;
659
      ENABLE_RX_TD_ECRC_TRIM                   : boolean;
660
      ENTER_RVRY_EI_L0                         : boolean;
661
      EXPANSION_ROM                            : bit_vector;
662
      EXT_CFG_CAP_PTR                          : bit_vector;
663
      EXT_CFG_XP_CAP_PTR                       : bit_vector;
664
      HEADER_TYPE                              : bit_vector;
665
      INFER_EI                                 : bit_vector;
666
      INTERRUPT_PIN                            : bit_vector;
667
      IS_SWITCH                                : boolean;
668
      LAST_CONFIG_DWORD                        : bit_vector;
669
      LINK_CAP_ASPM_SUPPORT                    : integer;
670
      LINK_CAP_CLOCK_POWER_MANAGEMENT          : boolean;
671
      LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP   : boolean;
672
      LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1    : integer;
673
      LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2    : integer;
674
      LINK_CAP_L0S_EXIT_LATENCY_GEN1           : integer;
675
      LINK_CAP_L0S_EXIT_LATENCY_GEN2           : integer;
676
      LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1     : integer;
677
      LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2     : integer;
678
      LINK_CAP_L1_EXIT_LATENCY_GEN1            : integer;
679
      LINK_CAP_L1_EXIT_LATENCY_GEN2            : integer;
680
      LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP : boolean;
681
      LINK_CAP_MAX_LINK_SPEED                  : bit_vector;
682
      LINK_CAP_MAX_LINK_WIDTH                  : bit_vector;
683
      LINK_CAP_RSVD_23_22                      : integer;
684
      LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE     : boolean;
685
      LINK_CONTROL_RCB                         : integer;
686
      LINK_CTRL2_DEEMPHASIS                    : boolean;
687
      LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE   : boolean;
688
      LINK_CTRL2_TARGET_LINK_SPEED             : bit_vector;
689
      LINK_STATUS_SLOT_CLOCK_CONFIG            : boolean;
690
      LL_ACK_TIMEOUT                           : bit_vector;
691
      LL_ACK_TIMEOUT_EN                        : boolean;
692
      LL_ACK_TIMEOUT_FUNC                      : integer;
693
      LL_REPLAY_TIMEOUT                        : bit_vector;
694
      LL_REPLAY_TIMEOUT_EN                     : boolean;
695
      LL_REPLAY_TIMEOUT_FUNC                   : integer;
696
      LTSSM_MAX_LINK_WIDTH                     : bit_vector;
697
      MSI_BASE_PTR                             : bit_vector;
698
      MSI_CAP_ID                               : bit_vector;
699
      MSI_CAP_MULTIMSGCAP                      : integer;
700
      MSI_CAP_MULTIMSG_EXTENSION               : integer;
701
      MSI_CAP_NEXTPTR                          : bit_vector;
702
      MSI_CAP_ON                               : boolean;
703
      MSI_CAP_PER_VECTOR_MASKING_CAPABLE       : boolean;
704
      MSI_CAP_64_BIT_ADDR_CAPABLE              : boolean;
705
      MSIX_BASE_PTR                            : bit_vector;
706
      MSIX_CAP_ID                              : bit_vector;
707
      MSIX_CAP_NEXTPTR                         : bit_vector;
708
      MSIX_CAP_ON                              : boolean;
709
      MSIX_CAP_PBA_BIR                         : integer;
710
      MSIX_CAP_PBA_OFFSET                      : bit_vector;
711
      MSIX_CAP_TABLE_BIR                       : integer;
712
      MSIX_CAP_TABLE_OFFSET                    : bit_vector;
713
      MSIX_CAP_TABLE_SIZE                      : bit_vector;
714
      N_FTS_COMCLK_GEN1                        : integer;
715
      N_FTS_COMCLK_GEN2                        : integer;
716
      N_FTS_GEN1                               : integer;
717
      N_FTS_GEN2                               : integer;
718
      PCIE_BASE_PTR                            : bit_vector;
719
      PCIE_CAP_CAPABILITY_ID                   : bit_vector;
720
      PCIE_CAP_CAPABILITY_VERSION              : bit_vector;
721
      PCIE_CAP_DEVICE_PORT_TYPE                : bit_vector;
722
      PCIE_CAP_INT_MSG_NUM                     : bit_vector;
723
      PCIE_CAP_NEXTPTR                         : bit_vector;
724
      PCIE_CAP_ON                              : boolean;
725
      PCIE_CAP_RSVD_15_14                      : integer;
726
      PCIE_CAP_SLOT_IMPLEMENTED                : boolean;
727
      PCIE_REVISION                            : integer;
728
      PGL0_LANE                                : integer;
729
      PGL1_LANE                                : integer;
730
      PGL2_LANE                                : integer;
731
      PGL3_LANE                                : integer;
732
      PGL4_LANE                                : integer;
733
      PGL5_LANE                                : integer;
734
      PGL6_LANE                                : integer;
735
      PGL7_LANE                                : integer;
736
      PL_AUTO_CONFIG                           : integer;
737
      PL_FAST_TRAIN                            : boolean;
738
      PM_BASE_PTR                              : bit_vector;
739
      PM_CAP_AUXCURRENT                        : integer;
740
      PM_CAP_DSI                               : boolean;
741
      PM_CAP_D1SUPPORT                         : boolean;
742
      PM_CAP_D2SUPPORT                         : boolean;
743
      PM_CAP_ID                                : bit_vector;
744
      PM_CAP_NEXTPTR                           : bit_vector;
745
      PM_CAP_ON                                : boolean;
746
      PM_CAP_PME_CLOCK                         : boolean;
747
      PM_CAP_PMESUPPORT                        : bit_vector;
748
      PM_CAP_RSVD_04                           : integer;
749
      PM_CAP_VERSION                           : integer;
750
      PM_CSR_BPCCEN                            : boolean;
751
      PM_CSR_B2B3                              : boolean;
752
      PM_CSR_NOSOFTRST                         : boolean;
753
      PM_DATA0                                 : bit_vector;
754
      PM_DATA1                                 : bit_vector;
755
      PM_DATA2                                 : bit_vector;
756
      PM_DATA3                                 : bit_vector;
757
      PM_DATA4                                 : bit_vector;
758
      PM_DATA5                                 : bit_vector;
759
      PM_DATA6                                 : bit_vector;
760
      PM_DATA7                                 : bit_vector;
761
      PM_DATA_SCALE0                           : bit_vector;
762
      PM_DATA_SCALE1                           : bit_vector;
763
      PM_DATA_SCALE2                           : bit_vector;
764
      PM_DATA_SCALE3                           : bit_vector;
765
      PM_DATA_SCALE4                           : bit_vector;
766
      PM_DATA_SCALE5                           : bit_vector;
767
      PM_DATA_SCALE6                           : bit_vector;
768
      PM_DATA_SCALE7                           : bit_vector;
769
      RECRC_CHK                                : integer;
770
      RECRC_CHK_TRIM                           : boolean;
771
      REVISION_ID                              : bit_vector;
772
      ROOT_CAP_CRS_SW_VISIBILITY               : boolean;
773
      SELECT_DLL_IF                            : boolean;
774
      SLOT_CAP_ATT_BUTTON_PRESENT              : boolean;
775
      SLOT_CAP_ATT_INDICATOR_PRESENT           : boolean;
776
      SLOT_CAP_ELEC_INTERLOCK_PRESENT          : boolean;
777
      SLOT_CAP_HOTPLUG_CAPABLE                 : boolean;
778
      SLOT_CAP_HOTPLUG_SURPRISE                : boolean;
779
      SLOT_CAP_MRL_SENSOR_PRESENT              : boolean;
780
      SLOT_CAP_NO_CMD_COMPLETED_SUPPORT        : boolean;
781
      SLOT_CAP_PHYSICAL_SLOT_NUM               : bit_vector;
782
      SLOT_CAP_POWER_CONTROLLER_PRESENT        : boolean;
783
      SLOT_CAP_POWER_INDICATOR_PRESENT         : boolean;
784
      SLOT_CAP_SLOT_POWER_LIMIT_SCALE          : integer;
785
      SLOT_CAP_SLOT_POWER_LIMIT_VALUE          : bit_vector;
786
      SPARE_BIT0                               : integer;
787
      SPARE_BIT1                               : integer;
788
      SPARE_BIT2                               : integer;
789
      SPARE_BIT3                               : integer;
790
      SPARE_BIT4                               : integer;
791
      SPARE_BIT5                               : integer;
792
      SPARE_BIT6                               : integer;
793
      SPARE_BIT7                               : integer;
794
      SPARE_BIT8                               : integer;
795
      SPARE_BYTE0                              : bit_vector;
796
      SPARE_BYTE1                              : bit_vector;
797
      SPARE_BYTE2                              : bit_vector;
798
      SPARE_BYTE3                              : bit_vector;
799
      SPARE_WORD0                              : bit_vector;
800
      SPARE_WORD1                              : bit_vector;
801
      SPARE_WORD2                              : bit_vector;
802
      SPARE_WORD3                              : bit_vector;
803
      SUBSYSTEM_ID                             : bit_vector;
804
      SUBSYSTEM_VENDOR_ID                      : bit_vector;
805
      TL_RBYPASS                               : boolean;
806
      TL_RX_RAM_RADDR_LATENCY                  : integer;
807
      TL_RX_RAM_RDATA_LATENCY                  : integer;
808
      TL_RX_RAM_WRITE_LATENCY                  : integer;
809
      TL_TFC_DISABLE                           : boolean;
810
      TL_TX_CHECKS_DISABLE                     : boolean;
811
      TL_TX_RAM_RADDR_LATENCY                  : integer;
812
      TL_TX_RAM_RDATA_LATENCY                  : integer;
813
      TL_TX_RAM_WRITE_LATENCY                  : integer;
814
      UPCONFIG_CAPABLE                         : boolean;
815
      UPSTREAM_FACING                          : boolean;
816
      UR_INV_REQ                               : boolean;
817
      USER_CLK_FREQ                            : integer;
818
      EXIT_LOOPBACK_ON_EI                      : boolean;
819
      VC_BASE_PTR                              : bit_vector;
820
      VC_CAP_ID                                : bit_vector;
821
      VC_CAP_NEXTPTR                           : bit_vector;
822
      VC_CAP_ON                                : boolean;
823
      VC_CAP_REJECT_SNOOP_TRANSACTIONS         : boolean;
824
      VC_CAP_VERSION                           : bit_vector;
825
      VC0_CPL_INFINITE                         : boolean;
826
      VC0_RX_RAM_LIMIT                         : bit_vector;
827
      VC0_TOTAL_CREDITS_CD                     : integer;
828
      VC0_TOTAL_CREDITS_CH                     : integer;
829
      VC0_TOTAL_CREDITS_NPH                    : integer;
830
      VC0_TOTAL_CREDITS_PD                     : integer;
831
      VC0_TOTAL_CREDITS_PH                     : integer;
832
      VC0_TX_LASTPACKET                        : integer;
833
      VENDOR_ID                                : bit_vector;
834
      VSEC_BASE_PTR                            : bit_vector;
835
      VSEC_CAP_HDR_ID                          : bit_vector;
836
      VSEC_CAP_HDR_LENGTH                      : bit_vector;
837
      VSEC_CAP_HDR_REVISION                    : bit_vector;
838
      VSEC_CAP_ID                              : bit_vector;
839
      VSEC_CAP_IS_LINK_VISIBLE                 : boolean;
840
      VSEC_CAP_NEXTPTR                         : bit_vector;
841
      VSEC_CAP_ON                              : boolean;
842
      VSEC_CAP_VERSION                         : bit_vector);
843
    port (
844
      PCIEXPRXN                           : in  std_logic_vector(3 downto 0);
845
      PCIEXPRXP                           : in  std_logic_vector(3 downto 0);
846
      PCIEXPTXN                           : out std_logic_vector(3 downto 0);
847
      PCIEXPTXP                           : out std_logic_vector(3 downto 0);
848
      SYSCLK                              : in  std_logic;
849
      FUNDRSTN                            : in  std_logic;
850
      TRNLNKUPN                           : out std_logic;
851
      PHYRDYN                             : out std_logic;
852
      USERRSTN                            : out std_logic;
853
      RECEIVEDFUNCLVLRSTN                 : out std_logic;
854
      LNKCLKEN                            : out std_logic;
855
      SYSRSTN                             : in  std_logic;
856
      PLRSTN                              : in  std_logic;
857
      DLRSTN                              : in  std_logic;
858
      TLRSTN                              : in  std_logic;
859
      FUNCLVLRSTN                         : in  std_logic;
860
      CMRSTN                              : in  std_logic;
861
      CMSTICKYRSTN                        : in  std_logic;
862
      TRNRBARHITN                         : out std_logic_vector(6 downto 0);
863
      TRNRD                               : out std_logic_vector(63 downto 0);
864
      TRNRECRCERRN                        : out std_logic;
865
      TRNREOFN                            : out std_logic;
866
      TRNRERRFWDN                         : out std_logic;
867
      TRNRREMN                            : out std_logic;
868
      TRNRSOFN                            : out std_logic;
869
      TRNRSRCDSCN                         : out std_logic;
870
      TRNRSRCRDYN                         : out std_logic;
871
      TRNRDSTRDYN                         : in  std_logic;
872
      TRNRNPOKN                           : in  std_logic;
873
      TRNRDLLPDATA                        : out std_logic_vector(31 downto 0);
874
      TRNRDLLPSRCRDYN                     : out std_logic;
875
      TRNTBUFAV                           : out std_logic_vector(5 downto 0);
876
      TRNTCFGREQN                         : out std_logic;
877
      TRNTDLLPDSTRDYN                     : out std_logic;
878
      TRNTDSTRDYN                         : out std_logic;
879
      TRNTERRDROPN                        : out std_logic;
880
      TRNTCFGGNTN                         : in  std_logic;
881
      TRNTD                               : in  std_logic_vector(63 downto 0);
882
      TRNTDLLPDATA                        : in  std_logic_vector(31 downto 0);
883
      TRNTDLLPSRCRDYN                     : in  std_logic;
884
      TRNTECRCGENN                        : in  std_logic;
885
      TRNTEOFN                            : in  std_logic;
886
      TRNTERRFWDN                         : in  std_logic;
887
      TRNTREMN                            : in  std_logic;
888
      TRNTSOFN                            : in  std_logic;
889
      TRNTSRCDSCN                         : in  std_logic;
890
      TRNTSRCRDYN                         : in  std_logic;
891
      TRNTSTRN                            : in  std_logic;
892
      TRNFCCPLD                           : out std_logic_vector(11 downto 0);
893
      TRNFCCPLH                           : out std_logic_vector(7 downto 0);
894
      TRNFCNPD                            : out std_logic_vector(11 downto 0);
895
      TRNFCNPH                            : out std_logic_vector(7 downto 0);
896
      TRNFCPD                             : out std_logic_vector(11 downto 0);
897
      TRNFCPH                             : out std_logic_vector(7 downto 0);
898
      TRNFCSEL                            : in  std_logic_vector(2 downto 0);
899
      CFGAERECRCCHECKEN                   : out std_logic;
900
      CFGAERECRCGENEN                     : out std_logic;
901
      CFGCOMMANDBUSMASTERENABLE           : out std_logic;
902
      CFGCOMMANDINTERRUPTDISABLE          : out std_logic;
903
      CFGCOMMANDIOENABLE                  : out std_logic;
904
      CFGCOMMANDMEMENABLE                 : out std_logic;
905
      CFGCOMMANDSERREN                    : out std_logic;
906
      CFGDEVCONTROLAUXPOWEREN             : out std_logic;
907
      CFGDEVCONTROLCORRERRREPORTINGEN     : out std_logic;
908
      CFGDEVCONTROLENABLERO               : out std_logic;
909
      CFGDEVCONTROLEXTTAGEN               : out std_logic;
910
      CFGDEVCONTROLFATALERRREPORTINGEN    : out std_logic;
911
      CFGDEVCONTROLMAXPAYLOAD             : out std_logic_vector(2 downto 0);
912
      CFGDEVCONTROLMAXREADREQ             : out std_logic_vector(2 downto 0);
913
      CFGDEVCONTROLNONFATALREPORTINGEN    : out std_logic;
914
      CFGDEVCONTROLNOSNOOPEN              : out std_logic;
915
      CFGDEVCONTROLPHANTOMEN              : out std_logic;
916
      CFGDEVCONTROLURERRREPORTINGEN       : out std_logic;
917
      CFGDEVCONTROL2CPLTIMEOUTDIS         : out std_logic;
918
      CFGDEVCONTROL2CPLTIMEOUTVAL         : out std_logic_vector(3 downto 0);
919
      CFGDEVSTATUSCORRERRDETECTED         : out std_logic;
920
      CFGDEVSTATUSFATALERRDETECTED        : out std_logic;
921
      CFGDEVSTATUSNONFATALERRDETECTED     : out std_logic;
922
      CFGDEVSTATUSURDETECTED              : out std_logic;
923
      CFGDO                               : out std_logic_vector(31 downto 0);
924
      CFGERRAERHEADERLOGSETN              : out std_logic;
925
      CFGERRCPLRDYN                       : out std_logic;
926
      CFGINTERRUPTDO                      : out std_logic_vector(7 downto 0);
927
      CFGINTERRUPTMMENABLE                : out std_logic_vector(2 downto 0);
928
      CFGINTERRUPTMSIENABLE               : out std_logic;
929
      CFGINTERRUPTMSIXENABLE              : out std_logic;
930
      CFGINTERRUPTMSIXFM                  : out std_logic;
931
      CFGINTERRUPTRDYN                    : out std_logic;
932
      CFGLINKCONTROLRCB                   : out std_logic;
933
      CFGLINKCONTROLASPMCONTROL           : out std_logic_vector(1 downto 0);
934
      CFGLINKCONTROLAUTOBANDWIDTHINTEN    : out std_logic;
935
      CFGLINKCONTROLBANDWIDTHINTEN        : out std_logic;
936
      CFGLINKCONTROLCLOCKPMEN             : out std_logic;
937
      CFGLINKCONTROLCOMMONCLOCK           : out std_logic;
938
      CFGLINKCONTROLEXTENDEDSYNC          : out std_logic;
939
      CFGLINKCONTROLHWAUTOWIDTHDIS        : out std_logic;
940
      CFGLINKCONTROLLINKDISABLE           : out std_logic;
941
      CFGLINKCONTROLRETRAINLINK           : out std_logic;
942
      CFGLINKSTATUSAUTOBANDWIDTHSTATUS    : out std_logic;
943
      CFGLINKSTATUSBANDWITHSTATUS         : out std_logic;
944
      CFGLINKSTATUSCURRENTSPEED           : out std_logic_vector(1 downto 0);
945
      CFGLINKSTATUSDLLACTIVE              : out std_logic;
946
      CFGLINKSTATUSLINKTRAINING           : out std_logic;
947
      CFGLINKSTATUSNEGOTIATEDWIDTH        : out std_logic_vector(3 downto 0);
948
      CFGMSGDATA                          : out std_logic_vector(15 downto 0);
949
      CFGMSGRECEIVED                      : out std_logic;
950
      CFGMSGRECEIVEDASSERTINTA            : out std_logic;
951
      CFGMSGRECEIVEDASSERTINTB            : out std_logic;
952
      CFGMSGRECEIVEDASSERTINTC            : out std_logic;
953
      CFGMSGRECEIVEDASSERTINTD            : out std_logic;
954
      CFGMSGRECEIVEDDEASSERTINTA          : out std_logic;
955
      CFGMSGRECEIVEDDEASSERTINTB          : out std_logic;
956
      CFGMSGRECEIVEDDEASSERTINTC          : out std_logic;
957
      CFGMSGRECEIVEDDEASSERTINTD          : out std_logic;
958
      CFGMSGRECEIVEDERRCOR                : out std_logic;
959
      CFGMSGRECEIVEDERRFATAL              : out std_logic;
960
      CFGMSGRECEIVEDERRNONFATAL           : out std_logic;
961
      CFGMSGRECEIVEDPMASNAK               : out std_logic;
962
      CFGMSGRECEIVEDPMETO                 : out std_logic;
963
      CFGMSGRECEIVEDPMETOACK              : out std_logic;
964
      CFGMSGRECEIVEDPMPME                 : out std_logic;
965
      CFGMSGRECEIVEDSETSLOTPOWERLIMIT     : out std_logic;
966
      CFGMSGRECEIVEDUNLOCK                : out std_logic;
967
      CFGPCIELINKSTATE                    : out std_logic_vector(2 downto 0);
968
      CFGPMCSRPMEEN                       : out std_logic;
969
      CFGPMCSRPMESTATUS                   : out std_logic;
970
      CFGPMCSRPOWERSTATE                  : out std_logic_vector(1 downto 0);
971
      CFGPMRCVASREQL1N                    : out std_logic;
972
      CFGPMRCVENTERL1N                    : out std_logic;
973
      CFGPMRCVENTERL23N                   : out std_logic;
974
      CFGPMRCVREQACKN                     : out std_logic;
975
      CFGRDWRDONEN                        : out std_logic;
976
      CFGSLOTCONTROLELECTROMECHILCTLPULSE : out std_logic;
977
      CFGTRANSACTION                      : out std_logic;
978
      CFGTRANSACTIONADDR                  : out std_logic_vector(6 downto 0);
979
      CFGTRANSACTIONTYPE                  : out std_logic;
980
      CFGVCTCVCMAP                        : out std_logic_vector(6 downto 0);
981
      CFGBYTEENN                          : in  std_logic_vector(3 downto 0);
982
      CFGDI                               : in  std_logic_vector(31 downto 0);
983
      CFGDSBUSNUMBER                      : in  std_logic_vector(7 downto 0);
984
      CFGDSDEVICENUMBER                   : in  std_logic_vector(4 downto 0);
985
      CFGDSFUNCTIONNUMBER                 : in  std_logic_vector(2 downto 0);
986
      CFGDSN                              : in  std_logic_vector(63 downto 0);
987
      CFGDWADDR                           : in  std_logic_vector(9 downto 0);
988
      CFGERRACSN                          : in  std_logic;
989
      CFGERRAERHEADERLOG                  : in  std_logic_vector(127 downto 0);
990
      CFGERRCORN                          : in  std_logic;
991
      CFGERRCPLABORTN                     : in  std_logic;
992
      CFGERRCPLTIMEOUTN                   : in  std_logic;
993
      CFGERRCPLUNEXPECTN                  : in  std_logic;
994
      CFGERRECRCN                         : in  std_logic;
995
      CFGERRLOCKEDN                       : in  std_logic;
996
      CFGERRPOSTEDN                       : in  std_logic;
997
      CFGERRTLPCPLHEADER                  : in  std_logic_vector(47 downto 0);
998
      CFGERRURN                           : in  std_logic;
999
      CFGINTERRUPTASSERTN                 : in  std_logic;
1000
      CFGINTERRUPTDI                      : in  std_logic_vector(7 downto 0);
1001
      CFGINTERRUPTN                       : in  std_logic;
1002
      CFGPMDIRECTASPML1N                  : in  std_logic;
1003
      CFGPMSENDPMACKN                     : in  std_logic;
1004
      CFGPMSENDPMETON                     : in  std_logic;
1005
      CFGPMSENDPMNAKN                     : in  std_logic;
1006
      CFGPMTURNOFFOKN                     : in  std_logic;
1007
      CFGPMWAKEN                          : in  std_logic;
1008
      CFGPORTNUMBER                       : in  std_logic_vector(7 downto 0);
1009
      CFGRDENN                            : in  std_logic;
1010
      CFGTRNPENDINGN                      : in  std_logic;
1011
      CFGWRENN                            : in  std_logic;
1012
      CFGWRREADONLYN                      : in  std_logic;
1013
      CFGWRRW1CASRWN                      : in  std_logic;
1014
      PLINITIALLINKWIDTH                  : out std_logic_vector(2 downto 0);
1015
      PLLANEREVERSALMODE                  : out std_logic_vector(1 downto 0);
1016
      PLLINKGEN2CAP                       : out std_logic;
1017
      PLLINKPARTNERGEN2SUPPORTED          : out std_logic;
1018
      PLLINKUPCFGCAP                      : out std_logic;
1019
      PLLTSSMSTATE                        : out std_logic_vector(5 downto 0);
1020
      PLPHYLNKUPN                         : out std_logic;
1021
      PLRECEIVEDHOTRST                    : out std_logic;
1022
      PLRXPMSTATE                         : out std_logic_vector(1 downto 0);
1023
      PLSELLNKRATE                        : out std_logic;
1024
      PLSELLNKWIDTH                       : out std_logic_vector(1 downto 0);
1025
      PLTXPMSTATE                         : out std_logic_vector(2 downto 0);
1026
      PLDIRECTEDLINKAUTON                 : in  std_logic;
1027
      PLDIRECTEDLINKCHANGE                : in  std_logic_vector(1 downto 0);
1028
      PLDIRECTEDLINKSPEED                 : in  std_logic;
1029
      PLDIRECTEDLINKWIDTH                 : in  std_logic_vector(1 downto 0);
1030
      PLDOWNSTREAMDEEMPHSOURCE            : in  std_logic;
1031
      PLUPSTREAMPREFERDEEMPH              : in  std_logic;
1032
      PLTRANSMITHOTRST                    : in  std_logic;
1033
      DBGSCLRA                            : out std_logic;
1034
      DBGSCLRB                            : out std_logic;
1035
      DBGSCLRC                            : out std_logic;
1036
      DBGSCLRD                            : out std_logic;
1037
      DBGSCLRE                            : out std_logic;
1038
      DBGSCLRF                            : out std_logic;
1039
      DBGSCLRG                            : out std_logic;
1040
      DBGSCLRH                            : out std_logic;
1041
      DBGSCLRI                            : out std_logic;
1042
      DBGSCLRJ                            : out std_logic;
1043
      DBGSCLRK                            : out std_logic;
1044
      DBGVECA                             : out std_logic_vector(63 downto 0);
1045
      DBGVECB                             : out std_logic_vector(63 downto 0);
1046
      DBGVECC                             : out std_logic_vector(11 downto 0);
1047
      PLDBGVEC                            : out std_logic_vector(11 downto 0);
1048
      DBGMODE                             : in  std_logic_vector(1 downto 0);
1049
      DBGSUBMODE                          : in  std_logic;
1050
      PLDBGMODE                           : in  std_logic_vector(2 downto 0);
1051
      PCIEDRPDO                           : out std_logic_vector(15 downto 0);
1052
      PCIEDRPDRDY                         : out std_logic;
1053
      PCIEDRPCLK                          : in  std_logic;
1054
      PCIEDRPDADDR                        : in  std_logic_vector(8 downto 0);
1055
      PCIEDRPDEN                          : in  std_logic;
1056
      PCIEDRPDI                           : in  std_logic_vector(15 downto 0);
1057
      PCIEDRPDWE                          : in  std_logic;
1058
      GTPLLLOCK                           : out std_logic;
1059
      PIPECLK                             : in  std_logic;
1060
      USERCLK                             : in  std_logic;
1061
      DRPCLK                              : in  std_logic;
1062
      CLOCKLOCKED                         : in  std_logic;
1063
      TxOutClk                            : out std_logic);
1064
   end component;
1065
 
1066
   function to_integer (
1067
      val_in    : bit_vector) return integer is
1068
 
1069
      constant vctr   : bit_vector(val_in'high-val_in'low downto 0) := val_in;
1070
      variable ret    : integer := 0;
1071
   begin
1072
      for index in vctr'range loop
1073
         if (vctr(index) = '1') then
1074
            ret := ret + (2**index);
1075
         end if;
1076
      end loop;
1077
      return(ret);
1078
   end to_integer;
1079
 
1080
   function to_stdlogic (
1081
      in_val      : in boolean) return std_logic is
1082
   begin
1083
      if (in_val) then
1084
         return('1');
1085
      else
1086
         return('0');
1087
      end if;
1088
   end to_stdlogic;
1089
 
1090
   function pad_gen (
1091
      in_vec   : bit_vector;
1092
      op_len   : integer)
1093
      return bit_vector is
1094
      variable ret : bit_vector(op_len-1 downto 0) := (others => '0');
1095
      constant len : integer := in_vec'length;  -- length of input vector
1096
   begin  -- pad_gen
1097
      for i in 0 to op_len-1 loop
1098
         if (i < len) then
1099
            ret(i) := in_vec(len-i-1);
1100
         else
1101
            ret(i) := '0';
1102
         end if;
1103
      end loop;  -- i
1104
      return ret;
1105
   end pad_gen;
1106
 
1107
   constant LINK_CAP_MAX_LINK_SPEED_int : integer := to_integer(LINK_CAP_MAX_LINK_SPEED);
1108
 
1109
   signal rx_func_level_reset_n                       : std_logic;
1110
   signal cfg_msg_received                            : std_logic;
1111
   signal cfg_msg_received_pme_to                     : std_logic;
1112
 
1113
   signal cfg_cmd_bme                                 : std_logic;
1114
   signal cfg_cmd_intdis                              : std_logic;
1115
   signal cfg_cmd_io_en                               : std_logic;
1116
   signal cfg_cmd_mem_en                              : std_logic;
1117
   signal cfg_cmd_serr_en                             : std_logic;
1118
   signal cfg_dev_control_aux_power_en                : std_logic;
1119
   signal cfg_dev_control_corr_err_reporting_en       : std_logic;
1120
   signal cfg_dev_control_enable_relaxed_order        : std_logic;
1121
   signal cfg_dev_control_ext_tag_en                  : std_logic;
1122
   signal cfg_dev_control_fatal_err_reporting_en      : std_logic;
1123
   signal cfg_dev_control_maxpayload                  : std_logic_vector(2 downto 0);
1124
   signal cfg_dev_control_max_read_req                : std_logic_vector(2 downto 0);
1125
   signal cfg_dev_control_non_fatal_reporting_en      : std_logic;
1126
   signal cfg_dev_control_nosnoop_en                  : std_logic;
1127
   signal cfg_dev_control_phantom_en                  : std_logic;
1128
   signal cfg_dev_control_ur_err_reporting_en         : std_logic;
1129
   signal cfg_dev_control2_cpltimeout_dis             : std_logic;
1130
   signal cfg_dev_control2_cpltimeout_val             : std_logic_vector(3 downto 0);
1131
   signal cfg_dev_status_corr_err_detected            : std_logic;
1132
   signal cfg_dev_status_fatal_err_detected           : std_logic;
1133
   signal cfg_dev_status_nonfatal_err_detected        : std_logic;
1134
   signal cfg_dev_status_ur_detected                  : std_logic;
1135
   signal cfg_link_control_auto_bandwidth_int_en      : std_logic;
1136
   signal cfg_link_control_bandwidth_int_en           : std_logic;
1137
   signal cfg_link_control_hw_auto_width_dis          : std_logic;
1138
   signal cfg_link_control_clock_pm_en                : std_logic;
1139
   signal cfg_link_control_extended_sync              : std_logic;
1140
   signal cfg_link_control_common_clock               : std_logic;
1141
   signal cfg_link_control_retrain_link               : std_logic;
1142
   signal cfg_link_control_linkdisable                : std_logic;
1143
   signal cfg_link_control_rcb                        : std_logic;
1144
   signal cfg_link_control_aspm_control               : std_logic_vector(1 downto 0);
1145
   signal cfg_link_status_autobandwidth_status        : std_logic;
1146
   signal cfg_link_status_bandwidth_status            : std_logic;
1147
   signal cfg_link_status_dll_active                  : std_logic;
1148
   signal cfg_link_status_link_training               : std_logic;
1149
   signal cfg_link_status_negotiated_link_width       : std_logic_vector(3 downto 0);
1150
   signal cfg_link_status_current_speed               : std_logic_vector(1 downto 0);
1151
   signal cfg_msg_data                                : std_logic_vector(15 downto 0);
1152
 
1153
   signal sys_reset_n                                 : std_logic;
1154
   signal sys_reset_n_d                               : std_logic;
1155
   signal phy_rdy_n                                   : std_logic;
1156
 
1157
   signal TxOutClk                                    : std_logic;
1158
   signal TxOutClk_bufg                               : std_logic;
1159
 
1160
   signal cfg_bus_number_d                            : std_logic_vector(7 downto 0);
1161
   signal cfg_device_number_d                         : std_logic_vector(4 downto 0);
1162
   signal cfg_function_number_d                       : std_logic_vector(2 downto 0);
1163
 
1164
   signal trn_rdllp_data                              : std_logic_vector(31 downto 0);
1165
   signal trn_rdllp_src_rdy_n                         : std_logic;
1166
   signal trn_rdllp_src_rdy                           : std_logic;
1167
 
1168
   -- assigns to outputs
1169
 
1170
   signal gt_pll_lock                                 : std_logic;
1171
 
1172
   signal pipe_clk                                    : std_logic;
1173
   signal user_clk                                    : std_logic;
1174
   signal clock_locked                                : std_logic;
1175
   signal phy_rdy                                     : std_logic;
1176
 
1177
   signal drp_clk                                     : std_logic;
1178
 
1179
   signal trn_reset_n_d                               : std_logic;
1180
   signal sys_reset_d                                 : std_logic;
1181
   signal trn_reset_n                                 : std_logic;
1182
   signal trn_reset_n_int1                            : std_logic;
1183
   signal trn_reset_n_1_d                             : std_logic;
1184
   signal trn_lnk_up_n                                : std_logic;
1185
   signal trn_lnk_up_n_1                              : std_logic;
1186
   signal user_reset_out_int                          : std_logic;
1187
   signal user_lnk_up_int                             : std_logic;
1188
   signal user_lnk_up_d                               : std_logic;
1189
   signal tx_cfg_req_int                              : std_logic;
1190
   signal cfg_pcie_link_state_int                     : std_logic_vector(2 downto 0);
1191
   signal cfg_pmcsr_powerstate_int                    : std_logic_vector(1 downto 0);
1192
   signal cfg_to_turnoff_int                          : std_logic;
1193
 
1194
   -- Declare intermediate signals for referenced outputs
1195
   signal trn_tcfg_req_n                              : std_logic;
1196
   signal trn_tcfg_gnt_n                              : std_logic;
1197
   signal trn_tcfg_gnt                                : std_logic;
1198
   signal trn_terr_drop_n                             : std_logic;
1199
   signal trn_rdst_rdy_n                              : std_logic;
1200
   signal trn_rnp_ok_n                                : std_logic;
1201
   signal trn_tdst_rdy_n                              : std_logic;
1202
   signal trn_tdst_rdy                                : std_logic;
1203
   signal trn_rd                                      : std_logic_vector(63 downto 0);
1204
   signal trn_rrem_n                                  : std_logic;
1205
   signal trn_rrem                                    : std_logic_vector(0 downto 0);
1206
   signal trn_td                                      : std_logic_vector(63 downto 0);
1207
   signal trn_trem_n                                  : std_logic;
1208
   signal trn_trem                                    : std_logic_vector(0 downto 0);
1209
   signal trn_rsof_n                                  : std_logic;
1210
   signal trn_reof_n                                  : std_logic;
1211
   signal trn_rsrc_rdy_n                              : std_logic;
1212
   signal trn_rsrc_dsc_n                              : std_logic;
1213
   signal trn_rerrfwd_n                               : std_logic;
1214
   signal trn_rbar_hit_n                              : std_logic_vector(6 downto 0);
1215
   signal trn_recrc_err_n                             : std_logic;
1216
   signal trn_rsof                                    : std_logic;
1217
   signal trn_reof                                    : std_logic;
1218
   signal trn_rsrc_rdy                                : std_logic;
1219
   signal trn_rdst_rdy                                : std_logic;
1220
   signal trn_rsrc_dsc                                : std_logic;
1221
   signal trn_rerrfwd                                 : std_logic;
1222
   signal trn_rbar_hit                                : std_logic_vector(6 downto 0);
1223
   signal trn_recrc_err                               : std_logic;
1224
   signal trn_tsof_n                                  : std_logic;
1225
   signal trn_teof_n                                  : std_logic;
1226
   signal trn_tsrc_rdy_n                              : std_logic;
1227
   signal trn_tsrc_dsc_n                              : std_logic;
1228
   signal trn_terrfwd_n                               : std_logic;
1229
   signal trn_tstr_n                                  : std_logic;
1230
   signal trn_tecrc_gen                               : std_logic;
1231
   signal trn_tsof                                    : std_logic;
1232
   signal trn_teof                                    : std_logic;
1233
   signal trn_tsrc_rdy                                : std_logic;
1234
   signal trn_tsrc_dsc                                : std_logic;
1235
   signal trn_terrfwd                                 : std_logic;
1236
   signal trn_tstr                                    : std_logic;
1237
   signal cfg_rd_wr_done_n                            : std_logic;
1238
   signal cfg_err_cpl_rdy_n                           : std_logic;
1239
   signal cfg_interrupt_rdy_n                         : std_logic;
1240
   signal cfg_byte_en_n                               : std_logic_vector(3 downto 0);
1241
   signal cfg_err_cor_n                               : std_logic;
1242
   signal cfg_err_cpl_abort_n                         : std_logic;
1243
   signal cfg_err_cpl_timeout_n                       : std_logic;
1244
   signal cfg_err_cpl_unexpect_n                      : std_logic;
1245
   signal cfg_err_ecrc_n                              : std_logic;
1246
   signal cfg_err_locked_n                            : std_logic;
1247
   signal cfg_err_posted_n                            : std_logic;
1248
   signal cfg_err_ur_n                                : std_logic;
1249
   signal cfg_interrupt_assert_n                      : std_logic;
1250
   signal cfg_interrupt_n                             : std_logic;
1251
   signal cfg_turnoff_ok_n                            : std_logic;
1252
   signal cfg_turnoff_ok_axi                          : std_logic;
1253
   signal cfg_pm_wake_n                               : std_logic;
1254
   signal cfg_rd_en_n                                 : std_logic;
1255
   signal cfg_trn_pending_n                           : std_logic;
1256
   signal cfg_wr_en_n                                 : std_logic;
1257
   signal tx_buf_av_int                               : std_logic_vector(5 downto 0);
1258
 
1259
   signal pl_sel_link_rate_int                        : std_logic;
1260
   signal pl_sel_link_width_int                       : std_logic_vector(1 downto 0);
1261
 
1262
   signal LINK_STATUS_SLOT_CLOCK_CONFIG_lstatus       : std_logic;
1263
 
1264
begin
1265
   -- Drive referenced outputs
1266
   user_clk_out           <= user_clk;
1267
   user_reset_out         <= user_reset_out_int;
1268
   user_lnk_up            <= user_lnk_up_int;
1269
   pl_sel_link_rate       <= pl_sel_link_rate_int;
1270
   pl_sel_link_width      <= pl_sel_link_width_int;
1271
   tx_buf_av              <= tx_buf_av_int;
1272
   tx_cfg_req_int         <= not(trn_tcfg_req_n);
1273
   tx_cfg_req             <= tx_cfg_req_int;
1274
   cfg_pcie_link_state    <= cfg_pcie_link_state_int;
1275
   cfg_pmcsr_powerstate   <= cfg_pmcsr_powerstate_int;
1276
   cfg_to_turnoff_int     <= cfg_msg_received_pme_to;
1277
   cfg_to_turnoff         <= cfg_to_turnoff_int;
1278
 
1279
   -- Invert outputs
1280
   tx_err_drop            <= not(trn_terr_drop_n);
1281
   cfg_rd_wr_done         <= not(cfg_rd_wr_done_n);
1282
   cfg_err_cpl_rdy        <= not(cfg_err_cpl_rdy_n);
1283
   cfg_interrupt_rdy      <= not(cfg_interrupt_rdy_n);
1284
   trn_tdst_rdy           <= not(trn_tdst_rdy_n);
1285
   trn_rsof               <= not(trn_rsof_n);
1286
   trn_reof               <= not(trn_reof_n);
1287
   trn_rrem(0)            <= not(trn_rrem_n);
1288
   trn_rsrc_rdy           <= not(trn_rsrc_rdy_n);
1289
   trn_rsrc_dsc           <= not(trn_rsrc_dsc_n);
1290
   trn_rerrfwd            <= not(trn_rerrfwd_n);
1291
   trn_rbar_hit           <= not(trn_rbar_hit_n);
1292
   trn_recrc_err          <= not(trn_recrc_err_n);
1293
   trn_rdllp_src_rdy      <= not(trn_rdllp_src_rdy_n);
1294
 
1295
   -- Invert inputs
1296
   cfg_byte_en_n          <= not(cfg_byte_en);
1297
   cfg_err_cor_n          <= not(cfg_err_cor);
1298
   cfg_err_cpl_abort_n    <= not(cfg_err_cpl_abort);
1299
   cfg_err_cpl_timeout_n  <= not(cfg_err_cpl_timeout);
1300
   cfg_err_cpl_unexpect_n <= not(cfg_err_cpl_unexpect);
1301
   cfg_err_ecrc_n         <= not(cfg_err_ecrc);
1302
   cfg_err_locked_n       <= not(cfg_err_locked);
1303
   cfg_err_posted_n       <= not(cfg_err_posted);
1304
   cfg_err_ur_n           <= not(cfg_err_ur);
1305
   cfg_interrupt_assert_n <= not(cfg_interrupt_assert);
1306
   cfg_interrupt_n        <= not(cfg_interrupt);
1307
   cfg_turnoff_ok_n       <= not(cfg_turnoff_ok_axi);
1308
   cfg_pm_wake_n          <= not(cfg_pm_wake);
1309
   cfg_rd_en_n            <= not(cfg_rd_en);
1310
   cfg_trn_pending_n      <= not(cfg_trn_pending);
1311
   cfg_wr_en_n            <= not(cfg_wr_en);
1312
   trn_tcfg_gnt_n         <= not(trn_tcfg_gnt);
1313
   trn_rdst_rdy_n         <= not(trn_rdst_rdy);
1314
   trn_rnp_ok_n           <= not(rx_np_ok);
1315
   trn_tsof_n             <= not(trn_tsof);
1316
   trn_teof_n             <= not(trn_teof);
1317
   trn_tsrc_rdy_n         <= not(trn_tsrc_rdy);
1318
   trn_tsrc_dsc_n         <= not(trn_tsrc_dsc);
1319
   trn_terrfwd_n          <= not(trn_terrfwd);
1320
   trn_trem_n             <= not(trn_trem(0));
1321
   trn_tstr_n             <= not(trn_tstr);
1322
 
1323
   LINK_STATUS_SLOT_CLOCK_CONFIG_lstatus <= '1' when (LINK_STATUS_SLOT_CLOCK_CONFIG) else '0';
1324
 
1325
   -- Calculated/concatenated oututs
1326
   cfg_status             <= "0000000000000000";
1327
   cfg_command            <= ("00000" &
1328
                              cfg_cmd_intdis &
1329
                              '0' &
1330
                              cfg_cmd_serr_en &
1331
                              "00000" &
1332
                              cfg_cmd_bme &
1333
                              cfg_cmd_mem_en &
1334
                              cfg_cmd_io_en);
1335
   cfg_dstatus            <= ("0000000000" &
1336
                              not(cfg_trn_pending_n) &
1337
                              '0' &
1338
                              cfg_dev_status_ur_detected &
1339
                              cfg_dev_status_fatal_err_detected &
1340
                              cfg_dev_status_nonfatal_err_detected &
1341
                              cfg_dev_status_corr_err_detected);
1342
   cfg_dcommand           <= ('0' &
1343
                              cfg_dev_control_max_read_req &
1344
                              cfg_dev_control_nosnoop_en &
1345
                              cfg_dev_control_aux_power_en &
1346
                              cfg_dev_control_phantom_en &
1347
                              cfg_dev_control_ext_tag_en &
1348
                              cfg_dev_control_maxpayload &
1349
                              cfg_dev_control_enable_relaxed_order &
1350
                              cfg_dev_control_ur_err_reporting_en &
1351
                              cfg_dev_control_fatal_err_reporting_en &
1352
                              cfg_dev_control_non_fatal_reporting_en &
1353
                              cfg_dev_control_corr_err_reporting_en);
1354
   cfg_lstatus            <= (cfg_link_status_autobandwidth_status &
1355
                              cfg_link_status_bandwidth_status &
1356
                              cfg_link_status_dll_active &
1357
                              LINK_STATUS_SLOT_CLOCK_CONFIG_lstatus &
1358
                              cfg_link_status_link_training &
1359
                              '0' &
1360
                              "00" &
1361
                              cfg_link_status_negotiated_link_width &
1362
                              "00" &
1363
                              cfg_link_status_current_speed);
1364
   cfg_lcommand           <= ("0000" &
1365
                              cfg_link_control_auto_bandwidth_int_en &
1366
                              cfg_link_control_bandwidth_int_en &
1367
                              cfg_link_control_hw_auto_width_dis &
1368
                              cfg_link_control_clock_pm_en &
1369
                              cfg_link_control_extended_sync &
1370
                              cfg_link_control_common_clock &
1371
                              cfg_link_control_retrain_link &
1372
                              cfg_link_control_linkdisable &
1373
                              cfg_link_control_rcb &
1374
                              '0' &
1375
                              cfg_link_control_aspm_control);
1376
   cfg_bus_number         <= cfg_bus_number_d;
1377
   cfg_device_number      <= cfg_device_number_d;
1378
   cfg_function_number    <= cfg_function_number_d;
1379
   cfg_dcommand2          <= ("00000000000" &
1380
                              cfg_dev_control2_cpltimeout_dis &
1381
                              cfg_dev_control2_cpltimeout_val);
1382
 
1383
   -- Capture Bus/Device/Function number
1384
 
1385
   process (user_clk)
1386
   begin
1387
      if (rising_edge(user_clk)) then
1388
         if (user_lnk_up_int = '0') then
1389
            cfg_bus_number_d       <= "00000000";
1390
            cfg_device_number_d    <= "00000";
1391
            cfg_function_number_d  <= "000";
1392
         elsif (cfg_msg_received = '0') then
1393
            cfg_bus_number_d       <= cfg_msg_data(15 downto 8);
1394
            cfg_device_number_d    <= cfg_msg_data(7 downto 3);
1395
            cfg_function_number_d  <= cfg_msg_data(2 downto 0);
1396
         end if;
1397
      end if;
1398
   end process;
1399
 
1400
   -- Generate user_lnk_up
1401
 
1402
   user_lnk_up_int_i : FDCP
1403
      generic map (
1404
         INIT  => '0'
1405
      )
1406
      port map (
1407
         Q    => user_lnk_up_int,
1408
         D    => user_lnk_up_d,
1409
         C    => user_clk,
1410
         CLR  => '0',
1411
         PRE  => '0'
1412
      );
1413
 
1414
   user_lnk_up_d <= not(trn_lnk_up_n_1);
1415
 
1416
   trn_lnk_up_n_1_i : FDCP
1417
      generic map (
1418
         INIT  => '1'
1419
      )
1420
      port map (
1421
         Q    => trn_lnk_up_n_1,
1422
         D    => trn_lnk_up_n,
1423
         C    => user_clk,
1424
         CLR  => '0',
1425
         PRE  => '0'
1426
      );
1427
 
1428
 
1429
   -- Generate user_reset_out
1430
 
1431
   trn_reset_n_d <= not(trn_reset_n_int1 and not(phy_rdy_n));
1432
   sys_reset_d   <= not(sys_reset_n_d);
1433
 
1434
   trn_reset_n_i : FDCP
1435
      generic map (
1436
         INIT  => '1'
1437
      )
1438
      port map (
1439
         Q    => user_reset_out_int,
1440
         D    => trn_reset_n_d,
1441
         C    => user_clk,
1442
         CLR  => sys_reset_d,
1443
         PRE  => '0'
1444
      );
1445
 
1446
 
1447
   trn_reset_n_1_d <= trn_reset_n and not(phy_rdy_n);
1448
   trn_reset_n_int_i : FDCP
1449
      generic map (
1450
         INIT  => '0'
1451
      )
1452
      port map (
1453
         Q    => trn_reset_n_int1,
1454
         D    => trn_reset_n_1_d,
1455
         C    => user_clk,
1456
         CLR  => sys_reset_d,
1457
         PRE  => '0'
1458
      );
1459
 
1460
 
1461
   ---------------------------------------------------------
1462
   -- AXI Basic Bridge
1463
   -- Converts between TRN and AXI
1464
   ---------------------------------------------------------
1465
 
1466
   axi_basic_top_i : axi_basic_top
1467
      generic map (
1468
         C_DATA_WIDTH     => 64,           -- RX/TX interface data width
1469
         C_REM_WIDTH      => 1,            -- trem/rrem width
1470
         C_STRB_WIDTH     => 8,            -- tstrb width
1471
         TCQ              => 1,            -- Clock to Q time
1472
 
1473
         C_FAMILY         => "V6",         -- Targeted FPGA family
1474
         C_ROOT_PORT      => FALSE,      -- PCIe block is in root port mode
1475
         C_PM_PRIORITY    => FALSE       -- Disable TX packet boundary thrtl
1476
      )
1477
      port map (
1478
         -------------------------------------------------
1479
         -- User Design I/O                             --
1480
         -------------------------------------------------
1481
 
1482
         -- AXI TX
1483
         -------------
1484
         s_axis_tx_tdata          => s_axis_tx_tdata,          --  input
1485
         s_axis_tx_tvalid         => s_axis_tx_tvalid,         --  input
1486
         s_axis_tx_tready         => s_axis_tx_tready,         --  output
1487
         s_axis_tx_tstrb          => s_axis_tx_tstrb,          --  input
1488
         s_axis_tx_tlast          => s_axis_tx_tlast,          --  input
1489
         s_axis_tx_tuser          => s_axis_tx_tuser,          --  input
1490
 
1491
         -- AXI RX
1492
         -------------
1493
         m_axis_rx_tdata          => m_axis_rx_tdata,          --  output
1494
         m_axis_rx_tvalid         => m_axis_rx_tvalid,         --  output
1495
         m_axis_rx_tready         => m_axis_rx_tready,         --  input
1496
         m_axis_rx_tstrb          => m_axis_rx_tstrb,          --  output
1497
         m_axis_rx_tlast          => m_axis_rx_tlast,          --  output
1498
         m_axis_rx_tuser          => m_axis_rx_tuser,          --  output
1499
 
1500
         -- User Misc.
1501
         -------------
1502
         user_turnoff_ok          => cfg_turnoff_ok,           --  input
1503
         user_tcfg_gnt            => tx_cfg_gnt,               --  input
1504
 
1505
         -------------------------------------------------
1506
         -- PCIe Block I/O                              --
1507
         -------------------------------------------------
1508
 
1509
         -- TRN TX
1510
         -------------
1511
         trn_td                   => trn_td,                   --  output
1512
         trn_tsof                 => trn_tsof,                 --  output
1513
         trn_teof                 => trn_teof,                 --  output
1514
         trn_tsrc_rdy             => trn_tsrc_rdy,             --  output
1515
         trn_tdst_rdy             => trn_tdst_rdy,             --  input
1516
         trn_tsrc_dsc             => trn_tsrc_dsc,             --  output
1517
         trn_trem                 => trn_trem,                 --  output
1518
         trn_terrfwd              => trn_terrfwd,              --  output
1519
         trn_tstr                 => trn_tstr,                 --  output
1520
         trn_tbuf_av              => tx_buf_av_int,            --  input
1521
         trn_tecrc_gen            => trn_tecrc_gen,            --  output
1522
 
1523
         -- TRN RX
1524
         -------------
1525
         trn_rd                   => trn_rd,                   --  input
1526
         trn_rsof                 => trn_rsof,                 --  input
1527
         trn_reof                 => trn_reof,                 --  input
1528
         trn_rsrc_rdy             => trn_rsrc_rdy,             --  input
1529
         trn_rdst_rdy             => trn_rdst_rdy,             --  output
1530
         trn_rsrc_dsc             => trn_rsrc_dsc,             --  input
1531
         trn_rrem                 => trn_rrem,                 --  input
1532
         trn_rerrfwd              => trn_rerrfwd,              --  input
1533
         trn_rbar_hit             => trn_rbar_hit,             --  input
1534
         trn_recrc_err            => trn_recrc_err,            --  input
1535
 
1536
         -- TRN Misc.
1537
         -------------
1538
         trn_tcfg_req             => tx_cfg_req_int,           --  input
1539
         trn_tcfg_gnt             => trn_tcfg_gnt,             --  output
1540
         trn_lnk_up               => user_lnk_up_int,          --  input
1541
 
1542
         -- Artix/Kintex/Virtex PM
1543
         -------------
1544
         cfg_pcie_link_state      => cfg_pcie_link_state_int,  --  input
1545
 
1546
         -- Virtex6 PM
1547
         -------------
1548
         cfg_pm_send_pme_to       => '0',                      --  input  NOT USED FOR EP
1549
         cfg_pmcsr_powerstate     => cfg_pmcsr_powerstate_int, --  input
1550
         trn_rdllp_data           => trn_rdllp_data,           --  input
1551
         trn_rdllp_src_rdy        => trn_rdllp_src_rdy,        --  input
1552
 
1553
         -- Power Mgmt for S6/V6
1554
         -------------
1555
         cfg_to_turnoff           => cfg_to_turnoff_int,       --  input
1556
         cfg_turnoff_ok           => cfg_turnoff_ok_axi,       --  output
1557
 
1558
         -- System
1559
         -------------
1560
         user_clk                 => user_clk,                 --  input
1561
         user_rst                 => user_reset_out_int,       --  input
1562
         np_counter               => open                      --  output
1563
   );
1564
 
1565
   ---------------------------------------------------------
1566
   -- PCI Express Reset Delay Module
1567
   ---------------------------------------------------------
1568
 
1569
   sys_reset_n <= not(sys_reset);
1570
 
1571
   pcie_reset_delay_i : pcie_reset_delay_v6
1572
      generic map (
1573
         PL_FAST_TRAIN  => PL_FAST_TRAIN,
1574
         REF_CLK_FREQ   => REF_CLK_FREQ
1575
      )
1576
      port map (
1577
         ref_clk              => TxOutClk_bufg,
1578
         sys_reset_n          => sys_reset_n,
1579
         delayed_sys_reset_n  => sys_reset_n_d
1580
      );
1581
 
1582
 
1583
   ---------------------------------------------------------
1584
   -- PCI Express Clocking Module
1585
   ---------------------------------------------------------
1586
 
1587
   pcie_clocking_i : pcie_clocking_v6
1588
      generic map (
1589
         CAP_LINK_WIDTH  => LINK_CAP_MAX_LINK_WIDTH_int,
1590
         CAP_LINK_SPEED  => LINK_CAP_MAX_LINK_SPEED_int,
1591
         REF_CLK_FREQ    => REF_CLK_FREQ,
1592
         USER_CLK_FREQ   => USER_CLK_FREQ
1593
      )
1594
      port map (
1595
         sys_clk        => TxOutClk,
1596
         gt_pll_lock    => gt_pll_lock,
1597
         sel_lnk_rate   => pl_sel_link_rate_int,
1598
         sel_lnk_width  => pl_sel_link_width_int,
1599
         sys_clk_bufg   => TxOutClk_bufg,
1600
         pipe_clk       => pipe_clk,
1601
         user_clk       => user_clk,
1602
         block_clk      => open,
1603
         drp_clk        => drp_clk,
1604
         clock_locked   => clock_locked
1605
      );
1606
 
1607
 
1608
   phy_rdy <= not(phy_rdy_n);
1609
 
1610
   ---------------------------------------------------------
1611
   -- Virtex6 PCI Express Block Module
1612
   ---------------------------------------------------------
1613
 
1614
   pcie_2_0_i : pcie_2_0_v6
1615
      generic map (
1616
         REF_CLK_FREQ                              => REF_CLK_FREQ,
1617
         PIPE_PIPELINE_STAGES                      => PIPE_PIPELINE_STAGES,
1618
         LINK_CAP_MAX_LINK_WIDTH_int               => LINK_CAP_MAX_LINK_WIDTH_int,
1619
         AER_BASE_PTR                              => AER_BASE_PTR,
1620
         AER_CAP_ECRC_CHECK_CAPABLE                => AER_CAP_ECRC_CHECK_CAPABLE,
1621
         AER_CAP_ECRC_GEN_CAPABLE                  => AER_CAP_ECRC_GEN_CAPABLE,
1622
         AER_CAP_ID                                => AER_CAP_ID,
1623
         AER_CAP_INT_MSG_NUM_MSI                   => AER_CAP_INT_MSG_NUM_MSI,
1624
         AER_CAP_INT_MSG_NUM_MSIX                  => AER_CAP_INT_MSG_NUM_MSIX,
1625
         AER_CAP_NEXTPTR                           => AER_CAP_NEXTPTR,
1626
         AER_CAP_ON                                => AER_CAP_ON,
1627
         AER_CAP_PERMIT_ROOTERR_UPDATE             => AER_CAP_PERMIT_ROOTERR_UPDATE,
1628
         AER_CAP_VERSION                           => AER_CAP_VERSION,
1629
         ALLOW_X8_GEN2                             => ALLOW_X8_GEN2,
1630
         BAR0                                      => pad_gen(BAR0, 32),
1631
         BAR1                                      => pad_gen(BAR1, 32),
1632
         BAR2                                      => pad_gen(BAR2, 32),
1633
         BAR3                                      => pad_gen(BAR3, 32),
1634
         BAR4                                      => pad_gen(BAR4, 32),
1635
         BAR5                                      => pad_gen(BAR5, 32),
1636
         CAPABILITIES_PTR                          => CAPABILITIES_PTR,
1637
         CARDBUS_CIS_POINTER                       => pad_gen(CARDBUS_CIS_POINTER, 32),
1638
         CLASS_CODE                                => pad_gen(CLASS_CODE, 24),
1639
         CMD_INTX_IMPLEMENTED                      => CMD_INTX_IMPLEMENTED,
1640
         CPL_TIMEOUT_DISABLE_SUPPORTED             => CPL_TIMEOUT_DISABLE_SUPPORTED,
1641
         CPL_TIMEOUT_RANGES_SUPPORTED              => pad_gen(CPL_TIMEOUT_RANGES_SUPPORTED, 4),
1642
         CRM_MODULE_RSTS                           => CRM_MODULE_RSTS,
1643
         DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE       => DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE,
1644
         DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE       => DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE,
1645
         DEV_CAP_ENDPOINT_L0S_LATENCY              => DEV_CAP_ENDPOINT_L0S_LATENCY,
1646
         DEV_CAP_ENDPOINT_L1_LATENCY               => DEV_CAP_ENDPOINT_L1_LATENCY,
1647
         DEV_CAP_EXT_TAG_SUPPORTED                 => DEV_CAP_EXT_TAG_SUPPORTED,
1648
         DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE      => DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE,
1649
         DEV_CAP_MAX_PAYLOAD_SUPPORTED             => DEV_CAP_MAX_PAYLOAD_SUPPORTED,
1650
         DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT         => DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT,
1651
         DEV_CAP_ROLE_BASED_ERROR                  => DEV_CAP_ROLE_BASED_ERROR,
1652
         DEV_CAP_RSVD_14_12                        => DEV_CAP_RSVD_14_12,
1653
         DEV_CAP_RSVD_17_16                        => DEV_CAP_RSVD_17_16,
1654
         DEV_CAP_RSVD_31_29                        => DEV_CAP_RSVD_31_29,
1655
         DEV_CONTROL_AUX_POWER_SUPPORTED           => DEV_CONTROL_AUX_POWER_SUPPORTED,
1656
         DEVICE_ID                                 => pad_gen(DEVICE_ID, 16),
1657
         DISABLE_ASPM_L1_TIMER                     => DISABLE_ASPM_L1_TIMER,
1658
         DISABLE_BAR_FILTERING                     => DISABLE_BAR_FILTERING,
1659
         DISABLE_ID_CHECK                          => DISABLE_ID_CHECK,
1660
         DISABLE_LANE_REVERSAL                     => DISABLE_LANE_REVERSAL,
1661
         DISABLE_RX_TC_FILTER                      => DISABLE_RX_TC_FILTER,
1662
         DISABLE_SCRAMBLING                        => DISABLE_SCRAMBLING,
1663
         DNSTREAM_LINK_NUM                         => DNSTREAM_LINK_NUM,
1664
         DSN_BASE_PTR                              => pad_gen(DSN_BASE_PTR, 12),
1665
         DSN_CAP_ID                                => DSN_CAP_ID,
1666
         DSN_CAP_NEXTPTR                           => pad_gen(DSN_CAP_NEXTPTR, 12),
1667
         DSN_CAP_ON                                => DSN_CAP_ON,
1668
         DSN_CAP_VERSION                           => DSN_CAP_VERSION,
1669
         ENABLE_MSG_ROUTE                          => pad_gen(ENABLE_MSG_ROUTE, 11),
1670
         ENABLE_RX_TD_ECRC_TRIM                    => ENABLE_RX_TD_ECRC_TRIM,
1671
         ENTER_RVRY_EI_L0                          => ENTER_RVRY_EI_L0,
1672
         EXPANSION_ROM                             => pad_gen(EXPANSION_ROM, 32),
1673
         EXT_CFG_CAP_PTR                           => EXT_CFG_CAP_PTR,
1674
         EXT_CFG_XP_CAP_PTR                        => pad_gen(EXT_CFG_XP_CAP_PTR, 10),
1675
         HEADER_TYPE                               => pad_gen(HEADER_TYPE, 8),
1676
         INFER_EI                                  => INFER_EI,
1677
         INTERRUPT_PIN                             => pad_gen(INTERRUPT_PIN, 8),
1678
         IS_SWITCH                                 => IS_SWITCH,
1679
         LAST_CONFIG_DWORD                         => LAST_CONFIG_DWORD,
1680
         LINK_CAP_ASPM_SUPPORT                     => LINK_CAP_ASPM_SUPPORT,
1681
         LINK_CAP_CLOCK_POWER_MANAGEMENT           => LINK_CAP_CLOCK_POWER_MANAGEMENT,
1682
         LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP    => LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP,
1683
         LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP  => LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP,
1684
         LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1     => LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1,
1685
         LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2     => LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2,
1686
         LINK_CAP_L0S_EXIT_LATENCY_GEN1            => LINK_CAP_L0S_EXIT_LATENCY_GEN1,
1687
         LINK_CAP_L0S_EXIT_LATENCY_GEN2            => LINK_CAP_L0S_EXIT_LATENCY_GEN2,
1688
         LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1      => LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1,
1689
         LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2      => LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2,
1690
         LINK_CAP_L1_EXIT_LATENCY_GEN1             => LINK_CAP_L1_EXIT_LATENCY_GEN1,
1691
         LINK_CAP_L1_EXIT_LATENCY_GEN2             => LINK_CAP_L1_EXIT_LATENCY_GEN2,
1692
         LINK_CAP_MAX_LINK_SPEED                   => pad_gen(LINK_CAP_MAX_LINK_SPEED, 4),
1693
         LINK_CAP_MAX_LINK_WIDTH                   => pad_gen(LINK_CAP_MAX_LINK_WIDTH, 6),
1694
         LINK_CAP_RSVD_23_22                       => LINK_CAP_RSVD_23_22,
1695
         LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE      => LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE,
1696
         LINK_CONTROL_RCB                          => LINK_CONTROL_RCB,
1697
         LINK_CTRL2_DEEMPHASIS                     => LINK_CTRL2_DEEMPHASIS,
1698
         LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE    => LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE,
1699
         LINK_CTRL2_TARGET_LINK_SPEED              => pad_gen(LINK_CTRL2_TARGET_LINK_SPEED, 4),
1700
         LINK_STATUS_SLOT_CLOCK_CONFIG             => LINK_STATUS_SLOT_CLOCK_CONFIG,
1701
         LL_ACK_TIMEOUT                            => pad_gen(LL_ACK_TIMEOUT, 15),
1702
         LL_ACK_TIMEOUT_EN                         => LL_ACK_TIMEOUT_EN,
1703
         LL_ACK_TIMEOUT_FUNC                       => LL_ACK_TIMEOUT_FUNC,
1704
         LL_REPLAY_TIMEOUT                         => pad_gen(LL_REPLAY_TIMEOUT, 15),
1705
         LL_REPLAY_TIMEOUT_EN                      => LL_REPLAY_TIMEOUT_EN,
1706
         LL_REPLAY_TIMEOUT_FUNC                    => LL_REPLAY_TIMEOUT_FUNC,
1707
         LTSSM_MAX_LINK_WIDTH                      => pad_gen(LTSSM_MAX_LINK_WIDTH, 6),
1708
         MSI_BASE_PTR                              => MSI_BASE_PTR,
1709
         MSI_CAP_ID                                => MSI_CAP_ID,
1710
         MSI_CAP_MULTIMSGCAP                       => MSI_CAP_MULTIMSGCAP,
1711
         MSI_CAP_MULTIMSG_EXTENSION                => MSI_CAP_MULTIMSG_EXTENSION,
1712
         MSI_CAP_NEXTPTR                           => MSI_CAP_NEXTPTR,
1713
         MSI_CAP_ON                                => MSI_CAP_ON,
1714
         MSI_CAP_PER_VECTOR_MASKING_CAPABLE        => MSI_CAP_PER_VECTOR_MASKING_CAPABLE,
1715
         MSI_CAP_64_BIT_ADDR_CAPABLE               => MSI_CAP_64_BIT_ADDR_CAPABLE,
1716
         MSIX_BASE_PTR                             => MSIX_BASE_PTR,
1717
         MSIX_CAP_ID                               => MSIX_CAP_ID,
1718
         MSIX_CAP_NEXTPTR                          => MSIX_CAP_NEXTPTR,
1719
         MSIX_CAP_ON                               => MSIX_CAP_ON,
1720
         MSIX_CAP_PBA_BIR                          => MSIX_CAP_PBA_BIR,
1721
         MSIX_CAP_PBA_OFFSET                       => pad_gen(MSIX_CAP_PBA_OFFSET, 29),
1722
         MSIX_CAP_TABLE_BIR                        => MSIX_CAP_TABLE_BIR,
1723
         MSIX_CAP_TABLE_OFFSET                     => pad_gen(MSIX_CAP_TABLE_OFFSET, 29),
1724
         MSIX_CAP_TABLE_SIZE                       => pad_gen(MSIX_CAP_TABLE_SIZE, 11),
1725
         N_FTS_COMCLK_GEN1                         => N_FTS_COMCLK_GEN1,
1726
         N_FTS_COMCLK_GEN2                         => N_FTS_COMCLK_GEN2,
1727
         N_FTS_GEN1                                => N_FTS_GEN1,
1728
         N_FTS_GEN2                                => N_FTS_GEN2,
1729
         PCIE_BASE_PTR                             => PCIE_BASE_PTR,
1730
         PCIE_CAP_CAPABILITY_ID                    => PCIE_CAP_CAPABILITY_ID,
1731
         PCIE_CAP_CAPABILITY_VERSION               => PCIE_CAP_CAPABILITY_VERSION,
1732
         PCIE_CAP_DEVICE_PORT_TYPE                 => pad_gen(PCIE_CAP_DEVICE_PORT_TYPE, 4),
1733
         PCIE_CAP_INT_MSG_NUM                      => pad_gen(PCIE_CAP_INT_MSG_NUM, 5),
1734
         PCIE_CAP_NEXTPTR                          => pad_gen(PCIE_CAP_NEXTPTR, 8),
1735
         PCIE_CAP_ON                               => PCIE_CAP_ON,
1736
         PCIE_CAP_RSVD_15_14                       => PCIE_CAP_RSVD_15_14,
1737
         PCIE_CAP_SLOT_IMPLEMENTED                 => PCIE_CAP_SLOT_IMPLEMENTED,
1738
         PCIE_REVISION                             => PCIE_REVISION,
1739
         PGL0_LANE                                 => PGL0_LANE,
1740
         PGL1_LANE                                 => PGL1_LANE,
1741
         PGL2_LANE                                 => PGL2_LANE,
1742
         PGL3_LANE                                 => PGL3_LANE,
1743
         PGL4_LANE                                 => PGL4_LANE,
1744
         PGL5_LANE                                 => PGL5_LANE,
1745
         PGL6_LANE                                 => PGL6_LANE,
1746
         PGL7_LANE                                 => PGL7_LANE,
1747
         PL_AUTO_CONFIG                            => PL_AUTO_CONFIG,
1748
         PL_FAST_TRAIN                             => PL_FAST_TRAIN,
1749
         PM_BASE_PTR                               => PM_BASE_PTR,
1750
         PM_CAP_AUXCURRENT                         => PM_CAP_AUXCURRENT,
1751
         PM_CAP_DSI                                => PM_CAP_DSI,
1752
         PM_CAP_D1SUPPORT                          => PM_CAP_D1SUPPORT,
1753
         PM_CAP_D2SUPPORT                          => PM_CAP_D2SUPPORT,
1754
         PM_CAP_ID                                 => PM_CAP_ID,
1755
         PM_CAP_NEXTPTR                            => PM_CAP_NEXTPTR,
1756
         PM_CAP_ON                                 => PM_CAP_ON,
1757
         PM_CAP_PME_CLOCK                          => PM_CAP_PME_CLOCK,
1758
         PM_CAP_PMESUPPORT                         => pad_gen(PM_CAP_PMESUPPORT, 5),
1759
         PM_CAP_RSVD_04                            => PM_CAP_RSVD_04,
1760
         PM_CAP_VERSION                            => PM_CAP_VERSION,
1761
         PM_CSR_BPCCEN                             => PM_CSR_BPCCEN,
1762
         PM_CSR_B2B3                               => PM_CSR_B2B3,
1763
         PM_CSR_NOSOFTRST                          => PM_CSR_NOSOFTRST,
1764
         PM_DATA_SCALE0                            => pad_gen(PM_DATA_SCALE0, 2),
1765
         PM_DATA_SCALE1                            => pad_gen(PM_DATA_SCALE1, 2),
1766
         PM_DATA_SCALE2                            => pad_gen(PM_DATA_SCALE2, 2),
1767
         PM_DATA_SCALE3                            => pad_gen(PM_DATA_SCALE3, 2),
1768
         PM_DATA_SCALE4                            => pad_gen(PM_DATA_SCALE4, 2),
1769
         PM_DATA_SCALE5                            => pad_gen(PM_DATA_SCALE5, 2),
1770
         PM_DATA_SCALE6                            => pad_gen(PM_DATA_SCALE6, 2),
1771
         PM_DATA_SCALE7                            => pad_gen(PM_DATA_SCALE7, 2),
1772
         PM_DATA0                                  => pad_gen(PM_DATA0, 8),
1773
         PM_DATA1                                  => pad_gen(PM_DATA1, 8),
1774
         PM_DATA2                                  => pad_gen(PM_DATA2, 8),
1775
         PM_DATA3                                  => pad_gen(PM_DATA3, 8),
1776
         PM_DATA4                                  => pad_gen(PM_DATA4, 8),
1777
         PM_DATA5                                  => pad_gen(PM_DATA5, 8),
1778
         PM_DATA6                                  => pad_gen(PM_DATA6, 8),
1779
         PM_DATA7                                  => pad_gen(PM_DATA7, 8),
1780
         RECRC_CHK                                 => RECRC_CHK,
1781
         RECRC_CHK_TRIM                            => RECRC_CHK_TRIM,
1782
         REVISION_ID                               => pad_gen(REVISION_ID, 8),
1783
         ROOT_CAP_CRS_SW_VISIBILITY                => ROOT_CAP_CRS_SW_VISIBILITY,
1784
         SELECT_DLL_IF                             => SELECT_DLL_IF,
1785
         SLOT_CAP_ATT_BUTTON_PRESENT               => SLOT_CAP_ATT_BUTTON_PRESENT,
1786
         SLOT_CAP_ATT_INDICATOR_PRESENT            => SLOT_CAP_ATT_INDICATOR_PRESENT,
1787
         SLOT_CAP_ELEC_INTERLOCK_PRESENT           => SLOT_CAP_ELEC_INTERLOCK_PRESENT,
1788
         SLOT_CAP_HOTPLUG_CAPABLE                  => SLOT_CAP_HOTPLUG_CAPABLE,
1789
         SLOT_CAP_HOTPLUG_SURPRISE                 => SLOT_CAP_HOTPLUG_SURPRISE,
1790
         SLOT_CAP_MRL_SENSOR_PRESENT               => SLOT_CAP_MRL_SENSOR_PRESENT,
1791
         SLOT_CAP_NO_CMD_COMPLETED_SUPPORT         => SLOT_CAP_NO_CMD_COMPLETED_SUPPORT,
1792
         SLOT_CAP_PHYSICAL_SLOT_NUM                => SLOT_CAP_PHYSICAL_SLOT_NUM,
1793
         SLOT_CAP_POWER_CONTROLLER_PRESENT         => SLOT_CAP_POWER_CONTROLLER_PRESENT,
1794
         SLOT_CAP_POWER_INDICATOR_PRESENT          => SLOT_CAP_POWER_INDICATOR_PRESENT,
1795
         SLOT_CAP_SLOT_POWER_LIMIT_SCALE           => SLOT_CAP_SLOT_POWER_LIMIT_SCALE,
1796
         SLOT_CAP_SLOT_POWER_LIMIT_VALUE           => SLOT_CAP_SLOT_POWER_LIMIT_VALUE,
1797
         SPARE_BIT0                                => SPARE_BIT0,
1798
         SPARE_BIT1                                => SPARE_BIT1,
1799
         SPARE_BIT2                                => SPARE_BIT2,
1800
         SPARE_BIT3                                => SPARE_BIT3,
1801
         SPARE_BIT4                                => SPARE_BIT4,
1802
         SPARE_BIT5                                => SPARE_BIT5,
1803
         SPARE_BIT6                                => SPARE_BIT6,
1804
         SPARE_BIT7                                => SPARE_BIT7,
1805
         SPARE_BIT8                                => SPARE_BIT8,
1806
         SPARE_BYTE0                               => SPARE_BYTE0,
1807
         SPARE_BYTE1                               => SPARE_BYTE1,
1808
         SPARE_BYTE2                               => SPARE_BYTE2,
1809
         SPARE_BYTE3                               => SPARE_BYTE3,
1810
         SPARE_WORD0                               => SPARE_WORD0,
1811
         SPARE_WORD1                               => SPARE_WORD1,
1812
         SPARE_WORD2                               => SPARE_WORD2,
1813
         SPARE_WORD3                               => SPARE_WORD3,
1814
         SUBSYSTEM_ID                              => pad_gen(SUBSYSTEM_ID, 16),
1815
         SUBSYSTEM_VENDOR_ID                       => pad_gen(SUBSYSTEM_VENDOR_ID, 16),
1816
         TL_RBYPASS                                => TL_RBYPASS,
1817
         TL_RX_RAM_RADDR_LATENCY                   => TL_RX_RAM_RADDR_LATENCY,
1818
         TL_RX_RAM_RDATA_LATENCY                   => TL_RX_RAM_RDATA_LATENCY,
1819
         TL_RX_RAM_WRITE_LATENCY                   => TL_RX_RAM_WRITE_LATENCY,
1820
         TL_TFC_DISABLE                            => TL_TFC_DISABLE,
1821
         TL_TX_CHECKS_DISABLE                      => TL_TX_CHECKS_DISABLE,
1822
         TL_TX_RAM_RADDR_LATENCY                   => TL_TX_RAM_RADDR_LATENCY,
1823
         TL_TX_RAM_RDATA_LATENCY                   => TL_TX_RAM_RDATA_LATENCY,
1824
         TL_TX_RAM_WRITE_LATENCY                   => TL_TX_RAM_WRITE_LATENCY,
1825
         UPCONFIG_CAPABLE                          => UPCONFIG_CAPABLE,
1826
         UPSTREAM_FACING                           => UPSTREAM_FACING,
1827
         EXIT_LOOPBACK_ON_EI                       => EXIT_LOOPBACK_ON_EI,
1828
         UR_INV_REQ                                => UR_INV_REQ,
1829
         USER_CLK_FREQ                             => USER_CLK_FREQ,
1830
         VC_BASE_PTR                               => pad_gen(VC_BASE_PTR, 12),
1831
         VC_CAP_ID                                 => VC_CAP_ID,
1832
         VC_CAP_NEXTPTR                            => pad_gen(VC_CAP_NEXTPTR, 12),
1833
         VC_CAP_ON                                 => VC_CAP_ON,
1834
         VC_CAP_REJECT_SNOOP_TRANSACTIONS          => VC_CAP_REJECT_SNOOP_TRANSACTIONS,
1835
         VC_CAP_VERSION                            => VC_CAP_VERSION,
1836
         VC0_CPL_INFINITE                          => VC0_CPL_INFINITE,
1837
         VC0_RX_RAM_LIMIT                          => pad_gen(VC0_RX_RAM_LIMIT, 13),
1838
         VC0_TOTAL_CREDITS_CD                      => VC0_TOTAL_CREDITS_CD,
1839
         VC0_TOTAL_CREDITS_CH                      => VC0_TOTAL_CREDITS_CH,
1840
         VC0_TOTAL_CREDITS_NPH                     => VC0_TOTAL_CREDITS_NPH,
1841
         VC0_TOTAL_CREDITS_PD                      => VC0_TOTAL_CREDITS_PD,
1842
         VC0_TOTAL_CREDITS_PH                      => VC0_TOTAL_CREDITS_PH,
1843
         VC0_TX_LASTPACKET                         => VC0_TX_LASTPACKET,
1844
         VENDOR_ID                                 => pad_gen(VENDOR_ID, 16),
1845
         VSEC_BASE_PTR                             => pad_gen(VSEC_BASE_PTR, 12),
1846
         VSEC_CAP_HDR_ID                           => VSEC_CAP_HDR_ID,
1847
         VSEC_CAP_HDR_LENGTH                       => VSEC_CAP_HDR_LENGTH,
1848
         VSEC_CAP_HDR_REVISION                     => VSEC_CAP_HDR_REVISION,
1849
         VSEC_CAP_ID                               => VSEC_CAP_ID,
1850
         VSEC_CAP_IS_LINK_VISIBLE                  => VSEC_CAP_IS_LINK_VISIBLE,
1851
         VSEC_CAP_NEXTPTR                          => pad_gen(VSEC_CAP_NEXTPTR, 12),
1852
         VSEC_CAP_ON                               => VSEC_CAP_ON,
1853
         VSEC_CAP_VERSION                          => VSEC_CAP_VERSION
1854
      )
1855
      port map (
1856
         PCIEXPRXN                            => pci_exp_rxn,
1857
         PCIEXPRXP                            => pci_exp_rxp,
1858
         PCIEXPTXN                            => pci_exp_txn,
1859
         PCIEXPTXP                            => pci_exp_txp,
1860
         SYSCLK                               => sys_clk,
1861
         TRNLNKUPN                            => trn_lnk_up_n,
1862
         FUNDRSTN                             => sys_reset_n_d,
1863
         PHYRDYN                              => phy_rdy_n,
1864
         LNKCLKEN                             => open,
1865
         USERRSTN                             => trn_reset_n,
1866
         RECEIVEDFUNCLVLRSTN                  => rx_func_level_reset_n,
1867
         SYSRSTN                              => phy_rdy,
1868
         PLRSTN                               => '1',
1869
         DLRSTN                               => '1',
1870
         TLRSTN                               => '1',
1871
         FUNCLVLRSTN                          => '1',
1872
         CMRSTN                               => '1',
1873
         CMSTICKYRSTN                         => '1',
1874
 
1875
         TRNRBARHITN                          => trn_rbar_hit_n,
1876
         TRNRD                                => trn_rd,
1877
         TRNRECRCERRN                         => trn_recrc_err_n,
1878
         TRNREOFN                             => trn_reof_n,
1879
         TRNRERRFWDN                          => trn_rerrfwd_n,
1880
         TRNRREMN                             => trn_rrem_n,
1881
         TRNRSOFN                             => trn_rsof_n,
1882
         TRNRSRCDSCN                          => trn_rsrc_dsc_n,
1883
         TRNRSRCRDYN                          => trn_rsrc_rdy_n,
1884
         TRNRDSTRDYN                          => trn_rdst_rdy_n,
1885
         TRNRNPOKN                            => trn_rnp_ok_n,
1886
         TRNRDLLPDATA                         => trn_rdllp_data,
1887
         TRNRDLLPSRCRDYN                      => trn_rdllp_src_rdy_n,
1888
 
1889
         TRNTBUFAV                            => tx_buf_av_int,
1890
         TRNTCFGREQN                          => trn_tcfg_req_n,
1891
         TRNTDLLPDSTRDYN                      => open,
1892
         TRNTDSTRDYN                          => trn_tdst_rdy_n,
1893
         TRNTERRDROPN                         => trn_terr_drop_n,
1894
         TRNTCFGGNTN                          => trn_tcfg_gnt_n,
1895
         TRNTD                                => trn_td,
1896
         TRNTDLLPDATA                         => (others => '0'),
1897
         TRNTDLLPSRCRDYN                      => '1',
1898
         TRNTECRCGENN                         => '1',
1899
         TRNTEOFN                             => trn_teof_n,
1900
         TRNTERRFWDN                          => trn_terrfwd_n,
1901
         TRNTREMN                             => trn_trem_n,
1902
         TRNTSOFN                             => trn_tsof_n,
1903
         TRNTSRCDSCN                          => trn_tsrc_dsc_n,
1904
         TRNTSRCRDYN                          => trn_tsrc_rdy_n,
1905
         TRNTSTRN                             => trn_tstr_n,
1906
         TRNFCCPLD                            => fc_cpld,
1907
         TRNFCCPLH                            => fc_cplh,
1908
         TRNFCNPD                             => fc_npd,
1909
         TRNFCNPH                             => fc_nph,
1910
         TRNFCPD                              => fc_pd,
1911
         TRNFCPH                              => fc_ph,
1912
         TRNFCSEL                             => fc_sel,
1913
         CFGAERECRCCHECKEN                    => open,
1914
         CFGAERECRCGENEN                      => open,
1915
         CFGCOMMANDBUSMASTERENABLE            => cfg_cmd_bme,
1916
         CFGCOMMANDINTERRUPTDISABLE           => cfg_cmd_intdis,
1917
         CFGCOMMANDIOENABLE                   => cfg_cmd_io_en,
1918
         CFGCOMMANDMEMENABLE                  => cfg_cmd_mem_en,
1919
         CFGCOMMANDSERREN                     => cfg_cmd_serr_en,
1920
         CFGDEVCONTROLAUXPOWEREN              => cfg_dev_control_aux_power_en,
1921
         CFGDEVCONTROLCORRERRREPORTINGEN      => cfg_dev_control_corr_err_reporting_en,
1922
         CFGDEVCONTROLENABLERO                => cfg_dev_control_enable_relaxed_order,
1923
         CFGDEVCONTROLEXTTAGEN                => cfg_dev_control_ext_tag_en,
1924
         CFGDEVCONTROLFATALERRREPORTINGEN     => cfg_dev_control_fatal_err_reporting_en,
1925
         CFGDEVCONTROLMAXPAYLOAD              => cfg_dev_control_maxpayload,
1926
         CFGDEVCONTROLMAXREADREQ              => cfg_dev_control_max_read_req,
1927
         CFGDEVCONTROLNONFATALREPORTINGEN     => cfg_dev_control_non_fatal_reporting_en,
1928
         CFGDEVCONTROLNOSNOOPEN               => cfg_dev_control_nosnoop_en,
1929
         CFGDEVCONTROLPHANTOMEN               => cfg_dev_control_phantom_en,
1930
         CFGDEVCONTROLURERRREPORTINGEN        => cfg_dev_control_ur_err_reporting_en,
1931
         CFGDEVCONTROL2CPLTIMEOUTDIS          => cfg_dev_control2_cpltimeout_dis,
1932
         CFGDEVCONTROL2CPLTIMEOUTVAL          => cfg_dev_control2_cpltimeout_val,
1933
         CFGDEVSTATUSCORRERRDETECTED          => cfg_dev_status_corr_err_detected,
1934
         CFGDEVSTATUSFATALERRDETECTED         => cfg_dev_status_fatal_err_detected,
1935
         CFGDEVSTATUSNONFATALERRDETECTED      => cfg_dev_status_nonfatal_err_detected,
1936
         CFGDEVSTATUSURDETECTED               => cfg_dev_status_ur_detected,
1937
         CFGDO                                => cfg_do,
1938
         CFGERRAERHEADERLOGSETN               => open,
1939
         CFGERRCPLRDYN                        => cfg_err_cpl_rdy_n,
1940
         CFGINTERRUPTDO                       => cfg_interrupt_do,
1941
         CFGINTERRUPTMMENABLE                 => cfg_interrupt_mmenable,
1942
         CFGINTERRUPTMSIENABLE                => cfg_interrupt_msienable,
1943
         CFGINTERRUPTMSIXENABLE               => cfg_interrupt_msixenable,
1944
         CFGINTERRUPTMSIXFM                   => cfg_interrupt_msixfm,
1945
         CFGINTERRUPTRDYN                     => cfg_interrupt_rdy_n,
1946
         CFGLINKCONTROLRCB                    => cfg_link_control_rcb,
1947
         CFGLINKCONTROLASPMCONTROL            => cfg_link_control_aspm_control,
1948
         CFGLINKCONTROLAUTOBANDWIDTHINTEN     => cfg_link_control_auto_bandwidth_int_en,
1949
         CFGLINKCONTROLBANDWIDTHINTEN         => cfg_link_control_bandwidth_int_en,
1950
         CFGLINKCONTROLCLOCKPMEN              => cfg_link_control_clock_pm_en,
1951
         CFGLINKCONTROLCOMMONCLOCK            => cfg_link_control_common_clock,
1952
         CFGLINKCONTROLEXTENDEDSYNC           => cfg_link_control_extended_sync,
1953
         CFGLINKCONTROLHWAUTOWIDTHDIS         => cfg_link_control_hw_auto_width_dis,
1954
         CFGLINKCONTROLLINKDISABLE            => cfg_link_control_linkdisable,
1955
         CFGLINKCONTROLRETRAINLINK            => cfg_link_control_retrain_link,
1956
         CFGLINKSTATUSAUTOBANDWIDTHSTATUS     => cfg_link_status_autobandwidth_status,
1957
         CFGLINKSTATUSBANDWITHSTATUS          => cfg_link_status_bandwidth_status,
1958
         CFGLINKSTATUSCURRENTSPEED            => cfg_link_status_current_speed,
1959
         CFGLINKSTATUSDLLACTIVE               => cfg_link_status_dll_active,
1960
         CFGLINKSTATUSLINKTRAINING            => cfg_link_status_link_training,
1961
         CFGLINKSTATUSNEGOTIATEDWIDTH         => cfg_link_status_negotiated_link_width,
1962
         CFGMSGDATA                           => cfg_msg_data,
1963
         CFGMSGRECEIVED                       => cfg_msg_received,
1964
         CFGMSGRECEIVEDASSERTINTA             => open,
1965
         CFGMSGRECEIVEDASSERTINTB             => open,
1966
         CFGMSGRECEIVEDASSERTINTC             => open,
1967
         CFGMSGRECEIVEDASSERTINTD             => open,
1968
         CFGMSGRECEIVEDDEASSERTINTA           => open,
1969
         CFGMSGRECEIVEDDEASSERTINTB           => open,
1970
         CFGMSGRECEIVEDDEASSERTINTC           => open,
1971
         CFGMSGRECEIVEDDEASSERTINTD           => open,
1972
         CFGMSGRECEIVEDERRCOR                 => open,
1973
         CFGMSGRECEIVEDERRFATAL               => open,
1974
         CFGMSGRECEIVEDERRNONFATAL            => open,
1975
         CFGMSGRECEIVEDPMASNAK                => open,
1976
         CFGMSGRECEIVEDPMETO                  => cfg_msg_received_pme_to,
1977
         CFGMSGRECEIVEDPMETOACK               => open,
1978
         CFGMSGRECEIVEDPMPME                  => open,
1979
         CFGMSGRECEIVEDSETSLOTPOWERLIMIT      => open,
1980
         CFGMSGRECEIVEDUNLOCK                 => open,
1981
         CFGPCIELINKSTATE                     => cfg_pcie_link_state_int,
1982
         CFGPMCSRPMEEN                        => cfg_pmcsr_pme_en,
1983
         CFGPMCSRPMESTATUS                    => cfg_pmcsr_pme_status,
1984
         CFGPMCSRPOWERSTATE                   => cfg_pmcsr_powerstate_int,
1985
         CFGPMRCVASREQL1N                     => open,
1986
         CFGPMRCVENTERL1N                     => open,
1987
         CFGPMRCVENTERL23N                    => open,
1988
         CFGPMRCVREQACKN                      => open,
1989
         CFGRDWRDONEN                         => cfg_rd_wr_done_n,
1990
         CFGSLOTCONTROLELECTROMECHILCTLPULSE  => open,
1991
         CFGTRANSACTION                       => open,
1992
         CFGTRANSACTIONADDR                   => open,
1993
         CFGTRANSACTIONTYPE                   => open,
1994
         CFGVCTCVCMAP                         => open,
1995
         CFGBYTEENN                           => cfg_byte_en_n,
1996
         CFGDI                                => cfg_di,
1997
         CFGDSBUSNUMBER                       => "00000000",
1998
         CFGDSDEVICENUMBER                    => "00000",
1999
         CFGDSFUNCTIONNUMBER                  => "000",
2000
         CFGDSN                               => cfg_dsn,
2001
         CFGDWADDR                            => cfg_dwaddr,
2002
         CFGERRACSN                           => '1',
2003
         CFGERRAERHEADERLOG                   => (others => '0'),
2004
         CFGERRCORN                           => cfg_err_cor_n,
2005
         CFGERRCPLABORTN                      => cfg_err_cpl_abort_n,
2006
         CFGERRCPLTIMEOUTN                    => cfg_err_cpl_timeout_n,
2007
         CFGERRCPLUNEXPECTN                   => cfg_err_cpl_unexpect_n,
2008
         CFGERRECRCN                          => cfg_err_ecrc_n,
2009
         CFGERRLOCKEDN                        => cfg_err_locked_n,
2010
         CFGERRPOSTEDN                        => cfg_err_posted_n,
2011
         CFGERRTLPCPLHEADER                   => cfg_err_tlp_cpl_header,
2012
         CFGERRURN                            => cfg_err_ur_n,
2013
         CFGINTERRUPTASSERTN                  => cfg_interrupt_assert_n,
2014
         CFGINTERRUPTDI                       => cfg_interrupt_di,
2015
         CFGINTERRUPTN                        => cfg_interrupt_n,
2016
         CFGPMDIRECTASPML1N                   => '1',
2017
         CFGPMSENDPMACKN                      => '1',
2018
         CFGPMSENDPMETON                      => '1',
2019
         CFGPMSENDPMNAKN                      => '1',
2020
         CFGPMTURNOFFOKN                      => cfg_turnoff_ok_n,
2021
         CFGPMWAKEN                           => cfg_pm_wake_n,
2022
         CFGPORTNUMBER                        => "00000000",
2023
         CFGRDENN                             => cfg_rd_en_n,
2024
         CFGTRNPENDINGN                       => cfg_trn_pending_n,
2025
         CFGWRENN                             => cfg_wr_en_n,
2026
         CFGWRREADONLYN                       => '1',
2027
         CFGWRRW1CASRWN                       => '1',
2028
 
2029
         PLINITIALLINKWIDTH                   => pl_initial_link_width,
2030
         PLLANEREVERSALMODE                   => pl_lane_reversal_mode,
2031
         PLLINKGEN2CAP                        => pl_link_gen2_capable,
2032
         PLLINKPARTNERGEN2SUPPORTED           => pl_link_partner_gen2_supported,
2033
         PLLINKUPCFGCAP                       => pl_link_upcfg_capable,
2034
         PLLTSSMSTATE                         => pl_ltssm_state,
2035
         PLPHYLNKUPN                          => open,                                 -- Debug
2036
         PLRECEIVEDHOTRST                     => pl_received_hot_rst,
2037
         PLRXPMSTATE                          => open,                                 -- Debug
2038
         PLSELLNKRATE                         => pl_sel_link_rate_int,
2039
         PLSELLNKWIDTH                        => pl_sel_link_width_int,
2040
         PLTXPMSTATE                          => open,                                 -- Debug
2041
         PLDIRECTEDLINKAUTON                  => pl_directed_link_auton,
2042
         PLDIRECTEDLINKCHANGE                 => pl_directed_link_change,
2043
         PLDIRECTEDLINKSPEED                  => pl_directed_link_speed,
2044
         PLDIRECTEDLINKWIDTH                  => pl_directed_link_width,
2045
         PLDOWNSTREAMDEEMPHSOURCE             => '1',
2046
         PLUPSTREAMPREFERDEEMPH               => pl_upstream_prefer_deemph,
2047
         PLTRANSMITHOTRST                     => '0',
2048
 
2049
         DBGSCLRA                             => open,
2050
         DBGSCLRB                             => open,
2051
         DBGSCLRC                             => open,
2052
         DBGSCLRD                             => open,
2053
         DBGSCLRE                             => open,
2054
         DBGSCLRF                             => open,
2055
         DBGSCLRG                             => open,
2056
         DBGSCLRH                             => open,
2057
         DBGSCLRI                             => open,
2058
         DBGSCLRJ                             => open,
2059
         DBGSCLRK                             => open,
2060
         DBGVECA                              => open,
2061
         DBGVECB                              => open,
2062
         DBGVECC                              => open,
2063
         PLDBGVEC                             => open,
2064
         DBGMODE                              => "00",
2065
         DBGSUBMODE                           => '0',
2066
         PLDBGMODE                            => "000",
2067
 
2068
         PCIEDRPDO                            => open,
2069
         PCIEDRPDRDY                          => open,
2070
         PCIEDRPCLK                           => '0',
2071
         PCIEDRPDADDR                         => "000000000",
2072
         PCIEDRPDEN                           => '0',
2073
         PCIEDRPDI                            => X"0000",
2074
         PCIEDRPDWE                           => '0',
2075
 
2076
         GTPLLLOCK                            => gt_pll_lock,
2077
         PIPECLK                              => pipe_clk,
2078
         USERCLK                              => user_clk,
2079
         DRPCLK                               => drp_clk,
2080
         CLOCKLOCKED                          => clock_locked,
2081
         TxOutClk                             => TxOutClk
2082
      );
2083
 
2084
end v6_pcie;
2085
 

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