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##############################################################
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#
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# Xilinx Core Generator version 13.1
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# Date: Wed Aug 17 14:10:54 2011
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#
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##############################################################
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#
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# This file contains the customisation parameters for a
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# Xilinx CORE Generator IP GUI. It is strongly recommended
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# that you do not manually alter this file as it may cause
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# unexpected and unsupported behavior.
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#
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##############################################################
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#
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# BEGIN Project Options
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SET addpads = false
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SET asysymbol = true
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SET busformat = BusFormatAngleBracketNotRipped
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SET createndf = false
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SET designentry = VHDL
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SET device = xc6vlx240t
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SET devicefamily = virtex6
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SET flowvendor = Other
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SET formalverification = false
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SET foundationsym = false
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SET implementationfiletype = Ngc
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SET package = ff1156
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SET removerpms = false
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SET simulationfiles = Behavioral
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SET speedgrade = -1
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SET verilogsim = false
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SET vhdlsim = true
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# END Project Options
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# BEGIN Select
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SELECT Virtex-6_Integrated_Block_for_PCI_Express family Xilinx,_Inc. 2.3
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# END Select
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# BEGIN Parameters
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CSET acceptable_l0s_latency=Maximum_of_64_ns
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CSET acceptable_l1_latency=No_limit
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CSET ack_nak_timeout_func=Absolute
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CSET ack_nak_timeout_value=0000
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CSET bar0_64bit=false
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CSET bar0_enabled=true
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CSET bar0_prefetchable=false
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CSET bar0_scale=Megabytes
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CSET bar0_size=2
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CSET bar0_type=Memory
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CSET bar1_64bit=false
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CSET bar1_enabled=true
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CSET bar1_prefetchable=false
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CSET bar1_scale=Megabytes
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CSET bar1_size=2
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CSET bar1_type=Memory
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CSET bar2_64bit=false
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CSET bar2_enabled=false
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CSET bar2_prefetchable=false
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CSET bar2_scale=Megabytes
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CSET bar2_size=2
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CSET bar2_type=N/A
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CSET bar3_64bit=false
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CSET bar3_enabled=false
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CSET bar3_prefetchable=false
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CSET bar3_scale=Kilobytes
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CSET bar3_size=2
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CSET bar3_type=N/A
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CSET bar4_64bit=false
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CSET bar4_enabled=false
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CSET bar4_prefetchable=false
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CSET bar4_scale=Kilobytes
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CSET bar4_size=2
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CSET bar4_type=N/A
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CSET bar5_enabled=false
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CSET bar5_prefetchable=false
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CSET bar5_scale=Kilobytes
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CSET bar5_size=2
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CSET bar5_type=N/A
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CSET base_class_menu=Simple_communication_controllers
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CSET buf_opt_bma=true
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CSET cardbus_cis_pointer=00000000
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CSET class_code_base=FF
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CSET class_code_interface=FF
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CSET class_code_sub=FF
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CSET component_name=cl_v6pcie_x4
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CSET cost_table=1
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CSET cpl_finite=false
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CSET cpl_timeout_disable_sup=false
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CSET cpl_timeout_range=Range_B
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CSET d0_pme_support=true
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CSET d0_power_consumed=0
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CSET d0_power_consumed_factor=0
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CSET d0_power_dissipated=0
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CSET d0_power_dissipated_factor=0
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CSET d1_pme_support=true
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CSET d1_power_consumed=0
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CSET d1_power_consumed_factor=0
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CSET d1_power_dissipated=0
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CSET d1_power_dissipated_factor=0
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CSET d1_support=false
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CSET d2_pme_support=true
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CSET d2_power_consumed=0
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CSET d2_power_consumed_factor=0
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CSET d2_power_dissipated=0
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CSET d2_power_dissipated_factor=0
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CSET d2_support=false
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CSET d3_power_consumed=0
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CSET d3_power_consumed_factor=0
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CSET d3_power_dissipated=0
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CSET d3_power_dissipated_factor=0
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CSET d3cold_pme_support=false
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CSET d3hot_pme_support=true
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CSET de_emph=0
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CSET device_id=5507
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CSET device_port_type=PCI_Express_Endpoint_device
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CSET device_specific_initialization=false
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CSET disable_tx_aspm_l0s=false
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CSET dll_link_active_cap=false
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CSET downstream_link_num=00
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CSET dsn_enabled=false
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CSET en_route_err_cor=false
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CSET en_route_err_ftl=false
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CSET en_route_err_nfl=false
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CSET en_route_inta=false
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CSET en_route_intb=false
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CSET en_route_intc=false
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CSET en_route_intd=false
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CSET en_route_pm_pme=false
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CSET en_route_pme_to=false
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CSET en_route_pme_to_ack=false
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CSET en_route_unlock=false
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CSET enable_ack_nak_timer=false
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CSET enable_lane_reversal=false
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CSET enable_replay_timer=true
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CSET enable_slot_clock_cfg=true
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CSET expansion_rom_enabled=false
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CSET expansion_rom_scale=Kilobytes
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CSET expansion_rom_size=2
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CSET ext_pci_cfg_space=false
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CSET ext_pci_cfg_space_addr=3FF
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CSET extended_tag_field=false
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CSET force_no_scrambling=false
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CSET hw_auton_spd_disable=false
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CSET intx_generation=true
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CSET io_base_limit_registers=Disabled
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CSET legacy_interrupt=INTA
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CSET link_speed=5.0_GT/s
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CSET max_payload_size=256_bytes
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CSET maximum_link_width=X4
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CSET msi_64b=true
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CSET msi_enabled=false
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CSET msi_vec_mask=false
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CSET msix_enabled=false
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CSET msix_pba_bir=BAR_0
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CSET msix_pba_offset=0
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CSET msix_table_bir=BAR_0
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CSET msix_table_offset=0
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CSET msix_table_size=1
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CSET multiple_message_capable=1_vector
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CSET no_soft_reset=true
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CSET pci_cfg_space=false
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CSET pci_cfg_space_addr=3F
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CSET pcie_blk_locn=X0Y0
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CSET pcie_cap_slot_implemented=false
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CSET pcie_debug_ports=false
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CSET perf_level=High
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CSET phantom_functions=No_function_number_bits_used
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CSET pipe_pipeline=None
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CSET prefetchable_memory_base_limit_registers=Disabled
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CSET rcb=64_byte
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CSET ref_clk_freq=100_MHz
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CSET replay_timeout_func=Add
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CSET replay_timeout_value=0026
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CSET revision_id=20
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CSET root_cap_crs=false
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CSET slot_cap_attn_butn=false
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CSET slot_cap_attn_ind=false
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CSET slot_cap_elec_interlock=false
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CSET slot_cap_hotplug_cap=false
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CSET slot_cap_hotplug_surprise=false
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CSET slot_cap_mrl=false
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CSET slot_cap_no_cmd_comp_sup=false
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CSET slot_cap_physical_slot_num=0
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CSET slot_cap_pwr_ctrl=false
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CSET slot_cap_pwr_ind=false
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CSET slot_cap_pwr_limit_scale=0
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CSET slot_cap_pwr_limit_value=0
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CSET sub_class_interface_menu=Generic_XT_compatible_serial_controller
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CSET subsystem_id=0002
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CSET subsystem_vendor_id=4953
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CSET trans_buf_pipeline=None
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CSET trgt_link_speed=4'h2
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CSET trim_tlp_digest=true
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CSET upconfigure_capable=true
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CSET user_clk_freq=250_default
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CSET vc_cap_enabled=false
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CSET vc_cap_reject_snoop=false
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CSET vendor_id=4953
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CSET vsec_enabled=false
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CSET xlnx_ref_board=ML_605
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# END Parameters
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GENERATE
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# CRC: 67fe597f
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