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-------------------------------------------------------------------------------
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--
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-- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
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--
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-- This file contains confidential and proprietary information
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-- of Xilinx, Inc. and is protected under U.S. and
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-- international copyright and other intellectual property
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-- laws.
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--
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-- DISCLAIMER
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-- This disclaimer is not a license and does not grant any
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-- rights to the materials distributed herewith. Except as
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-- otherwise provided in a valid license issued to you by
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-- Xilinx, and to the maximum extent permitted by applicable
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-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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-- (2) Xilinx shall not be liable (whether in contract or tort,
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-- including negligence, or under any other theory of
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-- liability) for any loss or damage of any kind or nature
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-- related to, arising under or in connection with these
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-- materials, including for any direct, or any indirect,
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-- special, incidental, or consequential loss or damage
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-- (including loss of data, profits, goodwill, or any type of
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-- loss or damage suffered as a result of any action brought
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-- by a third party) even if such damage or loss was
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-- reasonably foreseeable or Xilinx had been advised of the
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-- possibility of the same.
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--
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-- CRITICAL APPLICATIONS
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-- Xilinx products are not designed or intended to be fail-
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-- safe, or for use in any application requiring fail-safe
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-- performance, such as life-support or safety devices or
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-- systems, Class III medical devices, nuclear facilities,
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-- applications related to the deployment of airbags, or any
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-- other applications that could lead to death, personal
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-- injury, or severe property or environmental damage
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-- (individually and collectively, "Critical
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-- Applications"). Customer assumes the sole risk and
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-- liability of any use of Xilinx products in Critical
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-- Applications, subject only to applicable laws and
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-- regulations governing limitations on product liability.
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--
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-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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-- PART OF THIS FILE AT ALL TIMES.
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--
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-------------------------------------------------------------------------------
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-- Project : Virtex-6 Integrated Block for PCI Express
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-- File : gtx_rx_valid_filter_v6.vhd
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-- Version : 2.3
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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library unisim;
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use unisim.vcomponents.all;
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entity GTX_RX_VALID_FILTER_V6 is
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generic (
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CLK_COR_MIN_LAT : integer := 28
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);
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port (
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USER_RXCHARISK : out std_logic_vector(1 downto 0);
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USER_RXDATA : out std_logic_vector(15 downto 0);
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USER_RXVALID : out std_logic;
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USER_RXELECIDLE : out std_logic;
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USER_RX_STATUS : out std_logic_vector(2 downto 0);
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USER_RX_PHY_STATUS : out std_logic;
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GT_RXCHARISK : in std_logic_vector(1 downto 0);
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GT_RXDATA : in std_logic_vector(15 downto 0);
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GT_RXVALID : in std_logic;
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GT_RXELECIDLE : in std_logic;
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GT_RX_STATUS : in std_logic_vector(2 downto 0);
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GT_RX_PHY_STATUS : in std_logic;
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PLM_IN_L0 : in std_logic;
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PLM_IN_RS : in std_logic;
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USER_CLK : in std_logic;
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RESET : in std_logic
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);
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end GTX_RX_VALID_FILTER_V6;
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architecture v6_pcie of GTX_RX_VALID_FILTER_V6 is
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constant TCQ : integer := 1;
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constant EIOS_DET_IDL : std_logic_vector(4 downto 0) := "00001";
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constant EIOS_DET_NO_STR0 : std_logic_vector(4 downto 0) := "00010";
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constant EIOS_DET_STR0 : std_logic_vector(4 downto 0) := "00100";
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constant EIOS_DET_STR1 : std_logic_vector(4 downto 0) := "01000";
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constant EIOS_DET_DONE : std_logic_vector(4 downto 0) := "10000";
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constant EIOS_COM : std_logic_vector(7 downto 0) := "10111100";
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constant EIOS_IDL : std_logic_vector(7 downto 0) := "01111100";
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constant FTSOS_COM : std_logic_vector(7 downto 0) := "10111100";
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constant FTSOS_FTS : std_logic_vector(7 downto 0) := "00111100";
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constant USER_RXVLD_IDL : std_logic_vector(3 downto 0) := "0001";
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constant USER_RXVLD_EI : std_logic_vector(3 downto 0) := "0010";
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constant USER_RXVLD_EI_DB0 : std_logic_vector(3 downto 0) := "0100";
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constant USER_RXVLD_EI_DB1 : std_logic_vector(3 downto 0) := "1000";
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constant TS1_FILTER_IDLE : std_logic_vector(2 downto 0) := "001";
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constant TS1_FILTER_WAITVALID : std_logic_vector(2 downto 0) := "010";
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constant TS1_FILTER_DB : std_logic_vector(2 downto 0) := "100";
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FUNCTION to_stdlogicvector (
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val_in : IN integer;
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length : IN integer) RETURN std_logic_vector IS
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VARIABLE ret : std_logic_vector(length-1 DOWNTO 0) := (OTHERS => '0');
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VARIABLE num : integer := val_in;
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VARIABLE x : integer;
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BEGIN
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FOR index IN 0 TO length-1 LOOP
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x := num rem 2;
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num := num/2;
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IF (x = 1) THEN
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ret(index) := '1';
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ELSE
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ret(index) := '0';
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END IF;
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END LOOP;
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RETURN(ret);
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END to_stdlogicvector;
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FUNCTION to_stdlogic (
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in_val : IN boolean) RETURN std_logic IS
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BEGIN
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IF (in_val) THEN
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RETURN('1');
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ELSE
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RETURN('0');
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END IF;
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END to_stdlogic;
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signal reg_state_eios_det : std_logic_vector(4 downto 0);
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signal state_eios_det : std_logic_vector(4 downto 0);
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signal reg_eios_detected : std_logic;
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signal eios_detected : std_logic;
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signal reg_symbol_after_eios : std_logic;
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signal symbol_after_eios : std_logic;
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signal reg_state_rxvld_ei : std_logic_vector(3 downto 0);
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signal state_rxvld_ei : std_logic_vector(3 downto 0);
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signal reg_rxvld_count : std_logic_vector(4 downto 0);
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signal rxvld_count : std_logic_vector(4 downto 0);
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signal reg_rxvld_fallback : std_logic_vector(3 downto 0);
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signal rxvld_fallback : std_logic_vector(3 downto 0);
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signal gt_rxcharisk_q : std_logic_vector(1 downto 0);
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signal gt_rxdata_q : std_logic_vector(15 downto 0);
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signal gt_rxvalid_q : std_logic;
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signal gt_rxelecidle_q : std_logic;
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signal gt_rxelecidle_qq : std_logic;
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signal gt_rx_status_q : std_logic_vector(2 downto 0);
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signal gt_rx_phy_status_q : std_logic;
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signal gt_rx_is_skp0_q : std_logic;
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signal gt_rx_is_skp1_q : std_logic;
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signal ts1_state : std_logic_vector(2 downto 0);
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signal next_ts1_state : std_logic_vector(2 downto 0);
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signal ts1_resetcount : std_logic;
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signal ts1_count : std_logic_vector(8 downto 0);
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signal ts1_filter_done : std_logic;
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signal next_ts1_filter_done : std_logic;
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signal awake_in_progress_q : std_logic := '0';
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signal awake_in_progress : std_logic := '0';
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signal awake_see_com_q : std_logic := '0';
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signal awake_com_count_q : std_logic_vector(3 downto 0) := "0000";
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signal awake_com_count : std_logic_vector(3 downto 0) := "0000";
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signal awake_com_count_inced : std_logic_vector(3 downto 0) := "0000";
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signal awake_see_com_0 : std_logic;
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signal awake_see_com_1 : std_logic;
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signal awake_see_com : std_logic;
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signal awake_done : std_logic;
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signal awake_start : std_logic;
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signal rst_l : std_logic;
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-- Declare intermediate signals for referenced outputs
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signal USER_RXVALID_v6pcie1 : std_logic;
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signal USER_RXELECIDLE_v6pcie0 : std_logic;
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begin
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-- Drive referenced outputs
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USER_RXVALID <= USER_RXVALID_v6pcie1;
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USER_RXELECIDLE <= USER_RXELECIDLE_v6pcie0;
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-- EIOS detector
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process (USER_CLK)
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begin
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if (USER_CLK'event and USER_CLK = '1') then
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if (RESET = '1') then
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reg_eios_detected <= '0' after (TCQ)*1 ps;
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reg_state_eios_det <= EIOS_DET_IDL after (TCQ)*1 ps;
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reg_symbol_after_eios <= '0' after (TCQ)*1 ps;
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gt_rxcharisk_q <= "00" after (TCQ)*1 ps;
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gt_rxdata_q <= "0000000000000000" after (TCQ)*1 ps;
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gt_rxvalid_q <= '0' after (TCQ)*1 ps;
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gt_rxelecidle_q <= '0' after (TCQ)*1 ps;
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gt_rxelecidle_qq <= '0' after (TCQ)*1 ps;
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gt_rx_status_q <= "000" after (TCQ)*1 ps;
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gt_rx_phy_status_q <= '0' after (TCQ)*1 ps;
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gt_rx_is_skp0_q <= '0' after (TCQ)*1 ps;
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gt_rx_is_skp1_q <= '0' after (TCQ)*1 ps;
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else
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reg_eios_detected <= '0' after (TCQ)*1 ps;
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reg_symbol_after_eios <= '0' after (TCQ)*1 ps;
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gt_rxcharisk_q <= GT_RXCHARISK after (TCQ)*1 ps;
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gt_rxdata_q <= GT_RXDATA after (TCQ)*1 ps;
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gt_rxvalid_q <= GT_RXVALID after (TCQ)*1 ps;
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gt_rxelecidle_q <= GT_RXELECIDLE after (TCQ)*1 ps;
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gt_rxelecidle_qq <= gt_rxelecidle_q after (TCQ)*1 ps;
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gt_rx_status_q <= GT_RX_STATUS after (TCQ)*1 ps;
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gt_rx_phy_status_q <= GT_RX_PHY_STATUS after (TCQ)*1 ps;
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if ((GT_RXCHARISK(0) = '1') and (GT_RXDATA(7 downto 0) = FTSOS_FTS)) then
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gt_rx_is_skp0_q <= '1' after (TCQ)*1 ps;
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else
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gt_rx_is_skp0_q <= '0' after (TCQ)*1 ps;
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end if;
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if ((GT_RXCHARISK(1) = '1') and (GT_RXDATA(15 downto 8) = FTSOS_FTS)) then
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gt_rx_is_skp1_q <= '1' after (TCQ)*1 ps;
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else
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gt_rx_is_skp1_q <= '0' after (TCQ)*1 ps;
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end if;
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case state_eios_det is
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when EIOS_DET_IDL =>
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if ((gt_rxcharisk_q(0) = '1') and (gt_rxdata_q(7 downto 0) = EIOS_COM) and (gt_rxcharisk_q(1) = '1') and (gt_rxdata_q(15 downto 8) = EIOS_IDL)) then
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reg_state_eios_det <= EIOS_DET_NO_STR0 after (TCQ)*1 ps;
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reg_eios_detected <= '1' after (TCQ)*1 ps;
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elsif ((gt_rxcharisk_q(1) = '1') and (gt_rxdata_q(15 downto 8) = EIOS_COM)) then
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reg_state_eios_det <= EIOS_DET_STR0 after (TCQ)*1 ps;
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else
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reg_state_eios_det <= EIOS_DET_IDL after (TCQ)*1 ps;
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end if;
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when EIOS_DET_NO_STR0 =>
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if ((gt_rxcharisk_q(0) = '1') and (gt_rxdata_q(7 downto 0) = EIOS_IDL) and (gt_rxcharisk_q(1) = '1') and (gt_rxdata_q(15 downto 8) = EIOS_IDL)) then
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reg_state_eios_det <= EIOS_DET_DONE after (TCQ)*1 ps;
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else
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reg_state_eios_det <= EIOS_DET_IDL after (TCQ)*1 ps;
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end if;
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when EIOS_DET_STR0 =>
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if ((gt_rxcharisk_q(0) = '1') and (gt_rxdata_q(7 downto 0) = EIOS_IDL) and (gt_rxcharisk_q(1) = '1') and (gt_rxdata_q(15 downto 8) = EIOS_IDL)) then
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reg_state_eios_det <= EIOS_DET_STR1 after (TCQ)*1 ps;
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reg_eios_detected <= '1' after (TCQ)*1 ps;
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reg_symbol_after_eios <= '1' after (TCQ)*1 ps;
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else
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reg_state_eios_det <= EIOS_DET_IDL after (TCQ)*1 ps;
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end if;
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when EIOS_DET_STR1 =>
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if ((gt_rxcharisk_q(0) = '1') and (gt_rxdata_q(7 downto 0) = EIOS_IDL)) then
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reg_state_eios_det <= EIOS_DET_DONE after (TCQ)*1 ps;
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else
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reg_state_eios_det <= EIOS_DET_IDL after (TCQ)*1 ps;
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end if;
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when EIOS_DET_DONE =>
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reg_state_eios_det <= EIOS_DET_IDL after (TCQ)*1 ps;
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when others =>
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reg_state_eios_det <= EIOS_DET_IDL after (TCQ)*1 ps;
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end case;
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end if;
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end if;
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end process;
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state_eios_det <= reg_state_eios_det;
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eios_detected <= reg_eios_detected;
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symbol_after_eios <= reg_symbol_after_eios;
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-- user_rxvalid generation
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process (USER_CLK)
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begin
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300 |
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if (USER_CLK'event and USER_CLK = '1') then
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301 |
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if (RESET = '1') then
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reg_state_rxvld_ei <= USER_RXVLD_IDL after (TCQ)*1 ps;
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else
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case state_rxvld_ei is
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306 |
|
|
|
307 |
|
|
when USER_RXVLD_IDL =>
|
308 |
|
|
if (eios_detected = '1') then
|
309 |
|
|
reg_state_rxvld_ei <= USER_RXVLD_EI after (TCQ)*1 ps;
|
310 |
|
|
else
|
311 |
|
|
reg_state_rxvld_ei <= USER_RXVLD_IDL after (TCQ)*1 ps;
|
312 |
|
|
end if;
|
313 |
|
|
|
314 |
|
|
when USER_RXVLD_EI =>
|
315 |
|
|
if ((not(gt_rxvalid_q)) = '1') then
|
316 |
|
|
reg_state_rxvld_ei <= USER_RXVLD_EI_DB0 after (TCQ)*1 ps;
|
317 |
|
|
elsif (rxvld_fallback = "1111") then
|
318 |
|
|
reg_state_rxvld_ei <= USER_RXVLD_IDL after (TCQ)*1 ps;
|
319 |
|
|
else
|
320 |
|
|
reg_state_rxvld_ei <= USER_RXVLD_EI after (TCQ)*1 ps;
|
321 |
|
|
end if;
|
322 |
|
|
|
323 |
|
|
when USER_RXVLD_EI_DB0 =>
|
324 |
|
|
if (gt_rxvalid_q = '1') then
|
325 |
|
|
reg_state_rxvld_ei <= USER_RXVLD_EI_DB1 after (TCQ)*1 ps;
|
326 |
|
|
elsif ((not(PLM_IN_L0)) = '1') then
|
327 |
|
|
reg_state_rxvld_ei <= USER_RXVLD_IDL after (TCQ)*1 ps;
|
328 |
|
|
else
|
329 |
|
|
reg_state_rxvld_ei <= USER_RXVLD_EI_DB0 after (TCQ)*1 ps;
|
330 |
|
|
end if;
|
331 |
|
|
|
332 |
|
|
when USER_RXVLD_EI_DB1 =>
|
333 |
|
|
if (rxvld_count > to_stdlogicvector(CLK_COR_MIN_LAT, 5)) then
|
334 |
|
|
reg_state_rxvld_ei <= USER_RXVLD_IDL after (TCQ)*1 ps;
|
335 |
|
|
else
|
336 |
|
|
reg_state_rxvld_ei <= USER_RXVLD_EI_DB1 after (TCQ)*1 ps;
|
337 |
|
|
end if;
|
338 |
|
|
when others =>
|
339 |
|
|
reg_state_rxvld_ei <= USER_RXVLD_IDL after (TCQ)*1 ps;
|
340 |
|
|
end case;
|
341 |
|
|
end if;
|
342 |
|
|
end if;
|
343 |
|
|
end process;
|
344 |
|
|
|
345 |
|
|
|
346 |
|
|
state_rxvld_ei <= reg_state_rxvld_ei;
|
347 |
|
|
|
348 |
|
|
-- RxValid counter
|
349 |
|
|
|
350 |
|
|
process (USER_CLK)
|
351 |
|
|
begin
|
352 |
|
|
if (USER_CLK'event and USER_CLK = '1') then
|
353 |
|
|
|
354 |
|
|
if (RESET = '1') then
|
355 |
|
|
reg_rxvld_count <= "00000" after (TCQ)*1 ps;
|
356 |
|
|
else
|
357 |
|
|
|
358 |
|
|
if ((gt_rxvalid_q = '1') and (state_rxvld_ei = USER_RXVLD_EI_DB1)) then
|
359 |
|
|
reg_rxvld_count <= reg_rxvld_count + "00001" after (TCQ)*1 ps;
|
360 |
|
|
else
|
361 |
|
|
reg_rxvld_count <= "00000" after (TCQ)*1 ps;
|
362 |
|
|
end if;
|
363 |
|
|
|
364 |
|
|
end if;
|
365 |
|
|
end if;
|
366 |
|
|
end process;
|
367 |
|
|
|
368 |
|
|
|
369 |
|
|
rxvld_count <= reg_rxvld_count;
|
370 |
|
|
|
371 |
|
|
-- RxValid fallback
|
372 |
|
|
|
373 |
|
|
process (USER_CLK)
|
374 |
|
|
begin
|
375 |
|
|
if (USER_CLK'event and USER_CLK = '1') then
|
376 |
|
|
if (RESET = '1') then
|
377 |
|
|
reg_rxvld_fallback <= "0000" after (TCQ)*1 ps;
|
378 |
|
|
else
|
379 |
|
|
if (state_rxvld_ei = USER_RXVLD_EI) then
|
380 |
|
|
reg_rxvld_fallback <= reg_rxvld_fallback + "0001" after (TCQ)*1 ps;
|
381 |
|
|
else
|
382 |
|
|
reg_rxvld_fallback <= "0000" after (TCQ)*1 ps;
|
383 |
|
|
end if;
|
384 |
|
|
end if;
|
385 |
|
|
end if;
|
386 |
|
|
end process;
|
387 |
|
|
|
388 |
|
|
rxvld_fallback <= reg_rxvld_fallback;
|
389 |
|
|
|
390 |
|
|
-- Delay pipe_rx_elec_idle
|
391 |
|
|
|
392 |
|
|
rx_elec_idle_delay : SRL16E
|
393 |
|
|
generic map (
|
394 |
|
|
INIT => X"0000"
|
395 |
|
|
)
|
396 |
|
|
port map (
|
397 |
|
|
Q => USER_RXELECIDLE_v6pcie0,
|
398 |
|
|
D => gt_rxelecidle_q,
|
399 |
|
|
CLK => USER_CLK,
|
400 |
|
|
CE => '1',
|
401 |
|
|
A3 => '1',
|
402 |
|
|
A2 => '1',
|
403 |
|
|
A1 => '1',
|
404 |
|
|
A0 => '1'
|
405 |
|
|
);
|
406 |
|
|
|
407 |
|
|
awake_see_com_0 <= GT_RXVALID and (gt_rxcharisk_q(0) and to_stdlogic(gt_rxdata_q(7 downto 0) = EIOS_COM));
|
408 |
|
|
|
409 |
|
|
awake_see_com_1 <= GT_RXVALID and (gt_rxcharisk_q(1) and to_stdlogic(gt_rxdata_q(15 downto 8) = EIOS_COM));
|
410 |
|
|
|
411 |
|
|
awake_see_com <= (awake_see_com_0 or awake_see_com_1) and not(awake_see_com_q);
|
412 |
|
|
|
413 |
|
|
-- Count 8 COMs, (not back-to-back), when waking up from electrical idle
|
414 |
|
|
-- but not for L0s (which is L0).
|
415 |
|
|
|
416 |
|
|
awake_done <= awake_in_progress_q and to_stdlogic(awake_com_count_q(3 downto 0) >= X"b");
|
417 |
|
|
|
418 |
|
|
awake_start <= (not(gt_rxelecidle_q) and gt_rxelecidle_qq) or PLM_IN_RS;
|
419 |
|
|
|
420 |
|
|
awake_in_progress <= awake_start or (not(awake_done) and awake_in_progress_q);
|
421 |
|
|
|
422 |
|
|
awake_com_count_inced <= awake_com_count_q(3 downto 0) + "0001";
|
423 |
|
|
|
424 |
|
|
awake_com_count <= "0000" when (not(awake_in_progress_q) = '1') else
|
425 |
|
|
"0000" when (awake_start = '1') else
|
426 |
|
|
awake_com_count_inced(3 downto 0) when (awake_see_com_q = '1') else
|
427 |
|
|
awake_com_count_q(3 downto 0);
|
428 |
|
|
|
429 |
|
|
rst_l <= not(RESET);
|
430 |
|
|
|
431 |
|
|
process (USER_CLK)
|
432 |
|
|
begin
|
433 |
|
|
if (USER_CLK'event and USER_CLK = '1') then
|
434 |
|
|
if (rst_l = '0') then
|
435 |
|
|
awake_see_com_q <= '0';
|
436 |
|
|
awake_in_progress_q <= '0';
|
437 |
|
|
awake_com_count_q(3 downto 0) <= "0000";
|
438 |
|
|
else
|
439 |
|
|
awake_see_com_q <= awake_see_com;
|
440 |
|
|
awake_in_progress_q <= awake_in_progress;
|
441 |
|
|
awake_com_count_q(3 downto 0) <= awake_com_count(3 downto 0);
|
442 |
|
|
end if;
|
443 |
|
|
end if;
|
444 |
|
|
end process;
|
445 |
|
|
|
446 |
|
|
USER_RXVALID_v6pcie1 <= gt_rxvalid_q when ((state_rxvld_ei = USER_RXVLD_IDL) and (not(awake_in_progress_q) = '1')) else
|
447 |
|
|
'0';
|
448 |
|
|
USER_RXCHARISK(0) <= gt_rxcharisk_q(0) when (USER_RXVALID_v6pcie1 = '1') else
|
449 |
|
|
'0';
|
450 |
|
|
USER_RXCHARISK(1) <= gt_rxcharisk_q(1) when ((USER_RXVALID_v6pcie1 and not(symbol_after_eios)) = '1') else
|
451 |
|
|
'0';
|
452 |
|
|
USER_RXDATA(7 downto 0) <= FTSOS_COM when (gt_rx_is_skp0_q = '1') else
|
453 |
|
|
gt_rxdata_q(7 downto 0);
|
454 |
|
|
|
455 |
|
|
USER_RXDATA(15 downto 8) <= FTSOS_COM when (gt_rx_is_skp1_q = '1') else
|
456 |
|
|
gt_rxdata_q(15 downto 8);
|
457 |
|
|
|
458 |
|
|
USER_RX_STATUS <= gt_rx_status_q when (state_rxvld_ei = USER_RXVLD_IDL) else
|
459 |
|
|
"000";
|
460 |
|
|
USER_RX_PHY_STATUS <= gt_rx_phy_status_q;
|
461 |
|
|
|
462 |
|
|
end v6_pcie;
|
463 |
|
|
|
464 |
|
|
|