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-------------------------------------------------------------------------------
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--
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-- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
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--
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-- This file contains confidential and proprietary information
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-- of Xilinx, Inc. and is protected under U.S. and
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-- international copyright and other intellectual property
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-- laws.
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--
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-- DISCLAIMER
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-- This disclaimer is not a license and does not grant any
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-- rights to the materials distributed herewith. Except as
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-- otherwise provided in a valid license issued to you by
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-- Xilinx, and to the maximum extent permitted by applicable
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-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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-- (2) Xilinx shall not be liable (whether in contract or tort,
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-- including negligence, or under any other theory of
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-- liability) for any loss or damage of any kind or nature
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-- related to, arising under or in connection with these
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-- materials, including for any direct, or any indirect,
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-- special, incidental, or consequential loss or damage
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-- (including loss of data, profits, goodwill, or any type of
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-- loss or damage suffered as a result of any action brought
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-- by a third party) even if such damage or loss was
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-- reasonably foreseeable or Xilinx had been advised of the
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-- possibility of the same.
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--
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-- CRITICAL APPLICATIONS
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-- Xilinx products are not designed or intended to be fail-
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-- safe, or for use in any application requiring fail-safe
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-- performance, such as life-support or safety devices or
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-- systems, Class III medical devices, nuclear facilities,
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-- applications related to the deployment of airbags, or any
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-- other applications that could lead to death, personal
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-- injury, or severe property or environmental damage
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-- (individually and collectively, "Critical
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-- Applications"). Customer assumes the sole risk and
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-- liability of any use of Xilinx products in Critical
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-- Applications, subject only to applicable laws and
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-- regulations governing limitations on product liability.
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--
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-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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-- PART OF THIS FILE AT ALL TIMES.
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--
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-------------------------------------------------------------------------------
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-- Project : Virtex-6 Integrated Block for PCI Express
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-- File : gtx_tx_sync_rate_v6.vhd
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-- Version : 2.3
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--
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-- Module TX_SYNC
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--
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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-- Module TX_SYNC
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entity GTX_TX_SYNC_RATE_V6 is
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generic (
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C_SIMULATION : integer := 0 -- Set to 1 for simulation
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);
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port (
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ENPMAPHASEALIGN : out std_logic;
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PMASETPHASE : out std_logic;
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SYNC_DONE : out std_logic;
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OUT_DIV_RESET : out std_logic;
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PCS_RESET : out std_logic;
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USER_PHYSTATUS : out std_logic;
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TXALIGNDISABLE : out std_logic;
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DELAYALIGNRESET : out std_logic;
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USER_CLK : in std_logic;
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RESET : in std_logic;
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RATE : in std_logic;
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RATEDONE : in std_logic;
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GT_PHYSTATUS : in std_logic;
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RESETDONE : in std_logic
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);
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end GTX_TX_SYNC_RATE_V6;
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architecture v6_pcie of GTX_TX_SYNC_RATE_V6 is
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constant TCQ : integer := 1;
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FUNCTION to_stdlogic (
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in_val : IN boolean) RETURN std_logic IS
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BEGIN
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IF (in_val) THEN
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RETURN('1');
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ELSE
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RETURN('0');
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END IF;
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END to_stdlogic;
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constant IDLE : std_logic_vector(24 downto 0) := "0000000000000000000000001";
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constant PHASEALIGN : std_logic_vector(24 downto 0) := "0000000000000000000000010";
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constant RATECHANGE_DIVRESET : std_logic_vector(24 downto 0) := "0000000000000000000000100";
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constant RATECHANGE_DIVRESET_POST : std_logic_vector(24 downto 0) := "0000000000000000000001000";
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constant RATECHANGE_ENPMADISABLE : std_logic_vector(24 downto 0) := "0000000000000000000010000";
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constant RATECHANGE_ENPMADISABLE_POST : std_logic_vector(24 downto 0) := "0000000000000000000100000";
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constant RATECHANGE_PMARESET : std_logic_vector(24 downto 0) := "0000000000000000001000000";
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constant RATECHANGE_IDLE : std_logic_vector(24 downto 0) := "0000000000000000010000000";
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constant RATECHANGE_PCSRESET : std_logic_vector(24 downto 0) := "0000000000000000100000000";
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constant RATECHANGE_PCSRESET_POST : std_logic_vector(24 downto 0) := "0000000000000001000000000";
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constant RATECHANGE_ASSERTPHY : std_logic_vector(24 downto 0) := "0000000000000010000000000";
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constant RESET_STATE : std_logic_vector(24 downto 0) := "0000000000000100000000000";
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constant WAIT_PHYSTATUS : std_logic_vector(24 downto 0) := "0000000000010000000000000";
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constant RATECHANGE_PMARESET_POST : std_logic_vector(24 downto 0) := "0000000000100000000000000";
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constant RATECHANGE_DISABLEPHASE : std_logic_vector(24 downto 0) := "0000000001000000000000000";
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constant DELAYALIGNRST : std_logic_vector(24 downto 0) := "0000000010000000000000000";
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constant SETENPMAPHASEALIGN : std_logic_vector(24 downto 0) := "0000000100000000000000000";
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constant TXALIGNDISABLEDEASSERT : std_logic_vector(24 downto 0) := "0000001000000000000000000";
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constant RATECHANGE_TXDLYALIGNDISABLE : std_logic_vector(24 downto 0) := "0000010000000000000000000";
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constant GTXTEST_PULSE_1 : std_logic_vector(24 downto 0) := "0000100000000000000000000";
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constant RATECHANGE_DISABLE_TXALIGNDISABLE : std_logic_vector(24 downto 0) := "0001000000000000000000000";
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constant BEFORE_GTXTEST_PULSE1_1024CLKS : std_logic_vector(24 downto 0) := "0010000000000000000000000";
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constant BETWEEN_GTXTEST_PULSES : std_logic_vector(24 downto 0) := "0100000000000000000000000";
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constant GTXTEST_PULSE_2 : std_logic_vector(24 downto 0) := "1000000000000000000000000";
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function s_idx(
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constant C_SIMULATION : integer)
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return integer is
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variable sidx_out : integer := 8;
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begin -- s_idx
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if (C_SIMULATION /= 0) then
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sidx_out := 0;
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else
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sidx_out := 2;
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end if;
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return sidx_out;
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end s_idx;
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function pma_idx(
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constant C_SIMULATION : integer)
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return integer is
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variable pma_idx_out : integer := 8;
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begin -- pma_idx
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if (C_SIMULATION /= 0) then
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pma_idx_out := 0;
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else
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pma_idx_out := 7;
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end if;
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return pma_idx_out;
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end pma_idx;
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constant SYNC_IDX : integer := s_idx(C_SIMULATION);
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constant PMARESET_IDX : integer := pma_idx(C_SIMULATION);
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signal ENPMAPHASEALIGN_c : std_logic;
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signal PMASETPHASE_c : std_logic;
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signal SYNC_DONE_c : std_logic;
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signal OUT_DIV_RESET_c : std_logic;
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signal PCS_RESET_c : std_logic;
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signal USER_PHYSTATUS_c : std_logic;
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signal DELAYALIGNRESET_c : std_logic;
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signal TXALIGNDISABLE_c : std_logic;
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signal state : std_logic_vector(24 downto 0);
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signal nextstate : std_logic_vector(24 downto 0);
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signal wait_amt : std_logic_vector(15 downto 0);
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signal wait_c : std_logic_vector(15 downto 0);
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signal waitcounter : std_logic_vector(7 downto 0);
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signal nextwaitcounter : std_logic_vector(7 downto 0);
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signal waitcounter2 : std_logic_vector(7 downto 0);
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signal waitcounter2_check : std_logic_vector(7 downto 0);
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signal nextwaitcounter2 : std_logic_vector(7 downto 0);
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signal ratedone_r : std_logic;
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signal ratedone_r2 : std_logic;
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signal ratedone_pulse_i : std_logic;
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signal gt_phystatus_q : std_logic;
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-- Declare intermediate signals for referenced outputs
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signal state_v6pcie0 : std_logic_vector(4 downto 0);
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-- signal waitcounter_v6pcie1 : std_logic_vector(16 downto 0);
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begin
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-- Drive referenced outputs
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-- state <= state_v6pcie0;
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-- waitcounter <= waitcounter_v6pcie1;
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process (USER_CLK)
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begin
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if (USER_CLK'event and USER_CLK = '1') then
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if (RESET = '1') then
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state <= RESET_STATE after (TCQ)*1 ps;
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waitcounter <= X"00" after (TCQ)*1 ps;
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waitcounter2 <= X"00" after (TCQ)*1 ps;
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USER_PHYSTATUS <= GT_PHYSTATUS after (TCQ)*1 ps;
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SYNC_DONE <= '0' after (TCQ)*1 ps;
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ENPMAPHASEALIGN <= '0' after (TCQ)*1 ps;
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PMASETPHASE <= '0' after (TCQ)*1 ps;
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OUT_DIV_RESET <= '0' after (TCQ)*1 ps;
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PCS_RESET <= '0' after (TCQ)*1 ps;
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DELAYALIGNRESET <= '0' after (TCQ)*1 ps;
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TXALIGNDISABLE <= '1' after (TCQ)*1 ps;
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else
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state <= nextstate after (TCQ)*1 ps;
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waitcounter <= nextwaitcounter after (TCQ)*1 ps;
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waitcounter2 <= nextwaitcounter2 after (TCQ)*1 ps;
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USER_PHYSTATUS <= USER_PHYSTATUS_c after (TCQ)*1 ps;
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SYNC_DONE <= SYNC_DONE_c after (TCQ)*1 ps;
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ENPMAPHASEALIGN <= ENPMAPHASEALIGN_c after (TCQ)*1 ps;
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PMASETPHASE <= PMASETPHASE_c after (TCQ)*1 ps;
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OUT_DIV_RESET <= OUT_DIV_RESET_c after (TCQ)*1 ps;
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PCS_RESET <= PCS_RESET_c after (TCQ)*1 ps;
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DELAYALIGNRESET <= DELAYALIGNRESET_c after (TCQ)*1 ps;
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TXALIGNDISABLE <= TXALIGNDISABLE_c after (TCQ)*1 ps;
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end if;
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end if;
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end process;
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waitcounter2_check <= waitcounter2 + X"01" when (waitcounter = X"FF") else
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waitcounter2;
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process (state, GT_PHYSTATUS, waitcounter, waitcounter2, waitcounter2_check, ratedone_pulse_i, gt_phystatus_q, RESETDONE)
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begin
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-- DEFAULT CONDITIONS
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DELAYALIGNRESET_c <= '0';
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SYNC_DONE_c <= '0';
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ENPMAPHASEALIGN_c <= '1';
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PMASETPHASE_c <= '0';
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OUT_DIV_RESET_c <= '0';
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PCS_RESET_c <= '0';
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TXALIGNDISABLE_c <= '0';
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nextstate <= state;
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USER_PHYSTATUS_c <= GT_PHYSTATUS;
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nextwaitcounter <= waitcounter + X"01";
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nextwaitcounter2 <= waitcounter2_check;
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case state is
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-- START IN RESET
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when RESET_STATE =>
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TXALIGNDISABLE_c <= '1';
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ENPMAPHASEALIGN_c <= '0';
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nextstate <= BEFORE_GTXTEST_PULSE1_1024CLKS;
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nextwaitcounter <= X"00";
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nextwaitcounter2 <= X"00";
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-- Wait 1024 clocks before asseting GTXTEST[1] - Figure 3-9 UG366
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when BEFORE_GTXTEST_PULSE1_1024CLKS =>
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OUT_DIV_RESET_c <= '0';
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TXALIGNDISABLE_c <= '1';
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ENPMAPHASEALIGN_c <= '0';
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if ((waitcounter2(1)) = '1') then
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nextstate <= GTXTEST_PULSE_1;
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nextwaitcounter <= X"00";
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nextwaitcounter2 <= X"00";
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end if;
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-- Assert GTXTEST[1] for 256 clocks - Figure 3-9 UG366
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when GTXTEST_PULSE_1 =>
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OUT_DIV_RESET_c <= '1';
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TXALIGNDISABLE_c <= '1';
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ENPMAPHASEALIGN_c <= '0';
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if ((waitcounter(7)) = '1') then
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nextstate <= BETWEEN_GTXTEST_PULSES;
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nextwaitcounter <= X"00";
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nextwaitcounter2 <= X"00";
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end if;
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-- De-assert GTXTEST[1] for 256 clocks - Figure 3-9 UG366
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when BETWEEN_GTXTEST_PULSES =>
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OUT_DIV_RESET_c <= '0';
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TXALIGNDISABLE_c <= '1';
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ENPMAPHASEALIGN_c <= '0';
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if ((waitcounter(7)) = '1') then
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nextstate <= GTXTEST_PULSE_2;
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nextwaitcounter <= X"00";
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nextwaitcounter2 <= X"00";
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end if;
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-- Assert GTXTEST[1] for 256 clocks - Figure 3-9 UG366
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when GTXTEST_PULSE_2 =>
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OUT_DIV_RESET_c <= '1';
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TXALIGNDISABLE_c <= '1';
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ENPMAPHASEALIGN_c <= '0';
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if ((waitcounter(7)) = '1') then
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nextstate <= DELAYALIGNRST;
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nextwaitcounter <= X"00";
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nextwaitcounter2 <= X"00";
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end if;
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-- ASSERT TXDLYALIGNRESET FOR 16 CLOCK CYCLES
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when DELAYALIGNRST =>
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DELAYALIGNRESET_c <= '1';
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ENPMAPHASEALIGN_c <= '0';
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TXALIGNDISABLE_c <= '1';
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if ((waitcounter(4)) = '1') then
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nextstate <= SETENPMAPHASEALIGN;
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nextwaitcounter <= X"00";
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nextwaitcounter2 <= X"00";
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end if;
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-- ASSERT ENPMAPHASEALIGN FOR 32 CLOCK CYCLES
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when SETENPMAPHASEALIGN =>
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TXALIGNDISABLE_c <= '1';
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if ((waitcounter(5)) = '1') then
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nextstate <= PHASEALIGN;
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nextwaitcounter <= X"00";
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nextwaitcounter2 <= X"00";
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end if;
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321 |
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|
-- ASSERT PMASETPHASE OUT OF RESET for 32K CYCLES
|
323 |
|
|
when PHASEALIGN =>
|
324 |
|
|
PMASETPHASE_c <= '1';
|
325 |
|
|
TXALIGNDISABLE_c <= '1';
|
326 |
|
|
if ((waitcounter2(PMARESET_IDX)) = '1') then
|
327 |
|
|
nextstate <= TXALIGNDISABLEDEASSERT;
|
328 |
|
|
nextwaitcounter <= X"00";
|
329 |
|
|
nextwaitcounter2 <= X"00";
|
330 |
|
|
end if;
|
331 |
|
|
|
332 |
|
|
-- KEEP TXALIGNDISABLE ASSERTED for 64 CYCLES
|
333 |
|
|
when TXALIGNDISABLEDEASSERT =>
|
334 |
|
|
TXALIGNDISABLE_c <= '1';
|
335 |
|
|
if ((waitcounter(6)) = '1') then
|
336 |
|
|
nextwaitcounter <= X"00";
|
337 |
|
|
nextstate <= IDLE;
|
338 |
|
|
nextwaitcounter2 <= X"00";
|
339 |
|
|
end if;
|
340 |
|
|
|
341 |
|
|
-- NOW IN IDLE, ASSERT SYNC DONE, WAIT FOR RATECHANGE
|
342 |
|
|
when IDLE =>
|
343 |
|
|
SYNC_DONE_c <= '1';
|
344 |
|
|
if (ratedone_pulse_i = '1') then
|
345 |
|
|
USER_PHYSTATUS_c <= '0';
|
346 |
|
|
nextstate <= WAIT_PHYSTATUS;
|
347 |
|
|
nextwaitcounter <= X"00";
|
348 |
|
|
nextwaitcounter2 <= X"00";
|
349 |
|
|
end if;
|
350 |
|
|
|
351 |
|
|
-- WAIT FOR PHYSTATUS
|
352 |
|
|
when WAIT_PHYSTATUS =>
|
353 |
|
|
USER_PHYSTATUS_c <= '0';
|
354 |
|
|
if (gt_phystatus_q = '1') then
|
355 |
|
|
nextstate <= RATECHANGE_IDLE;
|
356 |
|
|
nextwaitcounter <= X"00";
|
357 |
|
|
nextwaitcounter2 <= X"00";
|
358 |
|
|
end if;
|
359 |
|
|
|
360 |
|
|
-- WAIT 64 CYCLES BEFORE WE START THE RATE CHANGE
|
361 |
|
|
when RATECHANGE_IDLE =>
|
362 |
|
|
USER_PHYSTATUS_c <= '0';
|
363 |
|
|
if ((waitcounter(6)) = '1') then
|
364 |
|
|
nextstate <= RATECHANGE_TXDLYALIGNDISABLE;
|
365 |
|
|
nextwaitcounter <= X"00";
|
366 |
|
|
nextwaitcounter2 <= X"00";
|
367 |
|
|
end if;
|
368 |
|
|
|
369 |
|
|
-- ASSERT TXALIGNDISABLE FOR 32 CYCLES
|
370 |
|
|
when RATECHANGE_TXDLYALIGNDISABLE =>
|
371 |
|
|
USER_PHYSTATUS_c <= '0';
|
372 |
|
|
TXALIGNDISABLE_c <= '1';
|
373 |
|
|
if ((waitcounter(5)) = '1') then
|
374 |
|
|
nextstate <= RATECHANGE_DIVRESET;
|
375 |
|
|
nextwaitcounter <= X"00";
|
376 |
|
|
nextwaitcounter2 <= X"00";
|
377 |
|
|
end if;
|
378 |
|
|
|
379 |
|
|
-- ASSERT DIV RESET FOR 16 CLOCK CYCLES
|
380 |
|
|
when RATECHANGE_DIVRESET =>
|
381 |
|
|
OUT_DIV_RESET_c <= '1';
|
382 |
|
|
USER_PHYSTATUS_c <= '0';
|
383 |
|
|
TXALIGNDISABLE_c <= '1';
|
384 |
|
|
if ((waitcounter(4)) = '1') then
|
385 |
|
|
nextstate <= RATECHANGE_DIVRESET_POST;
|
386 |
|
|
nextwaitcounter <= X"00";
|
387 |
|
|
nextwaitcounter2 <= X"00";
|
388 |
|
|
end if;
|
389 |
|
|
|
390 |
|
|
-- WAIT FOR 32 CLOCK CYCLES BEFORE NEXT STEP
|
391 |
|
|
when RATECHANGE_DIVRESET_POST =>
|
392 |
|
|
USER_PHYSTATUS_c <= '0';
|
393 |
|
|
TXALIGNDISABLE_c <= '1';
|
394 |
|
|
if ((waitcounter(5)) = '1') then
|
395 |
|
|
nextstate <= RATECHANGE_PMARESET;
|
396 |
|
|
nextwaitcounter <= X"00";
|
397 |
|
|
nextwaitcounter2 <= X"00";
|
398 |
|
|
end if;
|
399 |
|
|
|
400 |
|
|
-- ASSERT PMA RESET FOR 32K CYCLES
|
401 |
|
|
when RATECHANGE_PMARESET =>
|
402 |
|
|
PMASETPHASE_c <= '1';
|
403 |
|
|
USER_PHYSTATUS_c <= '0';
|
404 |
|
|
TXALIGNDISABLE_c <= '1';
|
405 |
|
|
if ((waitcounter2(PMARESET_IDX)) = '1') then
|
406 |
|
|
nextstate <= RATECHANGE_PMARESET_POST;
|
407 |
|
|
nextwaitcounter <= X"00";
|
408 |
|
|
nextwaitcounter2 <= X"00";
|
409 |
|
|
end if;
|
410 |
|
|
|
411 |
|
|
-- WAIT FOR 32 CYCLES BEFORE DISABLING TXALIGNDISABLE
|
412 |
|
|
when RATECHANGE_PMARESET_POST =>
|
413 |
|
|
USER_PHYSTATUS_c <= '0';
|
414 |
|
|
TXALIGNDISABLE_c <= '1';
|
415 |
|
|
if ((waitcounter(5)) = '1') then
|
416 |
|
|
nextstate <= RATECHANGE_DISABLE_TXALIGNDISABLE;
|
417 |
|
|
nextwaitcounter <= X"00";
|
418 |
|
|
nextwaitcounter2 <= X"00";
|
419 |
|
|
end if;
|
420 |
|
|
|
421 |
|
|
-- DISABLE TXALIGNDISABLE FOR 32 CYCLES
|
422 |
|
|
when RATECHANGE_DISABLE_TXALIGNDISABLE =>
|
423 |
|
|
USER_PHYSTATUS_c <= '0';
|
424 |
|
|
if ((waitcounter(5)) = '1') then
|
425 |
|
|
nextstate <= RATECHANGE_PCSRESET;
|
426 |
|
|
nextwaitcounter <= X"00";
|
427 |
|
|
nextwaitcounter2 <= X"00";
|
428 |
|
|
end if;
|
429 |
|
|
|
430 |
|
|
-- NOW ASSERT PCS RESET FOR 32 CYCLES
|
431 |
|
|
when RATECHANGE_PCSRESET =>
|
432 |
|
|
PCS_RESET_c <= '1';
|
433 |
|
|
USER_PHYSTATUS_c <= '0';
|
434 |
|
|
if ((waitcounter(5)) = '1') then
|
435 |
|
|
nextstate <= RATECHANGE_PCSRESET_POST;
|
436 |
|
|
nextwaitcounter <= X"00";
|
437 |
|
|
nextwaitcounter2 <= X"00";
|
438 |
|
|
end if;
|
439 |
|
|
|
440 |
|
|
-- WAIT FOR RESETDONE BEFORE ASSERTING PHY_STATUS_OUT
|
441 |
|
|
when RATECHANGE_PCSRESET_POST =>
|
442 |
|
|
USER_PHYSTATUS_c <= '0';
|
443 |
|
|
if (RESETDONE = '1') then
|
444 |
|
|
nextstate <= RATECHANGE_ASSERTPHY;
|
445 |
|
|
end if;
|
446 |
|
|
|
447 |
|
|
-- ASSERT PHYSTATUSOUT MEANING RATECHANGE IS DONE AND GO BACK TO IDLE
|
448 |
|
|
when RATECHANGE_ASSERTPHY =>
|
449 |
|
|
USER_PHYSTATUS_c <= '1';
|
450 |
|
|
nextstate <= IDLE;
|
451 |
|
|
|
452 |
|
|
when others =>
|
453 |
|
|
nextstate <= IDLE;
|
454 |
|
|
|
455 |
|
|
end case;
|
456 |
|
|
end process;
|
457 |
|
|
|
458 |
|
|
|
459 |
|
|
-- Generate Ratechange Pulse
|
460 |
|
|
|
461 |
|
|
process (USER_CLK)
|
462 |
|
|
begin
|
463 |
|
|
if (USER_CLK'event and USER_CLK = '1') then
|
464 |
|
|
|
465 |
|
|
if (RESET = '1') then
|
466 |
|
|
|
467 |
|
|
ratedone_r <= '0' after (TCQ)*1 ps;
|
468 |
|
|
ratedone_r2 <= '0' after (TCQ)*1 ps;
|
469 |
|
|
gt_phystatus_q <= '0' after (TCQ)*1 ps;
|
470 |
|
|
|
471 |
|
|
else
|
472 |
|
|
|
473 |
|
|
ratedone_r <= RATE after (TCQ)*1 ps;
|
474 |
|
|
ratedone_r2 <= ratedone_r after (TCQ)*1 ps;
|
475 |
|
|
gt_phystatus_q <= GT_PHYSTATUS after (TCQ)*1 ps;
|
476 |
|
|
|
477 |
|
|
end if;
|
478 |
|
|
|
479 |
|
|
end if;
|
480 |
|
|
end process;
|
481 |
|
|
|
482 |
|
|
|
483 |
|
|
ratedone_pulse_i <= to_stdlogic((ratedone_r /= ratedone_r2));
|
484 |
|
|
|
485 |
|
|
end v6_pcie;
|
486 |
|
|
|
487 |
|
|
|