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URL https://opencores.org/ocsvn/pcie_ds_dma/pcie_ds_dma/trunk

Subversion Repositories pcie_ds_dma

[/] [pcie_ds_dma/] [trunk/] [core/] [ds_dma64/] [pcie_src/] [pcie_core64_m1/] [source_virtex6/] [pcie_2_0_v6.vhd] - Blame information for rev 2

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-------------------------------------------------------------------------------
2
--
3
-- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
4
--
5
-- This file contains confidential and proprietary information
6
-- of Xilinx, Inc. and is protected under U.S. and
7
-- international copyright and other intellectual property
8
-- laws.
9
--
10
-- DISCLAIMER
11
-- This disclaimer is not a license and does not grant any
12
-- rights to the materials distributed herewith. Except as
13
-- otherwise provided in a valid license issued to you by
14
-- Xilinx, and to the maximum extent permitted by applicable
15
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
16
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
17
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
18
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
19
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
20
-- (2) Xilinx shall not be liable (whether in contract or tort,
21
-- including negligence, or under any other theory of
22
-- liability) for any loss or damage of any kind or nature
23
-- related to, arising under or in connection with these
24
-- materials, including for any direct, or any indirect,
25
-- special, incidental, or consequential loss or damage
26
-- (including loss of data, profits, goodwill, or any type of
27
-- loss or damage suffered as a result of any action brought
28
-- by a third party) even if such damage or loss was
29
-- reasonably foreseeable or Xilinx had been advised of the
30
-- possibility of the same.
31
--
32
-- CRITICAL APPLICATIONS
33
-- Xilinx products are not designed or intended to be fail-
34
-- safe, or for use in any application requiring fail-safe
35
-- performance, such as life-support or safety devices or
36
-- systems, Class III medical devices, nuclear facilities,
37
-- applications related to the deployment of airbags, or any
38
-- other applications that could lead to death, personal
39
-- injury, or severe property or environmental damage
40
-- (individually and collectively, "Critical
41
-- Applications"). Customer assumes the sole risk and
42
-- liability of any use of Xilinx products in Critical
43
-- Applications, subject only to applicable laws and
44
-- regulations governing limitations on product liability.
45
--
46
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
47
-- PART OF THIS FILE AT ALL TIMES.
48
--
49
-------------------------------------------------------------------------------
50
-- Project    : Virtex-6 Integrated Block for PCI Express
51
-- File       : pcie_2_0_v6.vhd
52
-- Version    : 2.3
53
-- Description: Solution wrapper for Virtex6 Hard Block for PCI Express
54
--             
55
--            
56
--
57
--------------------------------------------------------------------------------
58
 
59
library ieee;
60
   use ieee.std_logic_1164.all;
61
   use ieee.std_logic_unsigned.all;
62
 
63
library unisim;
64
use unisim.vcomponents.all;
65
 
66
entity pcie_2_0_v6 is
67
   generic (
68
      TCQ                                          : integer := 1;
69
      REF_CLK_FREQ                                 : integer := 0;               -- 0 - 100 MHz, 1 - 125 MHz, 2 - 250 MHz
70
      PIPE_PIPELINE_STAGES                         : integer := 0;               -- 0 - 0 stages, 1 - 1 stage, 2 - 2 stages
71
      LINK_CAP_MAX_LINK_WIDTH_int                  : integer := 8;
72
      AER_BASE_PTR                                 : bit_vector := X"128";
73
      AER_CAP_ECRC_CHECK_CAPABLE                   : boolean := FALSE;
74
      AER_CAP_ECRC_GEN_CAPABLE                     : boolean := FALSE;
75
      AER_CAP_ID                                   : bit_vector := X"0001";
76
      AER_CAP_INT_MSG_NUM_MSI                      : bit_vector := X"0A";
77
      AER_CAP_INT_MSG_NUM_MSIX                     : bit_vector := X"15";
78
      AER_CAP_NEXTPTR                              : bit_vector := X"160";
79
      AER_CAP_ON                                   : boolean := FALSE;
80
      AER_CAP_PERMIT_ROOTERR_UPDATE                : boolean := TRUE;
81
      AER_CAP_VERSION                              : bit_vector := X"1";
82
      ALLOW_X8_GEN2                                : boolean := FALSE;
83
      BAR0                                         : bit_vector := X"FFFFFF00";
84
      BAR1                                         : bit_vector := X"FFFF0000";
85
      BAR2                                         : bit_vector := X"FFFF000C";
86
      BAR3                                         : bit_vector := X"FFFFFFFF";
87
      BAR4                                         : bit_vector := X"00000000";
88
      BAR5                                         : bit_vector := X"00000000";
89
      CAPABILITIES_PTR                             : bit_vector := X"40";
90
      CARDBUS_CIS_POINTER                          : bit_vector := X"00000000";
91
      CLASS_CODE                                   : bit_vector := X"000000";
92
      CMD_INTX_IMPLEMENTED                         : boolean := TRUE;
93
      CPL_TIMEOUT_DISABLE_SUPPORTED                : boolean := FALSE;
94
      CPL_TIMEOUT_RANGES_SUPPORTED                 : bit_vector := X"0";
95
      CRM_MODULE_RSTS                              : bit_vector := X"00";
96
      DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE          : boolean := TRUE;
97
      DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE          : boolean := TRUE;
98
      DEV_CAP_ENDPOINT_L0S_LATENCY                 : integer := 0;
99
      DEV_CAP_ENDPOINT_L1_LATENCY                  : integer := 0;
100
      DEV_CAP_EXT_TAG_SUPPORTED                    : boolean := TRUE;
101
      DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE         : boolean := FALSE;
102
      DEV_CAP_MAX_PAYLOAD_SUPPORTED                : integer := 2;
103
      DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT            : integer := 0;
104
      DEV_CAP_ROLE_BASED_ERROR                     : boolean := TRUE;
105
      DEV_CAP_RSVD_14_12                           : integer := 0;
106
      DEV_CAP_RSVD_17_16                           : integer := 0;
107
      DEV_CAP_RSVD_31_29                           : integer := 0;
108
      DEV_CONTROL_AUX_POWER_SUPPORTED              : boolean := FALSE;
109
      DEVICE_ID                                    : bit_vector := X"0007";
110
      DISABLE_ASPM_L1_TIMER                        : boolean := FALSE;
111
      DISABLE_BAR_FILTERING                        : boolean := FALSE;
112
      DISABLE_ID_CHECK                             : boolean := FALSE;
113
      DISABLE_LANE_REVERSAL                        : boolean := FALSE;
114
      DISABLE_RX_TC_FILTER                         : boolean := FALSE;
115
      DISABLE_SCRAMBLING                           : boolean := FALSE;
116
      DNSTREAM_LINK_NUM                            : bit_vector := X"00";
117
      DSN_BASE_PTR                                 : bit_vector := X"100";
118
      DSN_CAP_ID                                   : bit_vector := X"0003";
119
      DSN_CAP_NEXTPTR                              : bit_vector := X"000";
120
      DSN_CAP_ON                                   : boolean := TRUE;
121
      DSN_CAP_VERSION                              : bit_vector := X"1";
122
      ENABLE_MSG_ROUTE                             : bit_vector := X"000";
123
      ENABLE_RX_TD_ECRC_TRIM                       : boolean := FALSE;
124
      ENTER_RVRY_EI_L0                             : boolean := TRUE;
125
      EXPANSION_ROM                                : bit_vector := X"FFFFF001";
126
      EXT_CFG_CAP_PTR                              : bit_vector := X"3F";
127
      EXT_CFG_XP_CAP_PTR                           : bit_vector := X"3FF";
128
      HEADER_TYPE                                  : bit_vector := X"00";
129
      INFER_EI                                     : bit_vector := X"00";
130
      INTERRUPT_PIN                                : bit_vector := X"01";
131
      IS_SWITCH                                    : boolean := FALSE;
132
      LAST_CONFIG_DWORD                            : bit_vector := X"042";
133
      LINK_CAP_ASPM_SUPPORT                        : integer := 1;
134
      LINK_CAP_CLOCK_POWER_MANAGEMENT              : boolean := FALSE;
135
      LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP       : boolean := FALSE;
136
      LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1        : integer := 7;
137
      LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2        : integer := 7;
138
      LINK_CAP_L0S_EXIT_LATENCY_GEN1               : integer := 7;
139
      LINK_CAP_L0S_EXIT_LATENCY_GEN2               : integer := 7;
140
      LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1         : integer := 7;
141
      LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2         : integer := 7;
142
      LINK_CAP_L1_EXIT_LATENCY_GEN1                : integer := 7;
143
      LINK_CAP_L1_EXIT_LATENCY_GEN2                : integer := 7;
144
      LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP     : boolean := FALSE;
145
      LINK_CAP_MAX_LINK_SPEED                      : bit_vector := X"1";
146
      LINK_CAP_MAX_LINK_WIDTH                      : bit_vector := X"08";
147
      LINK_CAP_RSVD_23_22                          : integer := 0;
148
      LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE         : boolean := FALSE;
149
      LINK_CONTROL_RCB                             : integer := 0;
150
      LINK_CTRL2_DEEMPHASIS                        : boolean := FALSE;
151
      LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE       : boolean := FALSE;
152
      LINK_CTRL2_TARGET_LINK_SPEED                 : bit_vector := X"2";
153
      LINK_STATUS_SLOT_CLOCK_CONFIG                : boolean := TRUE;
154
      LL_ACK_TIMEOUT                               : bit_vector := X"0000";
155
      LL_ACK_TIMEOUT_EN                            : boolean := FALSE;
156
      LL_ACK_TIMEOUT_FUNC                          : integer := 0;
157
      LL_REPLAY_TIMEOUT                            : bit_vector := X"0000";
158
      LL_REPLAY_TIMEOUT_EN                         : boolean := FALSE;
159
      LL_REPLAY_TIMEOUT_FUNC                       : integer := 0;
160
      LTSSM_MAX_LINK_WIDTH                         : bit_vector := X"01";
161
      MSI_BASE_PTR                                 : bit_vector := X"48";
162
      MSI_CAP_ID                                   : bit_vector := X"05";
163
      MSI_CAP_MULTIMSGCAP                          : integer := 0;
164
      MSI_CAP_MULTIMSG_EXTENSION                   : integer := 0;
165
      MSI_CAP_NEXTPTR                              : bit_vector := X"60";
166
      MSI_CAP_ON                                   : boolean := FALSE;
167
      MSI_CAP_PER_VECTOR_MASKING_CAPABLE           : boolean := TRUE;
168
      MSI_CAP_64_BIT_ADDR_CAPABLE                  : boolean := TRUE;
169
      MSIX_BASE_PTR                                : bit_vector := X"9C";
170
      MSIX_CAP_ID                                  : bit_vector := X"11";
171
      MSIX_CAP_NEXTPTR                             : bit_vector := X"00";
172
      MSIX_CAP_ON                                  : boolean := FALSE;
173
      MSIX_CAP_PBA_BIR                             : integer := 0;
174
      MSIX_CAP_PBA_OFFSET                          : bit_vector := X"00000050";
175
      MSIX_CAP_TABLE_BIR                           : integer := 0;
176
      MSIX_CAP_TABLE_OFFSET                        : bit_vector := X"00000040";
177
      MSIX_CAP_TABLE_SIZE                          : bit_vector := X"000";
178
      N_FTS_COMCLK_GEN1                            : integer := 255;
179
      N_FTS_COMCLK_GEN2                            : integer := 255;
180
      N_FTS_GEN1                                   : integer := 255;
181
      N_FTS_GEN2                                   : integer := 255;
182
      PCIE_BASE_PTR                                : bit_vector := X"60";
183
      PCIE_CAP_CAPABILITY_ID                       : bit_vector := X"10";
184
      PCIE_CAP_CAPABILITY_VERSION                  : bit_vector := X"2";
185
      PCIE_CAP_DEVICE_PORT_TYPE                    : bit_vector := X"0";
186
      PCIE_CAP_INT_MSG_NUM                         : bit_vector := X"00";
187
      PCIE_CAP_NEXTPTR                             : bit_vector := X"00";
188
      PCIE_CAP_ON                                  : boolean := TRUE;
189
      PCIE_CAP_RSVD_15_14                          : integer := 0;
190
      PCIE_CAP_SLOT_IMPLEMENTED                    : boolean := FALSE;
191
      PCIE_REVISION                                : integer := 2;
192
      PGL0_LANE                                    : integer := 0;
193
      PGL1_LANE                                    : integer := 1;
194
      PGL2_LANE                                    : integer := 2;
195
      PGL3_LANE                                    : integer := 3;
196
      PGL4_LANE                                    : integer := 4;
197
      PGL5_LANE                                    : integer := 5;
198
      PGL6_LANE                                    : integer := 6;
199
      PGL7_LANE                                    : integer := 7;
200
      PL_AUTO_CONFIG                               : integer := 0;
201
      PL_FAST_TRAIN                                : boolean := FALSE;
202
      PM_BASE_PTR                                  : bit_vector := X"40";
203
      PM_CAP_AUXCURRENT                            : integer := 0;
204
      PM_CAP_DSI                                   : boolean := FALSE;
205
      PM_CAP_D1SUPPORT                             : boolean := TRUE;
206
      PM_CAP_D2SUPPORT                             : boolean := TRUE;
207
      PM_CAP_ID                                    : bit_vector := X"11";
208
      PM_CAP_NEXTPTR                               : bit_vector := X"48";
209
      PM_CAP_ON                                    : boolean := TRUE;
210
      PM_CAP_PME_CLOCK                             : boolean := FALSE;
211
      PM_CAP_PMESUPPORT                            : bit_vector := X"0F";
212
      PM_CAP_RSVD_04                               : integer := 0;
213
      PM_CAP_VERSION                               : integer := 3;
214
      PM_CSR_BPCCEN                                : boolean := FALSE;
215
      PM_CSR_B2B3                                  : boolean := FALSE;
216
      PM_CSR_NOSOFTRST                             : boolean := TRUE;
217
      PM_DATA0                                     : bit_vector := X"01";
218
      PM_DATA1                                     : bit_vector := X"01";
219
      PM_DATA2                                     : bit_vector := X"01";
220
      PM_DATA3                                     : bit_vector := X"01";
221
      PM_DATA4                                     : bit_vector := X"01";
222
      PM_DATA5                                     : bit_vector := X"01";
223
      PM_DATA6                                     : bit_vector := X"01";
224
      PM_DATA7                                     : bit_vector := X"01";
225
      PM_DATA_SCALE0                               : bit_vector := X"1";
226
      PM_DATA_SCALE1                               : bit_vector := X"1";
227
      PM_DATA_SCALE2                               : bit_vector := X"1";
228
      PM_DATA_SCALE3                               : bit_vector := X"1";
229
      PM_DATA_SCALE4                               : bit_vector := X"1";
230
      PM_DATA_SCALE5                               : bit_vector := X"1";
231
      PM_DATA_SCALE6                               : bit_vector := X"1";
232
      PM_DATA_SCALE7                               : bit_vector := X"1";
233
      RECRC_CHK                                    : integer := 0;
234
      RECRC_CHK_TRIM                               : boolean := FALSE;
235
      REVISION_ID                                  : bit_vector := X"00";
236
      ROOT_CAP_CRS_SW_VISIBILITY                   : boolean := FALSE;
237
      SELECT_DLL_IF                                : boolean := FALSE;
238
      SLOT_CAP_ATT_BUTTON_PRESENT                  : boolean := FALSE;
239
      SLOT_CAP_ATT_INDICATOR_PRESENT               : boolean := FALSE;
240
      SLOT_CAP_ELEC_INTERLOCK_PRESENT              : boolean := FALSE;
241
      SLOT_CAP_HOTPLUG_CAPABLE                     : boolean := FALSE;
242
      SLOT_CAP_HOTPLUG_SURPRISE                    : boolean := FALSE;
243
      SLOT_CAP_MRL_SENSOR_PRESENT                  : boolean := FALSE;
244
      SLOT_CAP_NO_CMD_COMPLETED_SUPPORT            : boolean := FALSE;
245
      SLOT_CAP_PHYSICAL_SLOT_NUM                   : bit_vector := X"0000";
246
      SLOT_CAP_POWER_CONTROLLER_PRESENT            : boolean := FALSE;
247
      SLOT_CAP_POWER_INDICATOR_PRESENT             : boolean := FALSE;
248
      SLOT_CAP_SLOT_POWER_LIMIT_SCALE              : integer := 0;
249
      SLOT_CAP_SLOT_POWER_LIMIT_VALUE              : bit_vector := X"00";
250
      SPARE_BIT0                                   : integer := 0;
251
      SPARE_BIT1                                   : integer := 0;
252
      SPARE_BIT2                                   : integer := 0;
253
      SPARE_BIT3                                   : integer := 0;
254
      SPARE_BIT4                                   : integer := 0;
255
      SPARE_BIT5                                   : integer := 0;
256
      SPARE_BIT6                                   : integer := 0;
257
      SPARE_BIT7                                   : integer := 0;
258
      SPARE_BIT8                                   : integer := 0;
259
      SPARE_BYTE0                                  : bit_vector := X"00";
260
      SPARE_BYTE1                                  : bit_vector := X"00";
261
      SPARE_BYTE2                                  : bit_vector := X"00";
262
      SPARE_BYTE3                                  : bit_vector := X"00";
263
      SPARE_WORD0                                  : bit_vector := X"00000000";
264
      SPARE_WORD1                                  : bit_vector := X"00000000";
265
      SPARE_WORD2                                  : bit_vector := X"00000000";
266
      SPARE_WORD3                                  : bit_vector := X"00000000";
267
      SUBSYSTEM_ID                                 : bit_vector := X"0007";
268
      SUBSYSTEM_VENDOR_ID                          : bit_vector := X"10EE";
269
      TL_RBYPASS                                   : boolean := FALSE;
270
      TL_RX_RAM_RADDR_LATENCY                      : integer := 0;
271
      TL_RX_RAM_RDATA_LATENCY                      : integer := 2;
272
      TL_RX_RAM_WRITE_LATENCY                      : integer := 0;
273
      TL_TFC_DISABLE                               : boolean := FALSE;
274
      TL_TX_CHECKS_DISABLE                         : boolean := FALSE;
275
      TL_TX_RAM_RADDR_LATENCY                      : integer := 0;
276
      TL_TX_RAM_RDATA_LATENCY                      : integer := 2;
277
      TL_TX_RAM_WRITE_LATENCY                      : integer := 0;
278
      UPCONFIG_CAPABLE                             : boolean := TRUE;
279
      UPSTREAM_FACING                              : boolean := TRUE;
280
      UR_INV_REQ                                   : boolean := TRUE;
281
      USER_CLK_FREQ                                : integer := 3;
282
      EXIT_LOOPBACK_ON_EI                          : boolean := TRUE;
283
      VC_BASE_PTR                                  : bit_vector := X"10C";
284
      VC_CAP_ID                                    : bit_vector := X"0002";
285
      VC_CAP_NEXTPTR                               : bit_vector := X"000";
286
      VC_CAP_ON                                    : boolean := FALSE;
287
      VC_CAP_REJECT_SNOOP_TRANSACTIONS             : boolean := FALSE;
288
      VC_CAP_VERSION                               : bit_vector := X"1";
289
      VC0_CPL_INFINITE                             : boolean := TRUE;
290
      VC0_RX_RAM_LIMIT                             : bit_vector := X"03FF";
291
      VC0_TOTAL_CREDITS_CD                         : integer := 127;
292
      VC0_TOTAL_CREDITS_CH                         : integer := 31;
293
      VC0_TOTAL_CREDITS_NPH                        : integer := 12;
294
      VC0_TOTAL_CREDITS_PD                         : integer := 288;
295
      VC0_TOTAL_CREDITS_PH                         : integer := 32;
296
      VC0_TX_LASTPACKET                            : integer := 31;
297
      VENDOR_ID                                    : bit_vector := X"10EE";
298
      VSEC_BASE_PTR                                : bit_vector := X"160";
299
      VSEC_CAP_HDR_ID                              : bit_vector := X"1234";
300
      VSEC_CAP_HDR_LENGTH                          : bit_vector := X"018";
301
      VSEC_CAP_HDR_REVISION                        : bit_vector := X"1";
302
      VSEC_CAP_ID                                  : bit_vector := X"000B";
303
      VSEC_CAP_IS_LINK_VISIBLE                     : boolean := TRUE;
304
      VSEC_CAP_NEXTPTR                             : bit_vector := X"000";
305
      VSEC_CAP_ON                                  : boolean := FALSE;
306
      VSEC_CAP_VERSION                             : bit_vector := X"1"
307
   );
308
   port (
309
 
310
      PCIEXPRXN                                    : in std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);
311
      PCIEXPRXP                                    : in std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);
312
      PCIEXPTXN                                    : out std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);
313
      PCIEXPTXP                                    : out std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);
314
 
315
      SYSCLK                                       : in std_logic;
316
      FUNDRSTN                                     : in std_logic;
317
 
318
      TRNLNKUPN                                    : out std_logic;
319
 
320
      PHYRDYN                                      : out std_logic;
321
      USERRSTN                                     : out std_logic;
322
      RECEIVEDFUNCLVLRSTN                          : out std_logic;
323
      LNKCLKEN                                     : out std_logic;
324
      SYSRSTN                                      : in std_logic;
325
      PLRSTN                                       : in std_logic;
326
      DLRSTN                                       : in std_logic;
327
      TLRSTN                                       : in std_logic;
328
      FUNCLVLRSTN                                  : in std_logic;
329
      CMRSTN                                       : in std_logic;
330
      CMSTICKYRSTN                                 : in std_logic;
331
 
332
      TRNRBARHITN                                  : out std_logic_vector(6 downto 0);
333
      TRNRD                                        : out std_logic_vector(63 downto 0);
334
      TRNRECRCERRN                                 : out std_logic;
335
      TRNREOFN                                     : out std_logic;
336
 
337
      TRNRERRFWDN                                  : out std_logic;
338
      TRNRREMN                                     : out std_logic;
339
      TRNRSOFN                                     : out std_logic;
340
      TRNRSRCDSCN                                  : out std_logic;
341
      TRNRSRCRDYN                                  : out std_logic;
342
      TRNRDSTRDYN                                  : in std_logic;
343
      TRNRNPOKN                                    : in std_logic;
344
 
345
      TRNRDLLPDATA                                 : out std_logic_vector(31 downto 0);
346
      TRNRDLLPSRCRDYN                              : out std_logic;
347
 
348
      TRNTBUFAV                                    : out std_logic_vector(5 downto 0);
349
      TRNTCFGREQN                                  : out std_logic;
350
 
351
      TRNTDLLPDSTRDYN                              : out std_logic;
352
      TRNTDSTRDYN                                  : out std_logic;
353
 
354
      TRNTERRDROPN                                 : out std_logic;
355
 
356
      TRNTCFGGNTN                                  : in std_logic;
357
 
358
      TRNTD                                        : in std_logic_vector(63 downto 0);
359
      TRNTDLLPDATA                                 : in std_logic_vector(31 downto 0);
360
      TRNTDLLPSRCRDYN                              : in std_logic;
361
      TRNTECRCGENN                                 : in std_logic;
362
      TRNTEOFN                                     : in std_logic;
363
 
364
      TRNTERRFWDN                                  : in std_logic;
365
      TRNTREMN                                     : in std_logic;
366
 
367
      TRNTSOFN                                     : in std_logic;
368
      TRNTSRCDSCN                                  : in std_logic;
369
      TRNTSRCRDYN                                  : in std_logic;
370
      TRNTSTRN                                     : in std_logic;
371
 
372
      TRNFCCPLD                                    : out std_logic_vector(11 downto 0);
373
      TRNFCCPLH                                    : out std_logic_vector(7 downto 0);
374
      TRNFCNPD                                     : out std_logic_vector(11 downto 0);
375
      TRNFCNPH                                     : out std_logic_vector(7 downto 0);
376
      TRNFCPD                                      : out std_logic_vector(11 downto 0);
377
      TRNFCPH                                      : out std_logic_vector(7 downto 0);
378
      TRNFCSEL                                     : in std_logic_vector(2 downto 0);
379
 
380
      CFGAERECRCCHECKEN                            : out std_logic;
381
      CFGAERECRCGENEN                              : out std_logic;
382
      CFGCOMMANDBUSMASTERENABLE                    : out std_logic;
383
      CFGCOMMANDINTERRUPTDISABLE                   : out std_logic;
384
      CFGCOMMANDIOENABLE                           : out std_logic;
385
      CFGCOMMANDMEMENABLE                          : out std_logic;
386
      CFGCOMMANDSERREN                             : out std_logic;
387
      CFGDEVCONTROLAUXPOWEREN                      : out std_logic;
388
      CFGDEVCONTROLCORRERRREPORTINGEN              : out std_logic;
389
      CFGDEVCONTROLENABLERO                        : out std_logic;
390
      CFGDEVCONTROLEXTTAGEN                        : out std_logic;
391
      CFGDEVCONTROLFATALERRREPORTINGEN             : out std_logic;
392
      CFGDEVCONTROLMAXPAYLOAD                      : out std_logic_vector(2 downto 0);
393
      CFGDEVCONTROLMAXREADREQ                      : out std_logic_vector(2 downto 0);
394
      CFGDEVCONTROLNONFATALREPORTINGEN             : out std_logic;
395
      CFGDEVCONTROLNOSNOOPEN                       : out std_logic;
396
      CFGDEVCONTROLPHANTOMEN                       : out std_logic;
397
      CFGDEVCONTROLURERRREPORTINGEN                : out std_logic;
398
      CFGDEVCONTROL2CPLTIMEOUTDIS                  : out std_logic;
399
      CFGDEVCONTROL2CPLTIMEOUTVAL                  : out std_logic_vector(3 downto 0);
400
      CFGDEVSTATUSCORRERRDETECTED                  : out std_logic;
401
      CFGDEVSTATUSFATALERRDETECTED                 : out std_logic;
402
      CFGDEVSTATUSNONFATALERRDETECTED              : out std_logic;
403
      CFGDEVSTATUSURDETECTED                       : out std_logic;
404
      CFGDO                                        : out std_logic_vector(31 downto 0);
405
      CFGERRAERHEADERLOGSETN                       : out std_logic;
406
      CFGERRCPLRDYN                                : out std_logic;
407
      CFGINTERRUPTDO                               : out std_logic_vector(7 downto 0);
408
      CFGINTERRUPTMMENABLE                         : out std_logic_vector(2 downto 0);
409
      CFGINTERRUPTMSIENABLE                        : out std_logic;
410
      CFGINTERRUPTMSIXENABLE                       : out std_logic;
411
      CFGINTERRUPTMSIXFM                           : out std_logic;
412
      CFGINTERRUPTRDYN                             : out std_logic;
413
      CFGLINKCONTROLRCB                            : out std_logic;
414
      CFGLINKCONTROLASPMCONTROL                    : out std_logic_vector(1 downto 0);
415
      CFGLINKCONTROLAUTOBANDWIDTHINTEN             : out std_logic;
416
      CFGLINKCONTROLBANDWIDTHINTEN                 : out std_logic;
417
      CFGLINKCONTROLCLOCKPMEN                      : out std_logic;
418
      CFGLINKCONTROLCOMMONCLOCK                    : out std_logic;
419
      CFGLINKCONTROLEXTENDEDSYNC                   : out std_logic;
420
      CFGLINKCONTROLHWAUTOWIDTHDIS                 : out std_logic;
421
      CFGLINKCONTROLLINKDISABLE                    : out std_logic;
422
      CFGLINKCONTROLRETRAINLINK                    : out std_logic;
423
      CFGLINKSTATUSAUTOBANDWIDTHSTATUS             : out std_logic;
424
      CFGLINKSTATUSBANDWITHSTATUS                  : out std_logic;
425
      CFGLINKSTATUSCURRENTSPEED                    : out std_logic_vector(1 downto 0);
426
      CFGLINKSTATUSDLLACTIVE                       : out std_logic;
427
      CFGLINKSTATUSLINKTRAINING                    : out std_logic;
428
      CFGLINKSTATUSNEGOTIATEDWIDTH                 : out std_logic_vector(3 downto 0);
429
      CFGMSGDATA                                   : out std_logic_vector(15 downto 0);
430
      CFGMSGRECEIVED                               : out std_logic;
431
      CFGMSGRECEIVEDASSERTINTA                     : out std_logic;
432
      CFGMSGRECEIVEDASSERTINTB                     : out std_logic;
433
      CFGMSGRECEIVEDASSERTINTC                     : out std_logic;
434
      CFGMSGRECEIVEDASSERTINTD                     : out std_logic;
435
      CFGMSGRECEIVEDDEASSERTINTA                   : out std_logic;
436
      CFGMSGRECEIVEDDEASSERTINTB                   : out std_logic;
437
      CFGMSGRECEIVEDDEASSERTINTC                   : out std_logic;
438
      CFGMSGRECEIVEDDEASSERTINTD                   : out std_logic;
439
      CFGMSGRECEIVEDERRCOR                         : out std_logic;
440
      CFGMSGRECEIVEDERRFATAL                       : out std_logic;
441
      CFGMSGRECEIVEDERRNONFATAL                    : out std_logic;
442
      CFGMSGRECEIVEDPMASNAK                        : out std_logic;
443
      CFGMSGRECEIVEDPMETO                          : out std_logic;
444
      CFGMSGRECEIVEDPMETOACK                       : out std_logic;
445
      CFGMSGRECEIVEDPMPME                          : out std_logic;
446
      CFGMSGRECEIVEDSETSLOTPOWERLIMIT              : out std_logic;
447
      CFGMSGRECEIVEDUNLOCK                         : out std_logic;
448
      CFGPCIELINKSTATE                             : out std_logic_vector(2 downto 0);
449
      CFGPMCSRPMEEN                                : out std_logic;
450
      CFGPMCSRPMESTATUS                            : out std_logic;
451
      CFGPMCSRPOWERSTATE                           : out std_logic_vector(1 downto 0);
452
      CFGPMRCVASREQL1N                             : out std_logic;
453
      CFGPMRCVENTERL1N                             : out std_logic;
454
      CFGPMRCVENTERL23N                            : out std_logic;
455
      CFGPMRCVREQACKN                              : out std_logic;
456
      CFGRDWRDONEN                                 : out std_logic;
457
      CFGSLOTCONTROLELECTROMECHILCTLPULSE          : out std_logic;
458
      CFGTRANSACTION                               : out std_logic;
459
      CFGTRANSACTIONADDR                           : out std_logic_vector(6 downto 0);
460
      CFGTRANSACTIONTYPE                           : out std_logic;
461
      CFGVCTCVCMAP                                 : out std_logic_vector(6 downto 0);
462
      CFGBYTEENN                                   : in std_logic_vector(3 downto 0);
463
      CFGDI                                        : in std_logic_vector(31 downto 0);
464
      CFGDSBUSNUMBER                               : in std_logic_vector(7 downto 0);
465
      CFGDSDEVICENUMBER                            : in std_logic_vector(4 downto 0);
466
      CFGDSFUNCTIONNUMBER                          : in std_logic_vector(2 downto 0);
467
      CFGDSN                                       : in std_logic_vector(63 downto 0);
468
      CFGDWADDR                                    : in std_logic_vector(9 downto 0);
469
      CFGERRACSN                                   : in std_logic;
470
      CFGERRAERHEADERLOG                           : in std_logic_vector(127 downto 0);
471
      CFGERRCORN                                   : in std_logic;
472
      CFGERRCPLABORTN                              : in std_logic;
473
      CFGERRCPLTIMEOUTN                            : in std_logic;
474
      CFGERRCPLUNEXPECTN                           : in std_logic;
475
      CFGERRECRCN                                  : in std_logic;
476
      CFGERRLOCKEDN                                : in std_logic;
477
      CFGERRPOSTEDN                                : in std_logic;
478
      CFGERRTLPCPLHEADER                           : in std_logic_vector(47 downto 0);
479
      CFGERRURN                                    : in std_logic;
480
      CFGINTERRUPTASSERTN                          : in std_logic;
481
      CFGINTERRUPTDI                               : in std_logic_vector(7 downto 0);
482
      CFGINTERRUPTN                                : in std_logic;
483
      CFGPMDIRECTASPML1N                           : in std_logic;
484
      CFGPMSENDPMACKN                              : in std_logic;
485
      CFGPMSENDPMETON                              : in std_logic;
486
      CFGPMSENDPMNAKN                              : in std_logic;
487
      CFGPMTURNOFFOKN                              : in std_logic;
488
      CFGPMWAKEN                                   : in std_logic;
489
      CFGPORTNUMBER                                : in std_logic_vector(7 downto 0);
490
      CFGRDENN                                     : in std_logic;
491
      CFGTRNPENDINGN                               : in std_logic;
492
      CFGWRENN                                     : in std_logic;
493
      CFGWRREADONLYN                               : in std_logic;
494
      CFGWRRW1CASRWN                               : in std_logic;
495
 
496
      PLINITIALLINKWIDTH                           : out std_logic_vector(2 downto 0);
497
      PLLANEREVERSALMODE                           : out std_logic_vector(1 downto 0);
498
      PLLINKGEN2CAP                                : out std_logic;
499
      PLLINKPARTNERGEN2SUPPORTED                   : out std_logic;
500
      PLLINKUPCFGCAP                               : out std_logic;
501
      PLLTSSMSTATE                                 : out std_logic_vector(5 downto 0);
502
      PLPHYLNKUPN                                  : out std_logic;
503
      PLRECEIVEDHOTRST                             : out std_logic;
504
      PLRXPMSTATE                                  : out std_logic_vector(1 downto 0);
505
      PLSELLNKRATE                                 : out std_logic;
506
      PLSELLNKWIDTH                                : out std_logic_vector(1 downto 0);
507
      PLTXPMSTATE                                  : out std_logic_vector(2 downto 0);
508
      PLDIRECTEDLINKAUTON                          : in std_logic;
509
      PLDIRECTEDLINKCHANGE                         : in std_logic_vector(1 downto 0);
510
      PLDIRECTEDLINKSPEED                          : in std_logic;
511
      PLDIRECTEDLINKWIDTH                          : in std_logic_vector(1 downto 0);
512
      PLDOWNSTREAMDEEMPHSOURCE                     : in std_logic;
513
      PLUPSTREAMPREFERDEEMPH                       : in std_logic;
514
      PLTRANSMITHOTRST                             : in std_logic;
515
 
516
      DBGSCLRA                                     : out std_logic;
517
      DBGSCLRB                                     : out std_logic;
518
      DBGSCLRC                                     : out std_logic;
519
      DBGSCLRD                                     : out std_logic;
520
      DBGSCLRE                                     : out std_logic;
521
      DBGSCLRF                                     : out std_logic;
522
      DBGSCLRG                                     : out std_logic;
523
      DBGSCLRH                                     : out std_logic;
524
      DBGSCLRI                                     : out std_logic;
525
      DBGSCLRJ                                     : out std_logic;
526
      DBGSCLRK                                     : out std_logic;
527
      DBGVECA                                      : out std_logic_vector(63 downto 0);
528
      DBGVECB                                      : out std_logic_vector(63 downto 0);
529
      DBGVECC                                      : out std_logic_vector(11 downto 0);
530
      PLDBGVEC                                     : out std_logic_vector(11 downto 0);
531
      DBGMODE                                      : in std_logic_vector(1 downto 0);
532
      DBGSUBMODE                                   : in std_logic;
533
      PLDBGMODE                                    : in std_logic_vector(2 downto 0);
534
      PCIEDRPDO                                    : out std_logic_vector(15 downto 0);
535
      PCIEDRPDRDY                                  : out std_logic;
536
      PCIEDRPCLK                                   : in std_logic;
537
      PCIEDRPDADDR                                 : in std_logic_vector(8 downto 0);
538
      PCIEDRPDEN                                   : in std_logic;
539
      PCIEDRPDI                                    : in std_logic_vector(15 downto 0);
540
      PCIEDRPDWE                                   : in std_logic;
541
 
542
      GTPLLLOCK                                    : out std_logic;
543
      PIPECLK                                      : in std_logic;
544
 
545
      USERCLK                                      : in std_logic;
546
      DRPCLK                                       : in std_logic;
547
      CLOCKLOCKED                                  : in std_logic;
548
 
549
      TxOutClk                                     : out std_logic
550
   );
551
end pcie_2_0_v6;
552
 
553
architecture v6_pcie of pcie_2_0_v6 is
554
 
555
   component pcie_pipe_v6
556
     generic (
557
       NO_OF_LANES             : integer;
558
       LINK_CAP_MAX_LINK_SPEED : bit_vector;
559
       PIPE_PIPELINE_STAGES    : integer);
560
     port (
561
       pipe_tx_rcvr_det_i       : in  std_logic;
562
       pipe_tx_reset_i          : in  std_logic;
563
       pipe_tx_rate_i           : in  std_logic;
564
       pipe_tx_deemph_i         : in  std_logic;
565
       pipe_tx_margin_i         : in  std_logic_vector(2 downto 0);
566
       pipe_tx_swing_i          : in  std_logic;
567
       pipe_tx_rcvr_det_o       : out std_logic;
568
       pipe_tx_reset_o          : out std_logic;
569
       pipe_tx_rate_o           : out std_logic;
570
       pipe_tx_deemph_o         : out std_logic;
571
       pipe_tx_margin_o         : out std_logic_vector(2 downto 0);
572
       pipe_tx_swing_o          : out std_logic;
573
       pipe_rx0_char_is_k_o     : out std_logic_vector(1 downto 0);
574
       pipe_rx0_data_o          : out std_logic_vector(15 downto 0);
575
       pipe_rx0_valid_o         : out std_logic;
576
       pipe_rx0_chanisaligned_o : out std_logic;
577
       pipe_rx0_status_o        : out std_logic_vector(2 downto 0);
578
       pipe_rx0_phy_status_o    : out std_logic;
579
       pipe_rx0_elec_idle_o     : out std_logic;
580
       pipe_rx0_polarity_i      : in  std_logic;
581
       pipe_tx0_compliance_i    : in  std_logic;
582
       pipe_tx0_char_is_k_i     : in  std_logic_vector(1 downto 0);
583
       pipe_tx0_data_i          : in  std_logic_vector(15 downto 0);
584
       pipe_tx0_elec_idle_i     : in  std_logic;
585
       pipe_tx0_powerdown_i     : in  std_logic_vector(1 downto 0);
586
       pipe_rx0_char_is_k_i     : in  std_logic_vector(1 downto 0);
587
       pipe_rx0_data_i          : in  std_logic_vector(15 downto 0);
588
       pipe_rx0_valid_i         : in  std_logic;
589
       pipe_rx0_chanisaligned_i : in  std_logic;
590
       pipe_rx0_status_i        : in  std_logic_vector(2 downto 0);
591
       pipe_rx0_phy_status_i    : in  std_logic;
592
       pipe_rx0_elec_idle_i     : in  std_logic;
593
       pipe_rx0_polarity_o      : out std_logic;
594
       pipe_tx0_compliance_o    : out std_logic;
595
       pipe_tx0_char_is_k_o     : out std_logic_vector(1 downto 0);
596
       pipe_tx0_data_o          : out std_logic_vector(15 downto 0);
597
       pipe_tx0_elec_idle_o     : out std_logic;
598
       pipe_tx0_powerdown_o     : out std_logic_vector(1 downto 0);
599
       pipe_rx1_char_is_k_o     : out std_logic_vector(1 downto 0);
600
       pipe_rx1_data_o          : out std_logic_vector(15 downto 0);
601
       pipe_rx1_valid_o         : out std_logic;
602
       pipe_rx1_chanisaligned_o : out std_logic;
603
       pipe_rx1_status_o        : out std_logic_vector(2 downto 0);
604
       pipe_rx1_phy_status_o    : out std_logic;
605
       pipe_rx1_elec_idle_o     : out std_logic;
606
       pipe_rx1_polarity_i      : in  std_logic;
607
       pipe_tx1_compliance_i    : in  std_logic;
608
       pipe_tx1_char_is_k_i     : in  std_logic_vector(1 downto 0);
609
       pipe_tx1_data_i          : in  std_logic_vector(15 downto 0);
610
       pipe_tx1_elec_idle_i     : in  std_logic;
611
       pipe_tx1_powerdown_i     : in  std_logic_vector(1 downto 0);
612
       pipe_rx1_char_is_k_i     : in  std_logic_vector(1 downto 0);
613
       pipe_rx1_data_i          : in  std_logic_vector(15 downto 0);
614
       pipe_rx1_valid_i         : in  std_logic;
615
       pipe_rx1_chanisaligned_i : in  std_logic;
616
       pipe_rx1_status_i        : in  std_logic_vector(2 downto 0);
617
       pipe_rx1_phy_status_i    : in  std_logic;
618
       pipe_rx1_elec_idle_i     : in  std_logic;
619
       pipe_rx1_polarity_o      : out std_logic;
620
       pipe_tx1_compliance_o    : out std_logic;
621
       pipe_tx1_char_is_k_o     : out std_logic_vector(1 downto 0);
622
       pipe_tx1_data_o          : out std_logic_vector(15 downto 0);
623
       pipe_tx1_elec_idle_o     : out std_logic;
624
       pipe_tx1_powerdown_o     : out std_logic_vector(1 downto 0);
625
       pipe_rx2_char_is_k_o     : out std_logic_vector(1 downto 0);
626
       pipe_rx2_data_o          : out std_logic_vector(15 downto 0);
627
       pipe_rx2_valid_o         : out std_logic;
628
       pipe_rx2_chanisaligned_o : out std_logic;
629
       pipe_rx2_status_o        : out std_logic_vector(2 downto 0);
630
       pipe_rx2_phy_status_o    : out std_logic;
631
       pipe_rx2_elec_idle_o     : out std_logic;
632
       pipe_rx2_polarity_i      : in  std_logic;
633
       pipe_tx2_compliance_i    : in  std_logic;
634
       pipe_tx2_char_is_k_i     : in  std_logic_vector(1 downto 0);
635
       pipe_tx2_data_i          : in  std_logic_vector(15 downto 0);
636
       pipe_tx2_elec_idle_i     : in  std_logic;
637
       pipe_tx2_powerdown_i     : in  std_logic_vector(1 downto 0);
638
       pipe_rx2_char_is_k_i     : in  std_logic_vector(1 downto 0);
639
       pipe_rx2_data_i          : in  std_logic_vector(15 downto 0);
640
       pipe_rx2_valid_i         : in  std_logic;
641
       pipe_rx2_chanisaligned_i : in  std_logic;
642
       pipe_rx2_status_i        : in  std_logic_vector(2 downto 0);
643
       pipe_rx2_phy_status_i    : in  std_logic;
644
       pipe_rx2_elec_idle_i     : in  std_logic;
645
       pipe_rx2_polarity_o      : out std_logic;
646
       pipe_tx2_compliance_o    : out std_logic;
647
       pipe_tx2_char_is_k_o     : out std_logic_vector(1 downto 0);
648
       pipe_tx2_data_o          : out std_logic_vector(15 downto 0);
649
       pipe_tx2_elec_idle_o     : out std_logic;
650
       pipe_tx2_powerdown_o     : out std_logic_vector(1 downto 0);
651
       pipe_rx3_char_is_k_o     : out std_logic_vector(1 downto 0);
652
       pipe_rx3_data_o          : out std_logic_vector(15 downto 0);
653
       pipe_rx3_valid_o         : out std_logic;
654
       pipe_rx3_chanisaligned_o : out std_logic;
655
       pipe_rx3_status_o        : out std_logic_vector(2 downto 0);
656
       pipe_rx3_phy_status_o    : out std_logic;
657
       pipe_rx3_elec_idle_o     : out std_logic;
658
       pipe_rx3_polarity_i      : in  std_logic;
659
       pipe_tx3_compliance_i    : in  std_logic;
660
       pipe_tx3_char_is_k_i     : in  std_logic_vector(1 downto 0);
661
       pipe_tx3_data_i          : in  std_logic_vector(15 downto 0);
662
       pipe_tx3_elec_idle_i     : in  std_logic;
663
       pipe_tx3_powerdown_i     : in  std_logic_vector(1 downto 0);
664
       pipe_rx3_char_is_k_i     : in  std_logic_vector(1 downto 0);
665
       pipe_rx3_data_i          : in  std_logic_vector(15 downto 0);
666
       pipe_rx3_valid_i         : in  std_logic;
667
       pipe_rx3_chanisaligned_i : in  std_logic;
668
       pipe_rx3_status_i        : in  std_logic_vector(2 downto 0);
669
       pipe_rx3_phy_status_i    : in  std_logic;
670
       pipe_rx3_elec_idle_i     : in  std_logic;
671
       pipe_rx3_polarity_o      : out std_logic;
672
       pipe_tx3_compliance_o    : out std_logic;
673
       pipe_tx3_char_is_k_o     : out std_logic_vector(1 downto 0);
674
       pipe_tx3_data_o          : out std_logic_vector(15 downto 0);
675
       pipe_tx3_elec_idle_o     : out std_logic;
676
       pipe_tx3_powerdown_o     : out std_logic_vector(1 downto 0);
677
       pipe_rx4_char_is_k_o     : out std_logic_vector(1 downto 0);
678
       pipe_rx4_data_o          : out std_logic_vector(15 downto 0);
679
       pipe_rx4_valid_o         : out std_logic;
680
       pipe_rx4_chanisaligned_o : out std_logic;
681
       pipe_rx4_status_o        : out std_logic_vector(2 downto 0);
682
       pipe_rx4_phy_status_o    : out std_logic;
683
       pipe_rx4_elec_idle_o     : out std_logic;
684
       pipe_rx4_polarity_i      : in  std_logic;
685
       pipe_tx4_compliance_i    : in  std_logic;
686
       pipe_tx4_char_is_k_i     : in  std_logic_vector(1 downto 0);
687
       pipe_tx4_data_i          : in  std_logic_vector(15 downto 0);
688
       pipe_tx4_elec_idle_i     : in  std_logic;
689
       pipe_tx4_powerdown_i     : in  std_logic_vector(1 downto 0);
690
       pipe_rx4_char_is_k_i     : in  std_logic_vector(1 downto 0);
691
       pipe_rx4_data_i          : in  std_logic_vector(15 downto 0);
692
       pipe_rx4_valid_i         : in  std_logic;
693
       pipe_rx4_chanisaligned_i : in  std_logic;
694
       pipe_rx4_status_i        : in  std_logic_vector(2 downto 0);
695
       pipe_rx4_phy_status_i    : in  std_logic;
696
       pipe_rx4_elec_idle_i     : in  std_logic;
697
       pipe_rx4_polarity_o      : out std_logic;
698
       pipe_tx4_compliance_o    : out std_logic;
699
       pipe_tx4_char_is_k_o     : out std_logic_vector(1 downto 0);
700
       pipe_tx4_data_o          : out std_logic_vector(15 downto 0);
701
       pipe_tx4_elec_idle_o     : out std_logic;
702
       pipe_tx4_powerdown_o     : out std_logic_vector(1 downto 0);
703
       pipe_rx5_char_is_k_o     : out std_logic_vector(1 downto 0);
704
       pipe_rx5_data_o          : out std_logic_vector(15 downto 0);
705
       pipe_rx5_valid_o         : out std_logic;
706
       pipe_rx5_chanisaligned_o : out std_logic;
707
       pipe_rx5_status_o        : out std_logic_vector(2 downto 0);
708
       pipe_rx5_phy_status_o    : out std_logic;
709
       pipe_rx5_elec_idle_o     : out std_logic;
710
       pipe_rx5_polarity_i      : in  std_logic;
711
       pipe_tx5_compliance_i    : in  std_logic;
712
       pipe_tx5_char_is_k_i     : in  std_logic_vector(1 downto 0);
713
       pipe_tx5_data_i          : in  std_logic_vector(15 downto 0);
714
       pipe_tx5_elec_idle_i     : in  std_logic;
715
       pipe_tx5_powerdown_i     : in  std_logic_vector(1 downto 0);
716
       pipe_rx5_char_is_k_i     : in  std_logic_vector(1 downto 0);
717
       pipe_rx5_data_i          : in  std_logic_vector(15 downto 0);
718
       pipe_rx5_valid_i         : in  std_logic;
719
       pipe_rx5_chanisaligned_i : in  std_logic;
720
       pipe_rx5_status_i        : in  std_logic_vector(2 downto 0);
721
       pipe_rx5_phy_status_i    : in  std_logic;
722
       pipe_rx5_elec_idle_i     : in  std_logic;
723
       pipe_rx5_polarity_o      : out std_logic;
724
       pipe_tx5_compliance_o    : out std_logic;
725
       pipe_tx5_char_is_k_o     : out std_logic_vector(1 downto 0);
726
       pipe_tx5_data_o          : out std_logic_vector(15 downto 0);
727
       pipe_tx5_elec_idle_o     : out std_logic;
728
       pipe_tx5_powerdown_o     : out std_logic_vector(1 downto 0);
729
       pipe_rx6_char_is_k_o     : out std_logic_vector(1 downto 0);
730
       pipe_rx6_data_o          : out std_logic_vector(15 downto 0);
731
       pipe_rx6_valid_o         : out std_logic;
732
       pipe_rx6_chanisaligned_o : out std_logic;
733
       pipe_rx6_status_o        : out std_logic_vector(2 downto 0);
734
       pipe_rx6_phy_status_o    : out std_logic;
735
       pipe_rx6_elec_idle_o     : out std_logic;
736
       pipe_rx6_polarity_i      : in  std_logic;
737
       pipe_tx6_compliance_i    : in  std_logic;
738
       pipe_tx6_char_is_k_i     : in  std_logic_vector(1 downto 0);
739
       pipe_tx6_data_i          : in  std_logic_vector(15 downto 0);
740
       pipe_tx6_elec_idle_i     : in  std_logic;
741
       pipe_tx6_powerdown_i     : in  std_logic_vector(1 downto 0);
742
       pipe_rx6_char_is_k_i     : in  std_logic_vector(1 downto 0);
743
       pipe_rx6_data_i          : in  std_logic_vector(15 downto 0);
744
       pipe_rx6_valid_i         : in  std_logic;
745
       pipe_rx6_chanisaligned_i : in  std_logic;
746
       pipe_rx6_status_i        : in  std_logic_vector(2 downto 0);
747
       pipe_rx6_phy_status_i    : in  std_logic;
748
       pipe_rx6_elec_idle_i     : in  std_logic;
749
       pipe_rx6_polarity_o      : out std_logic;
750
       pipe_tx6_compliance_o    : out std_logic;
751
       pipe_tx6_char_is_k_o     : out std_logic_vector(1 downto 0);
752
       pipe_tx6_data_o          : out std_logic_vector(15 downto 0);
753
       pipe_tx6_elec_idle_o     : out std_logic;
754
       pipe_tx6_powerdown_o     : out std_logic_vector(1 downto 0);
755
       pipe_rx7_char_is_k_o     : out std_logic_vector(1 downto 0);
756
       pipe_rx7_data_o          : out std_logic_vector(15 downto 0);
757
       pipe_rx7_valid_o         : out std_logic;
758
       pipe_rx7_chanisaligned_o : out std_logic;
759
       pipe_rx7_status_o        : out std_logic_vector(2 downto 0);
760
       pipe_rx7_phy_status_o    : out std_logic;
761
       pipe_rx7_elec_idle_o     : out std_logic;
762
       pipe_rx7_polarity_i      : in  std_logic;
763
       pipe_tx7_compliance_i    : in  std_logic;
764
       pipe_tx7_char_is_k_i     : in  std_logic_vector(1 downto 0);
765
       pipe_tx7_data_i          : in  std_logic_vector(15 downto 0);
766
       pipe_tx7_elec_idle_i     : in  std_logic;
767
       pipe_tx7_powerdown_i     : in  std_logic_vector(1 downto 0);
768
       pipe_rx7_char_is_k_i     : in  std_logic_vector(1 downto 0);
769
       pipe_rx7_data_i          : in  std_logic_vector(15 downto 0);
770
       pipe_rx7_valid_i         : in  std_logic;
771
       pipe_rx7_chanisaligned_i : in  std_logic;
772
       pipe_rx7_status_i        : in  std_logic_vector(2 downto 0);
773
       pipe_rx7_phy_status_i    : in  std_logic;
774
       pipe_rx7_elec_idle_i     : in  std_logic;
775
       pipe_rx7_polarity_o      : out std_logic;
776
       pipe_tx7_compliance_o    : out std_logic;
777
       pipe_tx7_char_is_k_o     : out std_logic_vector(1 downto 0);
778
       pipe_tx7_data_o          : out std_logic_vector(15 downto 0);
779
       pipe_tx7_elec_idle_o     : out std_logic;
780
       pipe_tx7_powerdown_o     : out std_logic_vector(1 downto 0);
781
       pl_ltssm_state           : in  std_logic_vector(5 downto 0);
782
       pipe_clk                 : in  std_logic;
783
       rst_n                    : in  std_logic);
784
   end component;
785
 
786
   component pcie_gtx_v6
787
     generic (
788
       NO_OF_LANES             : integer;
789
       LINK_CAP_MAX_LINK_SPEED : bit_vector;
790
       REF_CLK_FREQ            : integer;
791
       PL_FAST_TRAIN           : boolean);
792
     port (
793
       pipe_tx_rcvr_det       : in  std_logic;
794
       pipe_tx_reset          : in  std_logic;
795
       pipe_tx_rate           : in  std_logic;
796
       pipe_tx_deemph         : in  std_logic;
797
       pipe_tx_margin         : in  std_logic_vector(2 downto 0);
798
       pipe_tx_swing          : in  std_logic;
799
       pipe_rx0_char_is_k     : out std_logic_vector(1 downto 0);
800
       pipe_rx0_data          : out std_logic_vector(15 downto 0);
801
       pipe_rx0_valid         : out std_logic;
802
       pipe_rx0_chanisaligned : out std_logic;
803
       pipe_rx0_status        : out std_logic_vector(2 downto 0);
804
       pipe_rx0_phy_status    : out std_logic;
805
       pipe_rx0_elec_idle     : out std_logic;
806
       pipe_rx0_polarity      : in  std_logic;
807
       pipe_tx0_compliance    : in  std_logic;
808
       pipe_tx0_char_is_k     : in  std_logic_vector(1 downto 0);
809
       pipe_tx0_data          : in  std_logic_vector(15 downto 0);
810
       pipe_tx0_elec_idle     : in  std_logic;
811
       pipe_tx0_powerdown     : in  std_logic_vector(1 downto 0);
812
       pipe_rx1_char_is_k     : out std_logic_vector(1 downto 0);
813
       pipe_rx1_data          : out std_logic_vector(15 downto 0);
814
       pipe_rx1_valid         : out std_logic;
815
       pipe_rx1_chanisaligned : out std_logic;
816
       pipe_rx1_status        : out std_logic_vector(2 downto 0);
817
       pipe_rx1_phy_status    : out std_logic;
818
       pipe_rx1_elec_idle     : out std_logic;
819
       pipe_rx1_polarity      : in  std_logic;
820
       pipe_tx1_compliance    : in  std_logic;
821
       pipe_tx1_char_is_k     : in  std_logic_vector(1 downto 0);
822
       pipe_tx1_data          : in  std_logic_vector(15 downto 0);
823
       pipe_tx1_elec_idle     : in  std_logic;
824
       pipe_tx1_powerdown     : in  std_logic_vector(1 downto 0);
825
       pipe_rx2_char_is_k     : out std_logic_vector(1 downto 0);
826
       pipe_rx2_data          : out std_logic_vector(15 downto 0);
827
       pipe_rx2_valid         : out std_logic;
828
       pipe_rx2_chanisaligned : out std_logic;
829
       pipe_rx2_status        : out std_logic_vector(2 downto 0);
830
       pipe_rx2_phy_status    : out std_logic;
831
       pipe_rx2_elec_idle     : out std_logic;
832
       pipe_rx2_polarity      : in  std_logic;
833
       pipe_tx2_compliance    : in  std_logic;
834
       pipe_tx2_char_is_k     : in  std_logic_vector(1 downto 0);
835
       pipe_tx2_data          : in  std_logic_vector(15 downto 0);
836
       pipe_tx2_elec_idle     : in  std_logic;
837
       pipe_tx2_powerdown     : in  std_logic_vector(1 downto 0);
838
       pipe_rx3_char_is_k     : out std_logic_vector(1 downto 0);
839
       pipe_rx3_data          : out std_logic_vector(15 downto 0);
840
       pipe_rx3_valid         : out std_logic;
841
       pipe_rx3_chanisaligned : out std_logic;
842
       pipe_rx3_status        : out std_logic_vector(2 downto 0);
843
       pipe_rx3_phy_status    : out std_logic;
844
       pipe_rx3_elec_idle     : out std_logic;
845
       pipe_rx3_polarity      : in  std_logic;
846
       pipe_tx3_compliance    : in  std_logic;
847
       pipe_tx3_char_is_k     : in  std_logic_vector(1 downto 0);
848
       pipe_tx3_data          : in  std_logic_vector(15 downto 0);
849
       pipe_tx3_elec_idle     : in  std_logic;
850
       pipe_tx3_powerdown     : in  std_logic_vector(1 downto 0);
851
       pipe_rx4_char_is_k     : out std_logic_vector(1 downto 0);
852
       pipe_rx4_data          : out std_logic_vector(15 downto 0);
853
       pipe_rx4_valid         : out std_logic;
854
       pipe_rx4_chanisaligned : out std_logic;
855
       pipe_rx4_status        : out std_logic_vector(2 downto 0);
856
       pipe_rx4_phy_status    : out std_logic;
857
       pipe_rx4_elec_idle     : out std_logic;
858
       pipe_rx4_polarity      : in  std_logic;
859
       pipe_tx4_compliance    : in  std_logic;
860
       pipe_tx4_char_is_k     : in  std_logic_vector(1 downto 0);
861
       pipe_tx4_data          : in  std_logic_vector(15 downto 0);
862
       pipe_tx4_elec_idle     : in  std_logic;
863
       pipe_tx4_powerdown     : in  std_logic_vector(1 downto 0);
864
       pipe_rx5_char_is_k     : out std_logic_vector(1 downto 0);
865
       pipe_rx5_data          : out std_logic_vector(15 downto 0);
866
       pipe_rx5_valid         : out std_logic;
867
       pipe_rx5_chanisaligned : out std_logic;
868
       pipe_rx5_status        : out std_logic_vector(2 downto 0);
869
       pipe_rx5_phy_status    : out std_logic;
870
       pipe_rx5_elec_idle     : out std_logic;
871
       pipe_rx5_polarity      : in  std_logic;
872
       pipe_tx5_compliance    : in  std_logic;
873
       pipe_tx5_char_is_k     : in  std_logic_vector(1 downto 0);
874
       pipe_tx5_data          : in  std_logic_vector(15 downto 0);
875
       pipe_tx5_elec_idle     : in  std_logic;
876
       pipe_tx5_powerdown     : in  std_logic_vector(1 downto 0);
877
       pipe_rx6_char_is_k     : out std_logic_vector(1 downto 0);
878
       pipe_rx6_data          : out std_logic_vector(15 downto 0);
879
       pipe_rx6_valid         : out std_logic;
880
       pipe_rx6_chanisaligned : out std_logic;
881
       pipe_rx6_status        : out std_logic_vector(2 downto 0);
882
       pipe_rx6_phy_status    : out std_logic;
883
       pipe_rx6_elec_idle     : out std_logic;
884
       pipe_rx6_polarity      : in  std_logic;
885
       pipe_tx6_compliance    : in  std_logic;
886
       pipe_tx6_char_is_k     : in  std_logic_vector(1 downto 0);
887
       pipe_tx6_data          : in  std_logic_vector(15 downto 0);
888
       pipe_tx6_elec_idle     : in  std_logic;
889
       pipe_tx6_powerdown     : in  std_logic_vector(1 downto 0);
890
       pipe_rx7_char_is_k     : out std_logic_vector(1 downto 0);
891
       pipe_rx7_data          : out std_logic_vector(15 downto 0);
892
       pipe_rx7_valid         : out std_logic;
893
       pipe_rx7_chanisaligned : out std_logic;
894
       pipe_rx7_status        : out std_logic_vector(2 downto 0);
895
       pipe_rx7_phy_status    : out std_logic;
896
       pipe_rx7_elec_idle     : out std_logic;
897
       pipe_rx7_polarity      : in  std_logic;
898
       pipe_tx7_compliance    : in  std_logic;
899
       pipe_tx7_char_is_k     : in  std_logic_vector(1 downto 0);
900
       pipe_tx7_data          : in  std_logic_vector(15 downto 0);
901
       pipe_tx7_elec_idle     : in  std_logic;
902
       pipe_tx7_powerdown     : in  std_logic_vector(1 downto 0);
903
       pci_exp_txn            : out std_logic_vector((NO_OF_LANES - 1) downto 0);
904
       pci_exp_txp            : out std_logic_vector((NO_OF_LANES - 1) downto 0);
905
       pci_exp_rxn            : in  std_logic_vector((NO_OF_LANES - 1) downto 0);
906
       pci_exp_rxp            : in  std_logic_vector((NO_OF_LANES - 1) downto 0);
907
       sys_clk                : in  std_logic;
908
       sys_rst_n              : in  std_logic;
909
       pipe_clk               : in  std_logic;
910
       drp_clk                : in  std_logic;
911
       clock_locked           : in  std_logic;
912
       gt_pll_lock            : out std_logic;
913
       pl_ltssm_state         : in  std_logic_vector(5 downto 0);
914
       phy_rdy_n              : out std_logic;
915
       TxOutClk               : out std_logic);
916
   end component;
917
 
918
   component pcie_bram_top_v6
919
     generic (
920
       DEV_CAP_MAX_PAYLOAD_SUPPORTED : integer;
921
       VC0_TX_LASTPACKET             : integer;
922
       TL_TX_RAM_RADDR_LATENCY       : integer;
923
       TL_TX_RAM_RDATA_LATENCY       : integer;
924
       TL_TX_RAM_WRITE_LATENCY       : integer;
925
       VC0_RX_LIMIT                  : bit_vector;
926
       TL_RX_RAM_RADDR_LATENCY       : integer;
927
       TL_RX_RAM_RDATA_LATENCY       : integer;
928
       TL_RX_RAM_WRITE_LATENCY       : integer);
929
     port (
930
       user_clk_i   : in  std_logic;
931
       reset_i      : in  std_logic;
932
       mim_tx_wen   : in  std_logic;
933
       mim_tx_waddr : in  std_logic_vector(12 downto 0);
934
       mim_tx_wdata : in  std_logic_vector(71 downto 0);
935
       mim_tx_ren   : in  std_logic;
936
       mim_tx_rce   : in  std_logic;
937
       mim_tx_raddr : in  std_logic_vector(12 downto 0);
938
       mim_tx_rdata : out std_logic_vector(71 downto 0);
939
       mim_rx_wen   : in  std_logic;
940
       mim_rx_waddr : in  std_logic_vector(12 downto 0);
941
       mim_rx_wdata : in  std_logic_vector(71 downto 0);
942
       mim_rx_ren   : in  std_logic;
943
       mim_rx_rce   : in  std_logic;
944
       mim_rx_raddr : in  std_logic_vector(12 downto 0);
945
       mim_rx_rdata : out std_logic_vector(71 downto 0));
946
   end component;
947
 
948
   component pcie_upconfig_fix_3451_v6
949
     generic (
950
       UPSTREAM_FACING         : boolean;
951
       PL_FAST_TRAIN           : boolean;
952
       LINK_CAP_MAX_LINK_WIDTH : bit_vector);
953
     port (
954
       pipe_clk                         : in  std_logic;
955
       pl_phy_lnkup_n                   : in  std_logic;
956
       pl_ltssm_state                   : in  std_logic_vector(5 downto 0);
957
       pl_sel_lnk_rate                  : in  std_logic;
958
       pl_directed_link_change          : in  std_logic_vector(1 downto 0);
959
       cfg_link_status_negotiated_width : in  std_logic_vector(3 downto 0);
960
       pipe_rx0_data                    : in std_logic_vector(15 downto 0);
961
       pipe_rx0_char_isk                : in std_logic_vector(1 downto 0);
962
       filter_pipe                      : out std_logic);
963
   end component;
964
 
965
   -- wire declarations
966
 
967
   signal LL2BADDLLPERRN                               : std_logic;
968
   signal LL2BADTLPERRN                                : std_logic;
969
   signal LL2PROTOCOLERRN                              : std_logic;
970
   signal LL2REPLAYROERRN                              : std_logic;
971
   signal LL2REPLAYTOERRN                              : std_logic;
972
   signal LL2SUSPENDOKN                                : std_logic;
973
   signal LL2TFCINIT1SEQN                              : std_logic;
974
   signal LL2TFCINIT2SEQN                              : std_logic;
975
   signal MIMRXRADDR                                   : std_logic_vector(12 downto 0);
976
   signal MIMRXRCE                                     : std_logic;
977
   signal MIMRXREN                                     : std_logic;
978
   signal MIMRXWADDR                                   : std_logic_vector(12 downto 0);
979
   signal MIMRXWDATA                                   : std_logic_vector(67 downto 0);
980
   signal MIMRXWDATA_tmp                               : std_logic_vector(71 downto 0);
981
   signal MIMRXWEN                                     : std_logic;
982
   signal MIMTXRADDR                                   : std_logic_vector(12 downto 0);
983
   signal MIMTXRCE                                     : std_logic;
984
   signal MIMTXREN                                     : std_logic;
985
   signal MIMTXWADDR                                   : std_logic_vector(12 downto 0);
986
   signal MIMTXWDATA                                   : std_logic_vector(68 downto 0);
987
   signal MIMTXWDATA_tmp                               : std_logic_vector(71 downto 0);
988
   signal MIMTXWEN                                     : std_logic;
989
   signal PIPERX0POLARITY                              : std_logic;
990
   signal PIPERX1POLARITY                              : std_logic;
991
   signal PIPERX2POLARITY                              : std_logic;
992
   signal PIPERX3POLARITY                              : std_logic;
993
   signal PIPERX4POLARITY                              : std_logic;
994
   signal PIPERX5POLARITY                              : std_logic;
995
   signal PIPERX6POLARITY                              : std_logic;
996
   signal PIPERX7POLARITY                              : std_logic;
997
   signal PIPETXDEEMPH                                 : std_logic;
998
   signal PIPETXMARGIN                                 : std_logic_vector(2 downto 0);
999
   signal PIPETXRATE                                   : std_logic;
1000
   signal PIPETXRCVRDET                                : std_logic;
1001
   signal PIPETXRESET                                  : std_logic;
1002
   signal PIPETX0CHARISK                               : std_logic_vector(1 downto 0);
1003
   signal PIPETX0COMPLIANCE                            : std_logic;
1004
   signal PIPETX0DATA                                  : std_logic_vector(15 downto 0);
1005
   signal PIPETX0ELECIDLE                              : std_logic;
1006
   signal PIPETX0POWERDOWN                             : std_logic_vector(1 downto 0);
1007
   signal PIPETX1CHARISK                               : std_logic_vector(1 downto 0);
1008
   signal PIPETX1COMPLIANCE                            : std_logic;
1009
   signal PIPETX1DATA                                  : std_logic_vector(15 downto 0);
1010
   signal PIPETX1ELECIDLE                              : std_logic;
1011
   signal PIPETX1POWERDOWN                             : std_logic_vector(1 downto 0);
1012
   signal PIPETX2CHARISK                               : std_logic_vector(1 downto 0);
1013
   signal PIPETX2COMPLIANCE                            : std_logic;
1014
   signal PIPETX2DATA                                  : std_logic_vector(15 downto 0);
1015
   signal PIPETX2ELECIDLE                              : std_logic;
1016
   signal PIPETX2POWERDOWN                             : std_logic_vector(1 downto 0);
1017
   signal PIPETX3CHARISK                               : std_logic_vector(1 downto 0);
1018
   signal PIPETX3COMPLIANCE                            : std_logic;
1019
   signal PIPETX3DATA                                  : std_logic_vector(15 downto 0);
1020
   signal PIPETX3ELECIDLE                              : std_logic;
1021
   signal PIPETX3POWERDOWN                             : std_logic_vector(1 downto 0);
1022
   signal PIPETX4CHARISK                               : std_logic_vector(1 downto 0);
1023
   signal PIPETX4COMPLIANCE                            : std_logic;
1024
   signal PIPETX4DATA                                  : std_logic_vector(15 downto 0);
1025
   signal PIPETX4ELECIDLE                              : std_logic;
1026
   signal PIPETX4POWERDOWN                             : std_logic_vector(1 downto 0);
1027
   signal PIPETX5CHARISK                               : std_logic_vector(1 downto 0);
1028
   signal PIPETX5COMPLIANCE                            : std_logic;
1029
   signal PIPETX5DATA                                  : std_logic_vector(15 downto 0);
1030
   signal PIPETX5ELECIDLE                              : std_logic;
1031
   signal PIPETX5POWERDOWN                             : std_logic_vector(1 downto 0);
1032
   signal PIPETX6CHARISK                               : std_logic_vector(1 downto 0);
1033
   signal PIPETX6COMPLIANCE                            : std_logic;
1034
   signal PIPETX6DATA                                  : std_logic_vector(15 downto 0);
1035
   signal PIPETX6ELECIDLE                              : std_logic;
1036
   signal PIPETX6POWERDOWN                             : std_logic_vector(1 downto 0);
1037
   signal PIPETX7CHARISK                               : std_logic_vector(1 downto 0);
1038
   signal PIPETX7COMPLIANCE                            : std_logic;
1039
   signal PIPETX7DATA                                  : std_logic_vector(15 downto 0);
1040
   signal PIPETX7ELECIDLE                              : std_logic;
1041
   signal PIPETX7POWERDOWN                             : std_logic_vector(1 downto 0);
1042
   signal PL2LINKUPN                                   : std_logic;
1043
   signal PL2RECEIVERERRN                              : std_logic;
1044
   signal PL2RECOVERYN                                 : std_logic;
1045
   signal PL2RXELECIDLE                                : std_logic;
1046
   signal PL2SUSPENDOK                                 : std_logic;
1047
   signal TL2ASPMSUSPENDCREDITCHECKOKN                 : std_logic;
1048
   signal TL2ASPMSUSPENDREQN                           : std_logic;
1049
   signal TL2PPMSUSPENDOKN                             : std_logic;
1050
   signal LL2SENDASREQL1N                              : std_logic;
1051
   signal LL2SENDENTERL1N                              : std_logic;
1052
   signal LL2SENDENTERL23N                             : std_logic;
1053
   signal LL2SUSPENDNOWN                               : std_logic;
1054
   signal LL2TLPRCVN                                   : std_logic;
1055
   signal MIMRXRDATA                                   : std_logic_vector(71 downto 0);
1056
   signal MIMTXRDATA                                   : std_logic_vector(71 downto 0);
1057
   signal PL2DIRECTEDLSTATE                            : std_logic_vector(4 downto 0);
1058
   signal TL2ASPMSUSPENDCREDITCHECKN                   : std_logic;
1059
   signal TL2PPMSUSPENDREQN                            : std_logic;
1060
   signal PIPERX0CHANISALIGNED                         : std_logic;
1061
   signal PIPERX0CHARISK                               : std_logic_vector(1 downto 0);
1062
   signal PIPERX0DATA                                  : std_logic_vector(15 downto 0);
1063
   signal PIPERX0ELECIDLE                              : std_logic;
1064
   signal PIPERX0PHYSTATUS                             : std_logic;
1065
   signal PIPERX0STATUS                                : std_logic_vector(2 downto 0);
1066
   signal PIPERX0VALID                                 : std_logic;
1067
   signal PIPERX1CHANISALIGNED                         : std_logic;
1068
   signal PIPERX1CHARISK                               : std_logic_vector(1 downto 0);
1069
   signal PIPERX1DATA                                  : std_logic_vector(15 downto 0);
1070
   signal PIPERX1ELECIDLE                              : std_logic;
1071
   signal PIPERX1PHYSTATUS                             : std_logic;
1072
   signal PIPERX1STATUS                                : std_logic_vector(2 downto 0);
1073
   signal PIPERX1VALID                                 : std_logic;
1074
   signal PIPERX2CHANISALIGNED                         : std_logic;
1075
   signal PIPERX2CHARISK                               : std_logic_vector(1 downto 0);
1076
   signal PIPERX2DATA                                  : std_logic_vector(15 downto 0);
1077
   signal PIPERX2ELECIDLE                              : std_logic;
1078
   signal PIPERX2PHYSTATUS                             : std_logic;
1079
   signal PIPERX2STATUS                                : std_logic_vector(2 downto 0);
1080
   signal PIPERX2VALID                                 : std_logic;
1081
   signal PIPERX3CHANISALIGNED                         : std_logic;
1082
   signal PIPERX3CHARISK                               : std_logic_vector(1 downto 0);
1083
   signal PIPERX3DATA                                  : std_logic_vector(15 downto 0);
1084
   signal PIPERX3ELECIDLE                              : std_logic;
1085
   signal PIPERX3PHYSTATUS                             : std_logic;
1086
   signal PIPERX3STATUS                                : std_logic_vector(2 downto 0);
1087
   signal PIPERX3VALID                                 : std_logic;
1088
   signal PIPERX4CHANISALIGNED                         : std_logic;
1089
   signal PIPERX4CHARISK                               : std_logic_vector(1 downto 0);
1090
   signal PIPERX4DATA                                  : std_logic_vector(15 downto 0);
1091
   signal PIPERX4ELECIDLE                              : std_logic;
1092
   signal PIPERX4PHYSTATUS                             : std_logic;
1093
   signal PIPERX4STATUS                                : std_logic_vector(2 downto 0);
1094
   signal PIPERX4VALID                                 : std_logic;
1095
   signal PIPERX5CHANISALIGNED                         : std_logic;
1096
   signal PIPERX5CHARISK                               : std_logic_vector(1 downto 0);
1097
   signal PIPERX5DATA                                  : std_logic_vector(15 downto 0);
1098
   signal PIPERX5ELECIDLE                              : std_logic;
1099
   signal PIPERX5PHYSTATUS                             : std_logic;
1100
   signal PIPERX5STATUS                                : std_logic_vector(2 downto 0);
1101
   signal PIPERX5VALID                                 : std_logic;
1102
   signal PIPERX6CHANISALIGNED                         : std_logic;
1103
   signal PIPERX6CHARISK                               : std_logic_vector(1 downto 0);
1104
   signal PIPERX6DATA                                  : std_logic_vector(15 downto 0);
1105
   signal PIPERX6ELECIDLE                              : std_logic;
1106
   signal PIPERX6PHYSTATUS                             : std_logic;
1107
   signal PIPERX6STATUS                                : std_logic_vector(2 downto 0);
1108
   signal PIPERX6VALID                                 : std_logic;
1109
   signal PIPERX7CHANISALIGNED                         : std_logic;
1110
   signal PIPERX7CHARISK                               : std_logic_vector(1 downto 0);
1111
   signal PIPERX7DATA                                  : std_logic_vector(15 downto 0);
1112
   signal PIPERX7ELECIDLE                              : std_logic;
1113
   signal PIPERX7PHYSTATUS                             : std_logic;
1114
   signal PIPERX7STATUS                                : std_logic_vector(2 downto 0);
1115
   signal PIPERX7VALID                                 : std_logic;
1116
 
1117
   signal PIPERX0POLARITYGT                            : std_logic;
1118
   signal PIPERX1POLARITYGT                            : std_logic;
1119
   signal PIPERX2POLARITYGT                            : std_logic;
1120
   signal PIPERX3POLARITYGT                            : std_logic;
1121
   signal PIPERX4POLARITYGT                            : std_logic;
1122
   signal PIPERX5POLARITYGT                            : std_logic;
1123
   signal PIPERX6POLARITYGT                            : std_logic;
1124
   signal PIPERX7POLARITYGT                            : std_logic;
1125
   signal PIPETXDEEMPHGT                               : std_logic;
1126
   signal PIPETXMARGINGT                               : std_logic_vector(2 downto 0);
1127
   signal PIPETXRATEGT                                 : std_logic;
1128
   signal PIPETXRCVRDETGT                              : std_logic;
1129
   signal PIPETX0CHARISKGT                             : std_logic_vector(1 downto 0);
1130
   signal PIPETX0COMPLIANCEGT                          : std_logic;
1131
   signal PIPETX0DATAGT                                : std_logic_vector(15 downto 0);
1132
   signal PIPETX0ELECIDLEGT                            : std_logic;
1133
   signal PIPETX0POWERDOWNGT                           : std_logic_vector(1 downto 0);
1134
   signal PIPETX1CHARISKGT                             : std_logic_vector(1 downto 0);
1135
   signal PIPETX1COMPLIANCEGT                          : std_logic;
1136
   signal PIPETX1DATAGT                                : std_logic_vector(15 downto 0);
1137
   signal PIPETX1ELECIDLEGT                            : std_logic;
1138
   signal PIPETX1POWERDOWNGT                           : std_logic_vector(1 downto 0);
1139
   signal PIPETX2CHARISKGT                             : std_logic_vector(1 downto 0);
1140
   signal PIPETX2COMPLIANCEGT                          : std_logic;
1141
   signal PIPETX2DATAGT                                : std_logic_vector(15 downto 0);
1142
   signal PIPETX2ELECIDLEGT                            : std_logic;
1143
   signal PIPETX2POWERDOWNGT                           : std_logic_vector(1 downto 0);
1144
   signal PIPETX3CHARISKGT                             : std_logic_vector(1 downto 0);
1145
   signal PIPETX3COMPLIANCEGT                          : std_logic;
1146
   signal PIPETX3DATAGT                                : std_logic_vector(15 downto 0);
1147
   signal PIPETX3ELECIDLEGT                            : std_logic;
1148
   signal PIPETX3POWERDOWNGT                           : std_logic_vector(1 downto 0);
1149
   signal PIPETX4CHARISKGT                             : std_logic_vector(1 downto 0);
1150
   signal PIPETX4COMPLIANCEGT                          : std_logic;
1151
   signal PIPETX4DATAGT                                : std_logic_vector(15 downto 0);
1152
   signal PIPETX4ELECIDLEGT                            : std_logic;
1153
   signal PIPETX4POWERDOWNGT                           : std_logic_vector(1 downto 0);
1154
   signal PIPETX5CHARISKGT                             : std_logic_vector(1 downto 0);
1155
   signal PIPETX5COMPLIANCEGT                          : std_logic;
1156
   signal PIPETX5DATAGT                                : std_logic_vector(15 downto 0);
1157
   signal PIPETX5ELECIDLEGT                            : std_logic;
1158
   signal PIPETX5POWERDOWNGT                           : std_logic_vector(1 downto 0);
1159
   signal PIPETX6CHARISKGT                             : std_logic_vector(1 downto 0);
1160
   signal PIPETX6COMPLIANCEGT                          : std_logic;
1161
   signal PIPETX6DATAGT                                : std_logic_vector(15 downto 0);
1162
   signal PIPETX6ELECIDLEGT                            : std_logic;
1163
   signal PIPETX6POWERDOWNGT                           : std_logic_vector(1 downto 0);
1164
   signal PIPETX7CHARISKGT                             : std_logic_vector(1 downto 0);
1165
   signal PIPETX7COMPLIANCEGT                          : std_logic;
1166
   signal PIPETX7DATAGT                                : std_logic_vector(15 downto 0);
1167
   signal PIPETX7ELECIDLEGT                            : std_logic;
1168
   signal PIPETX7POWERDOWNGT                           : std_logic_vector(1 downto 0);
1169
 
1170
   signal PIPERX0CHANISALIGNEDGT                       : std_logic;
1171
   signal PIPERX0CHARISKGT                             : std_logic_vector(1 downto 0);
1172
   signal PIPERX0DATAGT                                : std_logic_vector(15 downto 0);
1173
   signal PIPERX0ELECIDLEGT                            : std_logic;
1174
   signal PIPERX0PHYSTATUSGT                           : std_logic;
1175
   signal PIPERX0STATUSGT                              : std_logic_vector(2 downto 0);
1176
   signal PIPERX0VALIDGT                               : std_logic;
1177
   signal PIPERX1CHANISALIGNEDGT                       : std_logic;
1178
   signal PIPERX1CHARISKGT                             : std_logic_vector(1 downto 0);
1179
   signal PIPERX1DATAGT                                : std_logic_vector(15 downto 0);
1180
   signal PIPERX1ELECIDLEGT                            : std_logic;
1181
   signal PIPERX1PHYSTATUSGT                           : std_logic;
1182
   signal PIPERX1STATUSGT                              : std_logic_vector(2 downto 0);
1183
   signal PIPERX1VALIDGT                               : std_logic;
1184
   signal PIPERX2CHANISALIGNEDGT                       : std_logic;
1185
   signal PIPERX2CHARISKGT                             : std_logic_vector(1 downto 0);
1186
   signal PIPERX2DATAGT                                : std_logic_vector(15 downto 0);
1187
   signal PIPERX2ELECIDLEGT                            : std_logic;
1188
   signal PIPERX2PHYSTATUSGT                           : std_logic;
1189
   signal PIPERX2STATUSGT                              : std_logic_vector(2 downto 0);
1190
   signal PIPERX2VALIDGT                               : std_logic;
1191
   signal PIPERX3CHANISALIGNEDGT                       : std_logic;
1192
   signal PIPERX3CHARISKGT                             : std_logic_vector(1 downto 0);
1193
   signal PIPERX3DATAGT                                : std_logic_vector(15 downto 0);
1194
   signal PIPERX3ELECIDLEGT                            : std_logic;
1195
   signal PIPERX3PHYSTATUSGT                           : std_logic;
1196
   signal PIPERX3STATUSGT                              : std_logic_vector(2 downto 0);
1197
   signal PIPERX3VALIDGT                               : std_logic;
1198
   signal PIPERX4CHANISALIGNEDGT                       : std_logic;
1199
   signal PIPERX4CHARISKGT                             : std_logic_vector(1 downto 0);
1200
   signal PIPERX4DATAGT                                : std_logic_vector(15 downto 0);
1201
   signal PIPERX4ELECIDLEGT                            : std_logic;
1202
   signal PIPERX4PHYSTATUSGT                           : std_logic;
1203
   signal PIPERX4STATUSGT                              : std_logic_vector(2 downto 0);
1204
   signal PIPERX4VALIDGT                               : std_logic;
1205
   signal PIPERX5CHANISALIGNEDGT                       : std_logic;
1206
   signal PIPERX5CHARISKGT                             : std_logic_vector(1 downto 0);
1207
   signal PIPERX5DATAGT                                : std_logic_vector(15 downto 0);
1208
   signal PIPERX5ELECIDLEGT                            : std_logic;
1209
   signal PIPERX5PHYSTATUSGT                           : std_logic;
1210
   signal PIPERX5STATUSGT                              : std_logic_vector(2 downto 0);
1211
   signal PIPERX5VALIDGT                               : std_logic;
1212
   signal PIPERX6CHANISALIGNEDGT                       : std_logic;
1213
   signal PIPERX6CHARISKGT                             : std_logic_vector(1 downto 0);
1214
   signal PIPERX6DATAGT                                : std_logic_vector(15 downto 0);
1215
   signal PIPERX6ELECIDLEGT                            : std_logic;
1216
   signal PIPERX6PHYSTATUSGT                           : std_logic;
1217
   signal PIPERX6STATUSGT                              : std_logic_vector(2 downto 0);
1218
   signal PIPERX6VALIDGT                               : std_logic;
1219
   signal PIPERX7CHANISALIGNEDGT                       : std_logic;
1220
   signal PIPERX7CHARISKGT                             : std_logic_vector(1 downto 0);
1221
   signal PIPERX7DATAGT                                : std_logic_vector(15 downto 0);
1222
   signal PIPERX7ELECIDLEGT                            : std_logic;
1223
   signal PIPERX7PHYSTATUSGT                           : std_logic;
1224
   signal PIPERX7STATUSGT                              : std_logic_vector(2 downto 0);
1225
   signal PIPERX7VALIDGT                               : std_logic;
1226
 
1227
   signal filter_pipe_upconfig_fix_3451                : std_logic;
1228
 
1229
   -- Declare intermediate signals for referenced outputs
1230
   signal PCIEXPTXN_v6pcie100                          : std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);
1231
   signal PCIEXPTXP_v6pcie101                          : std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);
1232
   signal TRNLNKUPN_v6pcie123                          : std_logic;
1233
   signal PHYRDYN_v6pcie102                            : std_logic;
1234
   signal USERRSTN_v6pcie139                           : std_logic;
1235
   signal RECEIVEDFUNCLVLRSTN_v6pcie116                : std_logic;
1236
   signal LNKCLKEN_v6pcie97                            : std_logic;
1237
   signal TRNRBARHITN_v6pcie124                        : std_logic_vector(6 downto 0);
1238
   signal TRNRD_v6pcie125                              : std_logic_vector(63 downto 0);
1239
   signal TRNRECRCERRN_v6pcie126                       : std_logic;
1240
   signal TRNREOFN_v6pcie127                           : std_logic;
1241
   signal TRNRERRFWDN_v6pcie128                        : std_logic;
1242
   signal TRNRREMN_v6pcie129                           : std_logic;
1243
   signal TRNRSOFN_v6pcie130                           : std_logic;
1244
   signal TRNRSRCDSCN_v6pcie131                        : std_logic;
1245
   signal TRNRSRCRDYN_v6pcie132                        : std_logic;
1246
   signal TRNTBUFAV_v6pcie133                          : std_logic_vector(5 downto 0);
1247
   signal TRNTCFGREQN_v6pcie134                        : std_logic;
1248
   signal TRNTDLLPDSTRDYN_v6pcie135                    : std_logic;
1249
   signal TRNTDSTRDYN_v6pcie136                        : std_logic;
1250
   signal TRNTERRDROPN_v6pcie137                       : std_logic;
1251
   signal TRNFCCPLD_v6pcie117                          : std_logic_vector(11 downto 0);
1252
   signal TRNFCCPLH_v6pcie118                          : std_logic_vector(7 downto 0);
1253
   signal TRNFCNPD_v6pcie119                           : std_logic_vector(11 downto 0);
1254
   signal TRNFCNPH_v6pcie120                           : std_logic_vector(7 downto 0);
1255
   signal TRNFCPD_v6pcie121                            : std_logic_vector(11 downto 0);
1256
   signal TRNFCPH_v6pcie122                            : std_logic_vector(7 downto 0);
1257
   signal CFGAERECRCCHECKEN_v6pcie0                    : std_logic;
1258
   signal CFGAERECRCGENEN_v6pcie1                      : std_logic;
1259
   signal CFGCOMMANDBUSMASTERENABLE_v6pcie2            : std_logic;
1260
   signal CFGCOMMANDINTERRUPTDISABLE_v6pcie3           : std_logic;
1261
   signal CFGCOMMANDIOENABLE_v6pcie4                   : std_logic;
1262
   signal CFGCOMMANDMEMENABLE_v6pcie5                  : std_logic;
1263
   signal CFGCOMMANDSERREN_v6pcie6                     : std_logic;
1264
   signal CFGDEVCONTROLAUXPOWEREN_v6pcie9              : std_logic;
1265
   signal CFGDEVCONTROLCORRERRREPORTINGEN_v6pcie10     : std_logic;
1266
   signal CFGDEVCONTROLENABLERO_v6pcie11               : std_logic;
1267
   signal CFGDEVCONTROLEXTTAGEN_v6pcie12               : std_logic;
1268
   signal CFGDEVCONTROLFATALERRREPORTINGEN_v6pcie13    : std_logic;
1269
   signal CFGDEVCONTROLMAXPAYLOAD_v6pcie14             : std_logic_vector(2 downto 0);
1270
   signal CFGDEVCONTROLMAXREADREQ_v6pcie15             : std_logic_vector(2 downto 0);
1271
   signal CFGDEVCONTROLNONFATALREPORTINGEN_v6pcie16    : std_logic;
1272
   signal CFGDEVCONTROLNOSNOOPEN_v6pcie17              : std_logic;
1273
   signal CFGDEVCONTROLPHANTOMEN_v6pcie18              : std_logic;
1274
   signal CFGDEVCONTROLURERRREPORTINGEN_v6pcie19       : std_logic;
1275
   signal CFGDEVCONTROL2CPLTIMEOUTDIS_v6pcie7          : std_logic;
1276
   signal CFGDEVCONTROL2CPLTIMEOUTVAL_v6pcie8          : std_logic_vector(3 downto 0);
1277
   signal CFGDEVSTATUSCORRERRDETECTED_v6pcie20         : std_logic;
1278
   signal CFGDEVSTATUSFATALERRDETECTED_v6pcie21        : std_logic;
1279
   signal CFGDEVSTATUSNONFATALERRDETECTED_v6pcie22     : std_logic;
1280
   signal CFGDEVSTATUSURDETECTED_v6pcie23              : std_logic;
1281
   signal CFGDO_v6pcie24                               : std_logic_vector(31 downto 0);
1282
   signal CFGERRAERHEADERLOGSETN_v6pcie25              : std_logic;
1283
   signal CFGERRCPLRDYN_v6pcie26                       : std_logic;
1284
   signal CFGINTERRUPTDO_v6pcie27                      : std_logic_vector(7 downto 0);
1285
   signal CFGINTERRUPTMMENABLE_v6pcie28                : std_logic_vector(2 downto 0);
1286
   signal CFGINTERRUPTMSIENABLE_v6pcie29               : std_logic;
1287
   signal CFGINTERRUPTMSIXENABLE_v6pcie30              : std_logic;
1288
   signal CFGINTERRUPTMSIXFM_v6pcie31                  : std_logic;
1289
   signal CFGINTERRUPTRDYN_v6pcie32                    : std_logic;
1290
   signal CFGLINKCONTROLRCB_v6pcie41                   : std_logic;
1291
   signal CFGLINKCONTROLASPMCONTROL_v6pcie33           : std_logic_vector(1 downto 0);
1292
   signal CFGLINKCONTROLAUTOBANDWIDTHINTEN_v6pcie34    : std_logic;
1293
   signal CFGLINKCONTROLBANDWIDTHINTEN_v6pcie35        : std_logic;
1294
   signal CFGLINKCONTROLCLOCKPMEN_v6pcie36             : std_logic;
1295
   signal CFGLINKCONTROLCOMMONCLOCK_v6pcie37           : std_logic;
1296
   signal CFGLINKCONTROLEXTENDEDSYNC_v6pcie38          : std_logic;
1297
   signal CFGLINKCONTROLHWAUTOWIDTHDIS_v6pcie39        : std_logic;
1298
   signal CFGLINKCONTROLLINKDISABLE_v6pcie40           : std_logic;
1299
   signal CFGLINKCONTROLRETRAINLINK_v6pcie42           : std_logic;
1300
   signal CFGLINKSTATUSAUTOBANDWIDTHSTATUS_v6pcie43    : std_logic;
1301
   signal CFGLINKSTATUSBANDWITHSTATUS_v6pcie44         : std_logic;
1302
   signal CFGLINKSTATUSCURRENTSPEED_v6pcie45           : std_logic_vector(1 downto 0);
1303
   signal CFGLINKSTATUSDLLACTIVE_v6pcie46              : std_logic;
1304
   signal CFGLINKSTATUSLINKTRAINING_v6pcie47           : std_logic;
1305
   signal CFGLINKSTATUSNEGOTIATEDWIDTH_v6pcie48        : std_logic_vector(3 downto 0);
1306
   signal CFGMSGDATA_v6pcie49                          : std_logic_vector(15 downto 0);
1307
   signal CFGMSGRECEIVED_v6pcie50                      : std_logic;
1308
   signal CFGMSGRECEIVEDASSERTINTA_v6pcie51            : std_logic;
1309
   signal CFGMSGRECEIVEDASSERTINTB_v6pcie52            : std_logic;
1310
   signal CFGMSGRECEIVEDASSERTINTC_v6pcie53            : std_logic;
1311
   signal CFGMSGRECEIVEDASSERTINTD_v6pcie54            : std_logic;
1312
   signal CFGMSGRECEIVEDDEASSERTINTA_v6pcie55          : std_logic;
1313
   signal CFGMSGRECEIVEDDEASSERTINTB_v6pcie56          : std_logic;
1314
   signal CFGMSGRECEIVEDDEASSERTINTC_v6pcie57          : std_logic;
1315
   signal CFGMSGRECEIVEDDEASSERTINTD_v6pcie58          : std_logic;
1316
   signal CFGMSGRECEIVEDERRCOR_v6pcie59                : std_logic;
1317
   signal CFGMSGRECEIVEDERRFATAL_v6pcie60              : std_logic;
1318
   signal CFGMSGRECEIVEDERRNONFATAL_v6pcie61           : std_logic;
1319
   signal CFGMSGRECEIVEDPMASNAK_v6pcie62               : std_logic;
1320
   signal CFGMSGRECEIVEDPMETO_v6pcie63                 : std_logic;
1321
   signal CFGMSGRECEIVEDPMETOACK_v6pcie64              : std_logic;
1322
   signal CFGMSGRECEIVEDPMPME_v6pcie65                 : std_logic;
1323
   signal CFGMSGRECEIVEDSETSLOTPOWERLIMIT_v6pcie66     : std_logic;
1324
   signal CFGMSGRECEIVEDUNLOCK_v6pcie67                : std_logic;
1325
   signal CFGPCIELINKSTATE_v6pcie68                    : std_logic_vector(2 downto 0);
1326
   signal CFGPMCSRPMEEN_v6pcie69                       : std_logic;
1327
   signal CFGPMCSRPMESTATUS_v6pcie70                   : std_logic;
1328
   signal CFGPMCSRPOWERSTATE_v6pcie71                  : std_logic_vector(1 downto 0);
1329
   signal CFGPMRCVASREQL1N_v6pcie72                    : std_logic;
1330
   signal CFGPMRCVENTERL1N_v6pcie73                    : std_logic;
1331
   signal CFGPMRCVENTERL23N_v6pcie74                   : std_logic;
1332
   signal CFGPMRCVREQACKN_v6pcie75                     : std_logic;
1333
   signal CFGRDWRDONEN_v6pcie76                        : std_logic;
1334
   signal CFGSLOTCONTROLELECTROMECHILCTLPULSE_v6pcie77 : std_logic;
1335
   signal CFGTRANSACTION_v6pcie78                      : std_logic;
1336
   signal CFGTRANSACTIONADDR_v6pcie79                  : std_logic_vector(6 downto 0);
1337
   signal CFGTRANSACTIONTYPE_v6pcie80                  : std_logic;
1338
   signal CFGVCTCVCMAP_v6pcie81                        : std_logic_vector(6 downto 0);
1339
   signal PLINITIALLINKWIDTH_v6pcie104                 : std_logic_vector(2 downto 0);
1340
   signal PLLANEREVERSALMODE_v6pcie105                 : std_logic_vector(1 downto 0);
1341
   signal PLLINKGEN2CAP_v6pcie106                      : std_logic;
1342
   signal PLLINKPARTNERGEN2SUPPORTED_v6pcie107         : std_logic;
1343
   signal PLLINKUPCFGCAP_v6pcie108                     : std_logic;
1344
   signal PLLTSSMSTATE_v6pcie109                       : std_logic_vector(5 downto 0);
1345
   signal PLPHYLNKUPN_v6pcie110                        : std_logic;
1346
   signal PLRECEIVEDHOTRST_v6pcie111                   : std_logic;
1347
   signal PLRXPMSTATE_v6pcie112                        : std_logic_vector(1 downto 0);
1348
   signal PLSELLNKRATE_v6pcie113                       : std_logic;
1349
   signal PLSELLNKWIDTH_v6pcie114                      : std_logic_vector(1 downto 0);
1350
   signal PLTXPMSTATE_v6pcie115                        : std_logic_vector(2 downto 0);
1351
   signal DBGSCLRA_v6pcie82                            : std_logic;
1352
   signal DBGSCLRB_v6pcie83                            : std_logic;
1353
   signal DBGSCLRC_v6pcie84                            : std_logic;
1354
   signal DBGSCLRD_v6pcie85                            : std_logic;
1355
   signal DBGSCLRE_v6pcie86                            : std_logic;
1356
   signal DBGSCLRF_v6pcie87                            : std_logic;
1357
   signal DBGSCLRG_v6pcie88                            : std_logic;
1358
   signal DBGSCLRH_v6pcie89                            : std_logic;
1359
   signal DBGSCLRI_v6pcie90                            : std_logic;
1360
   signal DBGSCLRJ_v6pcie91                            : std_logic;
1361
   signal DBGSCLRK_v6pcie92                            : std_logic;
1362
   signal DBGVECA_v6pcie93                             : std_logic_vector(63 downto 0);
1363
   signal DBGVECB_v6pcie94                             : std_logic_vector(63 downto 0);
1364
   signal DBGVECC_v6pcie95                             : std_logic_vector(11 downto 0);
1365
   signal PLDBGVEC_v6pcie103                           : std_logic_vector(11 downto 0);
1366
   signal PCIEDRPDO_v6pcie98                           : std_logic_vector(15 downto 0);
1367
   signal PCIEDRPDRDY_v6pcie99                         : std_logic;
1368
   signal GTPLLLOCK_v6pcie96                           : std_logic;
1369
   signal TxOutClk_v6pcie138                           : std_logic;
1370
 
1371
   signal PIPERX0CHARISK_v6pcie                        : std_logic_vector(1 downto 0);
1372
   signal PIPERX1CHARISK_v6pcie                        : std_logic_vector(1 downto 0);
1373
   signal PIPERX2CHARISK_v6pcie                        : std_logic_vector(1 downto 0);
1374
   signal PIPERX3CHARISK_v6pcie                        : std_logic_vector(1 downto 0);
1375
   signal PIPERX4CHARISK_v6pcie                        : std_logic_vector(1 downto 0);
1376
   signal PIPERX5CHARISK_v6pcie                        : std_logic_vector(1 downto 0);
1377
   signal PIPERX6CHARISK_v6pcie                        : std_logic_vector(1 downto 0);
1378
   signal PIPERX7CHARISK_v6pcie                        : std_logic_vector(1 downto 0);
1379
 
1380
begin
1381
   -- Drive referenced outputs
1382
   PCIEXPTXN <= PCIEXPTXN_v6pcie100;
1383
   PCIEXPTXP <= PCIEXPTXP_v6pcie101;
1384
   TRNLNKUPN <= TRNLNKUPN_v6pcie123;
1385
   PHYRDYN <= PHYRDYN_v6pcie102;
1386
   USERRSTN <= USERRSTN_v6pcie139;
1387
   RECEIVEDFUNCLVLRSTN <= RECEIVEDFUNCLVLRSTN_v6pcie116;
1388
   LNKCLKEN <= LNKCLKEN_v6pcie97;
1389
   TRNRBARHITN <= TRNRBARHITN_v6pcie124;
1390
   TRNRD <= TRNRD_v6pcie125;
1391
   TRNRECRCERRN <= TRNRECRCERRN_v6pcie126;
1392
   TRNREOFN <= TRNREOFN_v6pcie127;
1393
   TRNRERRFWDN <= TRNRERRFWDN_v6pcie128;
1394
   TRNRREMN <= TRNRREMN_v6pcie129;
1395
   TRNRSOFN <= TRNRSOFN_v6pcie130;
1396
   TRNRSRCDSCN <= TRNRSRCDSCN_v6pcie131;
1397
   TRNRSRCRDYN <= TRNRSRCRDYN_v6pcie132;
1398
   TRNTBUFAV <= TRNTBUFAV_v6pcie133;
1399
   TRNTCFGREQN <= TRNTCFGREQN_v6pcie134;
1400
   TRNTDLLPDSTRDYN <= TRNTDLLPDSTRDYN_v6pcie135;
1401
   TRNTDSTRDYN <= TRNTDSTRDYN_v6pcie136;
1402
   TRNTERRDROPN <= TRNTERRDROPN_v6pcie137;
1403
   TRNFCCPLD <= TRNFCCPLD_v6pcie117;
1404
   TRNFCCPLH <= TRNFCCPLH_v6pcie118;
1405
   TRNFCNPD <= TRNFCNPD_v6pcie119;
1406
   TRNFCNPH <= TRNFCNPH_v6pcie120;
1407
   TRNFCPD <= TRNFCPD_v6pcie121;
1408
   TRNFCPH <= TRNFCPH_v6pcie122;
1409
   CFGAERECRCCHECKEN <= CFGAERECRCCHECKEN_v6pcie0;
1410
   CFGAERECRCGENEN <= CFGAERECRCGENEN_v6pcie1;
1411
   CFGCOMMANDBUSMASTERENABLE <= CFGCOMMANDBUSMASTERENABLE_v6pcie2;
1412
   CFGCOMMANDINTERRUPTDISABLE <= CFGCOMMANDINTERRUPTDISABLE_v6pcie3;
1413
   CFGCOMMANDIOENABLE <= CFGCOMMANDIOENABLE_v6pcie4;
1414
   CFGCOMMANDMEMENABLE <= CFGCOMMANDMEMENABLE_v6pcie5;
1415
   CFGCOMMANDSERREN <= CFGCOMMANDSERREN_v6pcie6;
1416
   CFGDEVCONTROLAUXPOWEREN <= CFGDEVCONTROLAUXPOWEREN_v6pcie9;
1417
   CFGDEVCONTROLCORRERRREPORTINGEN <= CFGDEVCONTROLCORRERRREPORTINGEN_v6pcie10;
1418
   CFGDEVCONTROLENABLERO <= CFGDEVCONTROLENABLERO_v6pcie11;
1419
   CFGDEVCONTROLEXTTAGEN <= CFGDEVCONTROLEXTTAGEN_v6pcie12;
1420
   CFGDEVCONTROLFATALERRREPORTINGEN <= CFGDEVCONTROLFATALERRREPORTINGEN_v6pcie13;
1421
   CFGDEVCONTROLMAXPAYLOAD <= CFGDEVCONTROLMAXPAYLOAD_v6pcie14;
1422
   CFGDEVCONTROLMAXREADREQ <= CFGDEVCONTROLMAXREADREQ_v6pcie15;
1423
   CFGDEVCONTROLNONFATALREPORTINGEN <= CFGDEVCONTROLNONFATALREPORTINGEN_v6pcie16;
1424
   CFGDEVCONTROLNOSNOOPEN <= CFGDEVCONTROLNOSNOOPEN_v6pcie17;
1425
   CFGDEVCONTROLPHANTOMEN <= CFGDEVCONTROLPHANTOMEN_v6pcie18;
1426
   CFGDEVCONTROLURERRREPORTINGEN <= CFGDEVCONTROLURERRREPORTINGEN_v6pcie19;
1427
   CFGDEVCONTROL2CPLTIMEOUTDIS <= CFGDEVCONTROL2CPLTIMEOUTDIS_v6pcie7;
1428
   CFGDEVCONTROL2CPLTIMEOUTVAL <= CFGDEVCONTROL2CPLTIMEOUTVAL_v6pcie8;
1429
   CFGDEVSTATUSCORRERRDETECTED <= CFGDEVSTATUSCORRERRDETECTED_v6pcie20;
1430
   CFGDEVSTATUSFATALERRDETECTED <= CFGDEVSTATUSFATALERRDETECTED_v6pcie21;
1431
   CFGDEVSTATUSNONFATALERRDETECTED <= CFGDEVSTATUSNONFATALERRDETECTED_v6pcie22;
1432
   CFGDEVSTATUSURDETECTED <= CFGDEVSTATUSURDETECTED_v6pcie23;
1433
   CFGDO <= CFGDO_v6pcie24;
1434
   CFGERRAERHEADERLOGSETN <= CFGERRAERHEADERLOGSETN_v6pcie25;
1435
   CFGERRCPLRDYN <= CFGERRCPLRDYN_v6pcie26;
1436
   CFGINTERRUPTDO <= CFGINTERRUPTDO_v6pcie27;
1437
   CFGINTERRUPTMMENABLE <= CFGINTERRUPTMMENABLE_v6pcie28;
1438
   CFGINTERRUPTMSIENABLE <= CFGINTERRUPTMSIENABLE_v6pcie29;
1439
   CFGINTERRUPTMSIXENABLE <= CFGINTERRUPTMSIXENABLE_v6pcie30;
1440
   CFGINTERRUPTMSIXFM <= CFGINTERRUPTMSIXFM_v6pcie31;
1441
   CFGINTERRUPTRDYN <= CFGINTERRUPTRDYN_v6pcie32;
1442
   CFGLINKCONTROLRCB <= CFGLINKCONTROLRCB_v6pcie41;
1443
   CFGLINKCONTROLASPMCONTROL <= CFGLINKCONTROLASPMCONTROL_v6pcie33;
1444
   CFGLINKCONTROLAUTOBANDWIDTHINTEN <= CFGLINKCONTROLAUTOBANDWIDTHINTEN_v6pcie34;
1445
   CFGLINKCONTROLBANDWIDTHINTEN <= CFGLINKCONTROLBANDWIDTHINTEN_v6pcie35;
1446
   CFGLINKCONTROLCLOCKPMEN <= CFGLINKCONTROLCLOCKPMEN_v6pcie36;
1447
   CFGLINKCONTROLCOMMONCLOCK <= CFGLINKCONTROLCOMMONCLOCK_v6pcie37;
1448
   CFGLINKCONTROLEXTENDEDSYNC <= CFGLINKCONTROLEXTENDEDSYNC_v6pcie38;
1449
   CFGLINKCONTROLHWAUTOWIDTHDIS <= CFGLINKCONTROLHWAUTOWIDTHDIS_v6pcie39;
1450
   CFGLINKCONTROLLINKDISABLE <= CFGLINKCONTROLLINKDISABLE_v6pcie40;
1451
   CFGLINKCONTROLRETRAINLINK <= CFGLINKCONTROLRETRAINLINK_v6pcie42;
1452
   CFGLINKSTATUSAUTOBANDWIDTHSTATUS <= CFGLINKSTATUSAUTOBANDWIDTHSTATUS_v6pcie43;
1453
   CFGLINKSTATUSBANDWITHSTATUS <= CFGLINKSTATUSBANDWITHSTATUS_v6pcie44;
1454
   CFGLINKSTATUSCURRENTSPEED <= CFGLINKSTATUSCURRENTSPEED_v6pcie45;
1455
   CFGLINKSTATUSDLLACTIVE <= CFGLINKSTATUSDLLACTIVE_v6pcie46;
1456
   CFGLINKSTATUSLINKTRAINING <= CFGLINKSTATUSLINKTRAINING_v6pcie47;
1457
   CFGLINKSTATUSNEGOTIATEDWIDTH <= CFGLINKSTATUSNEGOTIATEDWIDTH_v6pcie48;
1458
   CFGMSGDATA <= CFGMSGDATA_v6pcie49;
1459
   CFGMSGRECEIVED <= CFGMSGRECEIVED_v6pcie50;
1460
   CFGMSGRECEIVEDASSERTINTA <= CFGMSGRECEIVEDASSERTINTA_v6pcie51;
1461
   CFGMSGRECEIVEDASSERTINTB <= CFGMSGRECEIVEDASSERTINTB_v6pcie52;
1462
   CFGMSGRECEIVEDASSERTINTC <= CFGMSGRECEIVEDASSERTINTC_v6pcie53;
1463
   CFGMSGRECEIVEDASSERTINTD <= CFGMSGRECEIVEDASSERTINTD_v6pcie54;
1464
   CFGMSGRECEIVEDDEASSERTINTA <= CFGMSGRECEIVEDDEASSERTINTA_v6pcie55;
1465
   CFGMSGRECEIVEDDEASSERTINTB <= CFGMSGRECEIVEDDEASSERTINTB_v6pcie56;
1466
   CFGMSGRECEIVEDDEASSERTINTC <= CFGMSGRECEIVEDDEASSERTINTC_v6pcie57;
1467
   CFGMSGRECEIVEDDEASSERTINTD <= CFGMSGRECEIVEDDEASSERTINTD_v6pcie58;
1468
   CFGMSGRECEIVEDERRCOR <= CFGMSGRECEIVEDERRCOR_v6pcie59;
1469
   CFGMSGRECEIVEDERRFATAL <= CFGMSGRECEIVEDERRFATAL_v6pcie60;
1470
   CFGMSGRECEIVEDERRNONFATAL <= CFGMSGRECEIVEDERRNONFATAL_v6pcie61;
1471
   CFGMSGRECEIVEDPMASNAK <= CFGMSGRECEIVEDPMASNAK_v6pcie62;
1472
   CFGMSGRECEIVEDPMETO <= CFGMSGRECEIVEDPMETO_v6pcie63;
1473
   CFGMSGRECEIVEDPMETOACK <= CFGMSGRECEIVEDPMETOACK_v6pcie64;
1474
   CFGMSGRECEIVEDPMPME <= CFGMSGRECEIVEDPMPME_v6pcie65;
1475
   CFGMSGRECEIVEDSETSLOTPOWERLIMIT <= CFGMSGRECEIVEDSETSLOTPOWERLIMIT_v6pcie66;
1476
   CFGMSGRECEIVEDUNLOCK <= CFGMSGRECEIVEDUNLOCK_v6pcie67;
1477
   CFGPCIELINKSTATE <= CFGPCIELINKSTATE_v6pcie68;
1478
   CFGPMCSRPMEEN <= CFGPMCSRPMEEN_v6pcie69;
1479
   CFGPMCSRPMESTATUS <= CFGPMCSRPMESTATUS_v6pcie70;
1480
   CFGPMCSRPOWERSTATE <= CFGPMCSRPOWERSTATE_v6pcie71;
1481
   CFGPMRCVASREQL1N <= CFGPMRCVASREQL1N_v6pcie72;
1482
   CFGPMRCVENTERL1N <= CFGPMRCVENTERL1N_v6pcie73;
1483
   CFGPMRCVENTERL23N <= CFGPMRCVENTERL23N_v6pcie74;
1484
   CFGPMRCVREQACKN <= CFGPMRCVREQACKN_v6pcie75;
1485
   CFGRDWRDONEN <= CFGRDWRDONEN_v6pcie76;
1486
   CFGSLOTCONTROLELECTROMECHILCTLPULSE <= CFGSLOTCONTROLELECTROMECHILCTLPULSE_v6pcie77;
1487
   CFGTRANSACTION <= CFGTRANSACTION_v6pcie78;
1488
   CFGTRANSACTIONADDR <= CFGTRANSACTIONADDR_v6pcie79;
1489
   CFGTRANSACTIONTYPE <= CFGTRANSACTIONTYPE_v6pcie80;
1490
   CFGVCTCVCMAP <= CFGVCTCVCMAP_v6pcie81;
1491
   PLINITIALLINKWIDTH <= PLINITIALLINKWIDTH_v6pcie104;
1492
   PLLANEREVERSALMODE <= PLLANEREVERSALMODE_v6pcie105;
1493
   PLLINKGEN2CAP <= PLLINKGEN2CAP_v6pcie106;
1494
   PLLINKPARTNERGEN2SUPPORTED <= PLLINKPARTNERGEN2SUPPORTED_v6pcie107;
1495
   PLLINKUPCFGCAP <= PLLINKUPCFGCAP_v6pcie108;
1496
   PLLTSSMSTATE <= PLLTSSMSTATE_v6pcie109;
1497
   PLPHYLNKUPN <= PLPHYLNKUPN_v6pcie110;
1498
   PLRECEIVEDHOTRST <= PLRECEIVEDHOTRST_v6pcie111;
1499
   PLRXPMSTATE <= PLRXPMSTATE_v6pcie112;
1500
   PLSELLNKRATE <= PLSELLNKRATE_v6pcie113;
1501
   PLSELLNKWIDTH <= PLSELLNKWIDTH_v6pcie114;
1502
   PLTXPMSTATE <= PLTXPMSTATE_v6pcie115;
1503
   DBGSCLRA <= DBGSCLRA_v6pcie82;
1504
   DBGSCLRB <= DBGSCLRB_v6pcie83;
1505
   DBGSCLRC <= DBGSCLRC_v6pcie84;
1506
   DBGSCLRD <= DBGSCLRD_v6pcie85;
1507
   DBGSCLRE <= DBGSCLRE_v6pcie86;
1508
   DBGSCLRF <= DBGSCLRF_v6pcie87;
1509
   DBGSCLRG <= DBGSCLRG_v6pcie88;
1510
   DBGSCLRH <= DBGSCLRH_v6pcie89;
1511
   DBGSCLRI <= DBGSCLRI_v6pcie90;
1512
   DBGSCLRJ <= DBGSCLRJ_v6pcie91;
1513
   DBGSCLRK <= DBGSCLRK_v6pcie92;
1514
   DBGVECA <= DBGVECA_v6pcie93;
1515
   DBGVECB <= DBGVECB_v6pcie94;
1516
   DBGVECC <= DBGVECC_v6pcie95;
1517
   PLDBGVEC <= PLDBGVEC_v6pcie103;
1518
   PCIEDRPDO <= PCIEDRPDO_v6pcie98;
1519
   PCIEDRPDRDY <= PCIEDRPDRDY_v6pcie99;
1520
   GTPLLLOCK <= GTPLLLOCK_v6pcie96;
1521
   TxOutClk <= TxOutClk_v6pcie138;
1522
   LL2SENDASREQL1N <= '1';
1523
   LL2SENDENTERL1N <= '1';
1524
   LL2SENDENTERL23N <= '1';
1525
   LL2SUSPENDNOWN <= '1';
1526
   LL2TLPRCVN <= '1';
1527
   PL2DIRECTEDLSTATE <= "00000";
1528
 
1529
   -- Assignments to outputs
1530
 
1531
   PIPERX0CHARISK_v6pcie       <= "11" when (filter_pipe_upconfig_fix_3451 = '1') else
1532
                                  PIPERX0CHARISK;
1533
   PIPERX1CHARISK_v6pcie       <= "11" when (filter_pipe_upconfig_fix_3451 = '1') else
1534
                                  PIPERX1CHARISK;
1535
   PIPERX2CHARISK_v6pcie       <= "11" when (filter_pipe_upconfig_fix_3451 = '1') else
1536
                                  PIPERX2CHARISK;
1537
   PIPERX3CHARISK_v6pcie       <= "11" when (filter_pipe_upconfig_fix_3451 = '1') else
1538
                                  PIPERX3CHARISK;
1539
   PIPERX4CHARISK_v6pcie       <= "11" when (filter_pipe_upconfig_fix_3451 = '1') else
1540
                                  PIPERX4CHARISK;
1541
   PIPERX5CHARISK_v6pcie       <= "11" when (filter_pipe_upconfig_fix_3451 = '1') else
1542
                                  PIPERX5CHARISK;
1543
   PIPERX6CHARISK_v6pcie       <= "11" when (filter_pipe_upconfig_fix_3451 = '1') else
1544
                                  PIPERX6CHARISK;
1545
   PIPERX7CHARISK_v6pcie       <= "11" when (filter_pipe_upconfig_fix_3451 = '1') else
1546
                                  PIPERX7CHARISK;
1547
 
1548
   ---------------------------------------------------------
1549
   -- Virtex6 PCI Express Block Module
1550
   ---------------------------------------------------------
1551
 
1552
   pcie_block_i : PCIE_2_0
1553
      generic map (
1554
         AER_BASE_PTR                              => AER_BASE_PTR,
1555
         AER_CAP_ECRC_CHECK_CAPABLE                => AER_CAP_ECRC_CHECK_CAPABLE,
1556
         AER_CAP_ECRC_GEN_CAPABLE                  => AER_CAP_ECRC_GEN_CAPABLE,
1557
         AER_CAP_ID                                => AER_CAP_ID,
1558
         AER_CAP_INT_MSG_NUM_MSI                   => AER_CAP_INT_MSG_NUM_MSI,
1559
         AER_CAP_INT_MSG_NUM_MSIX                  => AER_CAP_INT_MSG_NUM_MSIX,
1560
         AER_CAP_NEXTPTR                           => AER_CAP_NEXTPTR,
1561
         AER_CAP_ON                                => AER_CAP_ON,
1562
         AER_CAP_PERMIT_ROOTERR_UPDATE             => AER_CAP_PERMIT_ROOTERR_UPDATE,
1563
         AER_CAP_VERSION                           => AER_CAP_VERSION,
1564
         ALLOW_X8_GEN2                             => ALLOW_X8_GEN2,
1565
         BAR0                                      => BAR0,
1566
         BAR1                                      => BAR1,
1567
         BAR2                                      => BAR2,
1568
         BAR3                                      => BAR3,
1569
         BAR4                                      => BAR4,
1570
         BAR5                                      => BAR5,
1571
         CAPABILITIES_PTR                          => CAPABILITIES_PTR,
1572
         CARDBUS_CIS_POINTER                       => CARDBUS_CIS_POINTER,
1573
         CLASS_CODE                                => CLASS_CODE,
1574
         CMD_INTX_IMPLEMENTED                      => CMD_INTX_IMPLEMENTED,
1575
         CPL_TIMEOUT_DISABLE_SUPPORTED             => CPL_TIMEOUT_DISABLE_SUPPORTED,
1576
         CPL_TIMEOUT_RANGES_SUPPORTED              => CPL_TIMEOUT_RANGES_SUPPORTED,
1577
         CRM_MODULE_RSTS                           => CRM_MODULE_RSTS,
1578
         DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE       => DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE,
1579
         DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE       => DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE,
1580
         DEV_CAP_ENDPOINT_L0S_LATENCY              => DEV_CAP_ENDPOINT_L0S_LATENCY,
1581
         DEV_CAP_ENDPOINT_L1_LATENCY               => DEV_CAP_ENDPOINT_L1_LATENCY,
1582
         DEV_CAP_EXT_TAG_SUPPORTED                 => DEV_CAP_EXT_TAG_SUPPORTED,
1583
         DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE      => DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE,
1584
         DEV_CAP_MAX_PAYLOAD_SUPPORTED             => DEV_CAP_MAX_PAYLOAD_SUPPORTED,
1585
         DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT         => DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT,
1586
         DEV_CAP_ROLE_BASED_ERROR                  => DEV_CAP_ROLE_BASED_ERROR,
1587
         DEV_CAP_RSVD_14_12                        => DEV_CAP_RSVD_14_12,
1588
         DEV_CAP_RSVD_17_16                        => DEV_CAP_RSVD_17_16,
1589
         DEV_CAP_RSVD_31_29                        => DEV_CAP_RSVD_31_29,
1590
         DEV_CONTROL_AUX_POWER_SUPPORTED           => DEV_CONTROL_AUX_POWER_SUPPORTED,
1591
         DEVICE_ID                                 => DEVICE_ID,
1592
         DISABLE_ASPM_L1_TIMER                     => DISABLE_ASPM_L1_TIMER,
1593
         DISABLE_BAR_FILTERING                     => DISABLE_BAR_FILTERING,
1594
         DISABLE_ID_CHECK                          => DISABLE_ID_CHECK,
1595
         DISABLE_LANE_REVERSAL                     => DISABLE_LANE_REVERSAL,
1596
         DISABLE_RX_TC_FILTER                      => DISABLE_RX_TC_FILTER,
1597
         DISABLE_SCRAMBLING                        => DISABLE_SCRAMBLING,
1598
         DNSTREAM_LINK_NUM                         => DNSTREAM_LINK_NUM,
1599
         DSN_BASE_PTR                              => DSN_BASE_PTR,
1600
         DSN_CAP_ID                                => DSN_CAP_ID,
1601
         DSN_CAP_NEXTPTR                           => DSN_CAP_NEXTPTR,
1602
         DSN_CAP_ON                                => DSN_CAP_ON,
1603
         DSN_CAP_VERSION                           => DSN_CAP_VERSION,
1604
         ENABLE_MSG_ROUTE                          => ENABLE_MSG_ROUTE,
1605
         ENABLE_RX_TD_ECRC_TRIM                    => ENABLE_RX_TD_ECRC_TRIM,
1606
         ENTER_RVRY_EI_L0                          => ENTER_RVRY_EI_L0,
1607
         EXPANSION_ROM                             => EXPANSION_ROM,
1608
         EXT_CFG_CAP_PTR                           => EXT_CFG_CAP_PTR,
1609
         EXT_CFG_XP_CAP_PTR                        => EXT_CFG_XP_CAP_PTR,
1610
         HEADER_TYPE                               => HEADER_TYPE,
1611
         INFER_EI                                  => INFER_EI,
1612
         INTERRUPT_PIN                             => INTERRUPT_PIN,
1613
         IS_SWITCH                                 => IS_SWITCH,
1614
         LAST_CONFIG_DWORD                         => LAST_CONFIG_DWORD,
1615
         LINK_CAP_ASPM_SUPPORT                     => LINK_CAP_ASPM_SUPPORT,
1616
         LINK_CAP_CLOCK_POWER_MANAGEMENT           => LINK_CAP_CLOCK_POWER_MANAGEMENT,
1617
         LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP    => LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP,
1618
         LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP  => LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP,
1619
         LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1     => LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1,
1620
         LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2     => LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2,
1621
         LINK_CAP_L0S_EXIT_LATENCY_GEN1            => LINK_CAP_L0S_EXIT_LATENCY_GEN1,
1622
         LINK_CAP_L0S_EXIT_LATENCY_GEN2            => LINK_CAP_L0S_EXIT_LATENCY_GEN2,
1623
         LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1      => LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1,
1624
         LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2      => LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2,
1625
         LINK_CAP_L1_EXIT_LATENCY_GEN1             => LINK_CAP_L1_EXIT_LATENCY_GEN1,
1626
         LINK_CAP_L1_EXIT_LATENCY_GEN2             => LINK_CAP_L1_EXIT_LATENCY_GEN2,
1627
         LINK_CAP_MAX_LINK_SPEED                   => LINK_CAP_MAX_LINK_SPEED,
1628
         LINK_CAP_MAX_LINK_WIDTH                   => LINK_CAP_MAX_LINK_WIDTH,
1629
         LINK_CAP_RSVD_23_22                       => LINK_CAP_RSVD_23_22,
1630
         LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE      => LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE,
1631
         LINK_CONTROL_RCB                          => LINK_CONTROL_RCB,
1632
         LINK_CTRL2_DEEMPHASIS                     => LINK_CTRL2_DEEMPHASIS,
1633
         LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE    => LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE,
1634
         LINK_CTRL2_TARGET_LINK_SPEED              => LINK_CTRL2_TARGET_LINK_SPEED,
1635
         LINK_STATUS_SLOT_CLOCK_CONFIG             => LINK_STATUS_SLOT_CLOCK_CONFIG,
1636
         LL_ACK_TIMEOUT                            => LL_ACK_TIMEOUT,
1637
         LL_ACK_TIMEOUT_EN                         => LL_ACK_TIMEOUT_EN,
1638
         LL_ACK_TIMEOUT_FUNC                       => LL_ACK_TIMEOUT_FUNC,
1639
         LL_REPLAY_TIMEOUT                         => LL_REPLAY_TIMEOUT,
1640
         LL_REPLAY_TIMEOUT_EN                      => LL_REPLAY_TIMEOUT_EN,
1641
         LL_REPLAY_TIMEOUT_FUNC                    => LL_REPLAY_TIMEOUT_FUNC,
1642
         LTSSM_MAX_LINK_WIDTH                      => LTSSM_MAX_LINK_WIDTH,
1643
         MSI_BASE_PTR                              => MSI_BASE_PTR,
1644
         MSI_CAP_ID                                => MSI_CAP_ID,
1645
         MSI_CAP_MULTIMSGCAP                       => MSI_CAP_MULTIMSGCAP,
1646
         MSI_CAP_MULTIMSG_EXTENSION                => MSI_CAP_MULTIMSG_EXTENSION,
1647
         MSI_CAP_NEXTPTR                           => MSI_CAP_NEXTPTR,
1648
         MSI_CAP_ON                                => MSI_CAP_ON,
1649
         MSI_CAP_PER_VECTOR_MASKING_CAPABLE        => MSI_CAP_PER_VECTOR_MASKING_CAPABLE,
1650
         MSI_CAP_64_BIT_ADDR_CAPABLE               => MSI_CAP_64_BIT_ADDR_CAPABLE,
1651
         MSIX_BASE_PTR                             => MSIX_BASE_PTR,
1652
         MSIX_CAP_ID                               => MSIX_CAP_ID,
1653
         MSIX_CAP_NEXTPTR                          => MSIX_CAP_NEXTPTR,
1654
         MSIX_CAP_ON                               => MSIX_CAP_ON,
1655
         MSIX_CAP_PBA_BIR                          => MSIX_CAP_PBA_BIR,
1656
         MSIX_CAP_PBA_OFFSET                       => MSIX_CAP_PBA_OFFSET,
1657
         MSIX_CAP_TABLE_BIR                        => MSIX_CAP_TABLE_BIR,
1658
         MSIX_CAP_TABLE_OFFSET                     => MSIX_CAP_TABLE_OFFSET,
1659
         MSIX_CAP_TABLE_SIZE                       => MSIX_CAP_TABLE_SIZE,
1660
         N_FTS_COMCLK_GEN1                         => N_FTS_COMCLK_GEN1,
1661
         N_FTS_COMCLK_GEN2                         => N_FTS_COMCLK_GEN2,
1662
         N_FTS_GEN1                                => N_FTS_GEN1,
1663
         N_FTS_GEN2                                => N_FTS_GEN2,
1664
         PCIE_BASE_PTR                             => PCIE_BASE_PTR,
1665
         PCIE_CAP_CAPABILITY_ID                    => PCIE_CAP_CAPABILITY_ID,
1666
         PCIE_CAP_CAPABILITY_VERSION               => PCIE_CAP_CAPABILITY_VERSION,
1667
         PCIE_CAP_DEVICE_PORT_TYPE                 => PCIE_CAP_DEVICE_PORT_TYPE,
1668
         PCIE_CAP_INT_MSG_NUM                      => PCIE_CAP_INT_MSG_NUM,
1669
         PCIE_CAP_NEXTPTR                          => PCIE_CAP_NEXTPTR,
1670
         PCIE_CAP_ON                               => PCIE_CAP_ON,
1671
         PCIE_CAP_RSVD_15_14                       => PCIE_CAP_RSVD_15_14,
1672
         PCIE_CAP_SLOT_IMPLEMENTED                 => PCIE_CAP_SLOT_IMPLEMENTED,
1673
         PCIE_REVISION                             => PCIE_REVISION,
1674
         PGL0_LANE                                 => PGL0_LANE,
1675
         PGL1_LANE                                 => PGL1_LANE,
1676
         PGL2_LANE                                 => PGL2_LANE,
1677
         PGL3_LANE                                 => PGL3_LANE,
1678
         PGL4_LANE                                 => PGL4_LANE,
1679
         PGL5_LANE                                 => PGL5_LANE,
1680
         PGL6_LANE                                 => PGL6_LANE,
1681
         PGL7_LANE                                 => PGL7_LANE,
1682
         PL_AUTO_CONFIG                            => PL_AUTO_CONFIG,
1683
         PL_FAST_TRAIN                             => PL_FAST_TRAIN,
1684
         PM_BASE_PTR                               => PM_BASE_PTR,
1685
         PM_CAP_AUXCURRENT                         => PM_CAP_AUXCURRENT,
1686
         PM_CAP_DSI                                => PM_CAP_DSI,
1687
         PM_CAP_D1SUPPORT                          => PM_CAP_D1SUPPORT,
1688
         PM_CAP_D2SUPPORT                          => PM_CAP_D2SUPPORT,
1689
         PM_CAP_ID                                 => PM_CAP_ID,
1690
         PM_CAP_NEXTPTR                            => PM_CAP_NEXTPTR,
1691
         PM_CAP_ON                                 => PM_CAP_ON,
1692
         PM_CAP_PME_CLOCK                          => PM_CAP_PME_CLOCK,
1693
         PM_CAP_PMESUPPORT                         => PM_CAP_PMESUPPORT,
1694
         PM_CAP_RSVD_04                            => PM_CAP_RSVD_04,
1695
         PM_CAP_VERSION                            => PM_CAP_VERSION,
1696
         PM_CSR_BPCCEN                             => PM_CSR_BPCCEN,
1697
         PM_CSR_B2B3                               => PM_CSR_B2B3,
1698
         PM_CSR_NOSOFTRST                          => PM_CSR_NOSOFTRST,
1699
         PM_DATA_SCALE0                            => PM_DATA_SCALE0,
1700
         PM_DATA_SCALE1                            => PM_DATA_SCALE1,
1701
         PM_DATA_SCALE2                            => PM_DATA_SCALE2,
1702
         PM_DATA_SCALE3                            => PM_DATA_SCALE3,
1703
         PM_DATA_SCALE4                            => PM_DATA_SCALE4,
1704
         PM_DATA_SCALE5                            => PM_DATA_SCALE5,
1705
         PM_DATA_SCALE6                            => PM_DATA_SCALE6,
1706
         PM_DATA_SCALE7                            => PM_DATA_SCALE7,
1707
         PM_DATA0                                  => PM_DATA0,
1708
         PM_DATA1                                  => PM_DATA1,
1709
         PM_DATA2                                  => PM_DATA2,
1710
         PM_DATA3                                  => PM_DATA3,
1711
         PM_DATA4                                  => PM_DATA4,
1712
         PM_DATA5                                  => PM_DATA5,
1713
         PM_DATA6                                  => PM_DATA6,
1714
         PM_DATA7                                  => PM_DATA7,
1715
         RECRC_CHK                                 => RECRC_CHK,
1716
         RECRC_CHK_TRIM                            => RECRC_CHK_TRIM,
1717
         REVISION_ID                               => REVISION_ID,
1718
         ROOT_CAP_CRS_SW_VISIBILITY                => ROOT_CAP_CRS_SW_VISIBILITY,
1719
         SELECT_DLL_IF                             => SELECT_DLL_IF,
1720
         SLOT_CAP_ATT_BUTTON_PRESENT               => SLOT_CAP_ATT_BUTTON_PRESENT,
1721
         SLOT_CAP_ATT_INDICATOR_PRESENT            => SLOT_CAP_ATT_INDICATOR_PRESENT,
1722
         SLOT_CAP_ELEC_INTERLOCK_PRESENT           => SLOT_CAP_ELEC_INTERLOCK_PRESENT,
1723
         SLOT_CAP_HOTPLUG_CAPABLE                  => SLOT_CAP_HOTPLUG_CAPABLE,
1724
         SLOT_CAP_HOTPLUG_SURPRISE                 => SLOT_CAP_HOTPLUG_SURPRISE,
1725
         SLOT_CAP_MRL_SENSOR_PRESENT               => SLOT_CAP_MRL_SENSOR_PRESENT,
1726
         SLOT_CAP_NO_CMD_COMPLETED_SUPPORT         => SLOT_CAP_NO_CMD_COMPLETED_SUPPORT,
1727
         SLOT_CAP_PHYSICAL_SLOT_NUM                => SLOT_CAP_PHYSICAL_SLOT_NUM,
1728
         SLOT_CAP_POWER_CONTROLLER_PRESENT         => SLOT_CAP_POWER_CONTROLLER_PRESENT,
1729
         SLOT_CAP_POWER_INDICATOR_PRESENT          => SLOT_CAP_POWER_INDICATOR_PRESENT,
1730
         SLOT_CAP_SLOT_POWER_LIMIT_SCALE           => SLOT_CAP_SLOT_POWER_LIMIT_SCALE,
1731
         SLOT_CAP_SLOT_POWER_LIMIT_VALUE           => SLOT_CAP_SLOT_POWER_LIMIT_VALUE,
1732
         SPARE_BIT0                                => SPARE_BIT0,
1733
         SPARE_BIT1                                => SPARE_BIT1,
1734
         SPARE_BIT2                                => SPARE_BIT2,
1735
         SPARE_BIT3                                => SPARE_BIT3,
1736
         SPARE_BIT4                                => SPARE_BIT4,
1737
         SPARE_BIT5                                => SPARE_BIT5,
1738
         SPARE_BIT6                                => SPARE_BIT6,
1739
         SPARE_BIT7                                => SPARE_BIT7,
1740
         SPARE_BIT8                                => SPARE_BIT8,
1741
         SPARE_BYTE0                               => SPARE_BYTE0,
1742
         SPARE_BYTE1                               => SPARE_BYTE1,
1743
         SPARE_BYTE2                               => SPARE_BYTE2,
1744
         SPARE_BYTE3                               => SPARE_BYTE3,
1745
         SPARE_WORD0                               => SPARE_WORD0,
1746
         SPARE_WORD1                               => SPARE_WORD1,
1747
         SPARE_WORD2                               => SPARE_WORD2,
1748
         SPARE_WORD3                               => SPARE_WORD3,
1749
         SUBSYSTEM_ID                              => SUBSYSTEM_ID,
1750
         SUBSYSTEM_VENDOR_ID                       => SUBSYSTEM_VENDOR_ID,
1751
         TL_RBYPASS                                => TL_RBYPASS,
1752
         TL_RX_RAM_RADDR_LATENCY                   => TL_RX_RAM_RADDR_LATENCY,
1753
         TL_RX_RAM_RDATA_LATENCY                   => TL_RX_RAM_RDATA_LATENCY,
1754
         TL_RX_RAM_WRITE_LATENCY                   => TL_RX_RAM_WRITE_LATENCY,
1755
         TL_TFC_DISABLE                            => TL_TFC_DISABLE,
1756
         TL_TX_CHECKS_DISABLE                      => TL_TX_CHECKS_DISABLE,
1757
         TL_TX_RAM_RADDR_LATENCY                   => TL_TX_RAM_RADDR_LATENCY,
1758
         TL_TX_RAM_RDATA_LATENCY                   => TL_TX_RAM_RDATA_LATENCY,
1759
         TL_TX_RAM_WRITE_LATENCY                   => TL_TX_RAM_WRITE_LATENCY,
1760
         UPCONFIG_CAPABLE                          => UPCONFIG_CAPABLE,
1761
         UPSTREAM_FACING                           => UPSTREAM_FACING,
1762
         EXIT_LOOPBACK_ON_EI                       => EXIT_LOOPBACK_ON_EI,
1763
         UR_INV_REQ                                => UR_INV_REQ,
1764
         USER_CLK_FREQ                             => USER_CLK_FREQ,
1765
         VC_BASE_PTR                               => VC_BASE_PTR,
1766
         VC_CAP_ID                                 => VC_CAP_ID,
1767
         VC_CAP_NEXTPTR                            => VC_CAP_NEXTPTR,
1768
         VC_CAP_ON                                 => VC_CAP_ON,
1769
         VC_CAP_REJECT_SNOOP_TRANSACTIONS          => VC_CAP_REJECT_SNOOP_TRANSACTIONS,
1770
         VC_CAP_VERSION                            => VC_CAP_VERSION,
1771
         VC0_CPL_INFINITE                          => VC0_CPL_INFINITE,
1772
         VC0_RX_RAM_LIMIT                          => VC0_RX_RAM_LIMIT,
1773
         VC0_TOTAL_CREDITS_CD                      => VC0_TOTAL_CREDITS_CD,
1774
         VC0_TOTAL_CREDITS_CH                      => VC0_TOTAL_CREDITS_CH,
1775
         VC0_TOTAL_CREDITS_NPH                     => VC0_TOTAL_CREDITS_NPH,
1776
         VC0_TOTAL_CREDITS_PD                      => VC0_TOTAL_CREDITS_PD,
1777
         VC0_TOTAL_CREDITS_PH                      => VC0_TOTAL_CREDITS_PH,
1778
         VC0_TX_LASTPACKET                         => VC0_TX_LASTPACKET,
1779
         VENDOR_ID                                 => VENDOR_ID,
1780
         VSEC_BASE_PTR                             => VSEC_BASE_PTR,
1781
         VSEC_CAP_HDR_ID                           => VSEC_CAP_HDR_ID,
1782
         VSEC_CAP_HDR_LENGTH                       => VSEC_CAP_HDR_LENGTH,
1783
         VSEC_CAP_HDR_REVISION                     => VSEC_CAP_HDR_REVISION,
1784
         VSEC_CAP_ID                               => VSEC_CAP_ID,
1785
         VSEC_CAP_IS_LINK_VISIBLE                  => VSEC_CAP_IS_LINK_VISIBLE,
1786
         VSEC_CAP_NEXTPTR                          => VSEC_CAP_NEXTPTR,
1787
         VSEC_CAP_ON                               => VSEC_CAP_ON,
1788
         VSEC_CAP_VERSION                          => VSEC_CAP_VERSION
1789
      )
1790
      port map (
1791
         CFGAERECRCCHECKEN                    => CFGAERECRCCHECKEN_v6pcie0,
1792
         CFGAERECRCGENEN                      => CFGAERECRCGENEN_v6pcie1,
1793
         CFGCOMMANDBUSMASTERENABLE            => CFGCOMMANDBUSMASTERENABLE_v6pcie2,
1794
         CFGCOMMANDINTERRUPTDISABLE           => CFGCOMMANDINTERRUPTDISABLE_v6pcie3,
1795
         CFGCOMMANDIOENABLE                   => CFGCOMMANDIOENABLE_v6pcie4,
1796
         CFGCOMMANDMEMENABLE                  => CFGCOMMANDMEMENABLE_v6pcie5,
1797
         CFGCOMMANDSERREN                     => CFGCOMMANDSERREN_v6pcie6,
1798
         CFGDEVCONTROLAUXPOWEREN              => CFGDEVCONTROLAUXPOWEREN_v6pcie9,
1799
         CFGDEVCONTROLCORRERRREPORTINGEN      => CFGDEVCONTROLCORRERRREPORTINGEN_v6pcie10,
1800
         CFGDEVCONTROLENABLERO                => CFGDEVCONTROLENABLERO_v6pcie11,
1801
         CFGDEVCONTROLEXTTAGEN                => CFGDEVCONTROLEXTTAGEN_v6pcie12,
1802
         CFGDEVCONTROLFATALERRREPORTINGEN     => CFGDEVCONTROLFATALERRREPORTINGEN_v6pcie13,
1803
         CFGDEVCONTROLMAXPAYLOAD              => CFGDEVCONTROLMAXPAYLOAD_v6pcie14,
1804
         CFGDEVCONTROLMAXREADREQ              => CFGDEVCONTROLMAXREADREQ_v6pcie15,
1805
         CFGDEVCONTROLNONFATALREPORTINGEN     => CFGDEVCONTROLNONFATALREPORTINGEN_v6pcie16,
1806
         CFGDEVCONTROLNOSNOOPEN               => CFGDEVCONTROLNOSNOOPEN_v6pcie17,
1807
         CFGDEVCONTROLPHANTOMEN               => CFGDEVCONTROLPHANTOMEN_v6pcie18,
1808
         CFGDEVCONTROLURERRREPORTINGEN        => CFGDEVCONTROLURERRREPORTINGEN_v6pcie19,
1809
         CFGDEVCONTROL2CPLTIMEOUTDIS          => CFGDEVCONTROL2CPLTIMEOUTDIS_v6pcie7,
1810
         CFGDEVCONTROL2CPLTIMEOUTVAL          => CFGDEVCONTROL2CPLTIMEOUTVAL_v6pcie8,
1811
         CFGDEVSTATUSCORRERRDETECTED          => CFGDEVSTATUSCORRERRDETECTED_v6pcie20,
1812
         CFGDEVSTATUSFATALERRDETECTED         => CFGDEVSTATUSFATALERRDETECTED_v6pcie21,
1813
         CFGDEVSTATUSNONFATALERRDETECTED      => CFGDEVSTATUSNONFATALERRDETECTED_v6pcie22,
1814
         CFGDEVSTATUSURDETECTED               => CFGDEVSTATUSURDETECTED_v6pcie23,
1815
         CFGDO                                => CFGDO_v6pcie24,
1816
         CFGERRAERHEADERLOGSETN               => CFGERRAERHEADERLOGSETN_v6pcie25,
1817
         CFGERRCPLRDYN                        => CFGERRCPLRDYN_v6pcie26,
1818
         CFGINTERRUPTDO                       => CFGINTERRUPTDO_v6pcie27,
1819
         CFGINTERRUPTMMENABLE                 => CFGINTERRUPTMMENABLE_v6pcie28,
1820
         CFGINTERRUPTMSIENABLE                => CFGINTERRUPTMSIENABLE_v6pcie29,
1821
         CFGINTERRUPTMSIXENABLE               => CFGINTERRUPTMSIXENABLE_v6pcie30,
1822
         CFGINTERRUPTMSIXFM                   => CFGINTERRUPTMSIXFM_v6pcie31,
1823
         CFGINTERRUPTRDYN                     => CFGINTERRUPTRDYN_v6pcie32,
1824
         CFGLINKCONTROLRCB                    => CFGLINKCONTROLRCB_v6pcie41,
1825
         CFGLINKCONTROLASPMCONTROL            => CFGLINKCONTROLASPMCONTROL_v6pcie33,
1826
         CFGLINKCONTROLAUTOBANDWIDTHINTEN     => CFGLINKCONTROLAUTOBANDWIDTHINTEN_v6pcie34,
1827
         CFGLINKCONTROLBANDWIDTHINTEN         => CFGLINKCONTROLBANDWIDTHINTEN_v6pcie35,
1828
         CFGLINKCONTROLCLOCKPMEN              => CFGLINKCONTROLCLOCKPMEN_v6pcie36,
1829
         CFGLINKCONTROLCOMMONCLOCK            => CFGLINKCONTROLCOMMONCLOCK_v6pcie37,
1830
         CFGLINKCONTROLEXTENDEDSYNC           => CFGLINKCONTROLEXTENDEDSYNC_v6pcie38,
1831
         CFGLINKCONTROLHWAUTOWIDTHDIS         => CFGLINKCONTROLHWAUTOWIDTHDIS_v6pcie39,
1832
         CFGLINKCONTROLLINKDISABLE            => CFGLINKCONTROLLINKDISABLE_v6pcie40,
1833
         CFGLINKCONTROLRETRAINLINK            => CFGLINKCONTROLRETRAINLINK_v6pcie42,
1834
         CFGLINKSTATUSAUTOBANDWIDTHSTATUS     => CFGLINKSTATUSAUTOBANDWIDTHSTATUS_v6pcie43,
1835
         CFGLINKSTATUSBANDWITHSTATUS          => CFGLINKSTATUSBANDWITHSTATUS_v6pcie44,
1836
         CFGLINKSTATUSCURRENTSPEED            => CFGLINKSTATUSCURRENTSPEED_v6pcie45,
1837
         CFGLINKSTATUSDLLACTIVE               => CFGLINKSTATUSDLLACTIVE_v6pcie46,
1838
         CFGLINKSTATUSLINKTRAINING            => CFGLINKSTATUSLINKTRAINING_v6pcie47,
1839
         CFGLINKSTATUSNEGOTIATEDWIDTH         => CFGLINKSTATUSNEGOTIATEDWIDTH_v6pcie48,
1840
         CFGMSGDATA                           => CFGMSGDATA_v6pcie49,
1841
         CFGMSGRECEIVED                       => CFGMSGRECEIVED_v6pcie50,
1842
         CFGMSGRECEIVEDASSERTINTA             => CFGMSGRECEIVEDASSERTINTA_v6pcie51,
1843
         CFGMSGRECEIVEDASSERTINTB             => CFGMSGRECEIVEDASSERTINTB_v6pcie52,
1844
         CFGMSGRECEIVEDASSERTINTC             => CFGMSGRECEIVEDASSERTINTC_v6pcie53,
1845
         CFGMSGRECEIVEDASSERTINTD             => CFGMSGRECEIVEDASSERTINTD_v6pcie54,
1846
         CFGMSGRECEIVEDDEASSERTINTA           => CFGMSGRECEIVEDDEASSERTINTA_v6pcie55,
1847
         CFGMSGRECEIVEDDEASSERTINTB           => CFGMSGRECEIVEDDEASSERTINTB_v6pcie56,
1848
         CFGMSGRECEIVEDDEASSERTINTC           => CFGMSGRECEIVEDDEASSERTINTC_v6pcie57,
1849
         CFGMSGRECEIVEDDEASSERTINTD           => CFGMSGRECEIVEDDEASSERTINTD_v6pcie58,
1850
         CFGMSGRECEIVEDERRCOR                 => CFGMSGRECEIVEDERRCOR_v6pcie59,
1851
         CFGMSGRECEIVEDERRFATAL               => CFGMSGRECEIVEDERRFATAL_v6pcie60,
1852
         CFGMSGRECEIVEDERRNONFATAL            => CFGMSGRECEIVEDERRNONFATAL_v6pcie61,
1853
         CFGMSGRECEIVEDPMASNAK                => CFGMSGRECEIVEDPMASNAK_v6pcie62,
1854
         CFGMSGRECEIVEDPMETO                  => CFGMSGRECEIVEDPMETO_v6pcie63,
1855
         CFGMSGRECEIVEDPMETOACK               => CFGMSGRECEIVEDPMETOACK_v6pcie64,
1856
         CFGMSGRECEIVEDPMPME                  => CFGMSGRECEIVEDPMPME_v6pcie65,
1857
         CFGMSGRECEIVEDSETSLOTPOWERLIMIT      => CFGMSGRECEIVEDSETSLOTPOWERLIMIT_v6pcie66,
1858
         CFGMSGRECEIVEDUNLOCK                 => CFGMSGRECEIVEDUNLOCK_v6pcie67,
1859
         CFGPCIELINKSTATE                     => CFGPCIELINKSTATE_v6pcie68,
1860
         CFGPMRCVASREQL1N                     => CFGPMRCVASREQL1N_v6pcie72,
1861
         CFGPMRCVENTERL1N                     => CFGPMRCVENTERL1N_v6pcie73,
1862
         CFGPMRCVENTERL23N                    => CFGPMRCVENTERL23N_v6pcie74,
1863
         CFGPMRCVREQACKN                      => CFGPMRCVREQACKN_v6pcie75,
1864
         CFGPMCSRPMEEN                        => CFGPMCSRPMEEN_v6pcie69,
1865
         CFGPMCSRPMESTATUS                    => CFGPMCSRPMESTATUS_v6pcie70,
1866
         CFGPMCSRPOWERSTATE                   => CFGPMCSRPOWERSTATE_v6pcie71,
1867
         CFGRDWRDONEN                         => CFGRDWRDONEN_v6pcie76,
1868
         CFGSLOTCONTROLELECTROMECHILCTLPULSE  => CFGSLOTCONTROLELECTROMECHILCTLPULSE_v6pcie77,
1869
         CFGTRANSACTION                       => CFGTRANSACTION_v6pcie78,
1870
         CFGTRANSACTIONADDR                   => CFGTRANSACTIONADDR_v6pcie79,
1871
         CFGTRANSACTIONTYPE                   => CFGTRANSACTIONTYPE_v6pcie80,
1872
         CFGVCTCVCMAP                         => CFGVCTCVCMAP_v6pcie81,
1873
         DBGSCLRA                             => DBGSCLRA_v6pcie82,
1874
         DBGSCLRB                             => DBGSCLRB_v6pcie83,
1875
         DBGSCLRC                             => DBGSCLRC_v6pcie84,
1876
         DBGSCLRD                             => DBGSCLRD_v6pcie85,
1877
         DBGSCLRE                             => DBGSCLRE_v6pcie86,
1878
         DBGSCLRF                             => DBGSCLRF_v6pcie87,
1879
         DBGSCLRG                             => DBGSCLRG_v6pcie88,
1880
         DBGSCLRH                             => DBGSCLRH_v6pcie89,
1881
         DBGSCLRI                             => DBGSCLRI_v6pcie90,
1882
         DBGSCLRJ                             => DBGSCLRJ_v6pcie91,
1883
         DBGSCLRK                             => DBGSCLRK_v6pcie92,
1884
         DBGVECA                              => DBGVECA_v6pcie93,
1885
         DBGVECB                              => DBGVECB_v6pcie94,
1886
         DBGVECC                              => DBGVECC_v6pcie95,
1887
         DRPDO                                => PCIEDRPDO_v6pcie98,
1888
         DRPDRDY                              => PCIEDRPDRDY_v6pcie99,
1889
         LL2BADDLLPERRN                       => LL2BADDLLPERRN,
1890
         LL2BADTLPERRN                        => LL2BADTLPERRN,
1891
         LL2PROTOCOLERRN                      => LL2PROTOCOLERRN,
1892
         LL2REPLAYROERRN                      => LL2REPLAYROERRN,
1893
         LL2REPLAYTOERRN                      => LL2REPLAYTOERRN,
1894
         LL2SUSPENDOKN                        => LL2SUSPENDOKN,
1895
         LL2TFCINIT1SEQN                      => LL2TFCINIT1SEQN,
1896
         LL2TFCINIT2SEQN                      => LL2TFCINIT2SEQN,
1897
         MIMRXRADDR                           => MIMRXRADDR,
1898
         MIMRXRCE                             => MIMRXRCE,
1899
         MIMRXREN                             => MIMRXREN,
1900
         MIMRXWADDR                           => MIMRXWADDR,
1901
         MIMRXWDATA                           => MIMRXWDATA,
1902
         MIMRXWEN                             => MIMRXWEN,
1903
         MIMTXRADDR                           => MIMTXRADDR,
1904
         MIMTXRCE                             => MIMTXRCE,
1905
         MIMTXREN                             => MIMTXREN,
1906
         MIMTXWADDR                           => MIMTXWADDR,
1907
         MIMTXWDATA                           => MIMTXWDATA,
1908
         MIMTXWEN                             => MIMTXWEN,
1909
         PIPERX0POLARITY                      => PIPERX0POLARITY,
1910
         PIPERX1POLARITY                      => PIPERX1POLARITY,
1911
         PIPERX2POLARITY                      => PIPERX2POLARITY,
1912
         PIPERX3POLARITY                      => PIPERX3POLARITY,
1913
         PIPERX4POLARITY                      => PIPERX4POLARITY,
1914
         PIPERX5POLARITY                      => PIPERX5POLARITY,
1915
         PIPERX6POLARITY                      => PIPERX6POLARITY,
1916
         PIPERX7POLARITY                      => PIPERX7POLARITY,
1917
         PIPETXDEEMPH                         => PIPETXDEEMPH,
1918
         PIPETXMARGIN                         => PIPETXMARGIN,
1919
         PIPETXRATE                           => PIPETXRATE,
1920
         PIPETXRCVRDET                        => PIPETXRCVRDET,
1921
         PIPETXRESET                          => PIPETXRESET,
1922
         PIPETX0CHARISK                       => PIPETX0CHARISK,
1923
         PIPETX0COMPLIANCE                    => PIPETX0COMPLIANCE,
1924
         PIPETX0DATA                          => PIPETX0DATA,
1925
         PIPETX0ELECIDLE                      => PIPETX0ELECIDLE,
1926
         PIPETX0POWERDOWN                     => PIPETX0POWERDOWN,
1927
         PIPETX1CHARISK                       => PIPETX1CHARISK,
1928
         PIPETX1COMPLIANCE                    => PIPETX1COMPLIANCE,
1929
         PIPETX1DATA                          => PIPETX1DATA,
1930
         PIPETX1ELECIDLE                      => PIPETX1ELECIDLE,
1931
         PIPETX1POWERDOWN                     => PIPETX1POWERDOWN,
1932
         PIPETX2CHARISK                       => PIPETX2CHARISK,
1933
         PIPETX2COMPLIANCE                    => PIPETX2COMPLIANCE,
1934
         PIPETX2DATA                          => PIPETX2DATA,
1935
         PIPETX2ELECIDLE                      => PIPETX2ELECIDLE,
1936
         PIPETX2POWERDOWN                     => PIPETX2POWERDOWN,
1937
         PIPETX3CHARISK                       => PIPETX3CHARISK,
1938
         PIPETX3COMPLIANCE                    => PIPETX3COMPLIANCE,
1939
         PIPETX3DATA                          => PIPETX3DATA,
1940
         PIPETX3ELECIDLE                      => PIPETX3ELECIDLE,
1941
         PIPETX3POWERDOWN                     => PIPETX3POWERDOWN,
1942
         PIPETX4CHARISK                       => PIPETX4CHARISK,
1943
         PIPETX4COMPLIANCE                    => PIPETX4COMPLIANCE,
1944
         PIPETX4DATA                          => PIPETX4DATA,
1945
         PIPETX4ELECIDLE                      => PIPETX4ELECIDLE,
1946
         PIPETX4POWERDOWN                     => PIPETX4POWERDOWN,
1947
         PIPETX5CHARISK                       => PIPETX5CHARISK,
1948
         PIPETX5COMPLIANCE                    => PIPETX5COMPLIANCE,
1949
         PIPETX5DATA                          => PIPETX5DATA,
1950
         PIPETX5ELECIDLE                      => PIPETX5ELECIDLE,
1951
         PIPETX5POWERDOWN                     => PIPETX5POWERDOWN,
1952
         PIPETX6CHARISK                       => PIPETX6CHARISK,
1953
         PIPETX6COMPLIANCE                    => PIPETX6COMPLIANCE,
1954
         PIPETX6DATA                          => PIPETX6DATA,
1955
         PIPETX6ELECIDLE                      => PIPETX6ELECIDLE,
1956
         PIPETX6POWERDOWN                     => PIPETX6POWERDOWN,
1957
         PIPETX7CHARISK                       => PIPETX7CHARISK,
1958
         PIPETX7COMPLIANCE                    => PIPETX7COMPLIANCE,
1959
         PIPETX7DATA                          => PIPETX7DATA,
1960
         PIPETX7ELECIDLE                      => PIPETX7ELECIDLE,
1961
         PIPETX7POWERDOWN                     => PIPETX7POWERDOWN,
1962
         PLDBGVEC                             => PLDBGVEC_v6pcie103,
1963
         PLINITIALLINKWIDTH                   => PLINITIALLINKWIDTH_v6pcie104,
1964
         PLLANEREVERSALMODE                   => PLLANEREVERSALMODE_v6pcie105,
1965
         PLLINKGEN2CAP                        => PLLINKGEN2CAP_v6pcie106,
1966
         PLLINKPARTNERGEN2SUPPORTED           => PLLINKPARTNERGEN2SUPPORTED_v6pcie107,
1967
         PLLINKUPCFGCAP                       => PLLINKUPCFGCAP_v6pcie108,
1968
         PLLTSSMSTATE                         => PLLTSSMSTATE_v6pcie109,
1969
         PLPHYLNKUPN                          => PLPHYLNKUPN_v6pcie110,
1970
         PLRECEIVEDHOTRST                     => PLRECEIVEDHOTRST_v6pcie111,
1971
         PLRXPMSTATE                          => PLRXPMSTATE_v6pcie112,
1972
         PLSELLNKRATE                         => PLSELLNKRATE_v6pcie113,
1973
         PLSELLNKWIDTH                        => PLSELLNKWIDTH_v6pcie114,
1974
         PLTXPMSTATE                          => PLTXPMSTATE_v6pcie115,
1975
         PL2LINKUPN                           => PL2LINKUPN,
1976
         PL2RECEIVERERRN                      => PL2RECEIVERERRN,
1977
         PL2RECOVERYN                         => PL2RECOVERYN,
1978
         PL2RXELECIDLE                        => PL2RXELECIDLE,
1979
         PL2SUSPENDOK                         => PL2SUSPENDOK,
1980
         RECEIVEDFUNCLVLRSTN                  => RECEIVEDFUNCLVLRSTN_v6pcie116,
1981
         LNKCLKEN                             => LNKCLKEN_v6pcie97,
1982
         TL2ASPMSUSPENDCREDITCHECKOKN         => TL2ASPMSUSPENDCREDITCHECKOKN,
1983
         TL2ASPMSUSPENDREQN                   => TL2ASPMSUSPENDREQN,
1984
         TL2PPMSUSPENDOKN                     => TL2PPMSUSPENDOKN,
1985
         TRNFCCPLD                            => TRNFCCPLD_v6pcie117,
1986
         TRNFCCPLH                            => TRNFCCPLH_v6pcie118,
1987
         TRNFCNPD                             => TRNFCNPD_v6pcie119,
1988
         TRNFCNPH                             => TRNFCNPH_v6pcie120,
1989
         TRNFCPD                              => TRNFCPD_v6pcie121,
1990
         TRNFCPH                              => TRNFCPH_v6pcie122,
1991
         TRNLNKUPN                            => TRNLNKUPN_v6pcie123,
1992
         TRNRBARHITN                          => TRNRBARHITN_v6pcie124,
1993
         TRNRD                                => TRNRD_v6pcie125,
1994
         TRNRDLLPDATA                         => TRNRDLLPDATA,
1995
         TRNRDLLPSRCRDYN                      => TRNRDLLPSRCRDYN,
1996
         TRNRECRCERRN                         => TRNRECRCERRN_v6pcie126,
1997
         TRNREOFN                             => TRNREOFN_v6pcie127,
1998
         TRNRERRFWDN                          => TRNRERRFWDN_v6pcie128,
1999
         TRNRREMN                             => TRNRREMN_v6pcie129,
2000
         TRNRSOFN                             => TRNRSOFN_v6pcie130,
2001
         TRNRSRCDSCN                          => TRNRSRCDSCN_v6pcie131,
2002
         TRNRSRCRDYN                          => TRNRSRCRDYN_v6pcie132,
2003
         TRNTBUFAV                            => TRNTBUFAV_v6pcie133,
2004
         TRNTCFGREQN                          => TRNTCFGREQN_v6pcie134,
2005
 
2006
         TRNTDLLPDSTRDYN                      => TRNTDLLPDSTRDYN_v6pcie135,
2007
         TRNTDSTRDYN                          => TRNTDSTRDYN_v6pcie136,
2008
         TRNTERRDROPN                         => TRNTERRDROPN_v6pcie137,
2009
 
2010
         USERRSTN                             => USERRSTN_v6pcie139,
2011
 
2012
         CFGBYTEENN                           => CFGBYTEENN,
2013
         CFGDI                                => CFGDI,
2014
 
2015
         CFGDSBUSNUMBER                       => CFGDSBUSNUMBER,
2016
         CFGDSDEVICENUMBER                    => CFGDSDEVICENUMBER,
2017
 
2018
         CFGDSFUNCTIONNUMBER                  => CFGDSFUNCTIONNUMBER,
2019
         CFGDSN                               => CFGDSN,
2020
         CFGDWADDR                            => CFGDWADDR,
2021
         CFGERRACSN                           => CFGERRACSN,
2022
 
2023
         CFGERRAERHEADERLOG                   => CFGERRAERHEADERLOG,
2024
         CFGERRCORN                           => CFGERRCORN,
2025
         CFGERRCPLABORTN                      => CFGERRCPLABORTN,
2026
         CFGERRCPLTIMEOUTN                    => CFGERRCPLTIMEOUTN,
2027
         CFGERRCPLUNEXPECTN                   => CFGERRCPLUNEXPECTN,
2028
         CFGERRECRCN                          => CFGERRECRCN,
2029
         CFGERRLOCKEDN                        => CFGERRLOCKEDN,
2030
         CFGERRPOSTEDN                        => CFGERRPOSTEDN,
2031
         CFGERRTLPCPLHEADER                   => CFGERRTLPCPLHEADER,
2032
         CFGERRURN                            => CFGERRURN,
2033
         CFGINTERRUPTASSERTN                  => CFGINTERRUPTASSERTN,
2034
         CFGINTERRUPTDI                       => CFGINTERRUPTDI,
2035
         CFGINTERRUPTN                        => CFGINTERRUPTN,
2036
         CFGPMDIRECTASPML1N                   => CFGPMDIRECTASPML1N,
2037
         CFGPMSENDPMACKN                      => CFGPMSENDPMACKN,
2038
         CFGPMSENDPMETON                      => CFGPMSENDPMETON,
2039
         CFGPMSENDPMNAKN                      => CFGPMSENDPMNAKN,
2040
         CFGPMTURNOFFOKN                      => CFGPMTURNOFFOKN,
2041
         CFGPMWAKEN                           => CFGPMWAKEN,
2042
         CFGPORTNUMBER                        => CFGPORTNUMBER,
2043
         CFGRDENN                             => CFGRDENN,
2044
         CFGTRNPENDINGN                       => CFGTRNPENDINGN,
2045
         CFGWRENN                             => CFGWRENN,
2046
         CFGWRREADONLYN                       => CFGWRREADONLYN,
2047
         CFGWRRW1CASRWN                       => CFGWRRW1CASRWN,
2048
         CMRSTN                               => CMRSTN,
2049
         CMSTICKYRSTN                         => CMSTICKYRSTN,
2050
         DBGMODE                              => DBGMODE,
2051
         DBGSUBMODE                           => DBGSUBMODE,
2052
         DLRSTN                               => DLRSTN,
2053
         DRPCLK                               => PCIEDRPCLK,
2054
         DRPDADDR                             => PCIEDRPDADDR,
2055
         DRPDEN                               => PCIEDRPDEN,
2056
         DRPDI                                => PCIEDRPDI,
2057
         DRPDWE                               => PCIEDRPDWE,
2058
         FUNCLVLRSTN                          => FUNCLVLRSTN,
2059
         LL2SENDASREQL1N                      => LL2SENDASREQL1N,
2060
         LL2SENDENTERL1N                      => LL2SENDENTERL1N,
2061
         LL2SENDENTERL23N                     => LL2SENDENTERL23N,
2062
         LL2SUSPENDNOWN                       => LL2SUSPENDNOWN,
2063
         LL2TLPRCVN                           => LL2TLPRCVN,
2064
         MIMRXRDATA                           => MIMRXRDATA(67 downto 0),
2065
         MIMTXRDATA                           => MIMTXRDATA(68 downto 0),
2066
         PIPECLK                              => PIPECLK,
2067
         PIPERX0CHANISALIGNED                 => PIPERX0CHANISALIGNED,
2068
         PIPERX0CHARISK                       => PIPERX0CHARISK_v6pcie,
2069
         PIPERX0DATA                          => PIPERX0DATA,
2070
         PIPERX0ELECIDLE                      => PIPERX0ELECIDLE,
2071
         PIPERX0PHYSTATUS                     => PIPERX0PHYSTATUS,
2072
         PIPERX0STATUS                        => PIPERX0STATUS,
2073
         PIPERX0VALID                         => PIPERX0VALID,
2074
         PIPERX1CHANISALIGNED                 => PIPERX1CHANISALIGNED,
2075
         PIPERX1CHARISK                       => PIPERX1CHARISK_v6pcie,
2076
         PIPERX1DATA                          => PIPERX1DATA,
2077
         PIPERX1ELECIDLE                      => PIPERX1ELECIDLE,
2078
         PIPERX1PHYSTATUS                     => PIPERX1PHYSTATUS,
2079
         PIPERX1STATUS                        => PIPERX1STATUS,
2080
         PIPERX1VALID                         => PIPERX1VALID,
2081
         PIPERX2CHANISALIGNED                 => PIPERX2CHANISALIGNED,
2082
         PIPERX2CHARISK                       => PIPERX2CHARISK_v6pcie,
2083
         PIPERX2DATA                          => PIPERX2DATA,
2084
         PIPERX2ELECIDLE                      => PIPERX2ELECIDLE,
2085
         PIPERX2PHYSTATUS                     => PIPERX2PHYSTATUS,
2086
         PIPERX2STATUS                        => PIPERX2STATUS,
2087
         PIPERX2VALID                         => PIPERX2VALID,
2088
         PIPERX3CHANISALIGNED                 => PIPERX3CHANISALIGNED,
2089
         PIPERX3CHARISK                       => PIPERX3CHARISK_v6pcie,
2090
         PIPERX3DATA                          => PIPERX3DATA,
2091
         PIPERX3ELECIDLE                      => PIPERX3ELECIDLE,
2092
         PIPERX3PHYSTATUS                     => PIPERX3PHYSTATUS,
2093
         PIPERX3STATUS                        => PIPERX3STATUS,
2094
         PIPERX3VALID                         => PIPERX3VALID,
2095
         PIPERX4CHANISALIGNED                 => PIPERX4CHANISALIGNED,
2096
         PIPERX4CHARISK                       => PIPERX4CHARISK_v6pcie,
2097
         PIPERX4DATA                          => PIPERX4DATA,
2098
         PIPERX4ELECIDLE                      => PIPERX4ELECIDLE,
2099
         PIPERX4PHYSTATUS                     => PIPERX4PHYSTATUS,
2100
         PIPERX4STATUS                        => PIPERX4STATUS,
2101
         PIPERX4VALID                         => PIPERX4VALID,
2102
         PIPERX5CHANISALIGNED                 => PIPERX5CHANISALIGNED,
2103
         PIPERX5CHARISK                       => PIPERX5CHARISK_v6pcie,
2104
         PIPERX5DATA                          => PIPERX5DATA,
2105
         PIPERX5ELECIDLE                      => PIPERX5ELECIDLE,
2106
         PIPERX5PHYSTATUS                     => PIPERX5PHYSTATUS,
2107
         PIPERX5STATUS                        => PIPERX5STATUS,
2108
         PIPERX5VALID                         => PIPERX5VALID,
2109
         PIPERX6CHANISALIGNED                 => PIPERX6CHANISALIGNED,
2110
         PIPERX6CHARISK                       => PIPERX6CHARISK_v6pcie,
2111
         PIPERX6DATA                          => PIPERX6DATA,
2112
         PIPERX6ELECIDLE                      => PIPERX6ELECIDLE,
2113
         PIPERX6PHYSTATUS                     => PIPERX6PHYSTATUS,
2114
         PIPERX6STATUS                        => PIPERX6STATUS,
2115
         PIPERX6VALID                         => PIPERX6VALID,
2116
         PIPERX7CHANISALIGNED                 => PIPERX7CHANISALIGNED,
2117
         PIPERX7CHARISK                       => PIPERX7CHARISK_v6pcie,
2118
         PIPERX7DATA                          => PIPERX7DATA,
2119
         PIPERX7ELECIDLE                      => PIPERX7ELECIDLE,
2120
         PIPERX7PHYSTATUS                     => PIPERX7PHYSTATUS,
2121
         PIPERX7STATUS                        => PIPERX7STATUS,
2122
         PIPERX7VALID                         => PIPERX7VALID,
2123
         PLDBGMODE                            => PLDBGMODE,
2124
         PLDIRECTEDLINKAUTON                  => PLDIRECTEDLINKAUTON,
2125
         PLDIRECTEDLINKCHANGE                 => PLDIRECTEDLINKCHANGE,
2126
         PLDIRECTEDLINKSPEED                  => PLDIRECTEDLINKSPEED,
2127
         PLDIRECTEDLINKWIDTH                  => PLDIRECTEDLINKWIDTH,
2128
         PLDOWNSTREAMDEEMPHSOURCE             => PLDOWNSTREAMDEEMPHSOURCE,
2129
         PLRSTN                               => PLRSTN,
2130
         PLTRANSMITHOTRST                     => PLTRANSMITHOTRST,
2131
         PLUPSTREAMPREFERDEEMPH               => PLUPSTREAMPREFERDEEMPH,
2132
         PL2DIRECTEDLSTATE                    => PL2DIRECTEDLSTATE,
2133
         SYSRSTN                              => SYSRSTN,
2134
         TLRSTN                               => TLRSTN,
2135
         TL2ASPMSUSPENDCREDITCHECKN           => '1',
2136
         TL2PPMSUSPENDREQN                    => '1',
2137
 
2138
         TRNFCSEL                             => TRNFCSEL,
2139
         TRNRDSTRDYN                          => TRNRDSTRDYN,
2140
         TRNRNPOKN                            => TRNRNPOKN,
2141
         TRNTCFGGNTN                          => TRNTCFGGNTN,
2142
         TRNTD                                => TRNTD,
2143
         TRNTDLLPDATA                         => TRNTDLLPDATA,
2144
 
2145
         TRNTDLLPSRCRDYN                      => TRNTDLLPSRCRDYN,
2146
         TRNTECRCGENN                         => TRNTECRCGENN,
2147
         TRNTEOFN                             => TRNTEOFN,
2148
         TRNTERRFWDN                          => TRNTERRFWDN,
2149
         TRNTREMN                             => TRNTREMN,
2150
         TRNTSOFN                             => TRNTSOFN,
2151
         TRNTSRCDSCN                          => TRNTSRCDSCN,
2152
         TRNTSRCRDYN                          => TRNTSRCRDYN,
2153
         TRNTSTRN                             => TRNTSTRN,
2154
         USERCLK                              => USERCLK
2155
      );
2156
 
2157
   ---------------------------------------------------------
2158
   -- Virtex6 PIPE Module
2159
   ---------------------------------------------------------
2160
 
2161
 
2162
 
2163
   pcie_pipe_i : pcie_pipe_v6
2164
      generic map (
2165
         NO_OF_LANES              => LINK_CAP_MAX_LINK_WIDTH_int,
2166
         LINK_CAP_MAX_LINK_SPEED  => LINK_CAP_MAX_LINK_SPEED,
2167
         PIPE_PIPELINE_STAGES     => PIPE_PIPELINE_STAGES
2168
      )
2169
      port map (
2170
 
2171
         -- Pipe Per-Link Signals 
2172
         pipe_tx_rcvr_det_i        => PIPETXRCVRDET,
2173
         pipe_tx_reset_i           => PIPETXRESET,
2174
         pipe_tx_rate_i            => PIPETXRATE,
2175
         pipe_tx_deemph_i          => PIPETXDEEMPH,
2176
         pipe_tx_margin_i          => PIPETXMARGIN,
2177
         pipe_tx_swing_i           => '0',
2178
 
2179
         pipe_tx_rcvr_det_o        => PIPETXRCVRDETGT,
2180
         pipe_tx_reset_o           => open,
2181
         pipe_tx_rate_o            => PIPETXRATEGT,
2182
         pipe_tx_deemph_o          => PIPETXDEEMPHGT,
2183
         pipe_tx_margin_o          => PIPETXMARGINGT,
2184
         pipe_tx_swing_o           => open,
2185
 
2186
         -- Pipe Per-Lane Signals - Lane 0
2187
         pipe_rx0_char_is_k_o      => PIPERX0CHARISK,
2188
         pipe_rx0_data_o           => PIPERX0DATA,
2189
         pipe_rx0_valid_o          => PIPERX0VALID,
2190
         pipe_rx0_chanisaligned_o  => PIPERX0CHANISALIGNED,
2191
         pipe_rx0_status_o         => PIPERX0STATUS,
2192
         pipe_rx0_phy_status_o     => PIPERX0PHYSTATUS,
2193
         pipe_rx0_elec_idle_i      => PIPERX0ELECIDLEGT,
2194
         pipe_rx0_polarity_i       => PIPERX0POLARITY,
2195
         pipe_tx0_compliance_i     => PIPETX0COMPLIANCE,
2196
         pipe_tx0_char_is_k_i      => PIPETX0CHARISK,
2197
         pipe_tx0_data_i           => PIPETX0DATA,
2198
         pipe_tx0_elec_idle_i      => PIPETX0ELECIDLE,
2199
         pipe_tx0_powerdown_i      => PIPETX0POWERDOWN,
2200
 
2201
         pipe_rx0_char_is_k_i      => PIPERX0CHARISKGT,
2202
         pipe_rx0_data_i           => PIPERX0DATAGT,
2203
         pipe_rx0_valid_i          => PIPERX0VALIDGT,
2204
         pipe_rx0_chanisaligned_i  => PIPERX0CHANISALIGNEDGT,
2205
         pipe_rx0_status_i         => PIPERX0STATUSGT,
2206
         pipe_rx0_phy_status_i     => PIPERX0PHYSTATUSGT,
2207
         pipe_rx0_elec_idle_o      => PIPERX0ELECIDLE,
2208
         pipe_rx0_polarity_o       => PIPERX0POLARITYGT,
2209
         pipe_tx0_compliance_o     => PIPETX0COMPLIANCEGT,
2210
         pipe_tx0_char_is_k_o      => PIPETX0CHARISKGT,
2211
         pipe_tx0_data_o           => PIPETX0DATAGT,
2212
         pipe_tx0_elec_idle_o      => PIPETX0ELECIDLEGT,
2213
         pipe_tx0_powerdown_o      => PIPETX0POWERDOWNGT,
2214
 
2215
         -- Pipe Per-Lane Signals - Lane 1
2216
         pipe_rx1_char_is_k_o      => PIPERX1CHARISK,
2217
         pipe_rx1_data_o           => PIPERX1DATA,
2218
         pipe_rx1_valid_o          => PIPERX1VALID,
2219
         pipe_rx1_chanisaligned_o  => PIPERX1CHANISALIGNED,
2220
         pipe_rx1_status_o         => PIPERX1STATUS,
2221
         pipe_rx1_phy_status_o     => PIPERX1PHYSTATUS,
2222
         pipe_rx1_elec_idle_i      => PIPERX1ELECIDLEGT,
2223
         pipe_rx1_polarity_i       => PIPERX1POLARITY,
2224
         pipe_tx1_compliance_i     => PIPETX1COMPLIANCE,
2225
         pipe_tx1_char_is_k_i      => PIPETX1CHARISK,
2226
         pipe_tx1_data_i           => PIPETX1DATA,
2227
         pipe_tx1_elec_idle_i      => PIPETX1ELECIDLE,
2228
         pipe_tx1_powerdown_i      => PIPETX1POWERDOWN,
2229
 
2230
         pipe_rx1_char_is_k_i      => PIPERX1CHARISKGT,
2231
         pipe_rx1_data_i           => PIPERX1DATAGT,
2232
         pipe_rx1_valid_i          => PIPERX1VALIDGT,
2233
         pipe_rx1_chanisaligned_i  => PIPERX1CHANISALIGNEDGT,
2234
         pipe_rx1_status_i         => PIPERX1STATUSGT,
2235
         pipe_rx1_phy_status_i     => PIPERX1PHYSTATUSGT,
2236
         pipe_rx1_elec_idle_o      => PIPERX1ELECIDLE,
2237
         pipe_rx1_polarity_o       => PIPERX1POLARITYGT,
2238
         pipe_tx1_compliance_o     => PIPETX1COMPLIANCEGT,
2239
         pipe_tx1_char_is_k_o      => PIPETX1CHARISKGT,
2240
         pipe_tx1_data_o           => PIPETX1DATAGT,
2241
         pipe_tx1_elec_idle_o      => PIPETX1ELECIDLEGT,
2242
         pipe_tx1_powerdown_o      => PIPETX1POWERDOWNGT,
2243
 
2244
         -- Pipe Per-Lane Signals - Lane 2
2245
         pipe_rx2_char_is_k_o      => PIPERX2CHARISK,
2246
         pipe_rx2_data_o           => PIPERX2DATA,
2247
         pipe_rx2_valid_o          => PIPERX2VALID,
2248
         pipe_rx2_chanisaligned_o  => PIPERX2CHANISALIGNED,
2249
         pipe_rx2_status_o         => PIPERX2STATUS,
2250
         pipe_rx2_phy_status_o     => PIPERX2PHYSTATUS,
2251
         pipe_rx2_elec_idle_i      => PIPERX2ELECIDLEGT,
2252
         pipe_rx2_polarity_i       => PIPERX2POLARITY,
2253
         pipe_tx2_compliance_i     => PIPETX2COMPLIANCE,
2254
         pipe_tx2_char_is_k_i      => PIPETX2CHARISK,
2255
         pipe_tx2_data_i           => PIPETX2DATA,
2256
         pipe_tx2_elec_idle_i      => PIPETX2ELECIDLE,
2257
         pipe_tx2_powerdown_i      => PIPETX2POWERDOWN,
2258
 
2259
         pipe_rx2_char_is_k_i      => PIPERX2CHARISKGT,
2260
         pipe_rx2_data_i           => PIPERX2DATAGT,
2261
         pipe_rx2_valid_i          => PIPERX2VALIDGT,
2262
         pipe_rx2_chanisaligned_i  => PIPERX2CHANISALIGNEDGT,
2263
         pipe_rx2_status_i         => PIPERX2STATUSGT,
2264
         pipe_rx2_phy_status_i     => PIPERX2PHYSTATUSGT,
2265
         pipe_rx2_elec_idle_o      => PIPERX2ELECIDLE,
2266
         pipe_rx2_polarity_o       => PIPERX2POLARITYGT,
2267
         pipe_tx2_compliance_o     => PIPETX2COMPLIANCEGT,
2268
         pipe_tx2_char_is_k_o      => PIPETX2CHARISKGT,
2269
         pipe_tx2_data_o           => PIPETX2DATAGT,
2270
         pipe_tx2_elec_idle_o      => PIPETX2ELECIDLEGT,
2271
         pipe_tx2_powerdown_o      => PIPETX2POWERDOWNGT,
2272
 
2273
         -- Pipe Per-Lane Signals - Lane 3
2274
         pipe_rx3_char_is_k_o      => PIPERX3CHARISK,
2275
         pipe_rx3_data_o           => PIPERX3DATA,
2276
         pipe_rx3_valid_o          => PIPERX3VALID,
2277
         pipe_rx3_chanisaligned_o  => PIPERX3CHANISALIGNED,
2278
         pipe_rx3_status_o         => PIPERX3STATUS,
2279
         pipe_rx3_phy_status_o     => PIPERX3PHYSTATUS,
2280
         pipe_rx3_elec_idle_i      => PIPERX3ELECIDLEGT,
2281
         pipe_rx3_polarity_i       => PIPERX3POLARITY,
2282
         pipe_tx3_compliance_i     => PIPETX3COMPLIANCE,
2283
         pipe_tx3_char_is_k_i      => PIPETX3CHARISK,
2284
         pipe_tx3_data_i           => PIPETX3DATA,
2285
         pipe_tx3_elec_idle_i      => PIPETX3ELECIDLE,
2286
         pipe_tx3_powerdown_i      => PIPETX3POWERDOWN,
2287
 
2288
         pipe_rx3_char_is_k_i      => PIPERX3CHARISKGT,
2289
         pipe_rx3_data_i           => PIPERX3DATAGT,
2290
         pipe_rx3_valid_i          => PIPERX3VALIDGT,
2291
         pipe_rx3_chanisaligned_i  => PIPERX3CHANISALIGNEDGT,
2292
         pipe_rx3_status_i         => PIPERX3STATUSGT,
2293
         pipe_rx3_phy_status_i     => PIPERX3PHYSTATUSGT,
2294
         pipe_rx3_elec_idle_o      => PIPERX3ELECIDLE,
2295
         pipe_rx3_polarity_o       => PIPERX3POLARITYGT,
2296
         pipe_tx3_compliance_o     => PIPETX3COMPLIANCEGT,
2297
         pipe_tx3_char_is_k_o      => PIPETX3CHARISKGT,
2298
         pipe_tx3_data_o           => PIPETX3DATAGT,
2299
         pipe_tx3_elec_idle_o      => PIPETX3ELECIDLEGT,
2300
         pipe_tx3_powerdown_o      => PIPETX3POWERDOWNGT,
2301
 
2302
         -- Pipe Per-Lane Signals - Lane 4
2303
         pipe_rx4_char_is_k_o      => PIPERX4CHARISK,
2304
         pipe_rx4_data_o           => PIPERX4DATA,
2305
         pipe_rx4_valid_o          => PIPERX4VALID,
2306
         pipe_rx4_chanisaligned_o  => PIPERX4CHANISALIGNED,
2307
         pipe_rx4_status_o         => PIPERX4STATUS,
2308
         pipe_rx4_phy_status_o     => PIPERX4PHYSTATUS,
2309
         pipe_rx4_elec_idle_i      => PIPERX4ELECIDLEGT,
2310
         pipe_rx4_polarity_i       => PIPERX4POLARITY,
2311
         pipe_tx4_compliance_i     => PIPETX4COMPLIANCE,
2312
         pipe_tx4_char_is_k_i      => PIPETX4CHARISK,
2313
         pipe_tx4_data_i           => PIPETX4DATA,
2314
         pipe_tx4_elec_idle_i      => PIPETX4ELECIDLE,
2315
         pipe_tx4_powerdown_i      => PIPETX4POWERDOWN,
2316
 
2317
         pipe_rx4_char_is_k_i      => PIPERX4CHARISKGT,
2318
         pipe_rx4_data_i           => PIPERX4DATAGT,
2319
         pipe_rx4_valid_i          => PIPERX4VALIDGT,
2320
         pipe_rx4_chanisaligned_i  => PIPERX4CHANISALIGNEDGT,
2321
         pipe_rx4_status_i         => PIPERX4STATUSGT,
2322
         pipe_rx4_phy_status_i     => PIPERX4PHYSTATUSGT,
2323
         pipe_rx4_elec_idle_o      => PIPERX4ELECIDLE,
2324
         pipe_rx4_polarity_o       => PIPERX4POLARITYGT,
2325
         pipe_tx4_compliance_o     => PIPETX4COMPLIANCEGT,
2326
         pipe_tx4_char_is_k_o      => PIPETX4CHARISKGT,
2327
         pipe_tx4_data_o           => PIPETX4DATAGT,
2328
         pipe_tx4_elec_idle_o      => PIPETX4ELECIDLEGT,
2329
         pipe_tx4_powerdown_o      => PIPETX4POWERDOWNGT,
2330
 
2331
         -- Pipe Per-Lane Signals - Lane 5
2332
         pipe_rx5_char_is_k_o      => PIPERX5CHARISK,
2333
         pipe_rx5_data_o           => PIPERX5DATA,
2334
         pipe_rx5_valid_o          => PIPERX5VALID,
2335
         pipe_rx5_chanisaligned_o  => PIPERX5CHANISALIGNED,
2336
         pipe_rx5_status_o         => PIPERX5STATUS,
2337
         pipe_rx5_phy_status_o     => PIPERX5PHYSTATUS,
2338
         pipe_rx5_elec_idle_i      => PIPERX5ELECIDLEGT,
2339
         pipe_rx5_polarity_i       => PIPERX5POLARITY,
2340
         pipe_tx5_compliance_i     => PIPETX5COMPLIANCE,
2341
         pipe_tx5_char_is_k_i      => PIPETX5CHARISK,
2342
         pipe_tx5_data_i           => PIPETX5DATA,
2343
         pipe_tx5_elec_idle_i      => PIPETX5ELECIDLE,
2344
         pipe_tx5_powerdown_i      => PIPETX5POWERDOWN,
2345
 
2346
         pipe_rx5_char_is_k_i      => PIPERX5CHARISKGT,
2347
         pipe_rx5_data_i           => PIPERX5DATAGT,
2348
         pipe_rx5_valid_i          => PIPERX5VALIDGT,
2349
         pipe_rx5_chanisaligned_i  => PIPERX5CHANISALIGNEDGT,
2350
         pipe_rx5_status_i         => PIPERX5STATUSGT,
2351
         pipe_rx5_phy_status_i     => PIPERX5PHYSTATUSGT,
2352
         pipe_rx5_elec_idle_o      => PIPERX5ELECIDLE,
2353
         pipe_rx5_polarity_o       => PIPERX5POLARITYGT,
2354
         pipe_tx5_compliance_o     => PIPETX5COMPLIANCEGT,
2355
         pipe_tx5_char_is_k_o      => PIPETX5CHARISKGT,
2356
         pipe_tx5_data_o           => PIPETX5DATAGT,
2357
         pipe_tx5_elec_idle_o      => PIPETX5ELECIDLEGT,
2358
         pipe_tx5_powerdown_o      => PIPETX5POWERDOWNGT,
2359
 
2360
         -- Pipe Per-Lane Signals - Lane 6
2361
         pipe_rx6_char_is_k_o      => PIPERX6CHARISK,
2362
         pipe_rx6_data_o           => PIPERX6DATA,
2363
         pipe_rx6_valid_o          => PIPERX6VALID,
2364
         pipe_rx6_chanisaligned_o  => PIPERX6CHANISALIGNED,
2365
         pipe_rx6_status_o         => PIPERX6STATUS,
2366
         pipe_rx6_phy_status_o     => PIPERX6PHYSTATUS,
2367
         pipe_rx6_elec_idle_i      => PIPERX6ELECIDLEGT,
2368
         pipe_rx6_polarity_i       => PIPERX6POLARITY,
2369
         pipe_tx6_compliance_i     => PIPETX6COMPLIANCE,
2370
         pipe_tx6_char_is_k_i      => PIPETX6CHARISK,
2371
         pipe_tx6_data_i           => PIPETX6DATA,
2372
         pipe_tx6_elec_idle_i      => PIPETX6ELECIDLE,
2373
         pipe_tx6_powerdown_i      => PIPETX6POWERDOWN,
2374
 
2375
         pipe_rx6_char_is_k_i      => PIPERX6CHARISKGT,
2376
         pipe_rx6_data_i           => PIPERX6DATAGT,
2377
         pipe_rx6_valid_i          => PIPERX6VALIDGT,
2378
         pipe_rx6_chanisaligned_i  => PIPERX6CHANISALIGNEDGT,
2379
         pipe_rx6_status_i         => PIPERX6STATUSGT,
2380
         pipe_rx6_phy_status_i     => PIPERX6PHYSTATUSGT,
2381
         pipe_rx6_elec_idle_o      => PIPERX6ELECIDLE,
2382
         pipe_rx6_polarity_o       => PIPERX6POLARITYGT,
2383
         pipe_tx6_compliance_o     => PIPETX6COMPLIANCEGT,
2384
         pipe_tx6_char_is_k_o      => PIPETX6CHARISKGT,
2385
         pipe_tx6_data_o           => PIPETX6DATAGT,
2386
         pipe_tx6_elec_idle_o      => PIPETX6ELECIDLEGT,
2387
         pipe_tx6_powerdown_o      => PIPETX6POWERDOWNGT,
2388
 
2389
         -- Pipe Per-Lane Signals - Lane 7
2390
         pipe_rx7_char_is_k_o      => PIPERX7CHARISK,
2391
         pipe_rx7_data_o           => PIPERX7DATA,
2392
         pipe_rx7_valid_o          => PIPERX7VALID,
2393
         pipe_rx7_chanisaligned_o  => PIPERX7CHANISALIGNED,
2394
         pipe_rx7_status_o         => PIPERX7STATUS,
2395
         pipe_rx7_phy_status_o     => PIPERX7PHYSTATUS,
2396
         pipe_rx7_elec_idle_i      => PIPERX7ELECIDLEGT,
2397
         pipe_rx7_polarity_i       => PIPERX7POLARITY,
2398
         pipe_tx7_compliance_i     => PIPETX7COMPLIANCE,
2399
         pipe_tx7_char_is_k_i      => PIPETX7CHARISK,
2400
         pipe_tx7_data_i           => PIPETX7DATA,
2401
         pipe_tx7_elec_idle_i      => PIPETX7ELECIDLE,
2402
         pipe_tx7_powerdown_i      => PIPETX7POWERDOWN,
2403
 
2404
         pipe_rx7_char_is_k_i      => PIPERX7CHARISKGT,
2405
         pipe_rx7_data_i           => PIPERX7DATAGT,
2406
         pipe_rx7_valid_i          => PIPERX7VALIDGT,
2407
         pipe_rx7_chanisaligned_i  => PIPERX7CHANISALIGNEDGT,
2408
         pipe_rx7_status_i         => PIPERX7STATUSGT,
2409
         pipe_rx7_phy_status_i     => PIPERX7PHYSTATUSGT,
2410
         pipe_rx7_elec_idle_o      => PIPERX7ELECIDLE,
2411
         pipe_rx7_polarity_o       => PIPERX7POLARITYGT,
2412
         pipe_tx7_compliance_o     => PIPETX7COMPLIANCEGT,
2413
         pipe_tx7_char_is_k_o      => PIPETX7CHARISKGT,
2414
         pipe_tx7_data_o           => PIPETX7DATAGT,
2415
         pipe_tx7_elec_idle_o      => PIPETX7ELECIDLEGT,
2416
         pipe_tx7_powerdown_o      => PIPETX7POWERDOWNGT,
2417
 
2418
         -- Non PIPE signals
2419
         pl_ltssm_state            => PLLTSSMSTATE_v6pcie109,
2420
         pipe_clk                  => PIPECLK,
2421
         rst_n                     => PHYRDYN_v6pcie102
2422
      );
2423
 
2424
   ---------------------------------------------------------
2425
   -- Virtex6 GTX Module
2426
   ---------------------------------------------------------
2427
 
2428
 
2429
 
2430
   pcie_gt_i : pcie_gtx_v6
2431
      generic map (
2432
         NO_OF_LANES              => LINK_CAP_MAX_LINK_WIDTH_int,
2433
         LINK_CAP_MAX_LINK_SPEED  => LINK_CAP_MAX_LINK_SPEED,
2434
         REF_CLK_FREQ             => REF_CLK_FREQ,
2435
         PL_FAST_TRAIN            => PL_FAST_TRAIN
2436
      )
2437
      port map (
2438
 
2439
         -- Pipe Common Signals 
2440
         pipe_tx_rcvr_det        => PIPETXRCVRDETGT,
2441
         pipe_tx_reset           => '0',
2442
         pipe_tx_rate            => PIPETXRATEGT,
2443
         pipe_tx_deemph          => PIPETXDEEMPHGT,
2444
         pipe_tx_margin          => PIPETXMARGINGT,
2445
         pipe_tx_swing           => '0',
2446
 
2447
         -- Pipe Per-Lane Signals - Lane 0
2448
         pipe_rx0_char_is_k      => PIPERX0CHARISKGT,
2449
         pipe_rx0_data           => PIPERX0DATAGT,
2450
         pipe_rx0_valid          => PIPERX0VALIDGT,
2451
         pipe_rx0_chanisaligned  => PIPERX0CHANISALIGNEDGT,
2452
         pipe_rx0_status         => PIPERX0STATUSGT,
2453
         pipe_rx0_phy_status     => PIPERX0PHYSTATUSGT,
2454
         pipe_rx0_elec_idle      => PIPERX0ELECIDLEGT,
2455
         pipe_rx0_polarity       => PIPERX0POLARITYGT,
2456
         pipe_tx0_compliance     => PIPETX0COMPLIANCEGT,
2457
         pipe_tx0_char_is_k      => PIPETX0CHARISKGT,
2458
         pipe_tx0_data           => PIPETX0DATAGT,
2459
         pipe_tx0_elec_idle      => PIPETX0ELECIDLEGT,
2460
         pipe_tx0_powerdown      => PIPETX0POWERDOWNGT,
2461
 
2462
         -- Pipe Per-Lane Signals - Lane 1
2463
         pipe_rx1_char_is_k      => PIPERX1CHARISKGT,
2464
         pipe_rx1_data           => PIPERX1DATAGT,
2465
         pipe_rx1_valid          => PIPERX1VALIDGT,
2466
         pipe_rx1_chanisaligned  => PIPERX1CHANISALIGNEDGT,
2467
         pipe_rx1_status         => PIPERX1STATUSGT,
2468
         pipe_rx1_phy_status     => PIPERX1PHYSTATUSGT,
2469
         pipe_rx1_elec_idle      => PIPERX1ELECIDLEGT,
2470
         pipe_rx1_polarity       => PIPERX1POLARITYGT,
2471
         pipe_tx1_compliance     => PIPETX1COMPLIANCEGT,
2472
         pipe_tx1_char_is_k      => PIPETX1CHARISKGT,
2473
         pipe_tx1_data           => PIPETX1DATAGT,
2474
         pipe_tx1_elec_idle      => PIPETX1ELECIDLEGT,
2475
         pipe_tx1_powerdown      => PIPETX1POWERDOWNGT,
2476
 
2477
         -- Pipe Per-Lane Signals - Lane 2
2478
         pipe_rx2_char_is_k      => PIPERX2CHARISKGT,
2479
         pipe_rx2_data           => PIPERX2DATAGT,
2480
         pipe_rx2_valid          => PIPERX2VALIDGT,
2481
         pipe_rx2_chanisaligned  => PIPERX2CHANISALIGNEDGT,
2482
         pipe_rx2_status         => PIPERX2STATUSGT,
2483
         pipe_rx2_phy_status     => PIPERX2PHYSTATUSGT,
2484
         pipe_rx2_elec_idle      => PIPERX2ELECIDLEGT,
2485
         pipe_rx2_polarity       => PIPERX2POLARITYGT,
2486
         pipe_tx2_compliance     => PIPETX2COMPLIANCEGT,
2487
         pipe_tx2_char_is_k      => PIPETX2CHARISKGT,
2488
         pipe_tx2_data           => PIPETX2DATAGT,
2489
         pipe_tx2_elec_idle      => PIPETX2ELECIDLEGT,
2490
         pipe_tx2_powerdown      => PIPETX2POWERDOWNGT,
2491
 
2492
         -- Pipe Per-Lane Signals - Lane 3
2493
         pipe_rx3_char_is_k      => PIPERX3CHARISKGT,
2494
         pipe_rx3_data           => PIPERX3DATAGT,
2495
         pipe_rx3_valid          => PIPERX3VALIDGT,
2496
         pipe_rx3_chanisaligned  => PIPERX3CHANISALIGNEDGT,
2497
         pipe_rx3_status         => PIPERX3STATUSGT,
2498
         pipe_rx3_phy_status     => PIPERX3PHYSTATUSGT,
2499
         pipe_rx3_elec_idle      => PIPERX3ELECIDLEGT,
2500
         pipe_rx3_polarity       => PIPERX3POLARITYGT,
2501
         pipe_tx3_compliance     => PIPETX3COMPLIANCEGT,
2502
         pipe_tx3_char_is_k      => PIPETX3CHARISKGT,
2503
         pipe_tx3_data           => PIPETX3DATAGT,
2504
         pipe_tx3_elec_idle      => PIPETX3ELECIDLEGT,
2505
         pipe_tx3_powerdown      => PIPETX3POWERDOWNGT,
2506
 
2507
         -- Pipe Per-Lane Signals - Lane 4
2508
         pipe_rx4_char_is_k      => PIPERX4CHARISKGT,
2509
         pipe_rx4_data           => PIPERX4DATAGT,
2510
         pipe_rx4_valid          => PIPERX4VALIDGT,
2511
         pipe_rx4_chanisaligned  => PIPERX4CHANISALIGNEDGT,
2512
         pipe_rx4_status         => PIPERX4STATUSGT,
2513
         pipe_rx4_phy_status     => PIPERX4PHYSTATUSGT,
2514
         pipe_rx4_elec_idle      => PIPERX4ELECIDLEGT,
2515
         pipe_rx4_polarity       => PIPERX4POLARITYGT,
2516
         pipe_tx4_compliance     => PIPETX4COMPLIANCEGT,
2517
         pipe_tx4_char_is_k      => PIPETX4CHARISKGT,
2518
         pipe_tx4_data           => PIPETX4DATAGT,
2519
         pipe_tx4_elec_idle      => PIPETX4ELECIDLEGT,
2520
         pipe_tx4_powerdown      => PIPETX4POWERDOWNGT,
2521
 
2522
         -- Pipe Per-Lane Signals - Lane 5
2523
         pipe_rx5_char_is_k      => PIPERX5CHARISKGT,
2524
         pipe_rx5_data           => PIPERX5DATAGT,
2525
         pipe_rx5_valid          => PIPERX5VALIDGT,
2526
         pipe_rx5_chanisaligned  => PIPERX5CHANISALIGNEDGT,
2527
         pipe_rx5_status         => PIPERX5STATUSGT,
2528
         pipe_rx5_phy_status     => PIPERX5PHYSTATUSGT,
2529
         pipe_rx5_elec_idle      => PIPERX5ELECIDLEGT,
2530
         pipe_rx5_polarity       => PIPERX5POLARITYGT,
2531
         pipe_tx5_compliance     => PIPETX5COMPLIANCEGT,
2532
         pipe_tx5_char_is_k      => PIPETX5CHARISKGT,
2533
         pipe_tx5_data           => PIPETX5DATAGT,
2534
         pipe_tx5_elec_idle      => PIPETX5ELECIDLEGT,
2535
         pipe_tx5_powerdown      => PIPETX5POWERDOWNGT,
2536
 
2537
         -- Pipe Per-Lane Signals - Lane 6
2538
         pipe_rx6_char_is_k      => PIPERX6CHARISKGT,
2539
         pipe_rx6_data           => PIPERX6DATAGT,
2540
         pipe_rx6_valid          => PIPERX6VALIDGT,
2541
         pipe_rx6_chanisaligned  => PIPERX6CHANISALIGNEDGT,
2542
         pipe_rx6_status         => PIPERX6STATUSGT,
2543
         pipe_rx6_phy_status     => PIPERX6PHYSTATUSGT,
2544
         pipe_rx6_elec_idle      => PIPERX6ELECIDLEGT,
2545
         pipe_rx6_polarity       => PIPERX6POLARITYGT,
2546
         pipe_tx6_compliance     => PIPETX6COMPLIANCEGT,
2547
         pipe_tx6_char_is_k      => PIPETX6CHARISKGT,
2548
         pipe_tx6_data           => PIPETX6DATAGT,
2549
         pipe_tx6_elec_idle      => PIPETX6ELECIDLEGT,
2550
         pipe_tx6_powerdown      => PIPETX6POWERDOWNGT,
2551
 
2552
         -- Pipe Per-Lane Signals - Lane 7
2553
         pipe_rx7_char_is_k      => PIPERX7CHARISKGT,
2554
         pipe_rx7_data           => PIPERX7DATAGT,
2555
         pipe_rx7_valid          => PIPERX7VALIDGT,
2556
         pipe_rx7_chanisaligned  => PIPERX7CHANISALIGNEDGT,
2557
         pipe_rx7_status         => PIPERX7STATUSGT,
2558
         pipe_rx7_phy_status     => PIPERX7PHYSTATUSGT,
2559
         pipe_rx7_elec_idle      => PIPERX7ELECIDLEGT,
2560
         pipe_rx7_polarity       => PIPERX7POLARITYGT,
2561
         pipe_tx7_compliance     => PIPETX7COMPLIANCEGT,
2562
         pipe_tx7_char_is_k      => PIPETX7CHARISKGT,
2563
         pipe_tx7_data           => PIPETX7DATAGT,
2564
         pipe_tx7_elec_idle      => PIPETX7ELECIDLEGT,
2565
         pipe_tx7_powerdown      => PIPETX7POWERDOWNGT,
2566
 
2567
         -- PCI Express Signals
2568
         pci_exp_txn             => PCIEXPTXN_v6pcie100,
2569
         pci_exp_txp             => PCIEXPTXP_v6pcie101,
2570
         pci_exp_rxn             => PCIEXPRXN,
2571
         pci_exp_rxp             => PCIEXPRXP,
2572
 
2573
         -- Non PIPE Signals
2574
         sys_clk                 => SYSCLK,
2575
         sys_rst_n               => FUNDRSTN,
2576
         pipe_clk                => PIPECLK,
2577
         drp_clk                 => DRPCLK,
2578
         clock_locked            => CLOCKLOCKED,
2579
         pl_ltssm_state          => PLLTSSMSTATE_v6pcie109,
2580
 
2581
         gt_pll_lock             => GTPLLLOCK_v6pcie96,
2582
         phy_rdy_n               => PHYRDYN_v6pcie102,
2583
         txoutclk                => TxOutClk_v6pcie138
2584
      );
2585
 
2586
   ---------------------------------------------------------
2587
   -- PCI Express BRAM Module
2588
   ---------------------------------------------------------
2589
 
2590
 
2591
   MIMTXWDATA_tmp <= "000" & MIMTXWDATA;
2592
   MIMRXWDATA_tmp <= "0000" & MIMRXWDATA;
2593
 
2594
   pcie_bram_i : pcie_bram_top_v6
2595
      generic map (
2596
         DEV_CAP_MAX_PAYLOAD_SUPPORTED  => DEV_CAP_MAX_PAYLOAD_SUPPORTED,
2597
         VC0_TX_LASTPACKET              => VC0_TX_LASTPACKET,
2598
         TL_TX_RAM_RADDR_LATENCY        => TL_TX_RAM_RADDR_LATENCY,
2599
         TL_TX_RAM_RDATA_LATENCY        => TL_TX_RAM_RDATA_LATENCY,
2600
         TL_TX_RAM_WRITE_LATENCY        => TL_TX_RAM_WRITE_LATENCY,
2601
         VC0_RX_LIMIT                   => VC0_RX_RAM_LIMIT,
2602
         TL_RX_RAM_RADDR_LATENCY        => TL_RX_RAM_RADDR_LATENCY,
2603
         TL_RX_RAM_RDATA_LATENCY        => TL_RX_RAM_RDATA_LATENCY,
2604
         TL_RX_RAM_WRITE_LATENCY        => TL_RX_RAM_WRITE_LATENCY
2605
      )
2606
      port map (
2607
 
2608
         user_clk_i    => USERCLK,
2609
         reset_i       => PHYRDYN_v6pcie102,
2610
 
2611
         mim_tx_waddr  => MIMTXWADDR,
2612
         mim_tx_wen    => MIMTXWEN,
2613
         mim_tx_ren    => MIMTXREN,
2614
         mim_tx_rce    => MIMTXRCE,
2615
         mim_tx_wdata  => MIMTXWDATA_tmp,
2616
         mim_tx_raddr  => MIMTXRADDR,
2617
         mim_tx_rdata  => MIMTXRDATA,
2618
 
2619
         mim_rx_waddr  => MIMRXWADDR,
2620
         mim_rx_wen    => MIMRXWEN,
2621
         mim_rx_ren    => MIMRXREN,
2622
         mim_rx_rce    => MIMRXRCE,
2623
         mim_rx_wdata  => MIMRXWDATA_tmp,
2624
         mim_rx_raddr  => MIMRXRADDR,
2625
         mim_rx_rdata  => MIMRXRDATA
2626
      );
2627
 
2628
   ---------------------------------------------------------
2629
   -- PCI Express Port Workarounds
2630
   ---------------------------------------------------------
2631
 
2632
 
2633
 
2634
   pcie_upconfig_fix_3451_v6_i : pcie_upconfig_fix_3451_v6
2635
      generic map (
2636
         UPSTREAM_FACING          => UPSTREAM_FACING,
2637
         PL_FAST_TRAIN            => PL_FAST_TRAIN,
2638
         LINK_CAP_MAX_LINK_WIDTH  => LINK_CAP_MAX_LINK_WIDTH
2639
      )
2640
      port map (
2641
 
2642
         pipe_clk                          => PIPECLK,
2643
         pl_phy_lnkup_n                    => PLPHYLNKUPN_v6pcie110,
2644
 
2645
         pl_ltssm_state                    => PLLTSSMSTATE_v6pcie109,
2646
         pl_sel_lnk_rate                   => PLSELLNKRATE_v6pcie113,
2647
         pl_directed_link_change           => PLDIRECTEDLINKCHANGE,
2648
 
2649
         cfg_link_status_negotiated_width  => CFGLINKSTATUSNEGOTIATEDWIDTH_v6pcie48,
2650
         pipe_rx0_data                     => PIPERX0DATAGT(15 downto 0),
2651
         pipe_rx0_char_isk                 => PIPERX0CHARISKGT(1 downto 0),
2652
 
2653
         filter_pipe                       => filter_pipe_upconfig_fix_3451
2654
      );
2655
 
2656
end v6_pcie;
2657
 
2658
 
2659
 

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