1 |
2 |
dsmv |
-------------------------------------------------------------------------------
|
2 |
|
|
--
|
3 |
|
|
-- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
|
4 |
|
|
--
|
5 |
|
|
-- This file contains confidential and proprietary information
|
6 |
|
|
-- of Xilinx, Inc. and is protected under U.S. and
|
7 |
|
|
-- international copyright and other intellectual property
|
8 |
|
|
-- laws.
|
9 |
|
|
--
|
10 |
|
|
-- DISCLAIMER
|
11 |
|
|
-- This disclaimer is not a license and does not grant any
|
12 |
|
|
-- rights to the materials distributed herewith. Except as
|
13 |
|
|
-- otherwise provided in a valid license issued to you by
|
14 |
|
|
-- Xilinx, and to the maximum extent permitted by applicable
|
15 |
|
|
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
16 |
|
|
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
17 |
|
|
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
18 |
|
|
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
19 |
|
|
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
20 |
|
|
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
21 |
|
|
-- including negligence, or under any other theory of
|
22 |
|
|
-- liability) for any loss or damage of any kind or nature
|
23 |
|
|
-- related to, arising under or in connection with these
|
24 |
|
|
-- materials, including for any direct, or any indirect,
|
25 |
|
|
-- special, incidental, or consequential loss or damage
|
26 |
|
|
-- (including loss of data, profits, goodwill, or any type of
|
27 |
|
|
-- loss or damage suffered as a result of any action brought
|
28 |
|
|
-- by a third party) even if such damage or loss was
|
29 |
|
|
-- reasonably foreseeable or Xilinx had been advised of the
|
30 |
|
|
-- possibility of the same.
|
31 |
|
|
--
|
32 |
|
|
-- CRITICAL APPLICATIONS
|
33 |
|
|
-- Xilinx products are not designed or intended to be fail-
|
34 |
|
|
-- safe, or for use in any application requiring fail-safe
|
35 |
|
|
-- performance, such as life-support or safety devices or
|
36 |
|
|
-- systems, Class III medical devices, nuclear facilities,
|
37 |
|
|
-- applications related to the deployment of airbags, or any
|
38 |
|
|
-- other applications that could lead to death, personal
|
39 |
|
|
-- injury, or severe property or environmental damage
|
40 |
|
|
-- (individually and collectively, "Critical
|
41 |
|
|
-- Applications"). Customer assumes the sole risk and
|
42 |
|
|
-- liability of any use of Xilinx products in Critical
|
43 |
|
|
-- Applications, subject only to applicable laws and
|
44 |
|
|
-- regulations governing limitations on product liability.
|
45 |
|
|
--
|
46 |
|
|
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
47 |
|
|
-- PART OF THIS FILE AT ALL TIMES.
|
48 |
|
|
--
|
49 |
|
|
-------------------------------------------------------------------------------
|
50 |
|
|
-- Project : Virtex-6 Integrated Block for PCI Express
|
51 |
|
|
-- File : pcie_bram_v6.vhd
|
52 |
|
|
-- Version : 2.3
|
53 |
|
|
--
|
54 |
|
|
-- Description: BlockRAM module for Virtex6 PCIe Block
|
55 |
|
|
--
|
56 |
|
|
--------------------------------------------------------------------------------
|
57 |
|
|
|
58 |
|
|
library ieee;
|
59 |
|
|
use ieee.std_logic_1164.all;
|
60 |
|
|
use ieee.std_logic_unsigned.all;
|
61 |
|
|
|
62 |
|
|
library unisim;
|
63 |
|
|
use unisim.vcomponents.all;
|
64 |
|
|
|
65 |
|
|
entity pcie_bram_v6 is
|
66 |
|
|
generic (
|
67 |
|
|
DOB_REG : integer := 0; -- 1 use the output register 0 don't use the output register
|
68 |
|
|
WIDTH : integer := 0 -- supported WIDTH's are: 4, 9, 18, 36 (uses RAMB36) and 72 (uses RAMB36SDP)
|
69 |
|
|
);
|
70 |
|
|
port (
|
71 |
|
|
|
72 |
|
|
user_clk_i : in std_logic; -- user clock
|
73 |
|
|
reset_i : in std_logic; -- bram reset
|
74 |
|
|
wen_i : in std_logic; -- write enable
|
75 |
|
|
waddr_i : in std_logic_vector(12 downto 0); -- write address
|
76 |
|
|
wdata_i : in std_logic_vector(WIDTH - 1 downto 0); -- write data
|
77 |
|
|
ren_i : in std_logic; -- read enable
|
78 |
|
|
rce_i : in std_logic; -- output register clock enable
|
79 |
|
|
raddr_i : in std_logic_vector(12 downto 0); -- read address
|
80 |
|
|
rdata_o : out std_logic_vector(WIDTH - 1 downto 0) -- read data
|
81 |
|
|
);
|
82 |
|
|
end pcie_bram_v6;
|
83 |
|
|
|
84 |
|
|
architecture v6_pcie of pcie_bram_v6 is
|
85 |
|
|
|
86 |
|
|
-- map the address bits
|
87 |
|
|
function msb_addr (
|
88 |
|
|
constant wdt : integer)
|
89 |
|
|
return integer is
|
90 |
|
|
variable addr_msb : integer := 8;
|
91 |
|
|
begin -- msb_addr
|
92 |
|
|
|
93 |
|
|
if (wdt = 4) then
|
94 |
|
|
addr_msb := 12;
|
95 |
|
|
elsif (wdt = 9) then
|
96 |
|
|
addr_msb := 11;
|
97 |
|
|
elsif (wdt = 18) then
|
98 |
|
|
addr_msb := 10;
|
99 |
|
|
elsif (wdt = 36) then
|
100 |
|
|
addr_msb := 9;
|
101 |
|
|
else
|
102 |
|
|
addr_msb := 8;
|
103 |
|
|
end if;
|
104 |
|
|
return addr_msb;
|
105 |
|
|
end msb_addr;
|
106 |
|
|
|
107 |
|
|
constant ADDR_MSB : integer := msb_addr(WIDTH);
|
108 |
|
|
|
109 |
|
|
-- set the width of the tied off low address bits
|
110 |
|
|
function alb (
|
111 |
|
|
constant wdt : integer)
|
112 |
|
|
return integer is
|
113 |
|
|
variable addr_lo_bit : integer := 8;
|
114 |
|
|
begin -- alb
|
115 |
|
|
|
116 |
|
|
if (wdt = 4) then
|
117 |
|
|
addr_lo_bit := 2;
|
118 |
|
|
elsif (wdt = 9) then
|
119 |
|
|
addr_lo_bit := 3;
|
120 |
|
|
elsif (wdt = 18) then
|
121 |
|
|
addr_lo_bit := 4;
|
122 |
|
|
elsif (wdt = 36) then
|
123 |
|
|
addr_lo_bit := 5;
|
124 |
|
|
else
|
125 |
|
|
addr_lo_bit := 0; -- for WIDTH 72 use RAMB36SDP
|
126 |
|
|
end if;
|
127 |
|
|
return addr_lo_bit;
|
128 |
|
|
end alb;
|
129 |
|
|
|
130 |
|
|
constant ADDR_LO_BITS : integer := alb(WIDTH);
|
131 |
|
|
|
132 |
|
|
-- map the data bits
|
133 |
|
|
function msb_d (
|
134 |
|
|
constant wdt : integer)
|
135 |
|
|
return integer is
|
136 |
|
|
variable dmsb : integer := 8;
|
137 |
|
|
begin -- msb_d
|
138 |
|
|
|
139 |
|
|
if (wdt = 4) then
|
140 |
|
|
dmsb := 3;
|
141 |
|
|
elsif (wdt = 9) then
|
142 |
|
|
dmsb := 7;
|
143 |
|
|
elsif (wdt = 18) then
|
144 |
|
|
dmsb := 15;
|
145 |
|
|
elsif (wdt = 36) then
|
146 |
|
|
dmsb := 31;
|
147 |
|
|
else
|
148 |
|
|
dmsb := 63;
|
149 |
|
|
end if;
|
150 |
|
|
return dmsb;
|
151 |
|
|
end msb_d;
|
152 |
|
|
|
153 |
|
|
constant D_MSB : integer := msb_d(WIDTH);
|
154 |
|
|
|
155 |
|
|
-- map the data parity bits
|
156 |
|
|
constant DP_LSB : integer := D_MSB + 1;
|
157 |
|
|
|
158 |
|
|
function msb_dp (
|
159 |
|
|
constant wdt : integer)
|
160 |
|
|
return integer is
|
161 |
|
|
variable dpmsb : integer := 8;
|
162 |
|
|
begin -- msb_dp
|
163 |
|
|
|
164 |
|
|
if (wdt = 4) then
|
165 |
|
|
dpmsb := 4;
|
166 |
|
|
elsif (wdt = 9) then
|
167 |
|
|
dpmsb := 8;
|
168 |
|
|
elsif (wdt = 18) then
|
169 |
|
|
dpmsb := 17;
|
170 |
|
|
elsif (wdt = 36) then
|
171 |
|
|
dpmsb := 35;
|
172 |
|
|
else
|
173 |
|
|
dpmsb := 71;
|
174 |
|
|
end if;
|
175 |
|
|
return dpmsb;
|
176 |
|
|
end msb_dp;
|
177 |
|
|
|
178 |
|
|
function pad_val (
|
179 |
|
|
in_vec : std_logic_vector;
|
180 |
|
|
range_hi : integer;
|
181 |
|
|
range_lo : integer;
|
182 |
|
|
pad : std_logic;
|
183 |
|
|
op_len : integer)
|
184 |
|
|
return std_logic_vector is
|
185 |
|
|
variable ret : std_logic_vector(op_len-1 downto 0) := (others => '0');
|
186 |
|
|
begin -- pad_val
|
187 |
|
|
for i in 0 to op_len-1 loop
|
188 |
|
|
if ((i >= range_lo) and (i <= range_hi)) then
|
189 |
|
|
ret(i) := in_vec(i - range_lo);
|
190 |
|
|
else
|
191 |
|
|
ret(i) := pad;
|
192 |
|
|
end if;
|
193 |
|
|
end loop; -- i
|
194 |
|
|
return ret;
|
195 |
|
|
end pad_val;
|
196 |
|
|
|
197 |
|
|
constant DP_MSB : integer := msb_dp(WIDTH);
|
198 |
|
|
|
199 |
|
|
constant DPW : integer := DP_MSB - DP_LSB + 1;
|
200 |
|
|
|
201 |
|
|
constant WRITE_MODE : string := "NO_CHANGE";
|
202 |
|
|
|
203 |
|
|
-- ground and tied_to_vcc_i signals
|
204 |
|
|
signal tied_to_ground_i : std_logic;
|
205 |
|
|
signal tied_to_ground_vec_i : std_logic_vector(31 downto 0);
|
206 |
|
|
signal tied_to_vcc_i : std_logic;
|
207 |
|
|
|
208 |
|
|
|
209 |
|
|
-- X-HDL generated signals
|
210 |
|
|
|
211 |
|
|
signal v6pcie2 : std_logic_vector(7 downto 0) := (others => '0');
|
212 |
|
|
signal v6pcie5 : std_logic_vector(15 downto 0) := (others => '0');
|
213 |
|
|
signal v6pcie7 : std_logic_vector(15 downto 0) := (others => '0');
|
214 |
|
|
signal v6pcie11 : std_logic_vector(31 downto 0) := (others => '0');
|
215 |
|
|
signal v6pcie12 : std_logic_vector(3 downto 0) := (others => '0');
|
216 |
|
|
signal v6pcie15 : std_logic_vector(63 downto 0) := (others => '0');
|
217 |
|
|
signal v6pcie16 : std_logic_vector(7 downto 0) := (others => '0');
|
218 |
|
|
signal v6pcie13 : std_logic_vector((DP_MSB - DP_LSB) downto 0) := (others => '0');
|
219 |
|
|
|
220 |
|
|
-- dob_unused and dopb_unused only needed when WIDTH < 36. how to declare
|
221 |
|
|
-- these accordingly.
|
222 |
|
|
signal dob_unused : std_logic_vector(31 - D_MSB - 1 downto 0);
|
223 |
|
|
signal dopb_unused : std_logic_vector(4 - DPW - 1 downto 0);
|
224 |
|
|
|
225 |
|
|
|
226 |
|
|
-- Declare intermediate signals for referenced outputs
|
227 |
|
|
signal rdata_o_v6pcie0 : std_logic_vector(WIDTH - 1 downto 0);
|
228 |
|
|
|
229 |
|
|
begin
|
230 |
|
|
|
231 |
|
|
--------------------------- Static signal Assignments ---------------------
|
232 |
|
|
|
233 |
|
|
tied_to_ground_i <= '0';
|
234 |
|
|
tied_to_ground_vec_i(31 downto 0) <= (others => '0');
|
235 |
|
|
tied_to_vcc_i <= '1';
|
236 |
|
|
|
237 |
|
|
-- Drive referenced outputs
|
238 |
|
|
rdata_o <= rdata_o_v6pcie0;
|
239 |
|
|
|
240 |
|
|
--synthesis translate_off
|
241 |
|
|
process
|
242 |
|
|
begin
|
243 |
|
|
--$display("[%t] %m DOB_REG %0d WIDTH %0d ADDR_MSB %0d ADDR_LO_BITS %0d DP_MSB %0d DP_LSB %0d D_MSB %0d",
|
244 |
|
|
-- $time, DOB_REG, WIDTH, ADDR_MSB, ADDR_LO_BITS, DP_MSB, DP_LSB, D_MSB);
|
245 |
|
|
|
246 |
|
|
case WIDTH is
|
247 |
|
|
when 4 | 9 | 18 | 36 | 72 =>
|
248 |
|
|
when others => -- case (WIDTH)
|
249 |
|
|
-- $display("[%t] %m Error WIDTH %0d not supported", now, to_stdlogic(WIDTH));
|
250 |
|
|
-- $finish();
|
251 |
|
|
end case;
|
252 |
|
|
wait;
|
253 |
|
|
end process;
|
254 |
|
|
|
255 |
|
|
--synthesis translate_on
|
256 |
|
|
|
257 |
|
|
use_ramb36sdp : if (WIDTH = 72) generate
|
258 |
|
|
|
259 |
|
|
v6pcie2 <= (others => wen_i);
|
260 |
|
|
rdata_o_v6pcie0 <= v6pcie16((DP_MSB - DP_LSB) downto 0) & v6pcie15(D_MSB downto 0);
|
261 |
|
|
|
262 |
|
|
-- use RAMB36SDP if the width is 72
|
263 |
|
|
ramb36sdp_i : RAMB36SDP
|
264 |
|
|
generic map (
|
265 |
|
|
DO_REG => DOB_REG
|
266 |
|
|
)
|
267 |
|
|
port map (
|
268 |
|
|
DBITERR => open,
|
269 |
|
|
ECCPARITY => open,
|
270 |
|
|
SBITERR => open,
|
271 |
|
|
WRCLK => user_clk_i,
|
272 |
|
|
SSR => '0',
|
273 |
|
|
WRADDR => waddr_i(ADDR_MSB downto 0),
|
274 |
|
|
DI => wdata_i(D_MSB downto 0),
|
275 |
|
|
DIP => wdata_i(DP_MSB downto DP_LSB),
|
276 |
|
|
WREN => wen_i,
|
277 |
|
|
WE => v6pcie2,
|
278 |
|
|
|
279 |
|
|
RDCLK => user_clk_i,
|
280 |
|
|
RDADDR => raddr_i(ADDR_MSB downto 0),
|
281 |
|
|
DO => v6pcie15,
|
282 |
|
|
DOP => v6pcie16,
|
283 |
|
|
RDEN => ren_i,
|
284 |
|
|
REGCE => rce_i
|
285 |
|
|
);
|
286 |
|
|
|
287 |
|
|
-- use RAMB36's if the width is 4, 9, 18, or 36
|
288 |
|
|
end generate;
|
289 |
|
|
use_ramb36_1 : if (WIDTH = 36) generate
|
290 |
|
|
|
291 |
|
|
v6pcie2 <= (others => wen_i);
|
292 |
|
|
v6pcie5 <= pad_val(waddr_i(ADDR_MSB downto 0), ADDR_MSB + ADDR_LO_BITS, ADDR_LO_BITS, '1', 16);
|
293 |
|
|
v6pcie7 <= pad_val(raddr_i(ADDR_MSB downto 0), ADDR_MSB + ADDR_LO_BITS, ADDR_LO_BITS, '1', 16);
|
294 |
|
|
rdata_o_v6pcie0 <= v6pcie16((DP_MSB - DP_LSB) downto 0) & v6pcie15(D_MSB downto 0);
|
295 |
|
|
|
296 |
|
|
ramb36_i : RAMB36
|
297 |
|
|
generic map (
|
298 |
|
|
DOA_REG => 0,
|
299 |
|
|
DOB_REG => DOB_REG,
|
300 |
|
|
READ_WIDTH_A => 0,
|
301 |
|
|
READ_WIDTH_B => WIDTH,
|
302 |
|
|
WRITE_WIDTH_A => WIDTH,
|
303 |
|
|
WRITE_WIDTH_B => 0,
|
304 |
|
|
WRITE_MODE_A => WRITE_MODE
|
305 |
|
|
)
|
306 |
|
|
port map (
|
307 |
|
|
CLKA => user_clk_i,
|
308 |
|
|
SSRA => '0',
|
309 |
|
|
REGCEA => '0',
|
310 |
|
|
CASCADEINLATA => '0',
|
311 |
|
|
CASCADEINREGA => '0',
|
312 |
|
|
CASCADEOUTLATA => open,
|
313 |
|
|
CASCADEOUTREGA => open,
|
314 |
|
|
DOA => open,
|
315 |
|
|
DOPA => open,
|
316 |
|
|
ADDRA => v6pcie5,
|
317 |
|
|
DIA => wdata_i(D_MSB downto 0),
|
318 |
|
|
DIPA => wdata_i(DP_MSB downto DP_LSB),
|
319 |
|
|
ENA => wen_i,
|
320 |
|
|
WEA => v6pcie2(3 downto 0),
|
321 |
|
|
CLKB => user_clk_i,
|
322 |
|
|
SSRB => '0',
|
323 |
|
|
WEB => "0000",
|
324 |
|
|
CASCADEINLATB => '0',
|
325 |
|
|
CASCADEINREGB => '0',
|
326 |
|
|
CASCADEOUTLATB => open,
|
327 |
|
|
CASCADEOUTREGB => open,
|
328 |
|
|
DIB => "00000000000000000000000000000000",
|
329 |
|
|
DIPB => "0000",
|
330 |
|
|
ADDRB => v6pcie7,
|
331 |
|
|
DOB => v6pcie15(31 downto 0),
|
332 |
|
|
DOPB => v6pcie16(3 downto 0),
|
333 |
|
|
ENB => ren_i,
|
334 |
|
|
REGCEB => rce_i
|
335 |
|
|
);
|
336 |
|
|
|
337 |
|
|
end generate;
|
338 |
|
|
use_ramb36_2 : if (WIDTH < 36 and WIDTH > 4) generate
|
339 |
|
|
|
340 |
|
|
v6pcie2 <= (others => wen_i);
|
341 |
|
|
v6pcie5 <= pad_val(waddr_i(ADDR_MSB downto 0), ADDR_MSB + ADDR_LO_BITS, ADDR_LO_BITS, '1', 16);
|
342 |
|
|
v6pcie7 <= pad_val(raddr_i(ADDR_MSB downto 0), ADDR_MSB + ADDR_LO_BITS, ADDR_LO_BITS, '1', 16);
|
343 |
|
|
v6pcie11 <= pad_val(wdata_i(D_MSB downto 0), D_MSB, 0, '0', 32);
|
344 |
|
|
v6pcie13 <= wdata_i(DP_MSB downto DP_LSB);
|
345 |
|
|
v6pcie12 <= pad_val(v6pcie13((DP_MSB - DP_LSB) downto 0), DP_MSB - DP_LSB, 0, '0', 4);
|
346 |
|
|
rdata_o_v6pcie0 <= v6pcie16((DP_MSB - DP_LSB) downto 0) & v6pcie15(D_MSB downto 0);
|
347 |
|
|
|
348 |
|
|
ramb36_i : RAMB36
|
349 |
|
|
generic map (
|
350 |
|
|
DOA_REG => 0,
|
351 |
|
|
DOB_REG => DOB_REG,
|
352 |
|
|
READ_WIDTH_A => 0,
|
353 |
|
|
READ_WIDTH_B => WIDTH,
|
354 |
|
|
WRITE_WIDTH_A => WIDTH,
|
355 |
|
|
WRITE_WIDTH_B => 0,
|
356 |
|
|
WRITE_MODE_A => WRITE_MODE
|
357 |
|
|
)
|
358 |
|
|
port map (
|
359 |
|
|
CLKA => user_clk_i,
|
360 |
|
|
SSRA => '0',
|
361 |
|
|
REGCEA => '0',
|
362 |
|
|
CASCADEINLATA => '0',
|
363 |
|
|
CASCADEINREGA => '0',
|
364 |
|
|
CASCADEOUTLATA => open,
|
365 |
|
|
CASCADEOUTREGA => open,
|
366 |
|
|
DOA => open,
|
367 |
|
|
DOPA => open,
|
368 |
|
|
ADDRA => v6pcie5,
|
369 |
|
|
DIA => v6pcie11,
|
370 |
|
|
DIPA => v6pcie12,
|
371 |
|
|
ENA => wen_i,
|
372 |
|
|
WEA => v6pcie2(3 downto 0),
|
373 |
|
|
CLKB => user_clk_i,
|
374 |
|
|
SSRB => '0',
|
375 |
|
|
WEB => "0000",
|
376 |
|
|
CASCADEINLATB => '0',
|
377 |
|
|
CASCADEINREGB => '0',
|
378 |
|
|
CASCADEOUTLATB => open,
|
379 |
|
|
CASCADEOUTREGB => open,
|
380 |
|
|
DIB => "00000000000000000000000000000000",
|
381 |
|
|
DIPB => "0000",
|
382 |
|
|
ADDRB => v6pcie7,
|
383 |
|
|
DOB => v6pcie15(31 downto 0),
|
384 |
|
|
DOPB => v6pcie16(3 downto 0),
|
385 |
|
|
ENB => ren_i,
|
386 |
|
|
REGCEB => rce_i
|
387 |
|
|
);
|
388 |
|
|
|
389 |
|
|
end generate;
|
390 |
|
|
use_ramb36_3 : if (WIDTH = 4) generate
|
391 |
|
|
|
392 |
|
|
v6pcie2 <= (others => wen_i);
|
393 |
|
|
v6pcie5 <= pad_val(waddr_i(ADDR_MSB downto 0), ADDR_MSB + ADDR_LO_BITS, ADDR_LO_BITS, '1', 16);
|
394 |
|
|
v6pcie7 <= pad_val(raddr_i(ADDR_MSB downto 0), ADDR_MSB + ADDR_LO_BITS, ADDR_LO_BITS, '1', 16);
|
395 |
|
|
v6pcie11 <= pad_val(wdata_i(D_MSB downto 0), D_MSB, 0, '0', 32);
|
396 |
|
|
rdata_o_v6pcie0 <= v6pcie15(D_MSB downto 0);
|
397 |
|
|
|
398 |
|
|
ramb36_i : RAMB36
|
399 |
|
|
generic map (
|
400 |
|
|
dob_reg => DOB_REG,
|
401 |
|
|
read_width_a => 0,
|
402 |
|
|
read_width_b => WIDTH,
|
403 |
|
|
write_width_a => WIDTH,
|
404 |
|
|
write_width_b => 0,
|
405 |
|
|
write_mode_a => WRITE_MODE
|
406 |
|
|
)
|
407 |
|
|
port map (
|
408 |
|
|
CLKA => user_clk_i,
|
409 |
|
|
SSRA => '0',
|
410 |
|
|
REGCEA => '0',
|
411 |
|
|
CASCADEINLATA => '0',
|
412 |
|
|
CASCADEINREGA => '0',
|
413 |
|
|
CASCADEOUTLATA => open,
|
414 |
|
|
CASCADEOUTREGA => open,
|
415 |
|
|
DOA => open,
|
416 |
|
|
DOPA => open,
|
417 |
|
|
ADDRA => v6pcie5,
|
418 |
|
|
DIA => v6pcie11,
|
419 |
|
|
DIPA => tied_to_ground_vec_i(3 downto 0),
|
420 |
|
|
ENA => wen_i,
|
421 |
|
|
WEA => v6pcie2(3 downto 0),
|
422 |
|
|
CLKB => user_clk_i,
|
423 |
|
|
SSRB => '0',
|
424 |
|
|
WEB => "0000",
|
425 |
|
|
CASCADEINLATB => '0',
|
426 |
|
|
CASCADEINREGB => '0',
|
427 |
|
|
CASCADEOUTLATB => open,
|
428 |
|
|
CASCADEOUTREGB => open,
|
429 |
|
|
ADDRB => v6pcie7,
|
430 |
|
|
DIB => tied_to_ground_vec_i,
|
431 |
|
|
DIPB => tied_to_ground_vec_i(3 downto 0),
|
432 |
|
|
DOB => v6pcie15(31 downto 0),
|
433 |
|
|
DOPB => open,
|
434 |
|
|
ENB => ren_i,
|
435 |
|
|
REGCEB => rce_i
|
436 |
|
|
);
|
437 |
|
|
|
438 |
|
|
|
439 |
|
|
-- block: use_ramb36
|
440 |
|
|
end generate;
|
441 |
|
|
|
442 |
|
|
-- pcie_bram_v6
|
443 |
|
|
end v6_pcie;
|
444 |
|
|
|
445 |
|
|
|