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[/] [pcie_ds_dma/] [trunk/] [core/] [ds_dma64/] [pcie_src/] [pcie_core64_m1/] [source_virtex6/] [pcie_clocking_v6.vhd] - Blame information for rev 2

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-------------------------------------------------------------------------------
2
--
3
-- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
4
--
5
-- This file contains confidential and proprietary information
6
-- of Xilinx, Inc. and is protected under U.S. and
7
-- international copyright and other intellectual property
8
-- laws.
9
--
10
-- DISCLAIMER
11
-- This disclaimer is not a license and does not grant any
12
-- rights to the materials distributed herewith. Except as
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-- otherwise provided in a valid license issued to you by
14
-- Xilinx, and to the maximum extent permitted by applicable
15
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
16
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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-- (2) Xilinx shall not be liable (whether in contract or tort,
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-- including negligence, or under any other theory of
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-- liability) for any loss or damage of any kind or nature
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-- related to, arising under or in connection with these
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-- materials, including for any direct, or any indirect,
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-- special, incidental, or consequential loss or damage
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-- (including loss of data, profits, goodwill, or any type of
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-- loss or damage suffered as a result of any action brought
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-- by a third party) even if such damage or loss was
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-- reasonably foreseeable or Xilinx had been advised of the
30
-- possibility of the same.
31
--
32
-- CRITICAL APPLICATIONS
33
-- Xilinx products are not designed or intended to be fail-
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-- safe, or for use in any application requiring fail-safe
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-- performance, such as life-support or safety devices or
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-- systems, Class III medical devices, nuclear facilities,
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-- applications related to the deployment of airbags, or any
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-- other applications that could lead to death, personal
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-- injury, or severe property or environmental damage
40
-- (individually and collectively, "Critical
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-- Applications"). Customer assumes the sole risk and
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-- liability of any use of Xilinx products in Critical
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-- Applications, subject only to applicable laws and
44
-- regulations governing limitations on product liability.
45
--
46
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
47
-- PART OF THIS FILE AT ALL TIMES.
48
--
49
-------------------------------------------------------------------------------
50
-- Project    : Virtex-6 Integrated Block for PCI Express
51
-- File       : pcie_clocking_v6.vhd
52
-- Version    : 2.3
53
---- Description: Clocking module for Virtex6 PCIe Block
54
----
55
----
56
----
57
----------------------------------------------------------------------------------
58
 
59
library ieee;
60
   use ieee.std_logic_1164.all;
61
 
62
library unisim;
63
use unisim.vcomponents.all;
64
 
65
entity pcie_clocking_v6 is
66
   generic (
67
 
68
      IS_ENDPOINT                                  : boolean := TRUE;
69
      CAP_LINK_WIDTH                               : integer := 8;              -- 1 - x1 , 2 - x2 , 4 - x4 , 8 - x8
70
      CAP_LINK_SPEED                               : integer := 1;              -- 1 - Gen1 , 2 - Gen2
71
      REF_CLK_FREQ                                 : integer := 0;               -- 0 - 100 MHz , 1 - 125 MHz , 2 - 250 MHz
72
      USER_CLK_FREQ                                : integer := 3               -- 0 - 31.25 MHz , 1 - 62.5 MHz , 2 - 125 MHz , 3 - 250 MHz , 4 - 500Mhz
73
 
74
   );
75
   port (
76
      sys_clk                                      : in std_logic;
77
      gt_pll_lock                                  : in std_logic;
78
      sel_lnk_rate                                 : in std_logic;
79
      sel_lnk_width                                : in std_logic_vector(1 downto 0);
80
      sys_clk_bufg                                 : out std_logic;
81
      pipe_clk                                     : out std_logic;
82
      user_clk                                     : out std_logic;
83
      block_clk                                    : out std_logic;
84
      drp_clk                                      : out std_logic;
85
      clock_locked                                 : out std_logic
86
   );
87
end pcie_clocking_v6;
88
 
89
architecture v6_pcie of pcie_clocking_v6 is
90
 
91
  -- MMCM Configuration
92
 
93
  function clkin_prd(
94
    constant REF_CLK_FREQ     : integer)
95
    return real is
96
     variable CLKIN_PERD : real := 0.0;
97
  begin  -- clkin_prd
98
 
99
    if (REF_CLK_FREQ = 0) then
100
      CLKIN_PERD := 10.0;
101
    elsif (REF_CLK_FREQ = 1) then
102
      CLKIN_PERD := 8.0;
103
    elsif (REF_CLK_FREQ = 2) then
104
      CLKIN_PERD := 4.0;
105
    else
106
      CLKIN_PERD := 0.0;
107
    end if;
108
    return CLKIN_PERD;
109
  end clkin_prd;
110
 
111
   constant mmcm_clockin_period                    : real := clkin_prd(REF_CLK_FREQ);
112
 
113
  function clkfb_mul(
114
    constant REF_CLK_FREQ     : integer)
115
    return real is
116
     variable CLKFB_MULT : real := 0.0;
117
  begin  -- clkfb_mul
118
 
119
    if (REF_CLK_FREQ = 0) then
120
      CLKFB_MULT := 10.0;
121
    elsif (REF_CLK_FREQ = 1) then
122
      CLKFB_MULT := 8.0;
123
    elsif (REF_CLK_FREQ = 2) then
124
      CLKFB_MULT := 8.0;
125
    else
126
      CLKFB_MULT := 0.0;
127
    end if;
128
    return CLKFB_MULT;
129
  end clkfb_mul;
130
 
131
   constant mmcm_clockfb_mult                      : real := clkfb_mul(REF_CLK_FREQ);
132
 
133
  function divclk_div(
134
    constant REF_CLK_FREQ     : integer)
135
    return integer is
136
     variable DIVCLK_DIVIDE : integer := 0;
137
  begin  -- divclk_div
138
 
139
    if (REF_CLK_FREQ = 0) then
140
      DIVCLK_DIVIDE := 1;
141
    elsif (REF_CLK_FREQ = 1) then
142
      DIVCLK_DIVIDE := 1;
143
    elsif (REF_CLK_FREQ = 2) then
144
      DIVCLK_DIVIDE := 2;
145
    else
146
      DIVCLK_DIVIDE := 0;
147
    end if;
148
    return DIVCLK_DIVIDE;
149
  end divclk_div;
150
 
151
   constant mmcm_divclk_divide                     : integer := divclk_div(REF_CLK_FREQ);
152
 
153
   constant mmcm_clock0_div                        : real := 4.0;
154
   constant mmcm_clock1_div                        : integer := 8;
155
 
156
   constant TCQ : integer := 1;
157
 
158
  function clk2_div(
159
    constant LNK_WDT          : integer;
160
    constant LNK_SPD          : integer;
161
    constant USR_CLK_FREQ     : integer)
162
    return integer is
163
     variable CLK_DIV : integer := 1;
164
  begin  -- clk2_div
165
 
166
    if ((LNK_WDT = 1) and (LNK_SPD = 1) and (USR_CLK_FREQ = 0)) then
167
      CLK_DIV := 32;
168
    elsif ((LNK_WDT = 1) and (LNK_SPD = 1) and (USR_CLK_FREQ = 1)) then
169
      CLK_DIV := 16;
170
    elsif ((LNK_WDT = 1) and (LNK_SPD = 2) and (USR_CLK_FREQ = 1)) then
171
      CLK_DIV := 16;
172
    elsif ((LNK_WDT = 2) and (LNK_SPD = 1) and (USR_CLK_FREQ = 1)) then
173
      CLK_DIV := 16;
174
    else
175
      CLK_DIV := 2;
176
    end if;
177
    return CLK_DIV;
178
  end clk2_div;
179
 
180
   constant mmcm_clock2_div                        : integer := clk2_div(CAP_LINK_WIDTH, CAP_LINK_SPEED, USER_CLK_FREQ);
181
   constant mmcm_clock3_div                        : integer := 2;
182
 
183
   signal mmcm_locked                              : std_logic;
184
   signal mmcm_clkfbin                             : std_logic;
185
   signal mmcm_clkfbout                            : std_logic;
186
   signal mmcm_reset                               : std_logic;
187
   signal clk_500                                  : std_logic;
188
   signal clk_250                                  : std_logic;
189
   signal clk_125                                  : std_logic;
190
   signal user_clk_prebuf                          : std_logic;
191
   signal sel_lnk_rate_d                           : std_logic;
192
   signal reg_clock_locked                         : std_logic_vector(1 downto 0) := "11";
193
 
194
   -- Declare intermediate signals for referenced outputs
195
   signal sys_clk_bufg_v6pcie3                         : std_logic;
196
   signal pipe_clk_v6pcie                              : std_logic;
197
   signal user_clk_v6pcie4                             : std_logic;
198
   signal block_clk_v6pcie0                            : std_logic;
199
   signal drp_clk_v6pcie1                              : std_logic;
200
 
201
  signal clock_locked_int : std_logic;
202
 
203
begin
204
   -- Drive referenced outputs
205
   sys_clk_bufg <= sys_clk_bufg_v6pcie3;
206
   pipe_clk <= pipe_clk_v6pcie;
207
   user_clk <= user_clk_v6pcie4;
208
   block_clk <= block_clk_v6pcie0;
209
   drp_clk <= drp_clk_v6pcie1;
210
   clock_locked <= clock_locked_int;
211
   clock_locked_int <= (not(reg_clock_locked(1))) and mmcm_locked;
212
 
213
 
214
   -- MMCM Reset
215
     mmcm_reset <= '0';
216
 
217
   -- PIPE Clock BUFG.
218
 
219
   GEN1_LINK : if (CAP_LINK_SPEED = 1) generate
220
      pipe_clk_bufg : BUFG port map (O  => pipe_clk_v6pcie, I  => clk_125 );
221
 
222
   end generate;
223
 
224
   GEN2_LINK : if (CAP_LINK_SPEED = 2) generate
225
      sel_lnk_rate_delay : SRL16E generic map ( INIT  => X"0000" )
226
                                  port map (
227
                                    Q    => sel_lnk_rate_d,
228
                                    D    => sel_lnk_rate,
229
                                    CLK  => pipe_clk_v6pcie,
230
                                    CE   => clock_locked_int,
231
                                    A3   => '1',
232
                                    A2   => '1',
233
                                    A1   => '1',
234
                                    A0   => '1'
235
                                    );
236
 
237
      pipe_clk_bufgmux : BUFGMUX port map (
238
                                    O   => pipe_clk_v6pcie,
239
                                    I0  => clk_125,
240
                                    I1  => clk_250,
241
                                    S   => sel_lnk_rate_d
242
                                    );
243
 
244
      end generate;
245
   ILLEGAL_LINK_SPEED : if ((CAP_LINK_SPEED /= 1) and (CAP_LINK_SPEED /= 2)) generate
246
 
247
         --$display("Confiuration Error : CAP_LINK_SPEED = %d, must be either 1 or 2.", CAP_LINK_SPEED);
248
         --$finish;
249
 
250
   end generate;
251
 
252
   -- User Clock BUFG.
253
   x1_GEN1_31_25 : if ((CAP_LINK_WIDTH = 1) and (CAP_LINK_SPEED = 1) and (USER_CLK_FREQ = 0)) generate
254
 
255
     user_clk_bufg : BUFG port map ( O => user_clk_v6pcie4, I => user_clk_prebuf );
256
 
257
   end generate;
258
 
259
   x1_GEN1_62_50 : if ((CAP_LINK_WIDTH = 1) and (CAP_LINK_SPEED = 1) and (USER_CLK_FREQ = 1)) generate
260
 
261
     user_clk_bufg : BUFG port map ( O => user_clk_v6pcie4, I => user_clk_prebuf );
262
 
263
   end generate;
264
 
265
   x1_GEN1_125_00 : if ((CAP_LINK_WIDTH = 1) and (CAP_LINK_SPEED = 1) and (USER_CLK_FREQ = 2)) generate
266
 
267
     user_clk_bufg : BUFG port map ( O => user_clk_v6pcie4, I => clk_125 );
268
 
269
   end generate;
270
 
271
   x1_GEN1_250_00 : if ((CAP_LINK_WIDTH = 1) and (CAP_LINK_SPEED = 1) and (USER_CLK_FREQ = 3)) generate
272
 
273
     user_clk_bufg : BUFG port map ( O => user_clk_v6pcie4, I => clk_250 );
274
 
275
   end generate;
276
 
277
   x1_GEN2_62_50 : if ((CAP_LINK_WIDTH = 1) and (CAP_LINK_SPEED = 2) and (USER_CLK_FREQ = 1)) generate
278
 
279
     user_clk_bufg : BUFG port map ( O => user_clk_v6pcie4, I  => user_clk_prebuf );
280
 
281
   end generate;
282
 
283
   x1_GEN2_125_00 : if ((CAP_LINK_WIDTH = 1) and (CAP_LINK_SPEED = 2) and (USER_CLK_FREQ = 2)) generate
284
 
285
     user_clk_bufg : BUFG port map ( O => user_clk_v6pcie4, I  => clk_125 );
286
 
287
   end generate;
288
 
289
   x1_GEN2_250_00 : if ((CAP_LINK_WIDTH = 1) and (CAP_LINK_SPEED = 2) and (USER_CLK_FREQ = 3)) generate
290
 
291
     user_clk_bufg : BUFG port map ( O => user_clk_v6pcie4, I => clk_250 );
292
 
293
   end generate;
294
 
295
   x2_GEN1_62_50 : if ((CAP_LINK_WIDTH = 2) and (CAP_LINK_SPEED = 1) and (USER_CLK_FREQ = 1)) generate
296
 
297
     user_clk_bufg : BUFG port map ( O => user_clk_v6pcie4, I => user_clk_prebuf );
298
 
299
   end generate;
300
 
301
   x2_GEN1_125_00 : if ((CAP_LINK_WIDTH = 2) and (CAP_LINK_SPEED = 1) and (USER_CLK_FREQ = 2)) generate
302
 
303
     user_clk_bufg : BUFG port map ( O => user_clk_v6pcie4, I => clk_125 );
304
 
305
   end generate;
306
 
307
   x2_GEN1_250_00 : if ((CAP_LINK_WIDTH = 2) and (CAP_LINK_SPEED = 1) and (USER_CLK_FREQ = 3)) generate
308
 
309
     user_clk_bufg : BUFG port map ( O => user_clk_v6pcie4, I => clk_250 );
310
 
311
   end generate;
312
 
313
   x2_GEN2_125_00 : if ((CAP_LINK_WIDTH = 2) and (CAP_LINK_SPEED = 2) and (USER_CLK_FREQ = 2)) generate
314
 
315
     user_clk_bufg : BUFG port map ( O => user_clk_v6pcie4, I => clk_125 );
316
 
317
   end generate;
318
 
319
   x2_GEN2_250_00 : if ((CAP_LINK_WIDTH = 2) and (CAP_LINK_SPEED = 2) and (USER_CLK_FREQ = 3)) generate
320
 
321
     user_clk_bufg : BUFG port map ( O => user_clk_v6pcie4, I => clk_250 );
322
 
323
   end generate;
324
 
325
   x4_GEN1_125_00 : if ((CAP_LINK_WIDTH = 4) and (CAP_LINK_SPEED = 1) and (USER_CLK_FREQ = 2)) generate
326
 
327
     user_clk_bufg : BUFG port map ( O => user_clk_v6pcie4, I => clk_125 );
328
 
329
   end generate;
330
 
331
   x4_GEN1_250_00 : if ((CAP_LINK_WIDTH = 4) and (CAP_LINK_SPEED = 1) and (USER_CLK_FREQ = 3)) generate
332
 
333
     user_clk_bufg : BUFG port map ( O => user_clk_v6pcie4, I => clk_250 );
334
 
335
   end generate;
336
 
337
   x4_GEN2_250_00 : if ((CAP_LINK_WIDTH = 4) and (CAP_LINK_SPEED = 2) and (USER_CLK_FREQ = 3)) generate
338
 
339
     user_clk_bufg : BUFG port map ( O => user_clk_v6pcie4, I => clk_250 );
340
 
341
   end generate;
342
 
343
   x8_GEN1_250_00 : if ((CAP_LINK_WIDTH = 8) and (CAP_LINK_SPEED = 1) and (USER_CLK_FREQ = 3)) generate
344
 
345
     user_clk_bufg : BUFG port map ( O => user_clk_v6pcie4, I => clk_250 );
346
 
347
   end generate;
348
 
349
   x8_GEN2_250_00 : if ((CAP_LINK_WIDTH = 8) and (CAP_LINK_SPEED = 2) and (USER_CLK_FREQ = 4)) generate
350
 
351
     user_clk_bufg : BUFG port map ( O => user_clk_v6pcie4, I => clk_250 );
352
 
353
     block_clk_bufg : BUFG port map ( O => block_clk_v6pcie0, I => clk_500 );
354
 
355
   end generate;
356
 
357
--   v6pcie42 : if (not((CAP_LINK_WIDTH = 8) and (CAP_LINK_SPEED = 2) and (USER_CLK_FREQ = 4))) generate
358
 
359
    --$display("Confiuration Error : Unsupported Link Width, Link Speed and User Clock Frequency Combination");
360
    --$finish;
361
 
362
--   end generate;
363
 
364
   -- DRP clk
365
   drp_clk_bufg_i : BUFG port map ( O => drp_clk_v6pcie1, I => clk_125 );
366
 
367
   -- Feedback BUFG. Required for Temp Compensation
368
   clkfbin_bufg_i : BUFG port map ( O => mmcm_clkfbin, I => mmcm_clkfbout );
369
 
370
   -- sys_clk BUFG. 
371
   sys_clk_bufg_i : BUFG port map ( O => sys_clk_bufg_v6pcie3, I => sys_clk );
372
 
373
   mmcm_adv_i : MMCM_ADV
374
      generic map (
375
         -- 5 for 100 MHz , 4 for 125 MHz , 2 for 250 MHz
376
         CLKFBOUT_MULT_F   => mmcm_clockfb_mult,
377
         DIVCLK_DIVIDE     => mmcm_divclk_divide,
378
         CLKFBOUT_PHASE    => 0.0,
379
         -- 10 for 100 MHz, 4 for 250 MHz
380
         CLKIN1_PERIOD     => mmcm_clockin_period,
381
         CLKIN2_PERIOD     => mmcm_clockin_period,
382
         -- 500 MHz / mmcm_clockx_div  
383
         CLKOUT0_DIVIDE_F  => mmcm_clock0_div,
384
         CLKOUT0_PHASE     => 0.0,
385
         CLKOUT1_DIVIDE    => mmcm_clock1_div,
386
         CLKOUT1_PHASE     => 0.0,
387
         CLKOUT2_DIVIDE    => mmcm_clock2_div,
388
         CLKOUT2_PHASE     => 0.0,
389
         CLKOUT3_DIVIDE    => mmcm_clock3_div,
390
         CLKOUT3_PHASE     => 0.0
391
      )
392
      port map (
393
         clkfbout      => mmcm_clkfbout,
394
         clkout0       => clk_250,              -- 250 MHz for pipe_clk
395
         clkout1       => clk_125,              -- 125 MHz for pipe_clk
396
         clkout2       => user_clk_prebuf,      -- user clk
397
         clkout3       => clk_500,
398
         clkout4       => open,
399
         clkout5       => open,
400
         clkout6       => open,
401
         do            => open,
402
         drdy          => open,
403
         clkfboutb     => open,
404
         clkfbstopped  => open,
405
         clkinstopped  => open,
406
         clkout0b      => open,
407
         clkout1b      => open,
408
         clkout2b      => open,
409
         clkout3b      => open,
410
         psdone        => open,
411
         locked        => mmcm_locked,
412
         clkfbin       => mmcm_clkfbin,
413
         clkin1        => sys_clk,
414
         clkin2        => '0',
415
         clkinsel      => '1',
416
         daddr         => "0000000",
417
         dclk          => '0',
418
         den           => '0',
419
         di            => "0000000000000000",
420
         dwe           => '0',
421
         psen          => '0',
422
         psincdec      => '0',
423
         pwrdwn        => '0',
424
         psclk         => '0',
425
         rst           => mmcm_reset
426
      );
427
 
428
  -- Synchronize MMCM locked output
429
  process (pipe_clk_v6pcie, gt_pll_lock)
430
  begin
431
 
432
    if ((not(gt_pll_lock)) = '1') then
433
 
434
      reg_clock_locked <= "11" after (TCQ)*1 ps;
435
 
436
    elsif (pipe_clk_v6pcie'event and pipe_clk_v6pcie = '1') then
437
 
438
      reg_clock_locked <= (reg_clock_locked(0) & '0') after (TCQ)*1 ps;
439
 
440
    end if;
441
  end process;
442
 
443
end v6_pcie;
444
 
445
 
446
 

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