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-------------------------------------------------------------------------------
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--
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-- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
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--
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-- This file contains confidential and proprietary information
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-- of Xilinx, Inc. and is protected under U.S. and
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-- international copyright and other intellectual property
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-- laws.
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--
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-- DISCLAIMER
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-- This disclaimer is not a license and does not grant any
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-- rights to the materials distributed herewith. Except as
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-- otherwise provided in a valid license issued to you by
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-- Xilinx, and to the maximum extent permitted by applicable
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-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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-- (2) Xilinx shall not be liable (whether in contract or tort,
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-- including negligence, or under any other theory of
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-- liability) for any loss or damage of any kind or nature
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-- related to, arising under or in connection with these
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-- materials, including for any direct, or any indirect,
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-- special, incidental, or consequential loss or damage
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-- (including loss of data, profits, goodwill, or any type of
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-- by a third party) even if such damage or loss was
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-- reasonably foreseeable or Xilinx had been advised of the
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-- possibility of the same.
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--
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-- CRITICAL APPLICATIONS
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-- Xilinx products are not designed or intended to be fail-
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-- safe, or for use in any application requiring fail-safe
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-- performance, such as life-support or safety devices or
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-- systems, Class III medical devices, nuclear facilities,
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-- applications related to the deployment of airbags, or any
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-- other applications that could lead to death, personal
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-- injury, or severe property or environmental damage
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-- (individually and collectively, "Critical
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-- Applications"). Customer assumes the sole risk and
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-- liability of any use of Xilinx products in Critical
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-- Applications, subject only to applicable laws and
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-- regulations governing limitations on product liability.
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--
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-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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-- PART OF THIS FILE AT ALL TIMES.
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--
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-------------------------------------------------------------------------------
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-- Project : Virtex-6 Integrated Block for PCI Express
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-- File : pcie_pipe_lane_v6.vhd
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-- Version : 2.3
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---- Description: PIPE per lane module for Virtex6 PCIe Block
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----
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----
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----
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----------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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entity pcie_pipe_lane_v6 is
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generic (
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PIPE_PIPELINE_STAGES : integer := 0 -- 0 - 0 stages, 1 - 1 stage, 2 - 2 stages
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);
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port (
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pipe_rx_char_is_k_o : out std_logic_vector(1 downto 0);
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pipe_rx_data_o : out std_logic_vector(15 downto 0);
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pipe_rx_valid_o : out std_logic;
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pipe_rx_chanisaligned_o : out std_logic;
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pipe_rx_status_o : out std_logic_vector(2 downto 0);
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pipe_rx_phy_status_o : out std_logic;
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pipe_rx_elec_idle_o : out std_logic;
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pipe_rx_polarity_i : in std_logic;
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pipe_tx_compliance_i : in std_logic;
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pipe_tx_char_is_k_i : in std_logic_vector(1 downto 0);
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pipe_tx_data_i : in std_logic_vector(15 downto 0);
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pipe_tx_elec_idle_i : in std_logic;
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pipe_tx_powerdown_i : in std_logic_vector(1 downto 0);
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pipe_rx_char_is_k_i : in std_logic_vector(1 downto 0);
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pipe_rx_data_i : in std_logic_vector(15 downto 0);
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pipe_rx_valid_i : in std_logic;
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pipe_rx_chanisaligned_i : in std_logic;
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pipe_rx_status_i : in std_logic_vector(2 downto 0);
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pipe_rx_phy_status_i : in std_logic;
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pipe_rx_elec_idle_i : in std_logic;
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pipe_rx_polarity_o : out std_logic;
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pipe_tx_compliance_o : out std_logic;
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pipe_tx_char_is_k_o : out std_logic_vector(1 downto 0);
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pipe_tx_data_o : out std_logic_vector(15 downto 0);
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pipe_tx_elec_idle_o : out std_logic;
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pipe_tx_powerdown_o : out std_logic_vector(1 downto 0);
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pipe_clk : in std_logic;
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rst_n : in std_logic
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);
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end pcie_pipe_lane_v6;
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architecture v6_pcie of pcie_pipe_lane_v6 is
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--******************************************************************//
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-- Reality check. //
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--******************************************************************//
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constant TCQ : integer := 1; -- clock to out delay model
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signal pipe_rx_char_is_k_q : std_logic_vector(1 downto 0);
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signal pipe_rx_data_q : std_logic_vector(15 downto 0);
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signal pipe_rx_valid_q : std_logic;
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signal pipe_rx_chanisaligned_q : std_logic;
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signal pipe_rx_status_q : std_logic_vector(2 downto 0);
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signal pipe_rx_phy_status_q : std_logic;
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signal pipe_rx_elec_idle_q : std_logic;
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signal pipe_rx_polarity_q : std_logic;
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signal pipe_tx_compliance_q : std_logic;
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signal pipe_tx_char_is_k_q : std_logic_vector(1 downto 0);
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signal pipe_tx_data_q : std_logic_vector(15 downto 0);
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signal pipe_tx_elec_idle_q : std_logic;
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signal pipe_tx_powerdown_q : std_logic_vector(1 downto 0);
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signal pipe_rx_char_is_k_qq : std_logic_vector(1 downto 0);
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signal pipe_rx_data_qq : std_logic_vector(15 downto 0);
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signal pipe_rx_valid_qq : std_logic;
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signal pipe_rx_chanisaligned_qq : std_logic;
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signal pipe_rx_status_qq : std_logic_vector(2 downto 0);
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signal pipe_rx_phy_status_qq : std_logic;
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signal pipe_rx_elec_idle_qq : std_logic;
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signal pipe_rx_polarity_qq : std_logic;
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signal pipe_tx_compliance_qq : std_logic;
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signal pipe_tx_char_is_k_qq : std_logic_vector(1 downto 0);
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signal pipe_tx_data_qq : std_logic_vector(15 downto 0);
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signal pipe_tx_elec_idle_qq : std_logic;
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signal pipe_tx_powerdown_qq : std_logic_vector(1 downto 0);
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begin
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v6pcie0 : if (PIPE_PIPELINE_STAGES = 0) generate
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pipe_rx_char_is_k_o <= pipe_rx_char_is_k_i;
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pipe_rx_data_o <= pipe_rx_data_i;
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pipe_rx_valid_o <= pipe_rx_valid_i;
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pipe_rx_chanisaligned_o <= pipe_rx_chanisaligned_i;
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pipe_rx_status_o <= pipe_rx_status_i;
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pipe_rx_phy_status_o <= pipe_rx_phy_status_i;
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pipe_rx_elec_idle_o <= pipe_rx_elec_idle_i;
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pipe_rx_polarity_o <= pipe_rx_polarity_i;
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pipe_tx_compliance_o <= pipe_tx_compliance_i;
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pipe_tx_char_is_k_o <= pipe_tx_char_is_k_i;
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pipe_tx_data_o <= pipe_tx_data_i;
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pipe_tx_elec_idle_o <= pipe_tx_elec_idle_i;
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pipe_tx_powerdown_o <= pipe_tx_powerdown_i;
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end generate;
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v6pcie1 : if (PIPE_PIPELINE_STAGES = 1) generate
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process (pipe_clk)
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begin
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if (pipe_clk'event and pipe_clk = '1') then
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if (rst_n = '1') then
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pipe_rx_char_is_k_q <= "00" after (TCQ)*1 ps;
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pipe_rx_data_q <= "0000000000000000" after (TCQ)*1 ps;
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pipe_rx_valid_q <= '0' after (TCQ)*1 ps;
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pipe_rx_chanisaligned_q <= '0' after (TCQ)*1 ps;
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pipe_rx_status_q <= "000" after (TCQ)*1 ps;
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pipe_rx_phy_status_q <= '0' after (TCQ)*1 ps;
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pipe_rx_elec_idle_q <= '0' after (TCQ)*1 ps;
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pipe_rx_polarity_q <= '0' after (TCQ)*1 ps;
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pipe_tx_compliance_q <= '0' after (TCQ)*1 ps;
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pipe_tx_char_is_k_q <= "00" after (TCQ)*1 ps;
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pipe_tx_data_q <= "0000000000000000" after (TCQ)*1 ps;
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pipe_tx_elec_idle_q <= '1' after (TCQ)*1 ps;
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pipe_tx_powerdown_q <= "10" after (TCQ)*1 ps;
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else
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pipe_rx_char_is_k_q <= pipe_rx_char_is_k_i after (TCQ)*1 ps;
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pipe_rx_data_q <= pipe_rx_data_i after (TCQ)*1 ps;
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pipe_rx_valid_q <= pipe_rx_valid_i after (TCQ)*1 ps;
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pipe_rx_chanisaligned_q <= pipe_rx_chanisaligned_i after (TCQ)*1 ps;
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pipe_rx_status_q <= pipe_rx_status_i after (TCQ)*1 ps;
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pipe_rx_phy_status_q <= pipe_rx_phy_status_i after (TCQ)*1 ps;
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pipe_rx_elec_idle_q <= pipe_rx_elec_idle_i after (TCQ)*1 ps;
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pipe_rx_polarity_q <= pipe_rx_polarity_i after (TCQ)*1 ps;
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pipe_tx_compliance_q <= pipe_tx_compliance_i after (TCQ)*1 ps;
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pipe_tx_char_is_k_q <= pipe_tx_char_is_k_i after (TCQ)*1 ps;
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pipe_tx_data_q <= pipe_tx_data_i after (TCQ)*1 ps;
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pipe_tx_elec_idle_q <= pipe_tx_elec_idle_i after (TCQ)*1 ps;
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pipe_tx_powerdown_q <= pipe_tx_powerdown_i after (TCQ)*1 ps;
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end if;
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end if;
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end process;
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pipe_rx_char_is_k_o <= pipe_rx_char_is_k_q;
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pipe_rx_data_o <= pipe_rx_data_q;
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pipe_rx_valid_o <= pipe_rx_valid_q;
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pipe_rx_chanisaligned_o <= pipe_rx_chanisaligned_q;
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pipe_rx_status_o <= pipe_rx_status_q;
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pipe_rx_phy_status_o <= pipe_rx_phy_status_q;
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pipe_rx_elec_idle_o <= pipe_rx_elec_idle_q;
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pipe_rx_polarity_o <= pipe_rx_polarity_q;
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pipe_tx_compliance_o <= pipe_tx_compliance_q;
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pipe_tx_char_is_k_o <= pipe_tx_char_is_k_q;
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pipe_tx_data_o <= pipe_tx_data_q;
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pipe_tx_elec_idle_o <= pipe_tx_elec_idle_q;
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pipe_tx_powerdown_o <= pipe_tx_powerdown_q;
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end generate;
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v6pcie3 : if (PIPE_PIPELINE_STAGES = 2) generate
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process (pipe_clk)
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begin
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if (pipe_clk'event and pipe_clk = '1') then
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if (rst_n = '1') then
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pipe_rx_char_is_k_q <= "00" after (TCQ)*1 ps;
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pipe_rx_data_q <= "0000000000000000" after (TCQ)*1 ps;
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pipe_rx_valid_q <= '0' after (TCQ)*1 ps;
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pipe_rx_chanisaligned_q <= '0' after (TCQ)*1 ps;
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pipe_rx_status_q <= "000" after (TCQ)*1 ps;
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pipe_rx_phy_status_q <= '0' after (TCQ)*1 ps;
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pipe_rx_elec_idle_q <= '0' after (TCQ)*1 ps;
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pipe_rx_polarity_q <= '0' after (TCQ)*1 ps;
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pipe_tx_compliance_q <= '0' after (TCQ)*1 ps;
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pipe_tx_char_is_k_q <= "00" after (TCQ)*1 ps;
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pipe_tx_data_q <= "0000000000000000" after (TCQ)*1 ps;
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pipe_tx_elec_idle_q <= '1' after (TCQ)*1 ps;
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pipe_tx_powerdown_q <= "10" after (TCQ)*1 ps;
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pipe_rx_char_is_k_qq <= "00" after (TCQ)*1 ps;
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pipe_rx_data_qq <= "0000000000000000" after (TCQ)*1 ps;
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pipe_rx_valid_qq <= '0' after (TCQ)*1 ps;
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pipe_rx_chanisaligned_qq <= '0' after (TCQ)*1 ps;
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pipe_rx_status_qq <= "000" after (TCQ)*1 ps;
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pipe_rx_phy_status_qq <= '0' after (TCQ)*1 ps;
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pipe_rx_elec_idle_qq <= '0' after (TCQ)*1 ps;
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pipe_rx_polarity_qq <= '0' after (TCQ)*1 ps;
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pipe_tx_compliance_qq <= '0' after (TCQ)*1 ps;
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pipe_tx_char_is_k_qq <= "00" after (TCQ)*1 ps;
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pipe_tx_data_qq <= "0000000000000000" after (TCQ)*1 ps;
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pipe_tx_elec_idle_qq <= '1' after (TCQ)*1 ps;
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pipe_tx_powerdown_qq <= "10" after (TCQ)*1 ps;
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else
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pipe_rx_char_is_k_q <= pipe_rx_char_is_k_i after (TCQ)*1 ps;
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pipe_rx_data_q <= pipe_rx_data_i after (TCQ)*1 ps;
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pipe_rx_valid_q <= pipe_rx_valid_i after (TCQ)*1 ps;
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pipe_rx_chanisaligned_q <= pipe_rx_chanisaligned_i after (TCQ)*1 ps;
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pipe_rx_status_q <= pipe_rx_status_i after (TCQ)*1 ps;
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pipe_rx_phy_status_q <= pipe_rx_phy_status_i after (TCQ)*1 ps;
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pipe_rx_elec_idle_q <= pipe_rx_elec_idle_i after (TCQ)*1 ps;
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pipe_rx_polarity_q <= pipe_rx_polarity_i after (TCQ)*1 ps;
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pipe_tx_compliance_q <= pipe_tx_compliance_i after (TCQ)*1 ps;
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pipe_tx_char_is_k_q <= pipe_tx_char_is_k_i after (TCQ)*1 ps;
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pipe_tx_data_q <= pipe_tx_data_i after (TCQ)*1 ps;
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pipe_tx_elec_idle_q <= pipe_tx_elec_idle_i after (TCQ)*1 ps;
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pipe_tx_powerdown_q <= pipe_tx_powerdown_i after (TCQ)*1 ps;
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pipe_rx_char_is_k_qq <= pipe_rx_char_is_k_q after (TCQ)*1 ps;
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pipe_rx_data_qq <= pipe_rx_data_q after (TCQ)*1 ps;
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pipe_rx_valid_qq <= pipe_rx_valid_q after (TCQ)*1 ps;
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pipe_rx_chanisaligned_qq <= pipe_rx_chanisaligned_q after (TCQ)*1 ps;
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pipe_rx_status_qq <= pipe_rx_status_q after (TCQ)*1 ps;
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pipe_rx_phy_status_qq <= pipe_rx_phy_status_q after (TCQ)*1 ps;
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pipe_rx_elec_idle_qq <= pipe_rx_elec_idle_q after (TCQ)*1 ps;
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pipe_rx_polarity_qq <= pipe_rx_polarity_q after (TCQ)*1 ps;
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pipe_tx_compliance_qq <= pipe_tx_compliance_q after (TCQ)*1 ps;
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pipe_tx_char_is_k_qq <= pipe_tx_char_is_k_q after (TCQ)*1 ps;
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pipe_tx_data_qq <= pipe_tx_data_q after (TCQ)*1 ps;
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281 |
|
|
pipe_tx_elec_idle_qq <= pipe_tx_elec_idle_q after (TCQ)*1 ps;
|
282 |
|
|
pipe_tx_powerdown_qq <= pipe_tx_powerdown_q after (TCQ)*1 ps;
|
283 |
|
|
end if;
|
284 |
|
|
end if;
|
285 |
|
|
end process;
|
286 |
|
|
|
287 |
|
|
pipe_rx_char_is_k_o <= pipe_rx_char_is_k_qq;
|
288 |
|
|
pipe_rx_data_o <= pipe_rx_data_qq;
|
289 |
|
|
pipe_rx_valid_o <= pipe_rx_valid_qq;
|
290 |
|
|
pipe_rx_chanisaligned_o <= pipe_rx_chanisaligned_qq;
|
291 |
|
|
pipe_rx_status_o <= pipe_rx_status_qq;
|
292 |
|
|
pipe_rx_phy_status_o <= pipe_rx_phy_status_qq;
|
293 |
|
|
pipe_rx_elec_idle_o <= pipe_rx_elec_idle_qq;
|
294 |
|
|
|
295 |
|
|
pipe_rx_polarity_o <= pipe_rx_polarity_qq;
|
296 |
|
|
pipe_tx_compliance_o <= pipe_tx_compliance_qq;
|
297 |
|
|
pipe_tx_char_is_k_o <= pipe_tx_char_is_k_qq;
|
298 |
|
|
pipe_tx_data_o <= pipe_tx_data_qq;
|
299 |
|
|
pipe_tx_elec_idle_o <= pipe_tx_elec_idle_qq;
|
300 |
|
|
pipe_tx_powerdown_o <= pipe_tx_powerdown_qq;
|
301 |
|
|
|
302 |
|
|
end generate;
|
303 |
|
|
|
304 |
|
|
end v6_pcie;
|
305 |
|
|
|
306 |
|
|
|