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-------------------------------------------------------------------------------
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--
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-- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
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--
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-- This file contains confidential and proprietary information
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-- of Xilinx, Inc. and is protected under U.S. and
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-- international copyright and other intellectual property
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-- laws.
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--
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-- DISCLAIMER
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-- This disclaimer is not a license and does not grant any
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-- rights to the materials distributed herewith. Except as
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-- otherwise provided in a valid license issued to you by
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-- Xilinx, and to the maximum extent permitted by applicable
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-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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-- (2) Xilinx shall not be liable (whether in contract or tort,
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-- including negligence, or under any other theory of
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-- liability) for any loss or damage of any kind or nature
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-- related to, arising under or in connection with these
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-- materials, including for any direct, or any indirect,
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-- special, incidental, or consequential loss or damage
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-- (including loss of data, profits, goodwill, or any type of
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-- loss or damage suffered as a result of any action brought
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-- by a third party) even if such damage or loss was
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-- reasonably foreseeable or Xilinx had been advised of the
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-- possibility of the same.
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--
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-- CRITICAL APPLICATIONS
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-- Xilinx products are not designed or intended to be fail-
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-- safe, or for use in any application requiring fail-safe
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-- performance, such as life-support or safety devices or
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-- systems, Class III medical devices, nuclear facilities,
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-- applications related to the deployment of airbags, or any
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-- other applications that could lead to death, personal
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-- injury, or severe property or environmental damage
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-- (individually and collectively, "Critical
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-- Applications"). Customer assumes the sole risk and
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-- liability of any use of Xilinx products in Critical
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-- Applications, subject only to applicable laws and
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-- regulations governing limitations on product liability.
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--
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-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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-- PART OF THIS FILE AT ALL TIMES.
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--
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-------------------------------------------------------------------------------
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-- Project : Virtex-6 Integrated Block for PCI Express
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-- File : pcie_reset_delay_v6.vhd
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-- Version : 2.3
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-- Description: sys_reset_n delay (20ms) for Virtex6 PCIe Block
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--
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--
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--
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--------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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entity pcie_reset_delay_v6 is
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generic (
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PL_FAST_TRAIN : boolean := FALSE;
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REF_CLK_FREQ : integer := 0 -- 0 - 100 MHz, 1 - 125 MHz, 2 - 250 MHz
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);
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port (
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ref_clk : in std_logic;
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sys_reset_n : in std_logic;
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delayed_sys_reset_n : out std_logic
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);
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end pcie_reset_delay_v6;
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architecture v6_pcie of pcie_reset_delay_v6 is
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constant TCQ : integer := 1;
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function t_bit(
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constant PL_FAST_TRAIN : boolean;
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constant REF_CLK_FREQ : integer)
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return integer is
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variable tbit_out : integer := 2;
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begin -- t_bit
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if (PL_FAST_TRAIN) then
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tbit_out := 2;
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else
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if (REF_CLK_FREQ = 0) then
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tbit_out := 20;
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elsif (REF_CLK_FREQ = 1) then
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tbit_out := 20;
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else
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tbit_out := 21;
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end if;
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end if;
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return tbit_out;
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end t_bit;
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constant TBIT : integer := t_bit(PL_FAST_TRAIN, REF_CLK_FREQ);
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signal reg_count_7_0 : std_logic_vector(7 downto 0);
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signal reg_count_15_8 : std_logic_vector(7 downto 0);
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signal reg_count_23_16 : std_logic_vector(7 downto 0);
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signal concat_count : std_logic_vector(23 downto 0);
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-- X-HDL generated signals
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signal v6pcie1 : std_logic_vector(7 downto 0);
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signal v6pcie2 : std_logic_vector(7 downto 0);
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-- Declare intermediate signals for referenced outputs
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signal delayed_sys_reset_n_v6pcie0 : std_logic;
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begin
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-- Drive referenced outputs
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delayed_sys_reset_n <= delayed_sys_reset_n_v6pcie0;
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concat_count <= (reg_count_23_16 & reg_count_15_8 & reg_count_7_0);
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v6pcie1 <= reg_count_15_8 + "00000001" when (reg_count_7_0 = "11111111") else
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reg_count_15_8;
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v6pcie2 <= reg_count_23_16 + "00000001" when ((reg_count_15_8 = "11111111") and (reg_count_7_0 = "11111111")) else
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reg_count_23_16;
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process (ref_clk, sys_reset_n)
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begin
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if ((not(sys_reset_n)) = '1') then
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reg_count_7_0 <= "00000000" after (TCQ)*1 ps;
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reg_count_15_8 <= "00000000" after (TCQ)*1 ps;
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reg_count_23_16 <= "00000000" after (TCQ)*1 ps;
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elsif (ref_clk'event and ref_clk = '1') then
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if (delayed_sys_reset_n_v6pcie0 /= '1') then
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reg_count_7_0 <= reg_count_7_0 + "00000001" after (TCQ)*1 ps;
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reg_count_15_8 <= v6pcie1 after (TCQ)*1 ps;
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reg_count_23_16 <= v6pcie2 after (TCQ)*1 ps;
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end if;
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end if;
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end process;
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delayed_sys_reset_n_v6pcie0 <= concat_count(TBIT);
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end v6_pcie;
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