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-------------------------------------------------------------------------------
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--
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-- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
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--
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-- This file contains confidential and proprietary information
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-- of Xilinx, Inc. and is protected under U.S. and
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-- international copyright and other intellectual property
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-- laws.
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--
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-- DISCLAIMER
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-- This disclaimer is not a license and does not grant any
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-- rights to the materials distributed herewith. Except as
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-- otherwise provided in a valid license issued to you by
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-- Xilinx, and to the maximum extent permitted by applicable
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-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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-- (2) Xilinx shall not be liable (whether in contract or tort,
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-- including negligence, or under any other theory of
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-- liability) for any loss or damage of any kind or nature
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-- related to, arising under or in connection with these
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-- materials, including for any direct, or any indirect,
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-- special, incidental, or consequential loss or damage
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-- (including loss of data, profits, goodwill, or any type of
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-- loss or damage suffered as a result of any action brought
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-- by a third party) even if such damage or loss was
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-- reasonably foreseeable or Xilinx had been advised of the
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-- possibility of the same.
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--
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-- CRITICAL APPLICATIONS
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-- Xilinx products are not designed or intended to be fail-
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-- safe, or for use in any application requiring fail-safe
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-- performance, such as life-support or safety devices or
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-- systems, Class III medical devices, nuclear facilities,
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-- applications related to the deployment of airbags, or any
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-- other applications that could lead to death, personal
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-- injury, or severe property or environmental damage
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-- (individually and collectively, "Critical
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-- Applications"). Customer assumes the sole risk and
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-- liability of any use of Xilinx products in Critical
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-- Applications, subject only to applicable laws and
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-- regulations governing limitations on product liability.
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--
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-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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-- PART OF THIS FILE AT ALL TIMES.
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--
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-------------------------------------------------------------------------------
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-- Project : Virtex-6 Integrated Block for PCI Express
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-- File : pcie_upconfig_fix_3451_v6.vhd
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-- Version : 2.3
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---- Description: Virtex6 Workaround for Root Port Upconfigurability Bug
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----
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----
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----------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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entity pcie_upconfig_fix_3451_v6 is
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generic (
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UPSTREAM_FACING : boolean := TRUE;
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PL_FAST_TRAIN : boolean := FALSE;
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LINK_CAP_MAX_LINK_WIDTH : bit_vector := X"08"
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);
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port (
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pipe_clk : in std_logic;
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pl_phy_lnkup_n : in std_logic;
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pl_ltssm_state : in std_logic_vector(5 downto 0);
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pl_sel_lnk_rate : in std_logic;
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pl_directed_link_change : in std_logic_vector(1 downto 0);
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cfg_link_status_negotiated_width : in std_logic_vector(3 downto 0);
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pipe_rx0_data : in std_logic_vector(15 downto 0);
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pipe_rx0_char_isk : in std_logic_vector(1 downto 0);
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filter_pipe : out std_logic
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);
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end pcie_upconfig_fix_3451_v6;
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architecture v6_pcie of pcie_upconfig_fix_3451_v6 is
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-- purpose: perform bitwise and and check for value
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function slv_check (
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val_in1 : std_logic_vector(7 downto 0);
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val_in2 : std_logic_vector(7 downto 0);
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val_check : std_logic_vector(7 downto 0))
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return std_logic is
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variable val_bw : std_logic_vector(7 downto 0) := X"00";
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begin -- slv_check
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for i in 7 downto 0 loop
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val_bw(i) := val_in1(i) and val_in2(i);
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end loop; -- i
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if val_bw = val_check then
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return '1';
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else
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return '0';
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end if;
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end slv_check;
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FUNCTION to_stdlogic (
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in_val : IN boolean) RETURN std_logic IS
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BEGIN
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IF (in_val) THEN
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RETURN('1');
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ELSE
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RETURN('0');
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END IF;
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END to_stdlogic;
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constant TCQ : integer := 1;
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signal reg_filter_pipe : std_logic;
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signal reg_tsx_counter : std_logic_vector(15 downto 0);
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signal tsx_counter : std_logic_vector(15 downto 0);
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signal cap_link_width : std_logic_vector(5 downto 0);
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signal reg_filter_used : std_logic;
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signal reg_com_then_pad : std_logic;
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signal reg_data0_b4 : std_logic;
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signal reg_data0_08 : std_logic;
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signal reg_data0_43 : std_logic;
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signal reg_data1_b4 : std_logic;
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signal reg_data1_08 : std_logic;
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signal reg_data1_43 : std_logic;
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signal reg_data0_com : std_logic;
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signal reg_data1_com : std_logic;
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signal reg_data1_pad : std_logic;
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signal data0_b4 : std_logic;
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signal data0_08 : std_logic;
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signal data0_43 : std_logic;
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signal data1_b4 : std_logic;
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signal data1_08 : std_logic;
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signal data1_43 : std_logic;
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signal data0_com : std_logic;
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signal data0_pad : std_logic;
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signal data1_com : std_logic;
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signal data1_pad : std_logic;
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signal com_then_pad0 : std_logic;
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signal com_then_pad1 : std_logic;
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signal com_then_pad : std_logic;
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signal filter_used : std_logic;
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signal com_then_pad_reg : std_logic;
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signal filter_used_reg : std_logic;
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-- X-HDL generated signals
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signal v6pcie1 : std_logic_vector(15 downto 0);
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signal v6pcie2 : std_logic_vector(15 downto 0);
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-- Declare intermediate signals for referenced outputs
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signal filter_pipe_v6pcie0 : std_logic;
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begin
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-- Drive referenced outputs
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filter_pipe <= filter_pipe_v6pcie0;
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-- Corrupting all Tsx on all lanes as soon as we do R.RC->R.RI transition to allow time for
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-- the core to see the TS1s on all the lanes being configured at the same time
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-- R.RI has a 2ms timeout.Corrupting tsxs for ~1/4 of that time
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-- 225 (00E1 Hex) pipe_clk cycles-sim_fast_train
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-- 60000 (EA60 Hex) pipe_clk cycles-without sim_fast_train
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-- Not taking any action when PLDIRECTEDLINKCHANGE is set
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-- Detect xx, COM then PAD,xx or COM,PAD then PAD,xx
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-- data0 will be the first symbol on lane 0, data1 will be the next symbol.
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-- Don't look for PAD on data1 since it's unnecessary.
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-- COM=0xbc and PAD=0xf7 (and isk).
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-- detect if (data & 0xb4) == 0xb4 and isk, and then
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-- if (data & 0x4b) == 0x08 or 0x43. This distinguishes COM and PAD, using
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-- no more than a 6-input LUT, so should be "free".
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data0_b4 <= pipe_rx0_char_isk(0) and slv_check(pipe_rx0_data(7 downto 0), X"b4", X"b4");
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data0_08 <= slv_check(pipe_rx0_data(7 downto 0), X"4b", X"08");
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data0_43 <= slv_check(pipe_rx0_data(7 downto 0), X"4b", X"43");
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data1_b4 <= pipe_rx0_char_isk(1) and slv_check(pipe_rx0_data(15 downto 8), X"b4", X"b4");
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data1_08 <= slv_check(pipe_rx0_data(15 downto 8), X"4b", X"08");
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data1_43 <= slv_check(pipe_rx0_data(15 downto 8), X"4b", X"43");
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data0_com <= reg_data0_b4 and reg_data0_08;
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data1_com <= reg_data1_b4 and reg_data1_08;
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data0_pad <= reg_data0_b4 and reg_data0_43;
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data1_pad <= reg_data1_b4 and reg_data1_43;
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com_then_pad0 <= reg_data0_com and reg_data1_pad and data0_pad;
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com_then_pad1 <= reg_data1_com and data0_pad and data1_pad;
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com_then_pad <= (com_then_pad0 or com_then_pad1) and not(reg_filter_used);
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filter_used <= to_stdlogic(pl_ltssm_state = "100000") and (reg_filter_pipe or reg_filter_used);
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com_then_pad_reg <= com_then_pad when ((not(pl_phy_lnkup_n)) = '1') else
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'0';
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filter_used_reg <= filter_used when ((not(pl_phy_lnkup_n)) = '1') else
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'0';
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process (pipe_clk)
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begin
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if (pipe_clk'event and pipe_clk = '1') then
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reg_data0_b4 <= data0_b4 after (TCQ)*1 ps;
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reg_data0_08 <= data0_08 after (TCQ)*1 ps;
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reg_data0_43 <= data0_43 after (TCQ)*1 ps;
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reg_data1_b4 <= data1_b4 after (TCQ)*1 ps;
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reg_data1_08 <= data1_08 after (TCQ)*1 ps;
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reg_data1_43 <= data1_43 after (TCQ)*1 ps;
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reg_data0_com <= data0_com after (TCQ)*1 ps;
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reg_data1_com <= data1_com after (TCQ)*1 ps;
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reg_data1_pad <= data1_pad after (TCQ)*1 ps;
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reg_com_then_pad <= com_then_pad_reg after (TCQ)*1 ps;
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reg_filter_used <= filter_used_reg after (TCQ)*1 ps;
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end if;
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end process;
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v6pcie1 <= X"0320" when (pl_sel_lnk_rate = '1') else
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X"0190";
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v6pcie2 <= X"00E1" when (PL_FAST_TRAIN) else
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v6pcie1;
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process (pipe_clk)
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begin
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if (pipe_clk'event and pipe_clk = '1') then
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if (pl_phy_lnkup_n = '1') then
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reg_tsx_counter <= "0000000000000000" after (TCQ)*1 ps;
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reg_filter_pipe <= '0' after (TCQ)*1 ps;
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elsif ((pl_ltssm_state = "100000") and (reg_com_then_pad = '1') and (("00" & cfg_link_status_negotiated_width) /= cap_link_width(5 downto 0)) and (pl_directed_link_change(1 downto 0) = "00")) then
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reg_tsx_counter <= "0000000000000000" after (TCQ)*1 ps;
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reg_filter_pipe <= '1' after (TCQ)*1 ps;
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elsif (filter_pipe_v6pcie0 = '1') then
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if (tsx_counter < v6pcie2) then
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reg_tsx_counter <= tsx_counter + "0000000000000001" after (TCQ)*1 ps;
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reg_filter_pipe <= '1' after (TCQ)*1 ps;
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else
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reg_tsx_counter <= "0000000000000000" after (TCQ)*1 ps;
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reg_filter_pipe <= '0' after (TCQ)*1 ps;
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end if;
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end if;
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end if;
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end process;
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filter_pipe_v6pcie0 <= '0' when (UPSTREAM_FACING) else
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reg_filter_pipe;
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tsx_counter <= reg_tsx_counter;
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cap_link_width <= to_stdlogicvector(LINK_CAP_MAX_LINK_WIDTH);
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end v6_pcie;
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