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-------------------------------------------------------------------------------
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--
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-- Title : pcie_core64_m10
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-- Author : Dmitry Smekhov
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-- Company : Instrumental Systems
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-- E-mail : dsmv@insys.ru
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--
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-- Version : 1.0
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--
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-------------------------------------------------------------------------------
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--
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-- Description : Контроллер шины PCI Express
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-- Модификация 10 - Artix 7 PCI Express 2.0 x4
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--
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-------------------------------------------------------------------------------
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--
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-- Version 1.0 15.08.2011
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-- Создан из pcie_core64_m4 v1.2
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--
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.core64_type_pkg.all;
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package pcie_core64_m10_pkg is
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--! контроллер PCI-Express
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component pcie_core64_m10 is
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generic (
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DEVICE_ID : in std_logic_vector := x"5507"; --! значение регистра DeviceID
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refclk : in integer:=100; --! Значение опорной тактовой частоты [МГц]
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is_simulation : in integer:=0; --! 0 - синтез, 1 - моделирование
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interrupt_number : in std_logic_vector( 1 downto 0 ):="00" -- номер INTx: 0 - INTA, 1 - INTB, 2 - INTC, 3 - INTD
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);
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port (
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---- PCI-Express ----
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txp : out std_logic_vector( 3 downto 0 );
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txn : out std_logic_vector( 3 downto 0 );
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rxp : in std_logic_vector( 3 downto 0 );
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rxn : in std_logic_vector( 3 downto 0 );
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mgt250 : in std_logic; --! тактовая частота 250 MHz или 100 МГц от PCI_Express
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perst : in std_logic; --! 0 - сброс
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px : out std_logic_vector( 7 downto 0 ); --! контрольные точки
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pcie_lstatus : out std_logic_vector( 15 downto 0 ); -- регистр LSTATUS
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pcie_link_up : out std_logic; -- 0 - завершена инициализация PCI-Express
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---- Локальная шина ----
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clk_out : out std_logic; --! тактовая частота 250 MHz
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reset_out : out std_logic; --! 0 - сброс
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dcm_rstp : out std_logic; --! 1 - сброс DCM 266 МГц
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---- BAR0 - блоки управления ----
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bp_host_data : out std_logic_vector( 31 downto 0 ); --! шина данных - выход
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bp_data : in std_logic_vector( 31 downto 0 ); --! шина данных - вход
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bp_adr : out std_logic_vector( 19 downto 0 ); --! адрес регистра
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bp_we : out std_logic_vector( 3 downto 0 ); --! 1 - запись в регистры
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bp_rd : out std_logic_vector( 3 downto 0 ); --! 1 - чтение из регистров блока
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bp_sel : out std_logic_vector( 1 downto 0 ); --! номер блока для чтения
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bp_reg_we : out std_logic; --! 1 - запись в регистр по адресам 0x100000 - 0x1FFFFF
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bp_reg_rd : out std_logic; --! 1 - чтение из регистра по адресам 0x100000 - 0x1FFFFF
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bp_irq : in std_logic; --! 1 - запрос прерывания
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---- BAR1 ----
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aclk : in std_logic; --! тактовая частота локальной шины - 266 МГц
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aclk_lock : in std_logic; --! 1 - захват частоты
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pb_master : out type_pb_master; --! запрос
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pb_slave : in type_pb_slave --! ответ
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);
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end component;
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end package;
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library ieee;
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use ieee.std_logic_1164.all;
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use work.core64_type_pkg.all;
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use work.core64_rx_engine_m2_pkg.all;
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use work.core64_tx_engine_m2_pkg.all;
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use work.core64_reg_access_pkg.all;
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use work.core64_pb_disp_pkg.all;
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use work.block_pe_fifo_ext_pkg.all;
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use work.core64_interrupt_pkg.all;
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--! контроллер PCI-Express
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entity pcie_core64_m10 is
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generic (
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DEVICE_ID : in std_logic_vector := x"5507"; --! значение регистра DeviceID
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refclk : in integer:=100; --! Значение опорной тактовой частоты [МГц]
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is_simulation : in integer:=0; --! 0 - синтез, 1 - моделирование
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interrupt_number : in std_logic_vector( 1 downto 0 ):="00" -- номер INTx: 0 - INTA, 1 - INTB, 2 - INTC, 3 - INTD
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);
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port (
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---- PCI-Express ----
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txp : out std_logic_vector( 3 downto 0 );
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txn : out std_logic_vector( 3 downto 0 );
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rxp : in std_logic_vector( 3 downto 0 );
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rxn : in std_logic_vector( 3 downto 0 );
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mgt250 : in std_logic; --! тактовая частота 250 MHz или 100 МГц от PCI_Express
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perst : in std_logic; --! 0 - сброс
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px : out std_logic_vector( 7 downto 0 ); --! контрольные точки
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pcie_lstatus : out std_logic_vector( 15 downto 0 ); --! регистр LSTATUS
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pcie_link_up : out std_logic; --! 0 - завершена инициализация PCI-Express
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---- Локальная шина ----
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clk_out : out std_logic; --! тактовая частота 250 MHz
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reset_out : out std_logic; --! 0 - сброс
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dcm_rstp : out std_logic; --! 1 - сброс DCM 266 МГц
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---- BAR0 - блоки управления ----
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bp_host_data : out std_logic_vector( 31 downto 0 ); --! шина данных - выход
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bp_data : in std_logic_vector( 31 downto 0 ); --! шина данных - вход
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bp_adr : out std_logic_vector( 19 downto 0 ); --! адрес регистра
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bp_we : out std_logic_vector( 3 downto 0 ); --! 1 - запись в регистры
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bp_rd : out std_logic_vector( 3 downto 0 ); --! 1 - чтение из регистров блока
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bp_sel : out std_logic_vector( 1 downto 0 ); --! номер блока для чтения
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bp_reg_we : out std_logic; --! 1 - запись в регистр по адресам 0x100000 - 0x1FFFFF
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bp_reg_rd : out std_logic; --! 1 - чтение из регистра по адресам 0x100000 - 0x1FFFFF
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bp_irq : in std_logic; --! 1 - запрос прерывания
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---- BAR1 ----
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aclk : in std_logic; --! тактовая частота локальной шины - 266 МГц
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aclk_lock : in std_logic; --! 1 - захват частоты
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pb_master : out type_pb_master; --! запрос
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pb_slave : in type_pb_slave --! ответ
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);
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end pcie_core64_m10;
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architecture pcie_core64_m10 of pcie_core64_m10 is
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function set_refclk( refclk : in integer ) return integer is
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variable ret : integer;
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begin
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case( refclk ) is
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when 100 => ret:=0; -- 100 MHz --
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when 250 => ret:=2; -- 250 MHz --
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when others => ret:=1; -- 125 MHz --
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end case;
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return ret;
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end set_refclk;
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constant REF_CLK_FREQ : integer:=set_refclk( refclk );
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function set_interrupt_pin( num : in std_logic_vector( 1 downto 0 ) ) return bit_vector is
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variable ret : bit_vector( 3 downto 0 );
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begin
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case( num ) is
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when "00" => ret:=x"1"; -- INTA --
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when "01" => ret:=x"2"; -- INTB --
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when "10" => ret:=x"3"; -- INTC --
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when "11" => ret:=x"4"; -- INTD --
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when others => ret:=x"0";
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end case;
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return ret;
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end set_interrupt_pin;
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constant INTERRUPT_PIN : bit_vector( 3 downto 0 ):=set_interrupt_pin( interrupt_number );
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constant C_DATA_WIDTH : integer:=64;
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component cl_a7pcie_x4 generic (
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--CFG_VEND_ID : std_logic_vector := X"4953";
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CFG_DEV_ID : std_logic_vector := X"5507";
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PL_FAST_TRAIN : string := "FALSE";
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REF_CLK_FREQ : integer := 0; -- 0 - 100 MHz; 1 - 125 MHz; 2 - 250 MHz
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PCIE_EXT_CLK : string := "FALSE";
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UPSTREAM_FACING : string := "TRUE"
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);
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port (
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-------------------------------------------------------------------------------------------------------------------
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-- 1. PCI Express (pci_exp) Interface --
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-------------------------------------------------------------------------------------------------------------------
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pci_exp_txp : out std_logic_vector(3 downto 0);
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pci_exp_txn : out std_logic_vector(3 downto 0);
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pci_exp_rxp : in std_logic_vector(3 downto 0);
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pci_exp_rxn : in std_logic_vector(3 downto 0);
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-------------------------------------------------------------------------------------------------------------------
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-- 2. Clocking Interface --
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-------------------------------------------------------------------------------------------------------------------
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PIPE_PCLK_IN : in std_logic:='0';
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PIPE_RXUSRCLK_IN : in std_logic:='0';
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PIPE_RXOUTCLK_IN : in std_logic_vector(3 downto 0):=(others=>'0');
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PIPE_DCLK_IN : in std_logic:='0';
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PIPE_USERCLK1_IN : in std_logic:='0';
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PIPE_USERCLK2_IN : in std_logic:='0';
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PIPE_OOBCLK_IN : in std_logic:='0';
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PIPE_MMCM_LOCK_IN : in std_logic:='0';
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PIPE_TXOUTCLK_OUT : out std_logic;
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PIPE_RXOUTCLK_OUT : out std_logic_vector(3 downto 0);
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PIPE_PCLK_SEL_OUT : out std_logic_vector(3 downto 0);
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PIPE_GEN3_OUT : out std_logic;
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-------------------------------------------------------------------------------------------------------------------
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-- 3. AXI-S Interface --
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-------------------------------------------------------------------------------------------------------------------
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-- Common
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user_clk_out : out std_logic;
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user_reset_out : out std_logic;
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user_lnk_up : out std_logic;
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-- TX
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tx_buf_av : out std_logic_vector(5 downto 0);
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tx_cfg_req : out std_logic;
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tx_err_drop : out std_logic;
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s_axis_tx_tready : out std_logic;
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s_axis_tx_tdata : in std_logic_vector((C_DATA_WIDTH - 1) downto 0);
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s_axis_tx_tkeep : in std_logic_vector((C_DATA_WIDTH / 8 - 1) downto 0);
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s_axis_tx_tlast : in std_logic;
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s_axis_tx_tvalid : in std_logic;
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s_axis_tx_tuser : in std_logic_vector(3 downto 0);
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tx_cfg_gnt : in std_logic;
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-- RX
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m_axis_rx_tdata : out std_logic_vector((C_DATA_WIDTH - 1) downto 0);
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m_axis_rx_tkeep : out std_logic_vector((C_DATA_WIDTH / 8 - 1) downto 0);
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m_axis_rx_tlast : out std_logic;
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m_axis_rx_tvalid : out std_logic;
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m_axis_rx_tready : in std_logic;
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m_axis_rx_tuser : out std_logic_vector(21 downto 0);
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rx_np_ok : in std_logic:='0'; -- ???
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rx_np_req : in std_logic:='0'; -- ???
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-- Flow Control
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fc_cpld : out std_logic_vector(11 downto 0);
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fc_cplh : out std_logic_vector(7 downto 0);
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fc_npd : out std_logic_vector(11 downto 0);
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fc_nph : out std_logic_vector(7 downto 0);
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fc_pd : out std_logic_vector(11 downto 0);
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fc_ph : out std_logic_vector(7 downto 0);
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fc_sel : in std_logic_vector(2 downto 0);
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-------------------------------------------------------------------------------------------------------------------
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-- 4. Configuration (CFG) Interface --
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-------------------------------------------------------------------------------------------------------------------
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---------------------------------------------------------------------
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-- EP and RP --
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---------------------------------------------------------------------
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cfg_mgmt_do : out std_logic_vector (31 downto 0);
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cfg_mgmt_rd_wr_done : out std_logic;
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cfg_status : out std_logic_vector(15 downto 0);
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cfg_command : out std_logic_vector(15 downto 0);
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cfg_dstatus : out std_logic_vector(15 downto 0);
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cfg_dcommand : out std_logic_vector(15 downto 0);
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cfg_lstatus : out std_logic_vector(15 downto 0);
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cfg_lcommand : out std_logic_vector(15 downto 0);
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cfg_dcommand2 : out std_logic_vector(15 downto 0);
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cfg_pcie_link_state : out std_logic_vector(2 downto 0);
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cfg_pmcsr_pme_en : out std_logic;
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cfg_pmcsr_powerstate : out std_logic_vector(1 downto 0);
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cfg_pmcsr_pme_status : out std_logic;
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cfg_received_func_lvl_rst : out std_logic;
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-- Management Interface
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cfg_mgmt_di : in std_logic_vector (31 downto 0):=(others=>'0');
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cfg_mgmt_byte_en : in std_logic_vector (3 downto 0):=(others=>'0');
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cfg_mgmt_dwaddr : in std_logic_vector (9 downto 0):=(others=>'0');
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cfg_mgmt_wr_en : in std_logic:='0';
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cfg_mgmt_rd_en : in std_logic:='0';
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cfg_mgmt_wr_readonly : in std_logic:='0';
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-- Error Reporting Interface
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cfg_err_ecrc : in std_logic:='0';
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cfg_err_ur : in std_logic:='0';
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cfg_err_cpl_timeout : in std_logic:='0';
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cfg_err_cpl_unexpect : in std_logic:='0';
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cfg_err_cpl_abort : in std_logic:='0';
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cfg_err_posted : in std_logic:='0';
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cfg_err_cor : in std_logic:='0';
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cfg_err_atomic_egress_blocked : in std_logic:='0';
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cfg_err_internal_cor : in std_logic:='0';
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|
|
cfg_err_malformed : in std_logic:='0';
|
314 |
|
|
cfg_err_mc_blocked : in std_logic:='0';
|
315 |
|
|
cfg_err_poisoned : in std_logic:='0';
|
316 |
|
|
cfg_err_norecovery : in std_logic:='0';
|
317 |
|
|
cfg_err_tlp_cpl_header : in std_logic_vector(47 downto 0):=(others=>'0');
|
318 |
|
|
cfg_err_cpl_rdy : out std_logic;
|
319 |
|
|
cfg_err_locked : in std_logic:='0';
|
320 |
|
|
cfg_err_acs : in std_logic:='0';
|
321 |
|
|
cfg_err_internal_uncor : in std_logic:='0';
|
322 |
|
|
cfg_trn_pending : in std_logic:='0';
|
323 |
|
|
cfg_pm_halt_aspm_l0s : in std_logic:='0';
|
324 |
|
|
cfg_pm_halt_aspm_l1 : in std_logic:='0';
|
325 |
|
|
cfg_pm_force_state_en : in std_logic:='0';
|
326 |
|
|
cfg_pm_force_state : in std_logic_vector(1 downto 0):=(others=>'0');
|
327 |
|
|
cfg_dsn : in std_logic_vector(63 downto 0):=(others=>'0');
|
328 |
|
|
|
329 |
|
|
---------------------------------------------------------------------
|
330 |
|
|
-- EP Only --
|
331 |
|
|
---------------------------------------------------------------------
|
332 |
|
|
cfg_interrupt : in std_logic;
|
333 |
|
|
cfg_interrupt_rdy : out std_logic;
|
334 |
|
|
cfg_interrupt_assert : in std_logic;
|
335 |
|
|
cfg_interrupt_di : in std_logic_vector(7 downto 0);
|
336 |
|
|
cfg_interrupt_do : out std_logic_vector(7 downto 0);
|
337 |
|
|
cfg_interrupt_mmenable : out std_logic_vector(2 downto 0);
|
338 |
|
|
cfg_interrupt_msienable : out std_logic;
|
339 |
|
|
cfg_interrupt_msixenable : out std_logic;
|
340 |
|
|
cfg_interrupt_msixfm : out std_logic;
|
341 |
|
|
cfg_interrupt_stat : in std_logic:='0';
|
342 |
|
|
cfg_pciecap_interrupt_msgnum : in std_logic_vector(4 downto 0):=(others=>'0');
|
343 |
|
|
cfg_to_turnoff : out std_logic;
|
344 |
|
|
cfg_turnoff_ok : in std_logic:='0';
|
345 |
|
|
cfg_bus_number : out std_logic_vector(7 downto 0);
|
346 |
|
|
cfg_device_number : out std_logic_vector(4 downto 0);
|
347 |
|
|
cfg_function_number : out std_logic_vector(2 downto 0);
|
348 |
|
|
cfg_pm_wake : in std_logic:='0';
|
349 |
|
|
|
350 |
|
|
---------------------------------------------------------------------
|
351 |
|
|
-- RP Only --
|
352 |
|
|
---------------------------------------------------------------------
|
353 |
|
|
cfg_pm_send_pme_to : in std_logic:='0';
|
354 |
|
|
cfg_ds_bus_number : in std_logic_vector(7 downto 0):=(others=>'0');
|
355 |
|
|
cfg_ds_device_number : in std_logic_vector(4 downto 0):=(others=>'0');
|
356 |
|
|
cfg_ds_function_number : in std_logic_vector(2 downto 0):=(others=>'0');
|
357 |
|
|
|
358 |
|
|
cfg_mgmt_wr_rw1c_as_rw : in std_logic:='0';
|
359 |
|
|
cfg_msg_received : out std_logic;
|
360 |
|
|
cfg_msg_data : out std_logic_vector(15 downto 0);
|
361 |
|
|
|
362 |
|
|
cfg_bridge_serr_en : out std_logic;
|
363 |
|
|
cfg_slot_control_electromech_il_ctl_pulse : out std_logic;
|
364 |
|
|
cfg_root_control_syserr_corr_err_en : out std_logic;
|
365 |
|
|
cfg_root_control_syserr_non_fatal_err_en : out std_logic;
|
366 |
|
|
cfg_root_control_syserr_fatal_err_en : out std_logic;
|
367 |
|
|
cfg_root_control_pme_int_en : out std_logic;
|
368 |
|
|
cfg_aer_rooterr_corr_err_reporting_en : out std_logic;
|
369 |
|
|
cfg_aer_rooterr_non_fatal_err_reporting_en : out std_logic;
|
370 |
|
|
cfg_aer_rooterr_fatal_err_reporting_en : out std_logic;
|
371 |
|
|
cfg_aer_rooterr_corr_err_received : out std_logic;
|
372 |
|
|
cfg_aer_rooterr_non_fatal_err_received : out std_logic;
|
373 |
|
|
cfg_aer_rooterr_fatal_err_received : out std_logic;
|
374 |
|
|
|
375 |
|
|
cfg_msg_received_err_cor : out std_logic;
|
376 |
|
|
cfg_msg_received_err_non_fatal : out std_logic;
|
377 |
|
|
cfg_msg_received_err_fatal : out std_logic;
|
378 |
|
|
cfg_msg_received_pm_as_nak : out std_logic;
|
379 |
|
|
cfg_msg_received_pm_pme : out std_logic;
|
380 |
|
|
cfg_msg_received_pme_to_ack : out std_logic;
|
381 |
|
|
cfg_msg_received_assert_int_a : out std_logic;
|
382 |
|
|
cfg_msg_received_assert_int_b : out std_logic;
|
383 |
|
|
cfg_msg_received_assert_int_c : out std_logic;
|
384 |
|
|
cfg_msg_received_assert_int_d : out std_logic;
|
385 |
|
|
cfg_msg_received_deassert_int_a : out std_logic;
|
386 |
|
|
cfg_msg_received_deassert_int_b : out std_logic;
|
387 |
|
|
cfg_msg_received_deassert_int_c : out std_logic;
|
388 |
|
|
cfg_msg_received_deassert_int_d : out std_logic;
|
389 |
|
|
cfg_msg_received_setslotpowerlimit : out std_logic;
|
390 |
|
|
|
391 |
|
|
-------------------------------------------------------------------------------------------------------------------
|
392 |
|
|
-- 5. Physical Layer Control and Status (PL) Interface --
|
393 |
|
|
-------------------------------------------------------------------------------------------------------------------
|
394 |
|
|
pl_directed_link_change : in std_logic_vector(1 downto 0):="00";
|
395 |
|
|
pl_directed_link_width : in std_logic_vector(1 downto 0):="00";
|
396 |
|
|
pl_directed_link_speed : in std_logic:='0';
|
397 |
|
|
pl_directed_link_auton : in std_logic:='0';
|
398 |
|
|
pl_upstream_prefer_deemph : in std_logic:='0';
|
399 |
|
|
|
400 |
|
|
pl_sel_lnk_rate : out std_logic;
|
401 |
|
|
pl_sel_lnk_width : out std_logic_vector(1 downto 0);
|
402 |
|
|
pl_ltssm_state : out std_logic_vector(5 downto 0);
|
403 |
|
|
pl_lane_reversal_mode : out std_logic_vector(1 downto 0);
|
404 |
|
|
|
405 |
|
|
pl_phy_lnk_up : out std_logic;
|
406 |
|
|
pl_tx_pm_state : out std_logic_vector(2 downto 0);
|
407 |
|
|
pl_rx_pm_state : out std_logic_vector(1 downto 0);
|
408 |
|
|
|
409 |
|
|
pl_link_upcfg_cap : out std_logic;
|
410 |
|
|
pl_link_gen2_cap : out std_logic;
|
411 |
|
|
pl_link_partner_gen2_supported : out std_logic;
|
412 |
|
|
pl_initial_link_width : out std_logic_vector(2 downto 0);
|
413 |
|
|
|
414 |
|
|
pl_directed_change_done : out std_logic;
|
415 |
|
|
|
416 |
|
|
---------------------------------------------------------------------
|
417 |
|
|
-- EP Only --
|
418 |
|
|
---------------------------------------------------------------------
|
419 |
|
|
pl_received_hot_rst : out std_logic;
|
420 |
|
|
---------------------------------------------------------------------
|
421 |
|
|
-- RP Only --
|
422 |
|
|
---------------------------------------------------------------------
|
423 |
|
|
pl_transmit_hot_rst : in std_logic:='0';
|
424 |
|
|
pl_downstream_deemph_source : in std_logic:='0';
|
425 |
|
|
-------------------------------------------------------------------------------------------------------------------
|
426 |
|
|
-- 6. AER interface --
|
427 |
|
|
-------------------------------------------------------------------------------------------------------------------
|
428 |
|
|
cfg_err_aer_headerlog : in std_logic_vector(127 downto 0):=(others=>'0');
|
429 |
|
|
cfg_aer_interrupt_msgnum : in std_logic_vector(4 downto 0):=(others=>'0');
|
430 |
|
|
cfg_err_aer_headerlog_set : out std_logic;
|
431 |
|
|
cfg_aer_ecrc_check_en : out std_logic;
|
432 |
|
|
cfg_aer_ecrc_gen_en : out std_logic;
|
433 |
|
|
-------------------------------------------------------------------------------------------------------------------
|
434 |
|
|
-- 7. VC interface --
|
435 |
|
|
-------------------------------------------------------------------------------------------------------------------
|
436 |
|
|
cfg_vc_tcvc_map : out std_logic_vector(6 downto 0);
|
437 |
|
|
|
438 |
|
|
-------------------------------------------------------------------------------------------------------------------
|
439 |
|
|
-- 8. System(SYS) Interface --
|
440 |
|
|
-------------------------------------------------------------------------------------------------------------------
|
441 |
|
|
PIPE_MMCM_RST_N : in std_logic; -- // Async | Async
|
442 |
|
|
sys_clk : in std_logic;
|
443 |
|
|
sys_rst_n : in std_logic);
|
444 |
|
|
end component;
|
445 |
|
|
|
446 |
|
|
--signal sys_clk_c : std_logic;
|
447 |
|
|
|
448 |
|
|
--signal sys_reset_n_c : std_logic;
|
449 |
|
|
signal trn_clk_c : std_logic;
|
450 |
|
|
signal user_reset : std_logic;
|
451 |
|
|
signal user_lnk_up : std_logic;
|
452 |
|
|
signal cfg_trn_pending_n_c : std_logic;
|
453 |
|
|
signal trn_tsof_n_c : std_logic;
|
454 |
|
|
signal trn_teof_n_c : std_logic;
|
455 |
|
|
signal trn_tsrc_rdy_n_c : std_logic;
|
456 |
|
|
signal trn_tdst_rdy_n_c : std_logic;
|
457 |
|
|
signal trn_tsrc_dsc_n_c : std_logic;
|
458 |
|
|
signal trn_terrfwd_n_c : std_logic;
|
459 |
|
|
signal trn_tdst_dsc_n_c : std_logic;
|
460 |
|
|
signal trn_td_c : std_logic_vector((64 - 1) downto 0);
|
461 |
|
|
signal trn_trem_n_c : std_logic_vector(7 downto 0);
|
462 |
|
|
signal trn_tbuf_av_c : std_logic_vector(( 4 -1 ) downto 0);
|
463 |
|
|
signal trn_rsof_n_c : std_logic;
|
464 |
|
|
signal trn_reof_n_c : std_logic;
|
465 |
|
|
signal trn_rsrc_rdy_n_c : std_logic;
|
466 |
|
|
signal trn_rsrc_dsc_n_c : std_logic;
|
467 |
|
|
signal trn_rdst_rdy_n_c : std_logic;
|
468 |
|
|
signal trn_rerrfwd_n_c : std_logic;
|
469 |
|
|
signal trn_rnp_ok_n_c : std_logic;
|
470 |
|
|
|
471 |
|
|
signal trn_rd_c : std_logic_vector((64 - 1) downto 0);
|
472 |
|
|
signal trn_rrem_n_c : std_logic_vector(7 downto 0);
|
473 |
|
|
signal trn_rbar_hit_n_c : std_logic_vector(6 downto 0);
|
474 |
|
|
signal trn_rfc_nph_av_c : std_logic_vector(7 downto 0);
|
475 |
|
|
signal trn_rfc_npd_av_c : std_logic_vector(11 downto 0);
|
476 |
|
|
signal trn_rfc_ph_av_c : std_logic_vector(7 downto 0);
|
477 |
|
|
signal trn_rfc_pd_av_c : std_logic_vector(11 downto 0);
|
478 |
|
|
signal trn_rcpl_streaming_n_c : std_logic;
|
479 |
|
|
|
480 |
|
|
signal cfg_do : std_logic_vector(31 downto 0);
|
481 |
|
|
signal cfg_di : std_logic_vector(31 downto 0);
|
482 |
|
|
signal cfg_dwaddr : std_logic_vector(9 downto 0) ;
|
483 |
|
|
signal cfg_byte_en : std_logic_vector(3 downto 0);
|
484 |
|
|
signal cfg_err_tlp_cpl_header : std_logic_vector(47 downto 0);
|
485 |
|
|
signal cfg_wr_en : std_logic;
|
486 |
|
|
signal cfg_rd_en : std_logic;
|
487 |
|
|
signal cfg_rd_wr_done : std_logic;
|
488 |
|
|
signal cfg_err_cor : std_logic;
|
489 |
|
|
signal cfg_err_ur : std_logic;
|
490 |
|
|
signal cfg_err_ecrc : std_logic;
|
491 |
|
|
signal cfg_err_cpl_timeout : std_logic;
|
492 |
|
|
signal cfg_err_cpl_abort : std_logic;
|
493 |
|
|
signal cfg_err_cpl_unexpect : std_logic;
|
494 |
|
|
signal cfg_err_posted : std_logic;
|
495 |
|
|
signal cfg_err_locked : std_logic;
|
496 |
|
|
signal cfg_trn_pending : std_logic;
|
497 |
|
|
signal cfg_dcommand2 : std_logic_vector(15 downto 0);
|
498 |
|
|
signal cfg_dsn : std_logic_vector(63 downto 0);
|
499 |
|
|
|
500 |
|
|
|
501 |
|
|
signal pl_initial_link_width : std_logic_vector(2 downto 0);
|
502 |
|
|
signal pl_lane_reversal_mode : std_logic_vector(1 downto 0);
|
503 |
|
|
signal pl_link_gen2_capable : std_logic;
|
504 |
|
|
signal pl_link_partner_gen2_supported : std_logic;
|
505 |
|
|
signal pl_link_upcfg_capable : std_logic;
|
506 |
|
|
signal pl_ltssm_state : std_logic_vector(5 downto 0);
|
507 |
|
|
signal pl_received_hot_rst : std_logic;
|
508 |
|
|
signal pl_sel_link_rate : std_logic;
|
509 |
|
|
signal pl_sel_link_width : std_logic_vector(1 downto 0);
|
510 |
|
|
signal pl_directed_link_auton : std_logic;
|
511 |
|
|
signal pl_directed_link_change : std_logic_vector(1 downto 0);
|
512 |
|
|
signal pl_directed_link_speed : std_logic;
|
513 |
|
|
signal pl_directed_link_width : std_logic_vector(1 downto 0);
|
514 |
|
|
signal pl_upstream_prefer_deemph : std_logic;
|
515 |
|
|
|
516 |
|
|
|
517 |
|
|
|
518 |
|
|
signal cfg_err_cpl_rdy : std_logic;
|
519 |
|
|
signal cfg_interrupt : std_logic;
|
520 |
|
|
signal cfg_interrupt_rdy : std_logic;
|
521 |
|
|
|
522 |
|
|
signal cfg_interrupt_assert : std_logic;
|
523 |
|
|
|
524 |
|
|
signal cfg_interrupt_n : std_logic;
|
525 |
|
|
signal cfg_interrupt_rdy_n : std_logic;
|
526 |
|
|
signal cfg_interrupt_assert_n : std_logic;
|
527 |
|
|
|
528 |
|
|
|
529 |
|
|
signal cfg_interrupt_di : std_logic_vector(7 downto 0);
|
530 |
|
|
signal cfg_interrupt_do : std_logic_vector(7 downto 0);
|
531 |
|
|
signal cfg_interrupt_mmenable : std_logic_vector(2 downto 0);
|
532 |
|
|
signal cfg_interrupt_msienable: std_logic;
|
533 |
|
|
|
534 |
|
|
signal cfg_turnoff_ok : std_logic;
|
535 |
|
|
signal cfg_to_turnoff : std_logic;
|
536 |
|
|
signal cfg_pm_wake : std_logic;
|
537 |
|
|
signal cfg_pcie_link_state : std_logic_vector(2 downto 0);
|
538 |
|
|
signal cfg_bus_number : std_logic_vector(7 downto 0);
|
539 |
|
|
signal cfg_device_number : std_logic_vector(4 downto 0);
|
540 |
|
|
signal cfg_function_number : std_logic_vector(2 downto 0);
|
541 |
|
|
signal cfg_status : std_logic_vector(15 downto 0);
|
542 |
|
|
signal cfg_command : std_logic_vector(15 downto 0);
|
543 |
|
|
signal cfg_dstatus : std_logic_vector(15 downto 0);
|
544 |
|
|
signal cfg_dcommand : std_logic_vector(15 downto 0);
|
545 |
|
|
signal cfg_lstatus : std_logic_vector(15 downto 0);
|
546 |
|
|
signal cfg_lcommand : std_logic_vector(15 downto 0);
|
547 |
|
|
--signal unsigned_fast_simulation: unsigned(0 downto 0);
|
548 |
|
|
signal vector_fast_simulation: std_logic_vector(0 downto 0):=(0=>'1');
|
549 |
|
|
|
550 |
|
|
signal fc_sel : std_logic_vector( 2 downto 0 );
|
551 |
|
|
signal sys_reset_p : std_logic;
|
552 |
|
|
|
553 |
|
|
signal refclkout : std_logic;
|
554 |
|
|
|
555 |
|
|
|
556 |
|
|
signal clk : std_logic;
|
557 |
|
|
signal rstp : std_logic;
|
558 |
|
|
signal trn_rx : type_axi_rx; --! приём пакета
|
559 |
|
|
signal trn_rx_back : type_axi_rx_back; --! готовность к приёму пакета
|
560 |
|
|
|
561 |
|
|
signal reg_access : type_reg_access; --! запрос на доступ к регистрам
|
562 |
|
|
|
563 |
|
|
signal rx_tx_engine : type_rx_tx_engine; --! обмен RX->TX
|
564 |
|
|
signal tx_rx_engine : type_tx_rx_engine; --! обмен TX->RX
|
565 |
|
|
|
566 |
|
|
signal rx_ext_fifo : type_rx_ext_fifo; --! обмен RX->EXT_FIFO
|
567 |
|
|
signal tx_ext_fifo : type_tx_ext_fifo;
|
568 |
|
|
signal tx_ext_fifo_back : type_tx_ext_fifo_back;
|
569 |
|
|
signal reg_access_back : type_reg_access_back;
|
570 |
|
|
signal completer_id : std_logic_vector( 15 downto 0 );
|
571 |
|
|
|
572 |
|
|
signal trn_tx : type_axi_tx;
|
573 |
|
|
signal trn_tx_back : type_axi_tx_back;
|
574 |
|
|
|
575 |
|
|
signal reg_disp : type_reg_disp;
|
576 |
|
|
signal reg_disp_back : type_reg_disp_back;
|
577 |
|
|
|
578 |
|
|
signal reg_ext_fifo : type_reg_ext_fifo;
|
579 |
|
|
signal reg_ext_fifo_back : type_reg_ext_fifo_back;
|
580 |
|
|
|
581 |
|
|
signal ext_fifo_disp : type_ext_fifo_disp; --! запрос на доступ от узла EXT_FIFO
|
582 |
|
|
signal ext_fifo_disp_back : type_ext_fifo_disp_back; --! ответ на запрос
|
583 |
|
|
|
584 |
|
|
signal pb_rstp : std_logic;
|
585 |
|
|
|
586 |
|
|
signal irq : std_logic;
|
587 |
|
|
|
588 |
|
|
function SET_FAST_TRAIN( is_simulation : integer ) return string is
|
589 |
|
|
|
590 |
|
|
constant ret_true : string:="TRUE";
|
591 |
|
|
constant ret_false : string:="FALSE";
|
592 |
|
|
|
593 |
|
|
begin
|
594 |
|
|
|
595 |
|
|
if( is_simulation=0 ) then
|
596 |
|
|
return ret_false;
|
597 |
|
|
else
|
598 |
|
|
return ret_true;
|
599 |
|
|
end if;
|
600 |
|
|
|
601 |
|
|
end SET_FAST_TRAIN;
|
602 |
|
|
|
603 |
|
|
constant PL_FAST_TRAIN : string:= SET_FAST_TRAIN( is_simulation );
|
604 |
|
|
|
605 |
|
|
begin
|
606 |
|
|
|
607 |
|
|
|
608 |
|
|
|
609 |
|
|
clk_out <= clk;
|
610 |
|
|
reset_out <= not pb_rstp after 1 ns when rising_edge( clk );
|
611 |
|
|
|
612 |
|
|
ep : cl_a7pcie_x4
|
613 |
|
|
generic map(
|
614 |
|
|
CFG_DEV_ID => DEVICE_ID,
|
615 |
|
|
REF_CLK_FREQ => REF_CLK_FREQ, -- 0 - 100 MHz; 1 - 125 MHz; 2 - 250 MHz
|
616 |
|
|
PL_FAST_TRAIN => PL_FAST_TRAIN
|
617 |
|
|
-- INTERRUPT_PIN => INTERRUPT_PIN,
|
618 |
|
|
-- PCIE_CAP_INT_MSG_NUM => INTERRUPT_PIN
|
619 |
|
|
|
620 |
|
|
)
|
621 |
|
|
port map(
|
622 |
|
|
pci_exp_txp => txp,
|
623 |
|
|
pci_exp_txn => txn,
|
624 |
|
|
pci_exp_rxp => rxp,
|
625 |
|
|
pci_exp_rxn => rxn,
|
626 |
|
|
user_clk_out => clk ,
|
627 |
|
|
user_reset_out => user_reset,
|
628 |
|
|
user_lnk_up => user_lnk_up,
|
629 |
|
|
tx_buf_av => trn_tx_back.trn_tbuf_av ,
|
630 |
|
|
tx_cfg_req => trn_tx_back.tx_cfg_req ,
|
631 |
|
|
tx_err_drop => trn_tx_back.tx_err_drop ,
|
632 |
|
|
s_axis_tx_tready => trn_tx_back.s_axis_tx_tready ,
|
633 |
|
|
s_axis_tx_tdata => trn_tx.s_axis_tx_tdata ,
|
634 |
|
|
s_axis_tx_tkeep => trn_tx.s_axis_tx_tstrb ,
|
635 |
|
|
s_axis_tx_tlast => trn_tx.s_axis_tx_tlast ,
|
636 |
|
|
s_axis_tx_tvalid => trn_tx.s_axis_tx_tvalid ,
|
637 |
|
|
s_axis_tx_tuser => trn_tx.s_axis_tx_tuser,
|
638 |
|
|
tx_cfg_gnt => trn_tx.tx_cfg_gnt ,
|
639 |
|
|
m_axis_rx_tdata => trn_rx.m_axis_rx_tdata ,
|
640 |
|
|
m_axis_rx_tkeep => trn_rx.m_axis_rx_tstrb ,
|
641 |
|
|
m_axis_rx_tlast => trn_rx.m_axis_rx_tlast ,
|
642 |
|
|
m_axis_rx_tvalid => trn_rx.m_axis_rx_tvalid ,
|
643 |
|
|
m_axis_rx_tready => trn_rx_back.m_axis_rx_tready ,
|
644 |
|
|
m_axis_rx_tuser => trn_rx.m_axis_rx_tuser,
|
645 |
50 |
dsmv |
rx_np_ok => trn_rx_back.rx_np_ok ,
|
646 |
|
|
rx_np_req => '1',
|
647 |
46 |
dsmv |
fc_cpld => trn_tx_back.fc_cpld ,
|
648 |
|
|
fc_cplh => trn_tx_back.fc_cplh ,
|
649 |
|
|
fc_npd => trn_tx_back.fc_npd ,
|
650 |
|
|
fc_nph => trn_tx_back.fc_nph ,
|
651 |
|
|
fc_pd => trn_tx_back.fc_pd ,
|
652 |
|
|
fc_ph => trn_tx_back.fc_ph ,
|
653 |
|
|
fc_sel => trn_tx.fc_sel ,
|
654 |
|
|
|
655 |
|
|
cfg_interrupt => cfg_interrupt ,
|
656 |
|
|
cfg_interrupt_rdy => cfg_interrupt_rdy ,
|
657 |
|
|
cfg_interrupt_assert => cfg_interrupt_assert ,
|
658 |
|
|
cfg_interrupt_di => cfg_interrupt_di ,
|
659 |
|
|
cfg_interrupt_do => cfg_interrupt_do ,
|
660 |
|
|
cfg_interrupt_mmenable => cfg_interrupt_mmenable ,
|
661 |
|
|
cfg_interrupt_msienable => cfg_interrupt_msienable ,
|
662 |
|
|
cfg_turnoff_ok => cfg_turnoff_ok ,
|
663 |
|
|
cfg_to_turnoff => cfg_to_turnoff ,
|
664 |
|
|
cfg_trn_pending => cfg_trn_pending ,
|
665 |
|
|
cfg_pm_wake => cfg_pm_wake ,
|
666 |
|
|
cfg_bus_number => cfg_bus_number ,
|
667 |
|
|
cfg_device_number => cfg_device_number ,
|
668 |
|
|
cfg_function_number => cfg_function_number ,
|
669 |
|
|
cfg_status => cfg_status ,
|
670 |
|
|
cfg_command => cfg_command ,
|
671 |
|
|
cfg_dstatus => cfg_dstatus ,
|
672 |
|
|
cfg_dcommand => trn_tx_back.cfg_dcommand ,
|
673 |
|
|
cfg_lstatus => cfg_lstatus ,
|
674 |
|
|
cfg_lcommand => cfg_lcommand ,
|
675 |
|
|
cfg_dcommand2 => cfg_dcommand2 ,
|
676 |
|
|
cfg_pcie_link_state => cfg_pcie_link_state ,
|
677 |
|
|
cfg_dsn => cfg_dsn ,
|
678 |
|
|
cfg_pmcsr_pme_en => open,
|
679 |
|
|
cfg_pmcsr_pme_status => open,
|
680 |
|
|
cfg_pmcsr_powerstate => open,
|
681 |
|
|
|
682 |
47 |
dsmv |
PIPE_MMCM_RST_N => '1',
|
683 |
46 |
dsmv |
sys_clk => mgt250,
|
684 |
|
|
sys_rst_n => perst
|
685 |
|
|
|
686 |
|
|
);
|
687 |
|
|
|
688 |
|
|
sys_reset_p <= not perst;
|
689 |
|
|
|
690 |
|
|
pcie_link_up <= not user_lnk_up;
|
691 |
|
|
pcie_lstatus <= cfg_lstatus;
|
692 |
|
|
|
693 |
|
|
rstp <= user_reset after 1 ns when rising_edge( clk );
|
694 |
|
|
dcm_rstp <= user_reset;
|
695 |
|
|
|
696 |
|
|
pb_rstp <= rstp or ( not aclk_lock ) after 1 ns when rising_edge( clk );
|
697 |
|
|
|
698 |
|
|
--trn_tx_back.cfg_dcommand <= cfg_dcommand;
|
699 |
|
|
-- trn_rnp_ok_n_c <= '0';
|
700 |
|
|
-- trn_rcpl_streaming_n_c <= '1';
|
701 |
|
|
-- trn_terrfwd_n_c <= '1';
|
702 |
|
|
--
|
703 |
|
|
-- cfg_err_cor <= '1';
|
704 |
|
|
-- cfg_err_ur <= '1';
|
705 |
|
|
-- cfg_err_ecrc <= '1';
|
706 |
|
|
-- cfg_err_cpl_timeout <= '1';
|
707 |
|
|
-- cfg_err_cpl_abort <= '1';
|
708 |
|
|
-- cfg_err_cpl_unexpect <= '1';
|
709 |
|
|
-- cfg_err_posted <= '0';
|
710 |
|
|
--
|
711 |
|
|
-- cfg_interrupt_di <= X"00";
|
712 |
|
|
--
|
713 |
|
|
-- cfg_pm_wake <= '1';
|
714 |
|
|
-- cfg_trn_pending <= '1';
|
715 |
|
|
-- cfg_dwaddr <= (others => '0');
|
716 |
|
|
-- cfg_err_tlp_cpl_header <= (others => '0');
|
717 |
|
|
-- cfg_di <= (others => '0');
|
718 |
|
|
-- cfg_byte_en <= X"F"; -- 4-bit bus
|
719 |
|
|
-- cfg_wr_en <= '1';
|
720 |
|
|
-- cfg_rd_en <= '1';
|
721 |
|
|
|
722 |
|
|
fc_sel <= "000";
|
723 |
|
|
|
724 |
|
|
-- rx_np_ok <= '1';
|
725 |
|
|
--
|
726 |
|
|
-- tx_cfg_gnt <= '1';
|
727 |
|
|
--
|
728 |
|
|
cfg_err_cor <= '0';
|
729 |
|
|
cfg_err_ur <= '0';
|
730 |
|
|
cfg_err_ecrc <= '0';
|
731 |
|
|
cfg_err_cpl_timeout <= '0';
|
732 |
|
|
cfg_err_cpl_abort <= '0';
|
733 |
|
|
cfg_err_cpl_unexpect <= '0';
|
734 |
|
|
cfg_err_posted <= '0';
|
735 |
|
|
cfg_err_locked <= '0';
|
736 |
|
|
cfg_pm_wake <= '0';
|
737 |
|
|
cfg_trn_pending <= '0';
|
738 |
|
|
|
739 |
|
|
-- trn_tx.s_axis_tx_tuser(0) <= '0'; -- Unused for S6
|
740 |
|
|
-- trn_tx.s_axis_tx_tuser(1) <= '0'; -- Error forward packet
|
741 |
|
|
-- trn_tx.s_axis_tx_tuser(2) <= '0'; -- Stream packet
|
742 |
|
|
|
743 |
|
|
-- cfg_interrupt_assert <= '0';
|
744 |
|
|
-- cfg_interrupt <= '0';
|
745 |
|
|
cfg_interrupt_di <= x"00";
|
746 |
|
|
|
747 |
|
|
cfg_err_tlp_cpl_header <= (OTHERS => '0');
|
748 |
|
|
cfg_dwaddr <= (OTHERS => '0');
|
749 |
|
|
cfg_rd_en <= '0';
|
750 |
|
|
cfg_wr_en <= '0';
|
751 |
|
|
cfg_byte_en <= X"0";
|
752 |
|
|
cfg_di <= (others => '0');
|
753 |
|
|
cfg_dsn <= (others=>'0');
|
754 |
|
|
|
755 |
|
|
|
756 |
|
|
-- cfg_completer_id <= (cfg_bus_number &
|
757 |
|
|
-- cfg_device_number &
|
758 |
|
|
-- cfg_function_number);
|
759 |
|
|
-- cfg_bus_mstr_enable <= cfg_command(2);
|
760 |
|
|
|
761 |
|
|
pl_directed_link_auton <= '0';
|
762 |
|
|
pl_directed_link_speed <= '0';
|
763 |
|
|
pl_directed_link_width <= "00";
|
764 |
|
|
pl_directed_link_change <= "00";
|
765 |
|
|
pl_upstream_prefer_deemph <= '1';
|
766 |
|
|
|
767 |
|
|
-- cfg_completer_id_c <= (cfg_bus_number &
|
768 |
|
|
-- cfg_device_number &
|
769 |
|
|
-- cfg_function_number);
|
770 |
|
|
-- cfg_bus_mstr_enable_c <= cfg_command(2);
|
771 |
|
|
|
772 |
|
|
|
773 |
|
|
|
774 |
|
|
rx: core64_rx_engine_m2
|
775 |
|
|
port map(
|
776 |
|
|
|
777 |
|
|
--- General ---
|
778 |
|
|
rstp => rstp, --! 1 - сброс
|
779 |
|
|
clk => clk, --! тактовая частота ядра - 250 MHz
|
780 |
|
|
|
781 |
|
|
trn_rx => trn_rx, --! приём пакета
|
782 |
|
|
trn_rx_back => trn_rx_back, --! готовность к приёму пакета
|
783 |
|
|
|
784 |
|
|
reg_access => reg_access, --! запрос на доступ к регистрам
|
785 |
|
|
|
786 |
|
|
rx_tx_engine => rx_tx_engine, --! обмен RX->TX
|
787 |
|
|
tx_rx_engine => tx_rx_engine, --! обмен TX->RX
|
788 |
|
|
|
789 |
|
|
rx_ext_fifo => rx_ext_fifo --! обмен RX->EXT_FIFO
|
790 |
|
|
|
791 |
|
|
|
792 |
|
|
|
793 |
|
|
);
|
794 |
|
|
|
795 |
|
|
|
796 |
|
|
tx: core64_tx_engine_m2
|
797 |
|
|
generic map(
|
798 |
|
|
interrupt_number => interrupt_number -- номер INTx: 0 - INTA, 1 - INTB, 2 - INTC, 3 - INTD
|
799 |
|
|
)
|
800 |
|
|
port map(
|
801 |
|
|
|
802 |
|
|
--- General ---
|
803 |
|
|
rstp => rstp, --! 1 - сброс
|
804 |
|
|
clk => clk, --! тактовая частота ядра - 250 MHz
|
805 |
|
|
|
806 |
|
|
trn_tx => trn_tx, --! передача пакета
|
807 |
|
|
trn_tx_back => trn_tx_back, --! готовность к передаче пакета
|
808 |
|
|
|
809 |
|
|
completer_id => completer_id, --! идентификатор устройства
|
810 |
|
|
|
811 |
|
|
--cfg_interrupt => cfg_interrupt_n, -- 0 - изменение состояния прерывания
|
812 |
|
|
--cfg_interrupt_assert => cfg_interrupt_assert_n, -- 0 - формирование прерывания, 1 - снятие прерывания
|
813 |
|
|
--cfg_interrupt_rdy => cfg_interrupt_rdy_n, -- 0 - подтверждение изменения прерывания
|
814 |
|
|
|
815 |
|
|
cfg_interrupt => '1', -- 0 - изменение состояния прерывания
|
816 |
|
|
cfg_interrupt_assert => '1', -- 0 - формирование прерывания, 1 - снятие прерывания
|
817 |
|
|
--cfg_interrupt_rdy => cfg_interrupt_rdy_n, -- 0 - подтверждение изменения прерывания
|
818 |
|
|
|
819 |
|
|
reg_access_back => reg_access_back, --! запрос на доступ к регистрам
|
820 |
|
|
|
821 |
|
|
rx_tx_engine => rx_tx_engine, --! обмен RX->TX
|
822 |
|
|
tx_rx_engine => tx_rx_engine, --! обмен TX->RX
|
823 |
|
|
|
824 |
|
|
tx_ext_fifo => tx_ext_fifo, --! обмен TX->EXT_FIFO
|
825 |
|
|
tx_ext_fifo_back=> tx_ext_fifo_back --! обмен TX->EXT_FIFO
|
826 |
|
|
|
827 |
|
|
);
|
828 |
|
|
|
829 |
|
|
completer_id <= (cfg_bus_number &
|
830 |
|
|
cfg_device_number &
|
831 |
|
|
cfg_function_number );
|
832 |
|
|
|
833 |
|
|
|
834 |
|
|
reg: core64_reg_access
|
835 |
|
|
port map(
|
836 |
|
|
--- General ---
|
837 |
|
|
rstp => rstp, --! 1 - сброс
|
838 |
|
|
clk => clk, --! тактовая частота ядра - 250 MHz
|
839 |
|
|
|
840 |
|
|
--- RX_ENGINE ----
|
841 |
|
|
reg_access => reg_access, --! запрос на доступ к регистрам
|
842 |
|
|
|
843 |
|
|
--- TX_ENGINE ----
|
844 |
|
|
reg_access_back => reg_access_back, --! ответ на запрос
|
845 |
|
|
|
846 |
|
|
---- PB_DISP ----
|
847 |
|
|
reg_disp => reg_disp, --! запрос на доступ к регистрам из BAR1
|
848 |
|
|
reg_disp_back => reg_disp_back, --! ответ на запрос
|
849 |
|
|
|
850 |
|
|
---- BLOCK EXT_FIFO ----
|
851 |
|
|
reg_ext_fifo => reg_ext_fifo, --! запрос на доступ к блокам управления EXT_FIFO
|
852 |
|
|
reg_ext_fifo_back => reg_ext_fifo_back, --! ответ на запрос
|
853 |
|
|
|
854 |
|
|
---- BAR0 - блоки управления ----
|
855 |
|
|
bp_host_data => bp_host_data, --! шина данных - выход
|
856 |
|
|
bp_data => bp_data, --! шина данных - вход
|
857 |
|
|
bp_adr => bp_adr, --! адрес регистра
|
858 |
|
|
bp_we => bp_we, --! 1 - запись в регистры
|
859 |
|
|
bp_rd => bp_rd, --! 1 - чтение из регистров блока
|
860 |
|
|
bp_sel => bp_sel, --! номер блока для чтения
|
861 |
|
|
bp_reg_we => bp_reg_we, --! 1 - запись в регистр по адресам 0x100000 - 0x1FFFFF
|
862 |
|
|
bp_reg_rd => bp_reg_rd, --! 1 - чтение из регистра по адресам 0x100000 - 0x1FFFFF
|
863 |
|
|
bp_irq => bp_irq --! 1 - запрос прерывания
|
864 |
|
|
);
|
865 |
|
|
|
866 |
|
|
|
867 |
|
|
disp: core64_pb_disp
|
868 |
|
|
port map(
|
869 |
|
|
--- General ---
|
870 |
|
|
rstp => pb_rstp, --! 1 - сброс
|
871 |
|
|
clk => clk, --! тактовая частота ядра - 250 MHz
|
872 |
|
|
|
873 |
|
|
---- PB_DISP ----
|
874 |
|
|
reg_disp => reg_disp, --! запрос на доступ к регистрам из BAR1
|
875 |
|
|
reg_disp_back => reg_disp_back, --! ответ на запрос
|
876 |
|
|
|
877 |
|
|
---- EXT_FIFO ----
|
878 |
|
|
ext_fifo_disp => ext_fifo_disp, --! запрос на доступ от узла EXT_FIFO
|
879 |
|
|
ext_fifo_disp_back => ext_fifo_disp_back, --! ответ на запрос
|
880 |
|
|
|
881 |
|
|
---- BAR1 ----
|
882 |
|
|
aclk => aclk, --! тактовая частота локальной шины - 266 МГц
|
883 |
|
|
pb_master => pb_master, --! запрос
|
884 |
|
|
pb_slave => pb_slave --! ответ
|
885 |
|
|
|
886 |
|
|
);
|
887 |
|
|
|
888 |
|
|
|
889 |
|
|
|
890 |
|
|
fifo: block_pe_fifo_ext
|
891 |
|
|
port map(
|
892 |
|
|
|
893 |
|
|
---- Global ----
|
894 |
|
|
rstp => pb_rstp,
|
895 |
|
|
clk => clk,
|
896 |
|
|
aclk => aclk,
|
897 |
|
|
|
898 |
|
|
---- TX_ENGINE ----
|
899 |
|
|
tx_ext_fifo => tx_ext_fifo,
|
900 |
|
|
tx_ext_fifo_back => tx_ext_fifo_back,
|
901 |
|
|
|
902 |
|
|
---- RX_ENGINE ----
|
903 |
|
|
rx_ext_fifo => rx_ext_fifo,
|
904 |
|
|
|
905 |
|
|
---- REG ----
|
906 |
|
|
reg_ext_fifo => reg_ext_fifo,
|
907 |
|
|
reg_ext_fifo_back => reg_ext_fifo_back,
|
908 |
|
|
|
909 |
|
|
---- DISP ----
|
910 |
|
|
ext_fifo_disp => ext_fifo_disp,
|
911 |
|
|
ext_fifo_disp_back => ext_fifo_disp_back,
|
912 |
|
|
|
913 |
|
|
irq => irq, -- 1 - запрос прерывания
|
914 |
|
|
|
915 |
|
|
test => px
|
916 |
|
|
);
|
917 |
|
|
|
918 |
|
|
|
919 |
|
|
|
920 |
|
|
|
921 |
|
|
int: core64_interrupt
|
922 |
|
|
port map(
|
923 |
|
|
|
924 |
|
|
rstp => pb_rstp, -- 1 - сброс
|
925 |
|
|
clk => clk, -- Тактовая частота ядра 250 МГц
|
926 |
|
|
|
927 |
|
|
irq => irq, -- 1 - запрос прерывания
|
928 |
|
|
|
929 |
|
|
cfg_command10 => cfg_command(10), -- 1 - прерывания запрещены
|
930 |
|
|
cfg_interrupt => cfg_interrupt_n, -- 0 - изменение состояния прерывания
|
931 |
|
|
cfg_interrupt_assert => cfg_interrupt_assert_n, -- 0 - формирование прерывания, 1 - сниятие прерывания
|
932 |
|
|
cfg_interrupt_rdy => cfg_interrupt_rdy_n -- 0 - подтверждение изменения прерывания
|
933 |
|
|
|
934 |
|
|
);
|
935 |
|
|
|
936 |
|
|
cfg_interrupt <= not cfg_interrupt_n;
|
937 |
|
|
cfg_interrupt_assert <= not cfg_interrupt_assert_n;
|
938 |
|
|
cfg_interrupt_rdy_n <= not cfg_interrupt_rdy;
|
939 |
|
|
|
940 |
|
|
--cfg_interrupt <= '0';
|
941 |
|
|
--cfg_interrupt_assert <= '0';
|
942 |
|
|
-- cfg_interrupt_n_c <= '1';
|
943 |
|
|
-- cfg_interrupt_assert_n_c <= '1';
|
944 |
|
|
|
945 |
|
|
end pcie_core64_m10;
|