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-------------------------------------------------------------------------------
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--
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-- Title : pcie_core64_m4
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-- Author : Dmitry Smekhov
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-- Company : Instrumental Systems
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-- E-mail : dsmv@insys.ru
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--
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-- Version : 1.2
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--
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-------------------------------------------------------------------------------
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--
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-- Description : Контроллер шины PCI Express
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-- Модификация 4 - Virtex 6 PCI Express 2.0 x4
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--
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-------------------------------------------------------------------------------
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--
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-- Version 1.2 28.06.2012
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-- Добавлена возможность формирования прерываний INTA-INTC
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-- Необходимо установить параметры в узле cl_v6pcie_x4
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-- INTERRUPT_PIN : bit_vector := X"1";
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-- PCIE_CAP_INT_MSG_NUM : bit_vector := X"1"
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-- Установка параметров через функцию set_interrupt_pin
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-- не работает.
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-- Узел cl_v6pcie_x4 должен сформировать правильное
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-- значение линиии прерывания в регистре INTERRUPT PIN
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--
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-------------------------------------------------------------------------------
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--
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-- Version 1.1 19.06.2012
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-- Добавлена установка регистра DeviceId через generic
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--
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-------------------------------------------------------------------------------
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--
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-- Version 1.0 15.08.2011
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-- Создан из pcie_core64_m1 v1.0
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--
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.core64_type_pkg.all;
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package pcie_core64_m4_pkg is
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--! контроллер PCI-Express
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component pcie_core64_m4 is
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generic (
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DEVICE_ID : in bit_vector := X"5507"; --! значение регистра DeviceID
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refclk : in integer:=100; --! Значение опорной тактовой частоты [МГц]
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is_simulation : in integer:=0; --! 0 - синтез, 1 - моделирование
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interrupt_number : in std_logic_vector( 1 downto 0 ):="00" -- номер INTx: 0 - INTA, 1 - INTB, 2 - INTC, 3 - INTD
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);
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port (
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---- PCI-Express ----
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txp : out std_logic_vector( 3 downto 0 );
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txn : out std_logic_vector( 3 downto 0 );
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rxp : in std_logic_vector( 3 downto 0 );
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rxn : in std_logic_vector( 3 downto 0 );
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mgt250 : in std_logic; --! тактовая частота 250 MHz или 100 МГц от PCI_Express
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perst : in std_logic; --! 0 - сброс
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px : out std_logic_vector( 7 downto 0 ); --! контрольные точки
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pcie_lstatus : out std_logic_vector( 15 downto 0 ); -- регистр LSTATUS
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pcie_link_up : out std_logic; -- 0 - завершена инициализация PCI-Express
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---- Локальная шина ----
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clk_out : out std_logic; --! тактовая частота 250 MHz
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reset_out : out std_logic; --! 0 - сброс
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dcm_rstp : out std_logic; --! 1 - сброс DCM 266 МГц
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---- BAR0 - блоки управления ----
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bp_host_data : out std_logic_vector( 31 downto 0 ); --! шина данных - выход
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bp_data : in std_logic_vector( 31 downto 0 ); --! шина данных - вход
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bp_adr : out std_logic_vector( 19 downto 0 ); --! адрес регистра
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bp_we : out std_logic_vector( 3 downto 0 ); --! 1 - запись в регистры
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bp_rd : out std_logic_vector( 3 downto 0 ); --! 1 - чтение из регистров блока
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bp_sel : out std_logic_vector( 1 downto 0 ); --! номер блока для чтения
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bp_reg_we : out std_logic; --! 1 - запись в регистр по адресам 0x100000 - 0x1FFFFF
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bp_reg_rd : out std_logic; --! 1 - чтение из регистра по адресам 0x100000 - 0x1FFFFF
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bp_irq : in std_logic; --! 1 - запрос прерывания
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---- BAR1 ----
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aclk : in std_logic; --! тактовая частота локальной шины - 266 МГц
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aclk_lock : in std_logic; --! 1 - захват частоты
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pb_master : out type_pb_master; --! запрос
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pb_slave : in type_pb_slave --! ответ
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);
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end component;
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end package;
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library ieee;
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use ieee.std_logic_1164.all;
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use work.core64_type_pkg.all;
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use work.core64_rx_engine_m2_pkg.all;
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use work.core64_tx_engine_m2_pkg.all;
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use work.core64_reg_access_pkg.all;
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use work.core64_pb_disp_pkg.all;
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use work.block_pe_fifo_ext_pkg.all;
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use work.core64_interrupt_pkg.all;
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--! контроллер PCI-Express
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entity pcie_core64_m4 is
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generic (
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DEVICE_ID : in bit_vector := X"5507"; --! значение регистра DeviceID
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refclk : in integer:=100; --! Значение опорной тактовой частоты [МГц]
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is_simulation : in integer:=0; --! 0 - синтез, 1 - моделирование
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interrupt_number : in std_logic_vector( 1 downto 0 ):="00" -- номер INTx: 0 - INTA, 1 - INTB, 2 - INTC, 3 - INTD
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);
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port (
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---- PCI-Express ----
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txp : out std_logic_vector( 3 downto 0 );
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txn : out std_logic_vector( 3 downto 0 );
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rxp : in std_logic_vector( 3 downto 0 );
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rxn : in std_logic_vector( 3 downto 0 );
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mgt250 : in std_logic; --! тактовая частота 250 MHz или 100 МГц от PCI_Express
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perst : in std_logic; --! 0 - сброс
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px : out std_logic_vector( 7 downto 0 ); --! контрольные точки
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pcie_lstatus : out std_logic_vector( 15 downto 0 ); --! регистр LSTATUS
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pcie_link_up : out std_logic; --! 0 - завершена инициализация PCI-Express
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---- Локальная шина ----
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clk_out : out std_logic; --! тактовая частота 250 MHz
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reset_out : out std_logic; --! 0 - сброс
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dcm_rstp : out std_logic; --! 1 - сброс DCM 266 МГц
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---- BAR0 - блоки управления ----
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bp_host_data : out std_logic_vector( 31 downto 0 ); --! шина данных - выход
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bp_data : in std_logic_vector( 31 downto 0 ); --! шина данных - вход
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bp_adr : out std_logic_vector( 19 downto 0 ); --! адрес регистра
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bp_we : out std_logic_vector( 3 downto 0 ); --! 1 - запись в регистры
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bp_rd : out std_logic_vector( 3 downto 0 ); --! 1 - чтение из регистров блока
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bp_sel : out std_logic_vector( 1 downto 0 ); --! номер блока для чтения
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bp_reg_we : out std_logic; --! 1 - запись в регистр по адресам 0x100000 - 0x1FFFFF
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bp_reg_rd : out std_logic; --! 1 - чтение из регистра по адресам 0x100000 - 0x1FFFFF
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bp_irq : in std_logic; --! 1 - запрос прерывания
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---- BAR1 ----
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aclk : in std_logic; --! тактовая частота локальной шины - 266 МГц
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aclk_lock : in std_logic; --! 1 - захват частоты
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pb_master : out type_pb_master; --! запрос
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pb_slave : in type_pb_slave --! ответ
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);
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end pcie_core64_m4;
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architecture pcie_core64_m4 of pcie_core64_m4 is
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function set_refclk( refclk : in integer ) return integer is
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variable ret : integer;
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begin
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case( refclk ) is
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when 100 => ret:=0; -- 100 MHz --
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when 250 => ret:=2; -- 250 MHz --
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when others => ret:=1; -- 125 MHz --
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end case;
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return ret;
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end set_refclk;
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constant REF_CLK_FREQ : integer:=set_refclk( refclk );
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function set_interrupt_pin( num : in std_logic_vector( 1 downto 0 ) ) return bit_vector is
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variable ret : bit_vector( 3 downto 0 );
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begin
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case( num ) is
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when "00" => ret:=x"1"; -- INTA --
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when "01" => ret:=x"2"; -- INTB --
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when "10" => ret:=x"3"; -- INTC --
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when "11" => ret:=x"4"; -- INTD --
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when others => ret:=x"0";
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end case;
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return ret;
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end set_interrupt_pin;
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constant INTERRUPT_PIN : bit_vector( 3 downto 0 ):=set_interrupt_pin( interrupt_number );
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component cl_v6pcie_x4
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generic (
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DEVICE_ID : in bit_vector := X"5507";
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REF_CLK_FREQ : integer := 0; -- 0 - 100 MHz; 1 - 125 MHz; 2 - 250 MHz
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PL_FAST_TRAIN : in boolean;
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DISABLE_LANE_REVERSAL : boolean := TRUE
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-- INTERRUPT_PIN : bit_vector := X"1";
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-- PCIE_CAP_INT_MSG_NUM : bit_vector := X"1"
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);
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port (
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pci_exp_txp : out std_logic_vector(3 downto 0);
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pci_exp_txn : out std_logic_vector(3 downto 0);
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pci_exp_rxp : in std_logic_vector(3 downto 0);
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pci_exp_rxn : in std_logic_vector(3 downto 0);
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user_clk_out : out std_logic;
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user_reset_out : out std_logic;
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user_lnk_up : out std_logic;
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tx_buf_av : out std_logic_vector(5 downto 0);
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tx_cfg_req : out std_logic;
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tx_err_drop : out std_logic;
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s_axis_tx_tready : out std_logic;
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s_axis_tx_tdata : in std_logic_vector(63 downto 0);
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s_axis_tx_tlast : in std_logic;
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s_axis_tx_tvalid : in std_logic;
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s_axis_tx_tstrb : in std_logic_vector(7 downto 0);
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s_axis_tx_tuser : in std_logic_vector(3 downto 0);
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tx_cfg_gnt : in std_logic;
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m_axis_rx_tdata : out std_logic_vector(63 downto 0);
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m_axis_rx_tstrb : out std_logic_vector(7 downto 0);
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m_axis_rx_tlast : out std_logic;
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m_axis_rx_tvalid : out std_logic;
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m_axis_rx_tready : in std_logic;
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m_axis_rx_tuser : out std_logic_vector(21 downto 0);
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rx_np_ok : in std_logic;
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fc_cpld : out std_logic_vector(11 downto 0);
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fc_cplh : out std_logic_vector(7 downto 0);
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fc_npd : out std_logic_vector(11 downto 0);
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fc_nph : out std_logic_vector(7 downto 0);
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fc_pd : out std_logic_vector(11 downto 0);
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fc_ph : out std_logic_vector(7 downto 0);
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fc_sel : in std_logic_vector(2 downto 0);
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cfg_do : out std_logic_vector(31 downto 0);
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cfg_rd_wr_done : out std_logic;
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cfg_di : in std_logic_vector(31 downto 0);
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cfg_byte_en : in std_logic_vector(3 downto 0);
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cfg_dwaddr : in std_logic_vector(9 downto 0);
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cfg_wr_en : in std_logic;
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cfg_rd_en : in std_logic;
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cfg_err_cor : in std_logic;
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cfg_err_ur : in std_logic;
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cfg_err_ecrc : in std_logic;
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cfg_err_cpl_timeout : in std_logic;
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cfg_err_cpl_abort : in std_logic;
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cfg_err_cpl_unexpect : in std_logic;
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cfg_err_posted : in std_logic;
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cfg_err_locked : in std_logic;
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cfg_err_tlp_cpl_header : in std_logic_vector(47 downto 0);
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cfg_err_cpl_rdy : out std_logic;
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cfg_interrupt : in std_logic;
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cfg_interrupt_rdy : out std_logic;
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cfg_interrupt_assert : in std_logic;
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cfg_interrupt_di : in std_logic_vector(7 downto 0);
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cfg_interrupt_do : out std_logic_vector(7 downto 0);
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cfg_interrupt_mmenable : out std_logic_vector(2 downto 0);
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cfg_interrupt_msienable : out std_logic;
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cfg_interrupt_msixenable : out std_logic;
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cfg_interrupt_msixfm : out std_logic;
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cfg_turnoff_ok : in std_logic;
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cfg_to_turnoff : out std_logic;
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cfg_trn_pending : in std_logic;
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cfg_pm_wake : in std_logic;
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cfg_bus_number : out std_logic_vector(7 downto 0);
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cfg_device_number : out std_logic_vector(4 downto 0);
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cfg_function_number : out std_logic_vector(2 downto 0);
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cfg_status : out std_logic_vector(15 downto 0);
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cfg_command : out std_logic_vector(15 downto 0);
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cfg_dstatus : out std_logic_vector(15 downto 0);
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cfg_dcommand : out std_logic_vector(15 downto 0);
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cfg_lstatus : out std_logic_vector(15 downto 0);
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cfg_lcommand : out std_logic_vector(15 downto 0);
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cfg_dcommand2 : out std_logic_vector(15 downto 0);
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cfg_pcie_link_state : out std_logic_vector(2 downto 0);
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cfg_dsn : in std_logic_vector(63 downto 0);
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cfg_pmcsr_pme_en : out std_logic;
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cfg_pmcsr_pme_status : out std_logic;
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cfg_pmcsr_powerstate : out std_logic_vector(1 downto 0);
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pl_initial_link_width : out std_logic_vector(2 downto 0);
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pl_lane_reversal_mode : out std_logic_vector(1 downto 0);
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pl_link_gen2_capable : out std_logic;
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pl_link_partner_gen2_supported : out std_logic;
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|
|
pl_link_upcfg_capable : out std_logic;
|
307 |
|
|
pl_ltssm_state : out std_logic_vector(5 downto 0);
|
308 |
|
|
pl_received_hot_rst : out std_logic;
|
309 |
|
|
pl_sel_link_rate : out std_logic;
|
310 |
|
|
pl_sel_link_width : out std_logic_vector(1 downto 0);
|
311 |
|
|
pl_directed_link_auton : in std_logic;
|
312 |
|
|
pl_directed_link_change : in std_logic_vector(1 downto 0);
|
313 |
|
|
pl_directed_link_speed : in std_logic;
|
314 |
|
|
pl_directed_link_width : in std_logic_vector(1 downto 0);
|
315 |
|
|
pl_upstream_prefer_deemph : in std_logic;
|
316 |
|
|
sys_clk : in std_logic;
|
317 |
|
|
sys_reset : in std_logic);
|
318 |
|
|
end component;
|
319 |
|
|
--signal sys_clk_c : std_logic;
|
320 |
|
|
|
321 |
|
|
--signal sys_reset_n_c : std_logic;
|
322 |
|
|
signal trn_clk_c : std_logic;
|
323 |
|
|
signal user_reset : std_logic;
|
324 |
|
|
signal user_lnk_up : std_logic;
|
325 |
|
|
signal cfg_trn_pending_n_c : std_logic;
|
326 |
|
|
signal trn_tsof_n_c : std_logic;
|
327 |
|
|
signal trn_teof_n_c : std_logic;
|
328 |
|
|
signal trn_tsrc_rdy_n_c : std_logic;
|
329 |
|
|
signal trn_tdst_rdy_n_c : std_logic;
|
330 |
|
|
signal trn_tsrc_dsc_n_c : std_logic;
|
331 |
|
|
signal trn_terrfwd_n_c : std_logic;
|
332 |
|
|
signal trn_tdst_dsc_n_c : std_logic;
|
333 |
|
|
signal trn_td_c : std_logic_vector((64 - 1) downto 0);
|
334 |
|
|
signal trn_trem_n_c : std_logic_vector(7 downto 0);
|
335 |
|
|
signal trn_tbuf_av_c : std_logic_vector(( 4 -1 ) downto 0);
|
336 |
|
|
signal trn_rsof_n_c : std_logic;
|
337 |
|
|
signal trn_reof_n_c : std_logic;
|
338 |
|
|
signal trn_rsrc_rdy_n_c : std_logic;
|
339 |
|
|
signal trn_rsrc_dsc_n_c : std_logic;
|
340 |
|
|
signal trn_rdst_rdy_n_c : std_logic;
|
341 |
|
|
signal trn_rerrfwd_n_c : std_logic;
|
342 |
|
|
signal trn_rnp_ok_n_c : std_logic;
|
343 |
|
|
|
344 |
|
|
signal trn_rd_c : std_logic_vector((64 - 1) downto 0);
|
345 |
|
|
signal trn_rrem_n_c : std_logic_vector(7 downto 0);
|
346 |
|
|
signal trn_rbar_hit_n_c : std_logic_vector(6 downto 0);
|
347 |
|
|
signal trn_rfc_nph_av_c : std_logic_vector(7 downto 0);
|
348 |
|
|
signal trn_rfc_npd_av_c : std_logic_vector(11 downto 0);
|
349 |
|
|
signal trn_rfc_ph_av_c : std_logic_vector(7 downto 0);
|
350 |
|
|
signal trn_rfc_pd_av_c : std_logic_vector(11 downto 0);
|
351 |
|
|
signal trn_rcpl_streaming_n_c : std_logic;
|
352 |
|
|
|
353 |
|
|
signal cfg_do : std_logic_vector(31 downto 0);
|
354 |
|
|
signal cfg_di : std_logic_vector(31 downto 0);
|
355 |
|
|
signal cfg_dwaddr : std_logic_vector(9 downto 0) ;
|
356 |
|
|
signal cfg_byte_en : std_logic_vector(3 downto 0);
|
357 |
|
|
signal cfg_err_tlp_cpl_header : std_logic_vector(47 downto 0);
|
358 |
|
|
signal cfg_wr_en : std_logic;
|
359 |
|
|
signal cfg_rd_en : std_logic;
|
360 |
|
|
signal cfg_rd_wr_done : std_logic;
|
361 |
|
|
signal cfg_err_cor : std_logic;
|
362 |
|
|
signal cfg_err_ur : std_logic;
|
363 |
|
|
signal cfg_err_ecrc : std_logic;
|
364 |
|
|
signal cfg_err_cpl_timeout : std_logic;
|
365 |
|
|
signal cfg_err_cpl_abort : std_logic;
|
366 |
|
|
signal cfg_err_cpl_unexpect : std_logic;
|
367 |
|
|
signal cfg_err_posted : std_logic;
|
368 |
|
|
signal cfg_err_locked : std_logic;
|
369 |
|
|
signal cfg_trn_pending : std_logic;
|
370 |
|
|
signal cfg_dcommand2 : std_logic_vector(15 downto 0);
|
371 |
|
|
signal cfg_dsn : std_logic_vector(63 downto 0);
|
372 |
|
|
|
373 |
|
|
|
374 |
|
|
signal pl_initial_link_width : std_logic_vector(2 downto 0);
|
375 |
|
|
signal pl_lane_reversal_mode : std_logic_vector(1 downto 0);
|
376 |
|
|
signal pl_link_gen2_capable : std_logic;
|
377 |
|
|
signal pl_link_partner_gen2_supported : std_logic;
|
378 |
|
|
signal pl_link_upcfg_capable : std_logic;
|
379 |
|
|
signal pl_ltssm_state : std_logic_vector(5 downto 0);
|
380 |
|
|
signal pl_received_hot_rst : std_logic;
|
381 |
|
|
signal pl_sel_link_rate : std_logic;
|
382 |
|
|
signal pl_sel_link_width : std_logic_vector(1 downto 0);
|
383 |
|
|
signal pl_directed_link_auton : std_logic;
|
384 |
|
|
signal pl_directed_link_change : std_logic_vector(1 downto 0);
|
385 |
|
|
signal pl_directed_link_speed : std_logic;
|
386 |
|
|
signal pl_directed_link_width : std_logic_vector(1 downto 0);
|
387 |
|
|
signal pl_upstream_prefer_deemph : std_logic;
|
388 |
|
|
|
389 |
|
|
|
390 |
|
|
|
391 |
|
|
signal cfg_err_cpl_rdy : std_logic;
|
392 |
|
|
signal cfg_interrupt : std_logic;
|
393 |
|
|
signal cfg_interrupt_rdy : std_logic;
|
394 |
|
|
|
395 |
|
|
signal cfg_interrupt_assert : std_logic;
|
396 |
|
|
|
397 |
|
|
signal cfg_interrupt_n : std_logic;
|
398 |
|
|
signal cfg_interrupt_rdy_n : std_logic;
|
399 |
|
|
signal cfg_interrupt_assert_n : std_logic;
|
400 |
|
|
|
401 |
|
|
|
402 |
|
|
signal cfg_interrupt_di : std_logic_vector(7 downto 0);
|
403 |
|
|
signal cfg_interrupt_do : std_logic_vector(7 downto 0);
|
404 |
|
|
signal cfg_interrupt_mmenable : std_logic_vector(2 downto 0);
|
405 |
|
|
signal cfg_interrupt_msienable: std_logic;
|
406 |
|
|
|
407 |
|
|
signal cfg_turnoff_ok : std_logic;
|
408 |
|
|
signal cfg_to_turnoff : std_logic;
|
409 |
|
|
signal cfg_pm_wake : std_logic;
|
410 |
|
|
signal cfg_pcie_link_state : std_logic_vector(2 downto 0);
|
411 |
|
|
signal cfg_bus_number : std_logic_vector(7 downto 0);
|
412 |
|
|
signal cfg_device_number : std_logic_vector(4 downto 0);
|
413 |
|
|
signal cfg_function_number : std_logic_vector(2 downto 0);
|
414 |
|
|
signal cfg_status : std_logic_vector(15 downto 0);
|
415 |
|
|
signal cfg_command : std_logic_vector(15 downto 0);
|
416 |
|
|
signal cfg_dstatus : std_logic_vector(15 downto 0);
|
417 |
|
|
signal cfg_dcommand : std_logic_vector(15 downto 0);
|
418 |
|
|
signal cfg_lstatus : std_logic_vector(15 downto 0);
|
419 |
|
|
signal cfg_lcommand : std_logic_vector(15 downto 0);
|
420 |
|
|
--signal unsigned_fast_simulation: unsigned(0 downto 0);
|
421 |
|
|
signal vector_fast_simulation: std_logic_vector(0 downto 0):=(0=>'1');
|
422 |
|
|
|
423 |
|
|
signal fc_sel : std_logic_vector( 2 downto 0 );
|
424 |
|
|
signal sys_reset_p : std_logic;
|
425 |
|
|
|
426 |
|
|
signal refclkout : std_logic;
|
427 |
|
|
|
428 |
|
|
|
429 |
|
|
signal clk : std_logic;
|
430 |
|
|
signal rstp : std_logic;
|
431 |
|
|
signal trn_rx : type_axi_rx; --! приём пакета
|
432 |
|
|
signal trn_rx_back : type_axi_rx_back; --! готовность к приёму пакета
|
433 |
|
|
|
434 |
|
|
signal reg_access : type_reg_access; --! запрос на доступ к регистрам
|
435 |
|
|
|
436 |
|
|
signal rx_tx_engine : type_rx_tx_engine; --! обмен RX->TX
|
437 |
|
|
signal tx_rx_engine : type_tx_rx_engine; --! обмен TX->RX
|
438 |
|
|
|
439 |
|
|
signal rx_ext_fifo : type_rx_ext_fifo; --! обмен RX->EXT_FIFO
|
440 |
|
|
signal tx_ext_fifo : type_tx_ext_fifo;
|
441 |
|
|
signal tx_ext_fifo_back : type_tx_ext_fifo_back;
|
442 |
|
|
signal reg_access_back : type_reg_access_back;
|
443 |
|
|
signal completer_id : std_logic_vector( 15 downto 0 );
|
444 |
|
|
|
445 |
|
|
signal trn_tx : type_axi_tx;
|
446 |
|
|
signal trn_tx_back : type_axi_tx_back;
|
447 |
|
|
|
448 |
|
|
signal reg_disp : type_reg_disp;
|
449 |
|
|
signal reg_disp_back : type_reg_disp_back;
|
450 |
|
|
|
451 |
|
|
signal reg_ext_fifo : type_reg_ext_fifo;
|
452 |
|
|
signal reg_ext_fifo_back : type_reg_ext_fifo_back;
|
453 |
|
|
|
454 |
|
|
signal ext_fifo_disp : type_ext_fifo_disp; --! запрос на доступ от узла EXT_FIFO
|
455 |
|
|
signal ext_fifo_disp_back : type_ext_fifo_disp_back; --! ответ на запрос
|
456 |
|
|
|
457 |
|
|
signal pb_rstp : std_logic;
|
458 |
|
|
|
459 |
|
|
signal irq : std_logic;
|
460 |
|
|
|
461 |
|
|
function SET_FAST_TRAIN( is_simulation : integer ) return boolean is
|
462 |
|
|
|
463 |
|
|
variable ret : boolean;
|
464 |
|
|
begin
|
465 |
|
|
|
466 |
|
|
if( is_simulation=0 ) then
|
467 |
|
|
ret:=false;
|
468 |
|
|
else
|
469 |
|
|
ret:=true;
|
470 |
|
|
end if;
|
471 |
|
|
return ret;
|
472 |
|
|
|
473 |
|
|
end SET_FAST_TRAIN;
|
474 |
|
|
|
475 |
|
|
constant PL_FAST_TRAIN : boolean:= SET_FAST_TRAIN( is_simulation );
|
476 |
|
|
|
477 |
|
|
begin
|
478 |
|
|
|
479 |
|
|
--gen_sim: if( is_simulation/=0 ) generate
|
480 |
|
|
-- vector_fast_simulation <= (others=>'1');
|
481 |
|
|
--end generate;
|
482 |
|
|
--
|
483 |
|
|
--gen_syn: if( is_simulation=0 ) generate
|
484 |
|
|
-- vector_fast_simulation <= (others=>'0');
|
485 |
|
|
--end generate;
|
486 |
|
|
|
487 |
|
|
|
488 |
|
|
clk_out <= clk;
|
489 |
|
|
reset_out <= not pb_rstp after 1 ns when rising_edge( clk );
|
490 |
|
|
|
491 |
|
|
ep : cl_v6pcie_x4
|
492 |
|
|
generic map(
|
493 |
|
|
DEVICE_ID => DEVICE_ID,
|
494 |
|
|
REF_CLK_FREQ => REF_CLK_FREQ, -- 0 - 100 MHz; 1 - 125 MHz; 2 - 250 MHz
|
495 |
|
|
PL_FAST_TRAIN => PL_FAST_TRAIN
|
496 |
|
|
-- INTERRUPT_PIN => INTERRUPT_PIN,
|
497 |
|
|
-- PCIE_CAP_INT_MSG_NUM => INTERRUPT_PIN
|
498 |
|
|
|
499 |
|
|
)
|
500 |
|
|
port map(
|
501 |
|
|
pci_exp_txp => txp,
|
502 |
|
|
pci_exp_txn => txn,
|
503 |
|
|
pci_exp_rxp => rxp,
|
504 |
|
|
pci_exp_rxn => rxn,
|
505 |
|
|
user_clk_out => clk ,
|
506 |
|
|
user_reset_out => user_reset,
|
507 |
|
|
user_lnk_up => user_lnk_up,
|
508 |
|
|
tx_buf_av => trn_tx_back.trn_tbuf_av ,
|
509 |
|
|
tx_cfg_req => trn_tx_back.tx_cfg_req ,
|
510 |
|
|
tx_err_drop => trn_tx_back.tx_err_drop ,
|
511 |
|
|
s_axis_tx_tready => trn_tx_back.s_axis_tx_tready ,
|
512 |
|
|
s_axis_tx_tdata => trn_tx.s_axis_tx_tdata ,
|
513 |
|
|
s_axis_tx_tstrb => trn_tx.s_axis_tx_tstrb ,
|
514 |
|
|
s_axis_tx_tlast => trn_tx.s_axis_tx_tlast ,
|
515 |
|
|
s_axis_tx_tvalid => trn_tx.s_axis_tx_tvalid ,
|
516 |
|
|
s_axis_tx_tuser => trn_tx.s_axis_tx_tuser,
|
517 |
|
|
tx_cfg_gnt => trn_tx.tx_cfg_gnt ,
|
518 |
|
|
m_axis_rx_tdata => trn_rx.m_axis_rx_tdata ,
|
519 |
|
|
m_axis_rx_tstrb => trn_rx.m_axis_rx_tstrb ,
|
520 |
|
|
m_axis_rx_tlast => trn_rx.m_axis_rx_tlast ,
|
521 |
|
|
m_axis_rx_tvalid => trn_rx.m_axis_rx_tvalid ,
|
522 |
|
|
m_axis_rx_tready => trn_rx_back.m_axis_rx_tready ,
|
523 |
|
|
m_axis_rx_tuser => trn_rx.m_axis_rx_tuser,
|
524 |
|
|
rx_np_ok => trn_rx_back.rx_np_ok ,
|
525 |
|
|
fc_cpld => trn_tx_back.fc_cpld ,
|
526 |
|
|
fc_cplh => trn_tx_back.fc_cplh ,
|
527 |
|
|
fc_npd => trn_tx_back.fc_npd ,
|
528 |
|
|
fc_nph => trn_tx_back.fc_nph ,
|
529 |
|
|
fc_pd => trn_tx_back.fc_pd ,
|
530 |
|
|
fc_ph => trn_tx_back.fc_ph ,
|
531 |
|
|
fc_sel => trn_tx.fc_sel ,
|
532 |
|
|
cfg_do => cfg_do ,
|
533 |
|
|
cfg_rd_wr_done => cfg_rd_wr_done,
|
534 |
|
|
cfg_di => cfg_di ,
|
535 |
|
|
cfg_byte_en => cfg_byte_en ,
|
536 |
|
|
cfg_dwaddr => cfg_dwaddr ,
|
537 |
|
|
cfg_wr_en => cfg_wr_en ,
|
538 |
|
|
cfg_rd_en => cfg_rd_en ,
|
539 |
|
|
|
540 |
|
|
cfg_err_cor => cfg_err_cor ,
|
541 |
|
|
cfg_err_ur => cfg_err_ur ,
|
542 |
|
|
cfg_err_ecrc => cfg_err_ecrc ,
|
543 |
|
|
cfg_err_cpl_timeout => cfg_err_cpl_timeout ,
|
544 |
|
|
cfg_err_cpl_abort => cfg_err_cpl_abort ,
|
545 |
|
|
cfg_err_cpl_unexpect => cfg_err_cpl_unexpect ,
|
546 |
|
|
cfg_err_posted => cfg_err_posted ,
|
547 |
|
|
cfg_err_locked => cfg_err_locked ,
|
548 |
|
|
cfg_err_tlp_cpl_header => cfg_err_tlp_cpl_header ,
|
549 |
|
|
cfg_err_cpl_rdy => cfg_err_cpl_rdy ,
|
550 |
|
|
cfg_interrupt => cfg_interrupt ,
|
551 |
|
|
--cfg_interrupt_rdy => cfg_interrupt_rdy ,
|
552 |
|
|
cfg_interrupt_assert => cfg_interrupt_assert ,
|
553 |
|
|
cfg_interrupt_di => cfg_interrupt_di ,
|
554 |
|
|
cfg_interrupt_do => cfg_interrupt_do ,
|
555 |
|
|
cfg_interrupt_mmenable => cfg_interrupt_mmenable ,
|
556 |
|
|
cfg_interrupt_msienable => cfg_interrupt_msienable ,
|
557 |
|
|
--cfg_interrupt_msixenable => cfg_interrupt_msixenable ,
|
558 |
|
|
--cfg_interrupt_msixfm => cfg_interrupt_msixfm ,
|
559 |
|
|
cfg_turnoff_ok => cfg_turnoff_ok ,
|
560 |
|
|
cfg_to_turnoff => cfg_to_turnoff ,
|
561 |
|
|
cfg_trn_pending => cfg_trn_pending ,
|
562 |
|
|
cfg_pm_wake => cfg_pm_wake ,
|
563 |
|
|
cfg_bus_number => cfg_bus_number ,
|
564 |
|
|
cfg_device_number => cfg_device_number ,
|
565 |
|
|
cfg_function_number => cfg_function_number ,
|
566 |
|
|
cfg_status => cfg_status ,
|
567 |
|
|
cfg_command => cfg_command ,
|
568 |
|
|
cfg_dstatus => cfg_dstatus ,
|
569 |
|
|
cfg_dcommand => trn_tx_back.cfg_dcommand ,
|
570 |
|
|
cfg_lstatus => cfg_lstatus ,
|
571 |
|
|
cfg_lcommand => cfg_lcommand ,
|
572 |
|
|
cfg_dcommand2 => cfg_dcommand2 ,
|
573 |
|
|
cfg_pcie_link_state => cfg_pcie_link_state ,
|
574 |
|
|
cfg_dsn => cfg_dsn ,
|
575 |
|
|
cfg_pmcsr_pme_en => open,
|
576 |
|
|
cfg_pmcsr_pme_status => open,
|
577 |
|
|
cfg_pmcsr_powerstate => open,
|
578 |
|
|
pl_initial_link_width => pl_initial_link_width ,
|
579 |
|
|
pl_lane_reversal_mode => pl_lane_reversal_mode ,
|
580 |
|
|
pl_link_gen2_capable => pl_link_gen2_capable ,
|
581 |
|
|
pl_link_partner_gen2_supported => pl_link_partner_gen2_supported ,
|
582 |
|
|
pl_link_upcfg_capable => pl_link_upcfg_capable ,
|
583 |
|
|
pl_ltssm_state => pl_ltssm_state ,
|
584 |
|
|
pl_received_hot_rst => pl_received_hot_rst ,
|
585 |
|
|
pl_sel_link_rate => pl_sel_link_rate ,
|
586 |
|
|
pl_sel_link_width => pl_sel_link_width ,
|
587 |
|
|
pl_directed_link_auton => pl_directed_link_auton ,
|
588 |
|
|
pl_directed_link_change => pl_directed_link_change ,
|
589 |
|
|
pl_directed_link_speed => pl_directed_link_speed ,
|
590 |
|
|
pl_directed_link_width => pl_directed_link_width ,
|
591 |
|
|
pl_upstream_prefer_deemph => pl_upstream_prefer_deemph ,
|
592 |
|
|
sys_clk => mgt250,
|
593 |
|
|
sys_reset => sys_reset_p
|
594 |
|
|
|
595 |
|
|
);
|
596 |
|
|
|
597 |
|
|
sys_reset_p <= not perst;
|
598 |
|
|
|
599 |
|
|
pcie_link_up <= not user_lnk_up;
|
600 |
|
|
pcie_lstatus <= cfg_lstatus;
|
601 |
|
|
|
602 |
|
|
rstp <= user_reset after 1 ns when rising_edge( clk );
|
603 |
|
|
dcm_rstp <= user_reset;
|
604 |
|
|
|
605 |
|
|
pb_rstp <= rstp or ( not aclk_lock ) after 1 ns when rising_edge( clk );
|
606 |
|
|
|
607 |
|
|
--trn_tx_back.cfg_dcommand <= cfg_dcommand;
|
608 |
|
|
-- trn_rnp_ok_n_c <= '0';
|
609 |
|
|
-- trn_rcpl_streaming_n_c <= '1';
|
610 |
|
|
-- trn_terrfwd_n_c <= '1';
|
611 |
|
|
--
|
612 |
|
|
-- cfg_err_cor <= '1';
|
613 |
|
|
-- cfg_err_ur <= '1';
|
614 |
|
|
-- cfg_err_ecrc <= '1';
|
615 |
|
|
-- cfg_err_cpl_timeout <= '1';
|
616 |
|
|
-- cfg_err_cpl_abort <= '1';
|
617 |
|
|
-- cfg_err_cpl_unexpect <= '1';
|
618 |
|
|
-- cfg_err_posted <= '0';
|
619 |
|
|
--
|
620 |
|
|
-- cfg_interrupt_di <= X"00";
|
621 |
|
|
--
|
622 |
|
|
-- cfg_pm_wake <= '1';
|
623 |
|
|
-- cfg_trn_pending <= '1';
|
624 |
|
|
-- cfg_dwaddr <= (others => '0');
|
625 |
|
|
-- cfg_err_tlp_cpl_header <= (others => '0');
|
626 |
|
|
-- cfg_di <= (others => '0');
|
627 |
|
|
-- cfg_byte_en <= X"F"; -- 4-bit bus
|
628 |
|
|
-- cfg_wr_en <= '1';
|
629 |
|
|
-- cfg_rd_en <= '1';
|
630 |
|
|
|
631 |
|
|
fc_sel <= "000";
|
632 |
|
|
|
633 |
|
|
-- rx_np_ok <= '1';
|
634 |
|
|
--
|
635 |
|
|
-- tx_cfg_gnt <= '1';
|
636 |
|
|
--
|
637 |
|
|
cfg_err_cor <= '0';
|
638 |
|
|
cfg_err_ur <= '0';
|
639 |
|
|
cfg_err_ecrc <= '0';
|
640 |
|
|
cfg_err_cpl_timeout <= '0';
|
641 |
|
|
cfg_err_cpl_abort <= '0';
|
642 |
|
|
cfg_err_cpl_unexpect <= '0';
|
643 |
|
|
cfg_err_posted <= '0';
|
644 |
|
|
cfg_err_locked <= '0';
|
645 |
|
|
cfg_pm_wake <= '0';
|
646 |
|
|
cfg_trn_pending <= '0';
|
647 |
|
|
|
648 |
|
|
-- trn_tx.s_axis_tx_tuser(0) <= '0'; -- Unused for S6
|
649 |
|
|
-- trn_tx.s_axis_tx_tuser(1) <= '0'; -- Error forward packet
|
650 |
|
|
-- trn_tx.s_axis_tx_tuser(2) <= '0'; -- Stream packet
|
651 |
|
|
|
652 |
|
|
-- cfg_interrupt_assert <= '0';
|
653 |
|
|
-- cfg_interrupt <= '0';
|
654 |
|
|
cfg_interrupt_di <= x"00";
|
655 |
|
|
|
656 |
|
|
cfg_err_tlp_cpl_header <= (OTHERS => '0');
|
657 |
|
|
cfg_dwaddr <= (OTHERS => '0');
|
658 |
|
|
cfg_rd_en <= '0';
|
659 |
|
|
cfg_wr_en <= '0';
|
660 |
|
|
cfg_byte_en <= X"0";
|
661 |
|
|
cfg_di <= (others => '0');
|
662 |
|
|
cfg_dsn <= (others=>'0');
|
663 |
|
|
|
664 |
|
|
|
665 |
|
|
-- cfg_completer_id <= (cfg_bus_number &
|
666 |
|
|
-- cfg_device_number &
|
667 |
|
|
-- cfg_function_number);
|
668 |
|
|
-- cfg_bus_mstr_enable <= cfg_command(2);
|
669 |
|
|
|
670 |
|
|
pl_directed_link_auton <= '0';
|
671 |
|
|
pl_directed_link_speed <= '0';
|
672 |
|
|
pl_directed_link_width <= "00";
|
673 |
|
|
pl_directed_link_change <= "00";
|
674 |
|
|
pl_upstream_prefer_deemph <= '1';
|
675 |
|
|
|
676 |
|
|
-- cfg_completer_id_c <= (cfg_bus_number &
|
677 |
|
|
-- cfg_device_number &
|
678 |
|
|
-- cfg_function_number);
|
679 |
|
|
-- cfg_bus_mstr_enable_c <= cfg_command(2);
|
680 |
|
|
|
681 |
|
|
|
682 |
|
|
|
683 |
|
|
rx: core64_rx_engine_m2
|
684 |
|
|
port map(
|
685 |
|
|
|
686 |
|
|
--- General ---
|
687 |
|
|
rstp => rstp, --! 1 - сброс
|
688 |
|
|
clk => clk, --! тактовая частота ядра - 250 MHz
|
689 |
|
|
|
690 |
|
|
trn_rx => trn_rx, --! приём пакета
|
691 |
|
|
trn_rx_back => trn_rx_back, --! готовность к приёму пакета
|
692 |
|
|
|
693 |
|
|
reg_access => reg_access, --! запрос на доступ к регистрам
|
694 |
|
|
|
695 |
|
|
rx_tx_engine => rx_tx_engine, --! обмен RX->TX
|
696 |
|
|
tx_rx_engine => tx_rx_engine, --! обмен TX->RX
|
697 |
|
|
|
698 |
|
|
rx_ext_fifo => rx_ext_fifo --! обмен RX->EXT_FIFO
|
699 |
|
|
|
700 |
|
|
|
701 |
|
|
|
702 |
|
|
);
|
703 |
|
|
|
704 |
|
|
|
705 |
|
|
tx: core64_tx_engine_m2
|
706 |
|
|
generic map(
|
707 |
|
|
interrupt_number => interrupt_number -- номер INTx: 0 - INTA, 1 - INTB, 2 - INTC, 3 - INTD
|
708 |
|
|
)
|
709 |
|
|
port map(
|
710 |
|
|
|
711 |
|
|
--- General ---
|
712 |
|
|
rstp => rstp, --! 1 - сброс
|
713 |
|
|
clk => clk, --! тактовая частота ядра - 250 MHz
|
714 |
|
|
|
715 |
|
|
trn_tx => trn_tx, --! передача пакета
|
716 |
|
|
trn_tx_back => trn_tx_back, --! готовность к передаче пакета
|
717 |
|
|
|
718 |
|
|
completer_id => completer_id, --! идентификатор устройства
|
719 |
|
|
|
720 |
|
|
cfg_interrupt => cfg_interrupt_n, -- 0 - изменение состояния прерывания
|
721 |
|
|
cfg_interrupt_assert => cfg_interrupt_assert_n, -- 0 - формирование прерывания, 1 - сниятие прерывания
|
722 |
|
|
cfg_interrupt_rdy => cfg_interrupt_rdy_n, -- 0 - подтверждение изменения прерывания
|
723 |
|
|
|
724 |
|
|
reg_access_back => reg_access_back, --! запрос на доступ к регистрам
|
725 |
|
|
|
726 |
|
|
rx_tx_engine => rx_tx_engine, --! обмен RX->TX
|
727 |
|
|
tx_rx_engine => tx_rx_engine, --! обмен TX->RX
|
728 |
|
|
|
729 |
|
|
tx_ext_fifo => tx_ext_fifo, --! обмен TX->EXT_FIFO
|
730 |
|
|
tx_ext_fifo_back=> tx_ext_fifo_back --! обмен TX->EXT_FIFO
|
731 |
|
|
|
732 |
|
|
);
|
733 |
|
|
|
734 |
|
|
completer_id <= (cfg_bus_number &
|
735 |
|
|
cfg_device_number &
|
736 |
|
|
cfg_function_number );
|
737 |
|
|
|
738 |
|
|
|
739 |
|
|
reg: core64_reg_access
|
740 |
|
|
port map(
|
741 |
|
|
--- General ---
|
742 |
|
|
rstp => rstp, --! 1 - сброс
|
743 |
|
|
clk => clk, --! тактовая частота ядра - 250 MHz
|
744 |
|
|
|
745 |
|
|
--- RX_ENGINE ----
|
746 |
|
|
reg_access => reg_access, --! запрос на доступ к регистрам
|
747 |
|
|
|
748 |
|
|
--- TX_ENGINE ----
|
749 |
|
|
reg_access_back => reg_access_back, --! ответ на запрос
|
750 |
|
|
|
751 |
|
|
---- PB_DISP ----
|
752 |
|
|
reg_disp => reg_disp, --! запрос на доступ к регистрам из BAR1
|
753 |
|
|
reg_disp_back => reg_disp_back, --! ответ на запрос
|
754 |
|
|
|
755 |
|
|
---- BLOCK EXT_FIFO ----
|
756 |
|
|
reg_ext_fifo => reg_ext_fifo, --! запрос на доступ к блокам управления EXT_FIFO
|
757 |
|
|
reg_ext_fifo_back => reg_ext_fifo_back, --! ответ на запрос
|
758 |
|
|
|
759 |
|
|
---- BAR0 - блоки управления ----
|
760 |
|
|
bp_host_data => bp_host_data, --! шина данных - выход
|
761 |
|
|
bp_data => bp_data, --! шина данных - вход
|
762 |
|
|
bp_adr => bp_adr, --! адрес регистра
|
763 |
|
|
bp_we => bp_we, --! 1 - запись в регистры
|
764 |
|
|
bp_rd => bp_rd, --! 1 - чтение из регистров блока
|
765 |
|
|
bp_sel => bp_sel, --! номер блока для чтения
|
766 |
|
|
bp_reg_we => bp_reg_we, --! 1 - запись в регистр по адресам 0x100000 - 0x1FFFFF
|
767 |
|
|
bp_reg_rd => bp_reg_rd, --! 1 - чтение из регистра по адресам 0x100000 - 0x1FFFFF
|
768 |
|
|
bp_irq => bp_irq --! 1 - запрос прерывания
|
769 |
|
|
);
|
770 |
|
|
|
771 |
|
|
|
772 |
|
|
disp: core64_pb_disp
|
773 |
|
|
port map(
|
774 |
|
|
--- General ---
|
775 |
|
|
rstp => pb_rstp, --! 1 - сброс
|
776 |
|
|
clk => clk, --! тактовая частота ядра - 250 MHz
|
777 |
|
|
|
778 |
|
|
---- PB_DISP ----
|
779 |
|
|
reg_disp => reg_disp, --! запрос на доступ к регистрам из BAR1
|
780 |
|
|
reg_disp_back => reg_disp_back, --! ответ на запрос
|
781 |
|
|
|
782 |
|
|
---- EXT_FIFO ----
|
783 |
|
|
ext_fifo_disp => ext_fifo_disp, --! запрос на доступ от узла EXT_FIFO
|
784 |
|
|
ext_fifo_disp_back => ext_fifo_disp_back, --! ответ на запрос
|
785 |
|
|
|
786 |
|
|
---- BAR1 ----
|
787 |
|
|
aclk => aclk, --! тактовая частота локальной шины - 266 МГц
|
788 |
|
|
pb_master => pb_master, --! запрос
|
789 |
|
|
pb_slave => pb_slave --! ответ
|
790 |
|
|
|
791 |
|
|
);
|
792 |
|
|
|
793 |
|
|
|
794 |
|
|
|
795 |
|
|
fifo: block_pe_fifo_ext
|
796 |
|
|
port map(
|
797 |
|
|
|
798 |
|
|
---- Global ----
|
799 |
|
|
rstp => pb_rstp,
|
800 |
|
|
clk => clk,
|
801 |
|
|
aclk => aclk,
|
802 |
|
|
|
803 |
|
|
---- TX_ENGINE ----
|
804 |
|
|
tx_ext_fifo => tx_ext_fifo,
|
805 |
|
|
tx_ext_fifo_back => tx_ext_fifo_back,
|
806 |
|
|
|
807 |
|
|
---- RX_ENGINE ----
|
808 |
|
|
rx_ext_fifo => rx_ext_fifo,
|
809 |
|
|
|
810 |
|
|
---- REG ----
|
811 |
|
|
reg_ext_fifo => reg_ext_fifo,
|
812 |
|
|
reg_ext_fifo_back => reg_ext_fifo_back,
|
813 |
|
|
|
814 |
|
|
---- DISP ----
|
815 |
|
|
ext_fifo_disp => ext_fifo_disp,
|
816 |
|
|
ext_fifo_disp_back => ext_fifo_disp_back,
|
817 |
|
|
|
818 |
|
|
irq => irq, -- 1 - запрос прерывания
|
819 |
|
|
|
820 |
|
|
test => px
|
821 |
|
|
);
|
822 |
|
|
|
823 |
|
|
|
824 |
|
|
|
825 |
|
|
|
826 |
|
|
int: core64_interrupt
|
827 |
|
|
port map(
|
828 |
|
|
|
829 |
|
|
rstp => pb_rstp, -- 1 - сброс
|
830 |
|
|
clk => clk, -- Тактовая частота ядра 250 МГц
|
831 |
|
|
|
832 |
|
|
irq => irq, -- 1 - запрос прерывания
|
833 |
|
|
|
834 |
|
|
cfg_command10 => cfg_command(10), -- 1 - прерывания запрещены
|
835 |
|
|
cfg_interrupt => cfg_interrupt_n, -- 0 - изменение состояния прерывания
|
836 |
|
|
cfg_interrupt_assert => cfg_interrupt_assert_n, -- 0 - формирование прерывания, 1 - сниятие прерывания
|
837 |
|
|
cfg_interrupt_rdy => cfg_interrupt_rdy_n -- 0 - подтверждение изменения прерывания
|
838 |
|
|
|
839 |
|
|
);
|
840 |
|
|
|
841 |
|
|
--cfg_interrupt <= not cfg_interrupt_n;
|
842 |
|
|
--cfg_interrupt_assert <= not cfg_interrupt_assert_n;
|
843 |
|
|
--cfg_interrupt_rdy_n <= not cfg_interrupt_rdy;
|
844 |
|
|
|
845 |
|
|
cfg_interrupt <= '0';
|
846 |
|
|
cfg_interrupt_assert <= '0';
|
847 |
|
|
-- cfg_interrupt_n_c <= '1';
|
848 |
|
|
-- cfg_interrupt_assert_n_c <= '1';
|
849 |
|
|
|
850 |
|
|
end pcie_core64_m4;
|