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-------------------------------------------------------------------------------
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--
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-- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
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--
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-- This file contains confidential and proprietary information
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-- of Xilinx, Inc. and is protected under U.S. and
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-- international copyright and other intellectual property
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-- laws.
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--
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-- DISCLAIMER
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-- This disclaimer is not a license and does not grant any
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-- rights to the materials distributed herewith. Except as
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-- otherwise provided in a valid license issued to you by
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-- Xilinx, and to the maximum extent permitted by applicable
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-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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-- (2) Xilinx shall not be liable (whether in contract or tort,
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-- including negligence, or under any other theory of
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-- liability) for any loss or damage of any kind or nature
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-- related to, arising under or in connection with these
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-- materials, including for any direct, or any indirect,
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-- special, incidental, or consequential loss or damage
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-- (including loss of data, profits, goodwill, or any type of
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-- loss or damage suffered as a result of any action brought
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-- by a third party) even if such damage or loss was
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-- reasonably foreseeable or Xilinx had been advised of the
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-- possibility of the same.
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--
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-- CRITICAL APPLICATIONS
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-- Xilinx products are not designed or intended to be fail-
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-- safe, or for use in any application requiring fail-safe
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-- performance, such as life-support or safety devices or
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-- systems, Class III medical devices, nuclear facilities,
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-- applications related to the deployment of airbags, or any
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-- other applications that could lead to death, personal
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-- injury, or severe property or environmental damage
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-- (individually and collectively, "Critical
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-- Applications"). Customer assumes the sole risk and
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-- liability of any use of Xilinx products in Critical
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-- Applications, subject only to applicable laws and
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-- regulations governing limitations on product liability.
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--
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-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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-- PART OF THIS FILE AT ALL TIMES.
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--
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-------------------------------------------------------------------------------
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-- Project : Virtex-6 Integrated Block for PCI Express
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-- File : pci_exp_usrapp_rx_m2.vhd
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-- Version : 2.3
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--
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--------------------------------------------------------------------------------
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--
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-- Version : 2.3.1 (28.10.2011) dsmv
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-- Description: update TRN_RX_TIMEOUT value (for fix RD problem in simulation)
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--------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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package pci_exp_usrapp_rx_m2_pkg is
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component pci_exp_usrapp_rx_m2 is
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generic (
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--TRN_RX_TIMEOUT : INTEGER :=30000
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TRN_RX_TIMEOUT : INTEGER :=3000000
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);
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port (
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trn_rdst_rdy_n : out std_logic;
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trn_rnp_ok_n : out std_logic;
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trn_rd : in std_logic_vector ((64 - 1) downto 0 );
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trn_rrem_n : in std_logic_vector ((8 - 1) downto 0 );
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trn_rsof_n : in std_logic;
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trn_reof_n : in std_logic;
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trn_rsrc_rdy_n : in std_logic;
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trn_rsrc_dsc_n : in std_logic;
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trn_rerrfwd_n : in std_logic;
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trn_rbar_hit_n : in std_logic_vector ((7 - 1) downto 0 );
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trn_clk : in std_logic;
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trn_reset_n : in std_logic;
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trn_lnk_up_n : in std_logic;
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--sim_time : in TIME;
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rx_tx_read_data : out std_logic_vector(31 downto 0);
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rx_tx_read_data_valid : out std_logic;
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tx_rx_read_data_valid : in std_logic
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);
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end component;
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end package;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_textio.all;
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use ieee.numeric_std.all;
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library std;
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use std.textio.all;
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use work.root_memory_pkg.all;
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entity pci_exp_usrapp_rx_m2 is
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generic (
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TRN_RX_TIMEOUT : INTEGER :=30000
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);
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port (
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trn_rdst_rdy_n : out std_logic;
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trn_rnp_ok_n : out std_logic;
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trn_rd : in std_logic_vector ((64 - 1) downto 0 );
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trn_rrem_n : in std_logic_vector ((8 - 1) downto 0 );
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trn_rsof_n : in std_logic;
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trn_reof_n : in std_logic;
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trn_rsrc_rdy_n : in std_logic;
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trn_rsrc_dsc_n : in std_logic;
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trn_rerrfwd_n : in std_logic;
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trn_rbar_hit_n : in std_logic_vector ((7 - 1) downto 0 );
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trn_clk : in std_logic;
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trn_reset_n : in std_logic;
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trn_lnk_up_n : in std_logic;
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--sim_time : in TIME;
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rx_tx_read_data : out std_logic_vector(31 downto 0);
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rx_tx_read_data_valid : out std_logic;
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tx_rx_read_data_valid : in std_logic
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);
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end pci_exp_usrapp_rx_m2;
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architecture rtl of pci_exp_usrapp_rx_m2 is
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type BYTE_ARRAY is array (999 downto 0) of std_logic_vector(7 downto 0);
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constant TRN_RX_RESET : std_logic_vector(4 downto 0) := "00001";
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constant TRN_RX_DOWN : std_logic_vector(4 downto 0) := "00010";
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constant TRN_RX_IDLE : std_logic_vector(4 downto 0) := "00100";
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constant TRN_RX_ACTIVE : std_logic_vector(4 downto 0) := "01000";
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constant TRN_RX_SRC_DSC : std_logic_vector(4 downto 0) := "10000";
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constant PCI_EXP_MEM_READ32 : std_logic_vector(6 downto 0) := "0000000";
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constant PCI_EXP_IO_READ : std_logic_vector(6 downto 0) := "0000010";
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constant PCI_EXP_CFG_READ0 : std_logic_vector(6 downto 0) := "0000100";
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constant PCI_EXP_COMPLETION_WO_DATA : std_logic_vector(6 downto 0) := "0001010";
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constant PCI_EXP_MEM_READ64 : std_logic_vector(6 downto 0) := "0100000";
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constant PCI_EXP_MSG_NODATA : std_logic_vector(6 downto 3) := "0110";
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constant PCI_EXP_MEM_WRITE32 : std_logic_vector(6 downto 0) := "1000000";
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constant PCI_EXP_IO_WRITE : std_logic_vector(6 downto 0) := "1000010";
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constant PCI_EXP_CFG_WRITE0 : std_logic_vector(6 downto 0) := "1000100";
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constant PCI_EXP_COMPLETION_DATA : std_logic_vector(6 downto 0) := "1001010";
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constant PCI_EXP_MEM_WRITE64 : std_logic_vector(6 downto 0) := "1100000";
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constant PCI_EXP_MSG_DATA : std_logic_vector(6 downto 3) := "1110";
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constant COMPLETER_ID_CFG : std_logic_vector(15 downto 0) := X"01A0";
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-- Global variables
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shared variable frame_store_rx : BYTE_ARRAY;
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shared variable frame_store_rx_idx : INTEGER;
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shared variable next_trn_rx_timeout : INTEGER;
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signal trn_rdst_rdy_n_c : std_logic;
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signal trn_rnp_ok_n_c : std_logic;
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signal read_data_valid_int : std_logic;
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signal read_data_valid_int_d : std_logic; -- added to prevent race condition
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signal trn_rx_state : std_logic_vector(4 downto 0);
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signal mem64r_request0 : std_logic;
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signal mem64r_request1 : std_logic;
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file RX_file : TEXT open write_mode is "rx.dat";
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--************************************************************
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-- Proc : writeNowToRx
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-- Inputs : Text String
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-- Outputs : None
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-- Description : Displays text string to Rx file pre-appended with
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-- current simulation time..
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-- *************************************************************/
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procedure writeNowToRx (
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text_string : in string
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) is
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variable L : line;
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begin
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write (L, String'("[ "));
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write (L, now);
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write (L, String'(" ] : "));
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write (L, text_string);
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writeline (rx_file, L);
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end writeNowToRx;
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--************************************************************
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-- Proc : writeNowToScreen
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-- Inputs : Text String
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-- Outputs : None
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-- Description : Displays current simulation time and text string to
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-- standard output.
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-- *************************************************************
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procedure writeNowToScreen (
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text_string : in string
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) is
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variable L : line;
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begin
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write (L, String'("[ "));
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write (L, now);
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write (L, String'(" ] : "));
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write (L, text_string);
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writeline (output, L);
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end writeNowToScreen;
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--************************************************************
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-- Proc : writeHexToRx
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-- Inputs : hex value with bit width that is multiple of 4
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-- Outputs : None
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-- Description : Displays nibble aligned hex value to Rx file
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--
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-- *************************************************************
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procedure writeHexToRx (
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text_string : in string;
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hexValue : in std_logic_vector
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) is
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variable L : line;
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begin
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write (L, text_string);
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hwrite(L, hexValue);
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writeline (rx_file, L);
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end writeHexToRx;
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--************************************************************
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-- Proc : PROC_READ_DATA
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-- Inputs : None
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-- Outputs : None
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-- Description : Consume clocks.
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-- *************************************************************/
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procedure PROC_READ_DATA (
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last : in INTEGER;
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trn_d : in std_logic_vector (63 downto 0);
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trn_rem : in std_logic_vector (7 downto 0)
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) is
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variable i : INTEGER;
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variable data_byte : std_logic_vector (7 downto 0);
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variable remain : INTEGER;
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variable hi_index : INTEGER;
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variable low_index : INTEGER;
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variable my_line : line;
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begin
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hi_index := 63;
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low_index := 56;
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if (last = 1) then
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if (trn_rem = X"0F") then
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remain := 4;
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else
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remain := 8;
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end if;
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else
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remain := 8;
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end if;
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for i in 0 to (remain - 1) loop
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data_byte := trn_d( hi_index downto low_index);
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hi_index := hi_index - 8;
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low_index := low_index - 8;
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frame_store_rx(frame_store_rx_idx) := data_byte;
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frame_store_rx_idx := frame_store_rx_idx + 1;
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end loop;
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end PROC_READ_DATA;
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--************************************************************
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-- Proc : PROC_DECIPHER_FRAME
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-- Inputs : None
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-- Outputs : fmt, tlp_type, traffic_class, td, ep, attr, length
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-- Description : Deciphers frame
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-- *************************************************************/
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procedure PROC_DECIPHER_FRAME (
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fmt : out std_logic_vector (1 downto 0);
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tlp_type : out std_logic_vector (4 downto 0);
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traffic_class : out std_logic_vector (2 downto 0);
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td : out std_logic;
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ep : out std_logic;
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attr : out std_logic_vector (1 downto 0);
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length : out std_logic_vector (9 downto 0)
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) is
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begin
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fmt := frame_store_rx(0)(6 downto 5);
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tlp_type := frame_store_rx(0)(4 downto 0);
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traffic_class := frame_store_rx(1)(6 downto 4);
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td := frame_store_rx(2)(7);
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ep := frame_store_rx(2)(6);
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attr := frame_store_rx(2)(5 downto 4);
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length(9 downto 8) := frame_store_rx(2)(1 downto 0);
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length(7 downto 0) := frame_store_rx(3);
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end PROC_DECIPHER_FRAME;
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-- ************************************************************
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|
|
-- Proc : PROC_3DW
|
365 |
|
|
-- Inputs : fmt, type, traffic_class, td, ep, attr, length,
|
366 |
|
|
-- payload,
|
367 |
|
|
-- Outputs : None
|
368 |
|
|
-- Description : Gets variables and prints frame
|
369 |
|
|
-- *************************************************************/
|
370 |
|
|
|
371 |
|
|
procedure PROC_3DW (
|
372 |
|
|
|
373 |
|
|
fmt : in std_logic_vector (1 downto 0);
|
374 |
|
|
tlp_type : in std_logic_vector (4 downto 0);
|
375 |
|
|
traffic_class : in std_logic_vector (2 downto 0);
|
376 |
|
|
td : in std_logic;
|
377 |
|
|
ep : in std_logic;
|
378 |
|
|
attr : in std_logic_vector (1 downto 0);
|
379 |
|
|
length : in std_logic_vector (9 downto 0);
|
380 |
|
|
payload : in INTEGER;
|
381 |
|
|
signal rx_tx_read_data : out std_logic_vector(31 downto 0);
|
382 |
|
|
signal read_data_valid_int : out std_logic
|
383 |
|
|
|
384 |
|
|
) is
|
385 |
|
|
|
386 |
|
|
variable requester_id : std_logic_vector (15 downto 0);
|
387 |
|
|
variable tag : std_logic_vector (7 downto 0);
|
388 |
|
|
variable byte_enables : std_logic_vector (7 downto 0);
|
389 |
|
|
variable address_low : std_logic_vector (31 downto 0);
|
390 |
|
|
variable completer_id : std_logic_vector (15 downto 0);
|
391 |
|
|
variable register_address : std_logic_vector (9 downto 0);
|
392 |
|
|
variable completion_status : std_logic_vector (2 downto 0);
|
393 |
|
|
variable i : INTEGER;
|
394 |
|
|
variable L : line;
|
395 |
|
|
variable fmt_type : std_logic_vector (6 downto 0);
|
396 |
|
|
|
397 |
|
|
begin
|
398 |
|
|
|
399 |
|
|
writeHexToRx (String'(" Traffic Class: 0x"), '0' & traffic_class);
|
400 |
|
|
write (L, String'(" TD: ")); write(L, td); writeline (rx_file, L);
|
401 |
|
|
write (L, String'(" EP: ")); write(L, ep); writeline (rx_file, L);
|
402 |
|
|
writeHexToRx (String'(" Attributes: 0x"), "00" & attr);
|
403 |
|
|
writeHexToRx (String'(" Length: 0x"), "00" & length);
|
404 |
|
|
|
405 |
|
|
|
406 |
|
|
fmt_type := fmt & tlp_type;
|
407 |
|
|
case (fmt_type) is
|
408 |
|
|
|
409 |
|
|
when PCI_EXP_CFG_READ0 | PCI_EXP_CFG_WRITE0 =>
|
410 |
|
|
|
411 |
|
|
requester_id := frame_store_rx(4) & frame_store_rx(5);
|
412 |
|
|
tag := frame_store_rx(6);
|
413 |
|
|
byte_enables := frame_store_rx(7);
|
414 |
|
|
completer_id := frame_store_rx(8) & frame_store_rx(9);
|
415 |
|
|
register_address(9 downto 8) := frame_store_rx(10)(1 downto 0);
|
416 |
|
|
register_address(7 downto 0) := frame_store_rx(11);
|
417 |
|
|
|
418 |
|
|
writeHexToRx ( String'(" Requester Id: 0x"), requester_id);
|
419 |
|
|
writeHexToRx ( String'(" Tag: 0x"), tag);
|
420 |
|
|
writeHexToRx ( String'(" Last and First Byte Enables: 0x"), byte_enables);
|
421 |
|
|
writeHexToRx ( String'(" Completer Id: 0x"), completer_id);
|
422 |
|
|
writeHexToRx (String'(" Register Address: 0x"), "00" & register_address);
|
423 |
|
|
|
424 |
|
|
if (payload = 1) then
|
425 |
|
|
|
426 |
|
|
write (L, String'("")); writeline(rx_file, L);
|
427 |
|
|
for i in 12 to (frame_store_rx_idx - 1) loop
|
428 |
|
|
writeHexToRx ( String'(" 0x"), frame_store_rx(i));
|
429 |
|
|
end loop;
|
430 |
|
|
|
431 |
|
|
end if;
|
432 |
|
|
write (L, String'("")); writeline(rx_file, L);
|
433 |
|
|
|
434 |
|
|
when PCI_EXP_COMPLETION_WO_DATA | PCI_EXP_COMPLETION_DATA=>
|
435 |
|
|
|
436 |
|
|
completer_id := frame_store_rx(4) & frame_store_rx(5);
|
437 |
|
|
completion_status(2 downto 0) := frame_store_rx(6)(7 downto 5);
|
438 |
|
|
requester_id := frame_store_rx(8) & frame_store_rx(9);
|
439 |
|
|
tag := frame_store_rx(10);
|
440 |
|
|
|
441 |
|
|
writeHexToRx ( String'(" Completer Id: 0x"), completer_id);
|
442 |
|
|
writeHexToRx ( String'(" Completion Status: 0x"), '0' & completion_status);
|
443 |
|
|
writeHexToRx ( String'(" Requester Id: 0x"), requester_id);
|
444 |
|
|
writeHexToRx ( String'(" Tag: 0x"), tag);
|
445 |
|
|
|
446 |
|
|
if (payload = 1) then
|
447 |
|
|
|
448 |
|
|
write (L, String'("")); writeline(rx_file, L);
|
449 |
|
|
for i in 12 to (frame_store_rx_idx - 1) loop
|
450 |
|
|
writeHexToRx ( String'(" 0x"), frame_store_rx(i));
|
451 |
|
|
end loop;
|
452 |
|
|
|
453 |
|
|
rx_tx_read_data <= frame_store_rx(15) & frame_store_rx(14) &
|
454 |
|
|
frame_store_rx(13) & frame_store_rx(12);
|
455 |
|
|
read_data_valid_int <= '1';
|
456 |
|
|
|
457 |
|
|
end if;
|
458 |
|
|
write (L, String'("")); writeline(rx_file, L);
|
459 |
|
|
|
460 |
|
|
when others =>
|
461 |
|
|
|
462 |
|
|
requester_id := frame_store_rx(4) & frame_store_rx(5);
|
463 |
|
|
tag := frame_store_rx(6);
|
464 |
|
|
byte_enables := frame_store_rx(7);
|
465 |
|
|
address_low(31 downto 24) := frame_store_rx(8);
|
466 |
|
|
address_low(23 downto 16) := frame_store_rx(9);
|
467 |
|
|
address_low(15 downto 8) := frame_store_rx(10);
|
468 |
|
|
address_low( 7 downto 0) := frame_store_rx(11);
|
469 |
|
|
|
470 |
|
|
writeHexToRx ( String'(" Requester Id: 0x"), requester_id);
|
471 |
|
|
writeHexToRx ( String'(" Tag: 0x"), tag);
|
472 |
|
|
writeHexToRx ( String'(" Last and First Byte Enables: 0x"), byte_enables);
|
473 |
|
|
writeHexToRx ( String'(" Address Low: 0x"), address_low);
|
474 |
|
|
|
475 |
|
|
if (payload = 1) then
|
476 |
|
|
|
477 |
|
|
write (L, String'("")); writeline(rx_file, L);
|
478 |
|
|
for i in 12 to (frame_store_rx_idx - 1) loop
|
479 |
|
|
writeHexToRx ( String'(" 0x"), frame_store_rx(i));
|
480 |
|
|
end loop;
|
481 |
|
|
|
482 |
|
|
end if;
|
483 |
|
|
write (L, String'("")); writeline(rx_file, L);
|
484 |
|
|
|
485 |
|
|
end case;
|
486 |
|
|
|
487 |
|
|
end PROC_3DW;
|
488 |
|
|
|
489 |
|
|
|
490 |
|
|
-- ************************************************************
|
491 |
|
|
-- Proc : PROC_4DW
|
492 |
|
|
-- Inputs : fmt, type, traffic_class, td, ep, attr, length
|
493 |
|
|
-- payload
|
494 |
|
|
-- Outputs : None
|
495 |
|
|
-- Description : Gets variables and prints frame
|
496 |
|
|
-- *************************************************************/
|
497 |
|
|
|
498 |
|
|
procedure PROC_4DW (
|
499 |
|
|
|
500 |
|
|
fmt : in std_logic_vector (1 downto 0);
|
501 |
|
|
tlp_type : in std_logic_vector (4 downto 0);
|
502 |
|
|
traffic_class : in std_logic_vector (2 downto 0);
|
503 |
|
|
td : in std_logic;
|
504 |
|
|
ep : in std_logic;
|
505 |
|
|
attr : in std_logic_vector (1 downto 0);
|
506 |
|
|
length : in std_logic_vector (9 downto 0);
|
507 |
|
|
payload : in INTEGER
|
508 |
|
|
|
509 |
|
|
) is
|
510 |
|
|
variable requester_id : std_logic_vector (15 downto 0);
|
511 |
|
|
variable tag : std_logic_vector (7 downto 0);
|
512 |
|
|
variable byte_enables : std_logic_vector (7 downto 0);
|
513 |
|
|
variable message_code : std_logic_vector (7 downto 0);
|
514 |
|
|
variable address_high : std_logic_vector (31 downto 0);
|
515 |
|
|
variable address_low : std_logic_vector (31 downto 0);
|
516 |
|
|
variable msg_type : std_logic_vector (2 downto 0);
|
517 |
|
|
variable i : INTEGER;
|
518 |
|
|
variable L : line;
|
519 |
|
|
variable fmt_type : std_logic_vector (6 downto 0);
|
520 |
|
|
|
521 |
|
|
begin
|
522 |
|
|
|
523 |
|
|
|
524 |
|
|
writeHexToRx (String'(" Traffic Class: 0x"), '0' & traffic_class);
|
525 |
|
|
write (L, String'(" TD: ")); write(L, td); writeline (rx_file, L);
|
526 |
|
|
write (L, String'(" EP: ")); write(L, ep); writeline (rx_file, L);
|
527 |
|
|
writeHexToRx (String'(" Attributes: 0x"), "00" & attr);
|
528 |
|
|
writeHexToRx (String'(" Length: 0x"), "00" & length);
|
529 |
|
|
|
530 |
|
|
requester_id := frame_store_rx(4) & frame_store_rx(5);
|
531 |
|
|
tag := frame_store_rx(6);
|
532 |
|
|
byte_enables := frame_store_rx(7);
|
533 |
|
|
message_code := frame_store_rx(7);
|
534 |
|
|
address_high(31 downto 24) := frame_store_rx(8);
|
535 |
|
|
address_high(23 downto 16) := frame_store_rx(9) ;
|
536 |
|
|
address_high(15 downto 8) := frame_store_rx(10);
|
537 |
|
|
address_high(7 downto 0) := frame_store_rx(11);
|
538 |
|
|
address_low(31 downto 24) := frame_store_rx(12);
|
539 |
|
|
address_low(23 downto 16) := frame_store_rx(13);
|
540 |
|
|
address_low(15 downto 8) := frame_store_rx(14) ;
|
541 |
|
|
address_low(7 downto 0) := frame_store_rx(15);
|
542 |
|
|
|
543 |
|
|
-- mem64r_adr_low := address_low;
|
544 |
|
|
-- mem64r_adr_high := address_high;
|
545 |
|
|
-- mem64r_tag := tag;
|
546 |
|
|
-- mem64r_size := conv_integer( length );
|
547 |
|
|
-- mem64r_requester_id := requester_id;
|
548 |
|
|
|
549 |
|
|
|
550 |
|
|
writeHexToRx ( String'(" Requester Id: 0x"), requester_id);
|
551 |
|
|
writeHexToRx ( String'(" Tag: 0x"), tag);
|
552 |
|
|
|
553 |
|
|
fmt_type := fmt & tlp_type;
|
554 |
|
|
|
555 |
|
|
if ((fmt_type(6 downto 3) = PCI_EXP_MSG_NODATA)
|
556 |
|
|
or (fmt_type(6 downto 3) = PCI_EXP_MSG_DATA)) then
|
557 |
|
|
|
558 |
|
|
msg_type := tlp_type(2 downto 0);
|
559 |
|
|
writeHexToRx ( String'(" Message Type: 0x"), '0' & msg_type);
|
560 |
|
|
writeHexToRx ( String'(" Message Code: 0x"), message_code);
|
561 |
|
|
writeHexToRx ( String'(" Address High: 0x"), address_high);
|
562 |
|
|
writeHexToRx ( String'(" Address Low: 0x"), address_low);
|
563 |
|
|
|
564 |
|
|
if (payload = 1) then
|
565 |
|
|
|
566 |
|
|
write (L, String'("")); writeline(rx_file, L);
|
567 |
|
|
for i in 16 to (frame_store_rx_idx - 1) loop
|
568 |
|
|
|
569 |
|
|
writeHexToRx ( String'(" 0x"), frame_store_rx(i));
|
570 |
|
|
|
571 |
|
|
end loop;
|
572 |
|
|
|
573 |
|
|
end if;
|
574 |
|
|
write (L, String'("")); writeline(rx_file, L);
|
575 |
|
|
|
576 |
|
|
else
|
577 |
|
|
|
578 |
|
|
case (fmt_type) is
|
579 |
|
|
|
580 |
|
|
when PCI_EXP_MEM_READ64 | PCI_EXP_MEM_WRITE64 =>
|
581 |
|
|
|
582 |
|
|
writeHexToRx ( String'(" Last and First Byte Enables: 0x"), byte_enables);
|
583 |
|
|
writeHexToRx ( String'(" Address High: 0x"), address_high);
|
584 |
|
|
writeHexToRx ( String'(" Address Low: 0x"), address_low);
|
585 |
|
|
|
586 |
|
|
if (payload = 1) then
|
587 |
|
|
|
588 |
|
|
write (L, String'("")); writeline(rx_file, L);
|
589 |
|
|
for i in 16 to (frame_store_rx_idx - 1) loop
|
590 |
|
|
|
591 |
|
|
writeHexToRx ( String'(" 0x"), frame_store_rx(i));
|
592 |
|
|
|
593 |
|
|
end loop;
|
594 |
|
|
|
595 |
|
|
end if;
|
596 |
|
|
|
597 |
|
|
write (L, String'("")); writeline(rx_file, L);
|
598 |
|
|
|
599 |
|
|
when others =>
|
600 |
|
|
|
601 |
|
|
write (L, String'(": Not a vaild frame")); writeline (rx_file, L); write (L, String'("")); writeline(rx_file, L);
|
602 |
|
|
assert (false)
|
603 |
|
|
report "Simulation Ended"
|
604 |
|
|
severity failure;
|
605 |
|
|
|
606 |
|
|
end case;
|
607 |
|
|
|
608 |
|
|
end if;
|
609 |
|
|
|
610 |
|
|
end PROC_4DW;
|
611 |
|
|
|
612 |
|
|
|
613 |
|
|
--************************************************************
|
614 |
|
|
-- Proc : PROC_PARSE_FRAME
|
615 |
|
|
-- Inputs : None
|
616 |
|
|
-- Outputs : None
|
617 |
|
|
-- Description : Parse frame data
|
618 |
|
|
-- *************************************************************/
|
619 |
|
|
|
620 |
|
|
procedure PROC_PARSE_FRAME (
|
621 |
|
|
|
622 |
|
|
signal rx_tx_read_data : out std_logic_vector(31 downto 0);
|
623 |
|
|
signal read_data_valid_int : out std_logic;
|
624 |
|
|
signal mem_request : out std_logic
|
625 |
|
|
|
626 |
|
|
) is
|
627 |
|
|
|
628 |
|
|
variable fmt : std_logic_vector (1 downto 0);
|
629 |
|
|
variable tlp_type : std_logic_vector (4 downto 0);
|
630 |
|
|
variable traffic_class : std_logic_vector (2 downto 0);
|
631 |
|
|
variable td : std_logic;
|
632 |
|
|
variable ep : std_logic;
|
633 |
|
|
variable attr : std_logic_vector (1 downto 0);
|
634 |
|
|
variable length : std_logic_vector (9 downto 0);
|
635 |
|
|
variable payload : INTEGER;
|
636 |
|
|
-- variable reqester_id : std_logic_vector(15 downto 0);
|
637 |
|
|
variable completer_id : std_logic_vector(15 downto 0);
|
638 |
|
|
variable tag : std_logic_vector(7 downto 0);
|
639 |
|
|
variable byte_enables : std_logic_vector(7 downto 0);
|
640 |
|
|
variable message_code : std_logic_vector(7 downto 0);
|
641 |
|
|
variable address_low : std_logic_vector(31 downto 0);
|
642 |
|
|
variable address_high : std_logic_vector(31 downto 0);
|
643 |
|
|
variable register_address : std_logic_vector (9 downto 0);
|
644 |
|
|
variable completion_status : std_logic_vector (2 downto 0);
|
645 |
|
|
variable log_file_ptr : std_logic_vector (31 downto 0);
|
646 |
|
|
variable frame_store_idx : INTEGER;
|
647 |
|
|
variable fmt_type : std_logic_vector (6 downto 0);
|
648 |
|
|
variable L : line;
|
649 |
|
|
|
650 |
|
|
variable requester_id : std_logic_vector (15 downto 0);
|
651 |
|
|
|
652 |
|
|
variable mem64r : type_memory_request_item;
|
653 |
|
|
|
654 |
|
|
variable frame_wr_index : integer;
|
655 |
|
|
variable frame_wr_size : integer;
|
656 |
|
|
variable frame_wr_data : std_logic_vector( 31 downto 0 );
|
657 |
|
|
|
658 |
|
|
begin
|
659 |
|
|
|
660 |
|
|
writeNowToScreen ( String'("PROC_PARSE_FRAME on Receive"));
|
661 |
|
|
|
662 |
|
|
PROC_DECIPHER_FRAME (fmt, tlp_type, traffic_class, td, ep, attr, length);
|
663 |
|
|
|
664 |
|
|
-- decode the packets received based on fmt and type
|
665 |
|
|
fmt_type := fmt & tlp_type;
|
666 |
|
|
|
667 |
|
|
if (fmt_type(6 downto 3) = PCI_EXP_MSG_NODATA) then
|
668 |
|
|
|
669 |
|
|
writeNowToRx("Message With No Data Frame");
|
670 |
|
|
payload := 0;
|
671 |
|
|
PROC_4DW(fmt, tlp_type, traffic_class, td, ep, attr, length, payload);
|
672 |
|
|
|
673 |
|
|
elsif (fmt_type(6 downto 3) = PCI_EXP_MSG_DATA) then
|
674 |
|
|
|
675 |
|
|
writeNowToRx("Message With Data Frame");
|
676 |
|
|
payload := 1;
|
677 |
|
|
PROC_4DW(fmt, tlp_type, traffic_class, td, ep, attr, length, payload);
|
678 |
|
|
|
679 |
|
|
else
|
680 |
|
|
|
681 |
|
|
case (fmt_type) is
|
682 |
|
|
|
683 |
|
|
when PCI_EXP_MEM_READ32 =>
|
684 |
|
|
|
685 |
|
|
writeNowToRx("Memory Read-32 Frame");
|
686 |
|
|
payload := 0;
|
687 |
|
|
PROC_3DW(fmt, tlp_type, traffic_class, td, ep, attr, length, payload, rx_tx_read_data, read_data_valid_int );
|
688 |
|
|
|
689 |
|
|
|
690 |
|
|
address_high(31 downto 24) := x"00";
|
691 |
|
|
address_high(23 downto 16) := x"00";
|
692 |
|
|
address_high(15 downto 8) := x"00";
|
693 |
|
|
address_high(7 downto 0) := x"00";
|
694 |
|
|
|
695 |
|
|
address_low(31 downto 24) := frame_store_rx(8);
|
696 |
|
|
address_low(23 downto 16) := frame_store_rx(9);
|
697 |
|
|
address_low(15 downto 8) := frame_store_rx(10) ;
|
698 |
|
|
address_low(7 downto 0) := frame_store_rx(11);
|
699 |
|
|
|
700 |
|
|
requester_id := frame_store_rx(4) & frame_store_rx(5);
|
701 |
|
|
tag := frame_store_rx(6);
|
702 |
|
|
|
703 |
|
|
mem64r.adr_low := address_low;
|
704 |
|
|
mem64r.adr_high := address_high;
|
705 |
|
|
mem64r.tag := tag;
|
706 |
|
|
mem64r.size := conv_integer( length );
|
707 |
|
|
mem64r.requester_id := requester_id;
|
708 |
|
|
|
709 |
|
|
memory_request_write( mem64r );
|
710 |
|
|
|
711 |
|
|
mem_request <= '1', '0' after 1 ns;
|
712 |
|
|
|
713 |
|
|
when PCI_EXP_IO_READ =>
|
714 |
|
|
|
715 |
|
|
writeNowToRx("IO Read Frame");
|
716 |
|
|
payload := 0;
|
717 |
|
|
PROC_3DW(fmt, tlp_type, traffic_class, td, ep, attr, length, payload, rx_tx_read_data, read_data_valid_int );
|
718 |
|
|
|
719 |
|
|
when PCI_EXP_CFG_READ0 =>
|
720 |
|
|
|
721 |
|
|
writeNowToRx("Config Read Type 0 Frame");
|
722 |
|
|
payload := 0;
|
723 |
|
|
PROC_3DW(fmt, tlp_type, traffic_class, td, ep, attr, length, payload, rx_tx_read_data, read_data_valid_int );
|
724 |
|
|
|
725 |
|
|
when PCI_EXP_COMPLETION_WO_DATA =>
|
726 |
|
|
|
727 |
|
|
writeNowToRx("Completion Without Data Frame");
|
728 |
|
|
payload := 0;
|
729 |
|
|
PROC_3DW(fmt, tlp_type, traffic_class, td, ep, attr, length, payload, rx_tx_read_data, read_data_valid_int );
|
730 |
|
|
|
731 |
|
|
when PCI_EXP_MEM_READ64 =>
|
732 |
|
|
|
733 |
|
|
writeNowToRx("Memory Read-64 Frame");
|
734 |
|
|
payload := 0;
|
735 |
|
|
PROC_4DW(fmt, tlp_type, traffic_class, td, ep, attr, length, payload); --, rx_tx_read_data, rx_tx_read_data_valid );
|
736 |
|
|
|
737 |
|
|
writeNowToRx("Memory Read-64 wait completion");
|
738 |
|
|
--mem64r_request <= 10;
|
739 |
|
|
|
740 |
|
|
address_high(31 downto 24) := frame_store_rx(8);
|
741 |
|
|
address_high(23 downto 16) := frame_store_rx(9) ;
|
742 |
|
|
address_high(15 downto 8) := frame_store_rx(10);
|
743 |
|
|
address_high(7 downto 0) := frame_store_rx(11);
|
744 |
|
|
address_low(31 downto 24) := frame_store_rx(12);
|
745 |
|
|
address_low(23 downto 16) := frame_store_rx(13);
|
746 |
|
|
address_low(15 downto 8) := frame_store_rx(14) ;
|
747 |
|
|
address_low(7 downto 0) := frame_store_rx(15);
|
748 |
|
|
|
749 |
|
|
requester_id := frame_store_rx(4) & frame_store_rx(5);
|
750 |
|
|
tag := frame_store_rx(6);
|
751 |
|
|
|
752 |
|
|
mem64r.adr_low := address_low;
|
753 |
|
|
mem64r.adr_high := address_high;
|
754 |
|
|
mem64r.tag := tag;
|
755 |
|
|
mem64r.size := conv_integer( length );
|
756 |
|
|
mem64r.requester_id := requester_id;
|
757 |
|
|
|
758 |
|
|
memory_request_write( mem64r );
|
759 |
|
|
|
760 |
|
|
mem_request <= '1', '0' after 1 ns;
|
761 |
|
|
-- loop
|
762 |
|
|
-- if( mem64r_request = 0 ) then
|
763 |
|
|
-- exit;
|
764 |
|
|
-- end if;
|
765 |
|
|
-- wait for 200 ns;
|
766 |
|
|
-- end loop;
|
767 |
|
|
|
768 |
|
|
when PCI_EXP_MEM_WRITE32 =>
|
769 |
|
|
|
770 |
|
|
writeNowToRx("Memory Write-32 Frame");
|
771 |
|
|
payload := 1;
|
772 |
|
|
PROC_3DW(fmt, tlp_type, traffic_class, td, ep, attr, length, payload, rx_tx_read_data, read_data_valid_int );
|
773 |
|
|
|
774 |
|
|
|
775 |
|
|
address_high(31 downto 24) := x"00";
|
776 |
|
|
address_high(23 downto 16) := x"00";
|
777 |
|
|
address_high(15 downto 8) := x"00";
|
778 |
|
|
address_high(7 downto 0) := x"00";
|
779 |
|
|
|
780 |
|
|
address_low(31 downto 24) := frame_store_rx(8);
|
781 |
|
|
address_low(23 downto 16) := frame_store_rx(9);
|
782 |
|
|
address_low(15 downto 8) := frame_store_rx(10) ;
|
783 |
|
|
address_low(7 downto 0) := frame_store_rx(11);
|
784 |
|
|
|
785 |
|
|
|
786 |
|
|
frame_wr_size:=(frame_store_rx_idx-16)/4;
|
787 |
|
|
for ii in 0 to frame_wr_size-1 loop
|
788 |
|
|
frame_wr_data( 7 downto 0 ) := frame_store_rx( 12+ii*4 );
|
789 |
|
|
frame_wr_data( 15 downto 8 ) := frame_store_rx( 12+ii*4+1 );
|
790 |
|
|
frame_wr_data( 23 downto 16 ) := frame_store_rx( 12+ii*4+2 );
|
791 |
|
|
frame_wr_data( 31 downto 24 ) := frame_store_rx( 12+ii*4+3 );
|
792 |
|
|
|
793 |
|
|
memory_write( address_high, address_low+ii*4, frame_wr_data );
|
794 |
|
|
|
795 |
|
|
end loop;
|
796 |
|
|
|
797 |
|
|
when PCI_EXP_IO_WRITE =>
|
798 |
|
|
|
799 |
|
|
writeNowToRx("IO Write Frame");
|
800 |
|
|
payload := 1;
|
801 |
|
|
PROC_3DW(fmt, tlp_type, traffic_class, td, ep, attr, length, payload, rx_tx_read_data, read_data_valid_int );
|
802 |
|
|
|
803 |
|
|
when PCI_EXP_CFG_WRITE0 =>
|
804 |
|
|
|
805 |
|
|
writeNowToRx("Config Write Type 0 Frame");
|
806 |
|
|
payload := 1;
|
807 |
|
|
PROC_3DW(fmt, tlp_type, traffic_class, td, ep, attr, length, payload, rx_tx_read_data, read_data_valid_int );
|
808 |
|
|
|
809 |
|
|
when PCI_EXP_COMPLETION_DATA =>
|
810 |
|
|
|
811 |
|
|
writeNowToRx("Completion With Data Frame");
|
812 |
|
|
payload := 1;
|
813 |
|
|
PROC_3DW(fmt, tlp_type, traffic_class, td, ep, attr, length, payload, rx_tx_read_data, read_data_valid_int );
|
814 |
|
|
|
815 |
|
|
when PCI_EXP_MEM_WRITE64 =>
|
816 |
|
|
|
817 |
|
|
writeNowToRx("Memory Write-64 Frame");
|
818 |
|
|
payload := 1;
|
819 |
|
|
PROC_4DW(fmt, tlp_type, traffic_class, td, ep, attr, length, payload);
|
820 |
|
|
|
821 |
|
|
address_high(31 downto 24) := frame_store_rx(8);
|
822 |
|
|
address_high(23 downto 16) := frame_store_rx(9) ;
|
823 |
|
|
address_high(15 downto 8) := frame_store_rx(10);
|
824 |
|
|
address_high(7 downto 0) := frame_store_rx(11);
|
825 |
|
|
address_low(31 downto 24) := frame_store_rx(12);
|
826 |
|
|
address_low(23 downto 16) := frame_store_rx(13);
|
827 |
|
|
address_low(15 downto 8) := frame_store_rx(14) ;
|
828 |
|
|
address_low(7 downto 0) := frame_store_rx(15);
|
829 |
|
|
|
830 |
|
|
|
831 |
|
|
frame_wr_size:=(frame_store_rx_idx-16)/4;
|
832 |
|
|
for ii in 0 to frame_wr_size-1 loop
|
833 |
|
|
frame_wr_data( 7 downto 0 ) := frame_store_rx( 16+ii*4 );
|
834 |
|
|
frame_wr_data( 15 downto 8 ) := frame_store_rx( 16+ii*4+1 );
|
835 |
|
|
frame_wr_data( 23 downto 16 ) := frame_store_rx( 16+ii*4+2 );
|
836 |
|
|
frame_wr_data( 31 downto 24 ) := frame_store_rx( 16+ii*4+3 );
|
837 |
|
|
|
838 |
|
|
memory_write( address_high, address_low+ii*4, frame_wr_data );
|
839 |
|
|
|
840 |
|
|
end loop;
|
841 |
|
|
|
842 |
|
|
when others =>
|
843 |
|
|
|
844 |
|
|
|
845 |
|
|
writeNowToRx("Not a vaild frame. fmt_type = ");
|
846 |
|
|
write (L, fmt_type);
|
847 |
|
|
writeline (rx_file, L);
|
848 |
|
|
assert (false)
|
849 |
|
|
report "Simulation Ended"
|
850 |
|
|
severity failure;
|
851 |
|
|
|
852 |
|
|
end case;
|
853 |
|
|
|
854 |
|
|
end if;
|
855 |
|
|
|
856 |
|
|
frame_store_rx_idx := 0; -- reset frame pointer
|
857 |
|
|
|
858 |
|
|
end PROC_PARSE_FRAME;
|
859 |
|
|
|
860 |
|
|
|
861 |
|
|
begin
|
862 |
|
|
|
863 |
|
|
trn_rdst_rdy_n <= trn_rdst_rdy_n_c;
|
864 |
|
|
trn_rnp_ok_n <= '0';
|
865 |
|
|
trn_rdst_rdy_n_c <= '0';
|
866 |
|
|
|
867 |
|
|
-- Transaction Receive User Interface State Machine
|
868 |
|
|
|
869 |
|
|
process (trn_clk, trn_reset_n)
|
870 |
|
|
begin
|
871 |
|
|
|
872 |
|
|
if (trn_reset_n = '0' ) then
|
873 |
|
|
|
874 |
|
|
trn_rx_state <= TRN_RX_RESET;
|
875 |
|
|
frame_store_rx_idx := 0;
|
876 |
|
|
rx_tx_read_data <= X"FFFFFFFF";
|
877 |
|
|
read_data_valid_int <= '0';
|
878 |
|
|
|
879 |
|
|
else
|
880 |
|
|
|
881 |
|
|
if (trn_clk'event and trn_clk = '1') then
|
882 |
|
|
|
883 |
|
|
case (trn_rx_state) is
|
884 |
|
|
|
885 |
|
|
when TRN_RX_RESET =>
|
886 |
|
|
|
887 |
|
|
if (trn_reset_n = '0') then
|
888 |
|
|
|
889 |
|
|
trn_rx_state <= TRN_RX_RESET;
|
890 |
|
|
|
891 |
|
|
else
|
892 |
|
|
|
893 |
|
|
trn_rx_state <= TRN_RX_DOWN;
|
894 |
|
|
|
895 |
|
|
end if;
|
896 |
|
|
|
897 |
|
|
when TRN_RX_DOWN =>
|
898 |
|
|
|
899 |
|
|
if (trn_lnk_up_n = '1') then
|
900 |
|
|
|
901 |
|
|
trn_rx_state <= TRN_RX_DOWN;
|
902 |
|
|
|
903 |
|
|
else
|
904 |
|
|
|
905 |
|
|
trn_rx_state <= TRN_RX_IDLE;
|
906 |
|
|
|
907 |
|
|
end if;
|
908 |
|
|
|
909 |
|
|
when TRN_RX_IDLE =>
|
910 |
|
|
|
911 |
|
|
read_data_valid_int <= '0';
|
912 |
|
|
if (trn_reset_n = '0') then
|
913 |
|
|
|
914 |
|
|
trn_rx_state <= TRN_RX_RESET;
|
915 |
|
|
|
916 |
|
|
elsif (trn_lnk_up_n = '1') then
|
917 |
|
|
|
918 |
|
|
trn_rx_state <= TRN_RX_DOWN;
|
919 |
|
|
|
920 |
|
|
elsif ((trn_rsof_n = '0') and (trn_rsrc_rdy_n = '0') and (trn_rdst_rdy_n_c = '0')) then
|
921 |
|
|
|
922 |
|
|
PROC_READ_DATA (0, trn_rd, trn_rrem_n);
|
923 |
|
|
trn_rx_state <= TRN_RX_ACTIVE;
|
924 |
|
|
|
925 |
|
|
else
|
926 |
|
|
|
927 |
|
|
trn_rx_state <= TRN_RX_IDLE;
|
928 |
|
|
|
929 |
|
|
end if;
|
930 |
|
|
|
931 |
|
|
when TRN_RX_ACTIVE =>
|
932 |
|
|
|
933 |
|
|
if (trn_reset_n = '0') then
|
934 |
|
|
|
935 |
|
|
trn_rx_state <= TRN_RX_RESET;
|
936 |
|
|
|
937 |
|
|
elsif (trn_lnk_up_n = '1') then
|
938 |
|
|
|
939 |
|
|
trn_rx_state <= TRN_RX_DOWN;
|
940 |
|
|
|
941 |
|
|
elsif ((trn_rsrc_rdy_n = '0') and (trn_reof_n = '0') and (trn_rdst_rdy_n_c = '0')) then
|
942 |
|
|
|
943 |
|
|
|
944 |
|
|
-- if( mem64r_request/=0 ) then
|
945 |
|
|
-- wait until ;
|
946 |
|
|
-- end if;
|
947 |
|
|
|
948 |
|
|
PROC_READ_DATA (1, trn_rd, trn_rrem_n);
|
949 |
|
|
PROC_PARSE_FRAME (rx_tx_read_data , read_data_valid_int, mem64r_request );
|
950 |
|
|
trn_rx_state <= TRN_RX_IDLE;
|
951 |
|
|
|
952 |
|
|
|
953 |
|
|
elsif ((trn_rsrc_rdy_n = '0') and (trn_rdst_rdy_n_c = '0')) then
|
954 |
|
|
|
955 |
|
|
PROC_READ_DATA (0, trn_rd, trn_rrem_n);
|
956 |
|
|
trn_rx_state <= TRN_RX_ACTIVE;
|
957 |
|
|
|
958 |
|
|
elsif ((trn_rsrc_rdy_n = '0') and (trn_reof_n = '0') and (trn_rsrc_dsc_n = '0')) then
|
959 |
|
|
|
960 |
|
|
-- if( mem64r_request/=0 ) then
|
961 |
|
|
-- wait until mem64r_request=0;
|
962 |
|
|
-- end if;
|
963 |
|
|
|
964 |
|
|
PROC_READ_DATA (1, trn_rd, trn_rrem_n);
|
965 |
|
|
PROC_PARSE_FRAME (rx_tx_read_data , read_data_valid_int, mem64r_request );
|
966 |
|
|
trn_rx_state <= TRN_RX_SRC_DSC;
|
967 |
|
|
|
968 |
|
|
else
|
969 |
|
|
|
970 |
|
|
trn_rx_state <= TRN_RX_ACTIVE;
|
971 |
|
|
|
972 |
|
|
end if;
|
973 |
|
|
|
974 |
|
|
when TRN_RX_SRC_DSC =>
|
975 |
|
|
|
976 |
|
|
if (trn_reset_n = '0') then
|
977 |
|
|
|
978 |
|
|
trn_rx_state <= TRN_RX_RESET;
|
979 |
|
|
|
980 |
|
|
elsif (trn_lnk_up_n = '1') then
|
981 |
|
|
|
982 |
|
|
trn_rx_state <= TRN_RX_DOWN;
|
983 |
|
|
|
984 |
|
|
else
|
985 |
|
|
|
986 |
|
|
trn_rx_state <= TRN_RX_IDLE;
|
987 |
|
|
|
988 |
|
|
end if;
|
989 |
|
|
|
990 |
|
|
when others =>
|
991 |
|
|
|
992 |
|
|
trn_rx_state <= TRN_RX_RESET;
|
993 |
|
|
|
994 |
|
|
end case;
|
995 |
|
|
|
996 |
|
|
end if;
|
997 |
|
|
|
998 |
|
|
end if;
|
999 |
|
|
|
1000 |
|
|
end process;
|
1001 |
|
|
|
1002 |
|
|
|
1003 |
|
|
process (trn_clk, trn_reset_n)
|
1004 |
|
|
begin
|
1005 |
|
|
|
1006 |
|
|
if (trn_reset_n = '0' ) then
|
1007 |
|
|
|
1008 |
|
|
next_trn_rx_timeout := TRN_RX_TIMEOUT;
|
1009 |
|
|
|
1010 |
|
|
else
|
1011 |
|
|
|
1012 |
|
|
if (trn_clk'event and trn_clk = '1') then
|
1013 |
|
|
|
1014 |
|
|
if (next_trn_rx_timeout = 0) then
|
1015 |
|
|
|
1016 |
|
|
assert (false)
|
1017 |
|
|
report "RX Simulation Timeout."
|
1018 |
|
|
severity failure;
|
1019 |
|
|
|
1020 |
|
|
elsif (trn_lnk_up_n = '0') then
|
1021 |
|
|
|
1022 |
|
|
next_trn_rx_timeout := next_trn_rx_timeout - 1;
|
1023 |
|
|
|
1024 |
|
|
end if;
|
1025 |
|
|
|
1026 |
|
|
end if;
|
1027 |
|
|
|
1028 |
|
|
end if;
|
1029 |
|
|
|
1030 |
|
|
end process;
|
1031 |
|
|
|
1032 |
|
|
|
1033 |
|
|
-- Following is used to allow rx to tx communication to occur over two trn clocks - avoiding race conditions
|
1034 |
|
|
process (trn_clk)
|
1035 |
|
|
begin
|
1036 |
|
|
|
1037 |
|
|
if (trn_clk'event and trn_clk = '1') then
|
1038 |
|
|
|
1039 |
|
|
read_data_valid_int_d <= read_data_valid_int;
|
1040 |
|
|
end if;
|
1041 |
|
|
|
1042 |
|
|
end process;
|
1043 |
|
|
|
1044 |
|
|
|
1045 |
|
|
process (trn_clk)
|
1046 |
|
|
begin
|
1047 |
|
|
|
1048 |
|
|
if (trn_clk'event and trn_clk = '1') then
|
1049 |
|
|
|
1050 |
|
|
if (trn_lnk_up_n = '0') then
|
1051 |
|
|
|
1052 |
|
|
if ((tx_rx_read_data_valid = '1' ) and ((read_data_valid_int = '1') or (read_data_valid_int_d = '1'))) then
|
1053 |
|
|
|
1054 |
|
|
rx_tx_read_data_valid <= '1';
|
1055 |
|
|
|
1056 |
|
|
else
|
1057 |
|
|
|
1058 |
|
|
rx_tx_read_data_valid <= '0';
|
1059 |
|
|
|
1060 |
|
|
end if;
|
1061 |
|
|
|
1062 |
|
|
end if;
|
1063 |
|
|
|
1064 |
|
|
end if;
|
1065 |
|
|
|
1066 |
|
|
end process;
|
1067 |
|
|
|
1068 |
|
|
--mem64r_request <= mem64r_request0 or mem64r_request1;
|
1069 |
|
|
end; -- pci_exp_usrapp_rx_m2
|