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[/] [pcie_ds_dma/] [trunk/] [core/] [ds_dma64/] [pcie_src/] [pcie_sim/] [dsport/] [pci_exp_usrapp_tx_m2.vhd] - Blame information for rev 2

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-------------------------------------------------------------------------------
2
--
3
-- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
4
--
5
-- This file contains confidential and proprietary information
6
-- of Xilinx, Inc. and is protected under U.S. and
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-- international copyright and other intellectual property
8
-- laws.
9
--
10
-- DISCLAIMER
11
-- This disclaimer is not a license and does not grant any
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-- rights to the materials distributed herewith. Except as
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-- otherwise provided in a valid license issued to you by
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-- Xilinx, and to the maximum extent permitted by applicable
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-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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-- (2) Xilinx shall not be liable (whether in contract or tort,
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-- including negligence, or under any other theory of
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-- liability) for any loss or damage of any kind or nature
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-- related to, arising under or in connection with these
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-- materials, including for any direct, or any indirect,
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-- special, incidental, or consequential loss or damage
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-- (including loss of data, profits, goodwill, or any type of
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-- loss or damage suffered as a result of any action brought
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-- by a third party) even if such damage or loss was
29
-- reasonably foreseeable or Xilinx had been advised of the
30
-- possibility of the same.
31
--
32
-- CRITICAL APPLICATIONS
33
-- Xilinx products are not designed or intended to be fail-
34
-- safe, or for use in any application requiring fail-safe
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-- performance, such as life-support or safety devices or
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-- systems, Class III medical devices, nuclear facilities,
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-- applications related to the deployment of airbags, or any
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-- other applications that could lead to death, personal
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-- injury, or severe property or environmental damage
40
-- (individually and collectively, "Critical
41
-- Applications"). Customer assumes the sole risk and
42
-- liability of any use of Xilinx products in Critical
43
-- Applications, subject only to applicable laws and
44
-- regulations governing limitations on product liability.
45
--
46
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
47
-- PART OF THIS FILE AT ALL TIMES.
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--
49
-------------------------------------------------------------------------------
50
-- Project    : Virtex-6 Integrated Block for PCI Express
51
-- File       : pci_exp_usrapp_tx_m2.vhd
52
-- Version    : 2.3
53
-- Filename: pci_exp_usrapp_tx_m2.vhd
54
--
55
-- Description:  PCI Express dsport Tx interface.
56
--
57
------------------------------------------------------------------------------
58
 
59
 
60
library ieee;
61
use ieee.std_logic_1164.all;
62
 
63
library work;
64
use work.cmd_sim_pkg.all;
65
 
66
package pci_exp_usrapp_tx_m2_pkg is
67
 
68
component pci_exp_usrapp_tx_m2 is
69
 
70
port (
71
 
72
  trn_td                   : out std_logic_vector (63 downto 0 );
73
  trn_trem_n               : out std_logic_vector (7 downto 0 );
74
  trn_tsof_n               : out std_logic;
75
  trn_teof_n               : out std_logic;
76
  trn_terrfwd_n            : out std_logic;
77
  trn_tsrc_rdy_n           : out std_logic;
78
  trn_tsrc_dsc_n           : out std_logic;
79
  trn_clk                  : in std_logic;
80
  trn_reset_n              : in std_logic;
81
  trn_lnk_up_n             : in std_logic;
82
  trn_tdst_rdy_n           : in std_logic;
83
  trn_tdst_dsc_n           : in std_logic;
84
  trn_tbuf_av              : in std_logic_vector (5 downto 0);
85
  speed_change_done_n      : in std_logic;
86
  rx_tx_read_data          : in std_logic_vector(31 downto 0);
87
  rx_tx_read_data_valid    : in std_logic;
88
  tx_rx_read_data_valid    : out std_logic;
89
 
90
                ---- Test ----
91
  cmd                                      : in  bh_cmd;        -- êîìàíäà
92
  ret                                      : out bh_ret         -- îòâåò  
93
 
94
);
95
 
96
end component;
97
 
98
end package;
99
 
100
library ieee;
101
use ieee.std_logic_1164.all;
102
use ieee.std_logic_arith.all;
103
use ieee.std_logic_unsigned.all;
104
use ieee.std_logic_textio.all;
105
use ieee.numeric_std.all;
106
library std;
107
use std.textio.all;
108
 
109
library work;
110
use work.cmd_sim_pkg.all;
111
use work.test_interface.all;
112
use work.root_memory_pkg.all;
113
 
114
 
115
entity pci_exp_usrapp_tx_m2 is
116
 
117
port (
118
 
119
  trn_td                   : out std_logic_vector (63 downto 0 );
120
  trn_trem_n               : out std_logic_vector (7 downto 0 );
121
  trn_tsof_n               : out std_logic;
122
  trn_teof_n               : out std_logic;
123
  trn_terrfwd_n            : out std_logic;
124
  trn_tsrc_rdy_n           : out std_logic;
125
  trn_tsrc_dsc_n           : out std_logic;
126
  trn_clk                  : in std_logic;
127
  trn_reset_n              : in std_logic;
128
  trn_lnk_up_n             : in std_logic;
129
  trn_tdst_rdy_n           : in std_logic;
130
  trn_tdst_dsc_n           : in std_logic;
131
  trn_tbuf_av              : in std_logic_vector (5 downto 0);
132
  speed_change_done_n      : in std_logic;
133
  rx_tx_read_data          : in std_logic_vector(31 downto 0);
134
  rx_tx_read_data_valid    : in std_logic;
135
  tx_rx_read_data_valid    : out std_logic;
136
 
137
                ---- Test ----
138
  cmd                                      : in  bh_cmd;        -- êîìàíäà
139
  ret                                      : out bh_ret         -- îòâåò  
140
 
141
);
142
 
143
end pci_exp_usrapp_tx_m2;
144
 
145
architecture rtl of pci_exp_usrapp_tx_m2 is
146
 
147
 
148
 
149
 
150
begin
151
 
152
 
153
 
154
trn_td <= trn_td_c;
155
trn_trem_n <= trn_trem_n_c;
156
 
157
pr_main: process
158
 
159
variable vret: bh_ret:=(0, (others=>(others=>'0')) );
160
 
161
variable        byte_count              : std_logic_vector( 11 downto 0 );
162
variable        adr                             : integer;
163
variable        data                    : std_logic_vector( 31 downto 0 );
164
 
165
variable        mem64r                  : type_memory_request_item;
166
variable        mem64r_ready    : integer;
167
variable        size                    : integer;
168
variable        completion_cnt  : integer;
169
variable        completion_size : integer;
170
variable        completion_adr  : std_logic_vector( 6 downto 0 );
171
variable        index                   : integer;
172
 
173
variable        flag_pass               : integer:=0;
174
 
175
begin
176
 
177
      pio_check_design := true; -- By default check to make sure that the core has been configured
178
                                                -- appropriately for the PIO Design (see user guide for details)
179
      NUMBER_OF_IO_BARS := 0;
180
      NUMBER_OF_MEM32_BARS := 0;
181
      NUMBER_OF_MEM64_BARS :=0;
182
 
183
      frame_store_tx_idx := 0;
184
      success := true;
185
 
186
      trn_tsof_n <= '1';
187
      trn_teof_n <= '1';
188
      trn_terrfwd_n <= '1';
189
      trn_tsrc_rdy_n <= '1';
190
      trn_tsrc_dsc_n <= '1';
191
      trn_td_c <= (others => '0');
192
      tx_rx_read_data_valid <= '0';
193
 
194
 
195
        wait for 1 us;
196
 
197
      writeNowToScreen(String'("Init start"));
198
 
199
      PROC_SYSTEM_INITIALIZATION(trn_reset_n, trn_lnk_up_n, speed_change_done_n);
200
 
201
      PROC_BAR_INIT (tx_rx_read_data_valid, rx_tx_read_data_valid, rx_tx_read_data, trn_td_c,
202
        trn_tsof_n, trn_teof_n, trn_trem_n_c, trn_tsrc_rdy_n, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
203
 
204
      PROC_TX_CLK_EAT(300, trn_clk);
205
 
206
          writeNowToScreen(String'("BUS Master Enable "));
207
 
208
      PROC_READ_CFG_DW(conv_std_logic_vector(1, 10), cfg_rdwr_int);
209
      PROC_WRITE_CFG_DW(conv_std_logic_vector(1, 10), x"00000007", "1110", cfg_rdwr_int);
210
      PROC_READ_CFG_DW(conv_std_logic_vector(1, 10), cfg_rdwr_int);
211
 
212
          wait for 5 us;
213
 
214
 
215
      writeNowToScreen(String'("Init complete"));
216
 
217
          loop
218
 
219
                wait for 10 ns;
220
 
221
--              wait until cmd'event or mem64r_request'event;
222
--              loop
223
--                      if( cmd'event and cmd.cmd/=0 ) then
224
--                              exit;
225
--                      end if;
226
 
227
                        memory_request_read( mem64r_ready, mem64r );
228
 
229
                        if( mem64r_ready=1 ) then
230
 
231
                                adr:=conv_integer( mem64r.adr_low( 31 downto 0 ) );
232
                                size:=mem64r.size;
233
 
234
                                -- îïðåäåëåíèå ÷èñëà îòâåòîâ 
235
                                completion_cnt := size/memory_request_completion_size;
236
 
237
                                completion_adr:=(others=>'0');
238
 
239
                                flag_pass:=0;
240
 
241
                                for cpl_ii in 0 to completion_cnt-1 loop
242
                                        if( size>memory_request_completion_size ) then
243
                                                completion_size:=memory_request_completion_size;
244
                                        else
245
                                                completion_size:=size;
246
                                        end if;
247
 
248
                                        if( adr>=16#100000# and adr<=16#10FFFF# ) then
249
                                                index:=adr-16#100000#;
250
                                                index:=index/4;
251
                                                for ii in 0 to completion_size loop
252
                                                        data:=conv_std_logic_vector( root_mem_0x10(index+ii), 32 );
253
                                                        DATA_STORE(ii*4+0)       := data( 7 downto 0 );
254
                                                        DATA_STORE(ii*4+1)      := data( 15 downto 8 );
255
                                                        DATA_STORE(ii*4+2)      := data( 23 downto 16 );
256
                                                        DATA_STORE(ii*4+3)      := data( 31 downto 24 );
257
                                                end loop;
258
 
259
--                                              if( now>200 us and now<260 us and adr=16#00100080# ) then
260
--                                                      flag_pass:=1;
261
--                                              end if;
262
 
263
 
264
                                        elsif( adr>=16#800000# and adr<=16#80FFFF# ) then
265
                                                index:=adr-16#800000#;
266
                                                index:=index/4;
267
                                                for ii in 0 to completion_size loop
268
                                                        data:=conv_std_logic_vector( root_mem_0x80(index+ii), 32 );
269
                                                        DATA_STORE(ii*4+0)       := data( 7 downto 0 );
270
                                                        DATA_STORE(ii*4+1)      := data( 15 downto 8 );
271
                                                        DATA_STORE(ii*4+2)      := data( 23 downto 16 );
272
                                                        DATA_STORE(ii*4+3)      := data( 31 downto 24 );
273
                                                end loop;
274
 
275
--                                              if( now>300 us and now<360 us  ) then
276
--                                                      flag_pass:=1;
277
--                                              end if;
278
 
279
                                        else
280
                                                for ii in 0 to completion_size loop
281
                                                        DATA_STORE(ii*4+0):=x"FF";
282
                                                        DATA_STORE(ii*4+1):=x"FF";
283
                                                        DATA_STORE(ii*4+2):=x"FF";
284
                                                        DATA_STORE(ii*4+3):=x"FF";
285
                                                end loop;
286
 
287
                                        end if;
288
 
289
 
290
 
291
                                        --DATA_STORE(0):=x"AA";
292
 
293
 
294
 
295
                                        byte_count( 11 downto 2 ) := conv_std_logic_vector( completion_size, 10 );
296
                                        byte_count( 1 downto 0 )  := "00";
297
 
298
                                        if( flag_pass=0 ) then
299
 
300
                                         PROC_TX_COMPLETION_DATA (
301
 
302
                                                mem64r.tag,     --tag                      : in std_logic_vector (7 downto 0);
303
                                                "000",  --tc                       : in std_logic_vector (2 downto 0);
304
                                                byte_count( 11 downto 2 ),      --len                      : in std_logic_vector (9 downto 0);
305
                                                byte_count,                                     --byte_count               : in std_logic_vector (11 downto 0);
306
                                                completion_adr,                         --lower_addr               : in std_logic_vector (6 downto 0);
307
                                                "000",  --comp_status              : in std_logic_vector (2 downto 0);
308
                                                '0',     --ep                       : in std_logic;
309
                                                trn_td_c, trn_tsof_n, trn_teof_n , trn_trem_n_c, trn_tsrc_rdy_n, trn_terrfwd_n, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk
310
                                          );
311
                                        end if;
312
 
313
                                        completion_adr := completion_adr + completion_size*4;
314
                                        size:= size - completion_size;
315
                                        adr:=adr+completion_size*4;
316
 
317
 
318
                                end loop;
319
                        end if;
320
 
321
 
322
 
323
                if( cmd.cmd/=0 ) then
324
 
325
                        case( cmd.cmd ) is
326
                                when 1 => -- data_read --
327
 
328
                            PROC_TX_MEMORY_READ_32 (
329
                              X"03", "000", "0000000001", cmd.adr(0), X"0", X"F",
330
                              trn_td_c, trn_tsof_n, trn_teof_n , trn_trem_n_c, trn_tsrc_rdy_n, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
331
 
332
                            PROC_WAIT_FOR_READ_DATA (tx_rx_read_data_valid, rx_tx_read_data_valid, rx_tx_read_data, trn_clk);
333
 
334
                                          vret.data(0)(  31 downto 0 )  := P_READ_DATA;
335
 
336
                                          vret.ret:=1;
337
 
338
                                                wait for 1 ns;
339
                                                ret<=vret;
340
                                                wait until cmd'event and cmd.cmd=0;
341
                                                vret.ret:=0;
342
                                                ret<=vret;
343
 
344
 
345
                                when 2 => -- data_write --
346
 
347
 
348
                            DATA_STORE(3) := cmd.data(0)( 31 downto 24 );
349
                            DATA_STORE(2) := cmd.data(0)( 23 downto 16 );
350
                            DATA_STORE(1) := cmd.data(0)( 15 downto 8 );
351
                            DATA_STORE(0) := cmd.data(0)( 7 downto 0 );
352
 
353
 
354
                            PROC_TX_MEMORY_WRITE_32 (
355
                                          X"02", "000", "0000000001", cmd.adr(0), X"0", X"F",'0',
356
 
357
                              trn_td_c, trn_tsof_n, trn_teof_n , trn_trem_n_c, trn_tsrc_rdy_n, trn_terrfwd_n,
358
                              trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
359
 
360
                                          vret.ret:=1;
361
 
362
                                                wait for 1 ns;
363
                                                ret<=vret;
364
                                                wait until cmd'event and cmd.cmd=0;
365
                                                vret.ret:=0;
366
                                                ret<=vret;
367
 
368
 
369
                                when 20 => -- int_mem_write --
370
                                        adr:=conv_integer( cmd.adr(0)( 31 downto 0 ) );
371
                                        if( adr>=16#100000# and adr<=16#10FFFF# ) then
372
                                                index:=adr-16#100000#;
373
                                                index:=index/4;
374
                                                root_mem_0x10(index):= conv_integer( cmd.data(0)(31 downto 0) );
375
                                        elsif( adr>=16#800000# and adr<=16#80FFFF# ) then
376
                                                index:=adr-16#800000#;
377
                                                index:=index/4;
378
                                                root_mem_0x80(index):= conv_integer( cmd.data(0)(31 downto 0) );
379
                                        end if;
380
                                        vret.ret:=1;
381
 
382
                                        wait for 1 ns;
383
                                        ret<=vret;
384
                                        wait until cmd'event and cmd.cmd=0;
385
                                        vret.ret:=0;
386
                                        ret<=vret;
387
 
388
 
389
                                when 21 => -- int_mem_read --
390
 
391
                                        data:=x"FFFFFFFF";
392
                                        adr:=conv_integer( cmd.adr(0)( 31 downto 0 ) );
393
                                        if( adr>=16#100000# and adr<=16#10FFFF# ) then
394
                                                index:=adr-16#100000#;
395
                                                index:=index/4;
396
                                                data:=conv_std_logic_vector( root_mem_0x10(index), 32 );
397
                                        elsif( adr>=16#800000# and adr<=16#80FFFF# ) then
398
                                                index:=adr-16#800000#;
399
                                                index:=index/4;
400
                                                data:=conv_std_logic_vector( root_mem_0x80(index), 32 );
401
                                        end if;
402
                                        vret.ret:=1;
403
                                        vret.data(0)(  31 downto 0 ):=data;
404
 
405
                                        wait for 1 ns;
406
                                        ret<=vret;
407
                                        wait until cmd'event and cmd.cmd=0;
408
                                        vret.ret:=0;
409
                                        ret<=vret;
410
 
411
                                when others=>
412
                                        null;
413
 
414
                        end case;
415
 
416
 
417
          end if;
418
 
419
          end loop;
420
 
421
          wait;
422
 
423
 
424
 
425
 
426
end process;
427
 
428
 
429
end; -- pci_exp_usrapp_tx_m2

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