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-------------------------------------------------------------------------------
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--
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-- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
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--
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-- This file contains confidential and proprietary information
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-- of Xilinx, Inc. and is protected under U.S. and
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-- international copyright and other intellectual property
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-- laws.
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--
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-- DISCLAIMER
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-- This disclaimer is not a license and does not grant any
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-- rights to the materials distributed herewith. Except as
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-- otherwise provided in a valid license issued to you by
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-- Xilinx, and to the maximum extent permitted by applicable
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-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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-- (2) Xilinx shall not be liable (whether in contract or tort,
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-- including negligence, or under any other theory of
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-- liability) for any loss or damage of any kind or nature
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-- related to, arising under or in connection with these
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-- materials, including for any direct, or any indirect,
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-- special, incidental, or consequential loss or damage
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-- (including loss of data, profits, goodwill, or any type of
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-- loss or damage suffered as a result of any action brought
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-- by a third party) even if such damage or loss was
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-- reasonably foreseeable or Xilinx had been advised of the
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-- possibility of the same.
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--
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-- CRITICAL APPLICATIONS
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-- Xilinx products are not designed or intended to be fail-
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-- safe, or for use in any application requiring fail-safe
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-- performance, such as life-support or safety devices or
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-- systems, Class III medical devices, nuclear facilities,
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-- applications related to the deployment of airbags, or any
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-- other applications that could lead to death, personal
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-- injury, or severe property or environmental damage
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-- (individually and collectively, "Critical
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-- Applications"). Customer assumes the sole risk and
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-- liability of any use of Xilinx products in Critical
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-- Applications, subject only to applicable laws and
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-- regulations governing limitations on product liability.
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--
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-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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-- PART OF THIS FILE AT ALL TIMES.
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--
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-------------------------------------------------------------------------------
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-- Project : Virtex-6 Integrated Block for PCI Express
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-- File : pcie_2_0_v6_rp.vhd
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-- Version : 2.3
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-- Description: Virtex6 solution wrapper : Root Port for PCI Express
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--
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--
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--
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--------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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library unisim;
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use unisim.vcomponents.all;
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entity pcie_2_0_v6_rp is
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generic (
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TCQ : integer := 1;
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REF_CLK_FREQ : integer := 0; -- 0 - 100 MHz, 1 - 125 MHz, 2 - 250 MHz
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PIPE_PIPELINE_STAGES : integer := 0; -- 0 - 0 stages, 1 - 1 stage, 2 - 2 stages
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LINK_CAP_MAX_LINK_WIDTH_int : integer := 8;
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AER_BASE_PTR : bit_vector := X"128";
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AER_CAP_ECRC_CHECK_CAPABLE : boolean := FALSE;
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AER_CAP_ECRC_GEN_CAPABLE : boolean := FALSE;
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AER_CAP_ID : bit_vector := X"0001";
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AER_CAP_INT_MSG_NUM_MSI : bit_vector := X"0A";
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AER_CAP_INT_MSG_NUM_MSIX : bit_vector := X"15";
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AER_CAP_NEXTPTR : bit_vector := X"160";
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AER_CAP_ON : boolean := FALSE;
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AER_CAP_PERMIT_ROOTERR_UPDATE : boolean := TRUE;
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AER_CAP_VERSION : bit_vector := X"1";
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ALLOW_X8_GEN2 : boolean := FALSE;
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BAR0 : bit_vector := X"FFFFFF00";
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BAR1 : bit_vector := X"FFFF0000";
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BAR2 : bit_vector := X"FFFF000C";
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BAR3 : bit_vector := X"FFFFFFFF";
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BAR4 : bit_vector := X"00000000";
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BAR5 : bit_vector := X"00000000";
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CAPABILITIES_PTR : bit_vector := X"40";
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CARDBUS_CIS_POINTER : bit_vector := X"00000000";
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CLASS_CODE : bit_vector := X"000000";
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CMD_INTX_IMPLEMENTED : boolean := TRUE;
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CPL_TIMEOUT_DISABLE_SUPPORTED : boolean := FALSE;
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CPL_TIMEOUT_RANGES_SUPPORTED : bit_vector := X"0";
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CRM_MODULE_RSTS : bit_vector := X"00";
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DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE : boolean := TRUE;
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DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE : boolean := TRUE;
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DEV_CAP_ENDPOINT_L0S_LATENCY : integer := 0;
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DEV_CAP_ENDPOINT_L1_LATENCY : integer := 0;
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DEV_CAP_EXT_TAG_SUPPORTED : boolean := TRUE;
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DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE : boolean := FALSE;
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DEV_CAP_MAX_PAYLOAD_SUPPORTED : integer := 2;
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DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT : integer := 0;
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DEV_CAP_ROLE_BASED_ERROR : boolean := TRUE;
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DEV_CAP_RSVD_14_12 : integer := 0;
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DEV_CAP_RSVD_17_16 : integer := 0;
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DEV_CAP_RSVD_31_29 : integer := 0;
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DEV_CONTROL_AUX_POWER_SUPPORTED : boolean := FALSE;
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DEVICE_ID : bit_vector := X"0007";
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DISABLE_ASPM_L1_TIMER : boolean := FALSE;
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DISABLE_BAR_FILTERING : boolean := FALSE;
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DISABLE_ID_CHECK : boolean := FALSE;
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DISABLE_LANE_REVERSAL : boolean := FALSE;
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DISABLE_RX_TC_FILTER : boolean := FALSE;
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DISABLE_SCRAMBLING : boolean := FALSE;
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DNSTREAM_LINK_NUM : bit_vector := X"00";
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DSN_BASE_PTR : bit_vector := X"100";
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DSN_CAP_ID : bit_vector := X"0003";
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DSN_CAP_NEXTPTR : bit_vector := X"000";
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DSN_CAP_ON : boolean := TRUE;
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DSN_CAP_VERSION : bit_vector := X"1";
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ENABLE_MSG_ROUTE : bit_vector := X"000";
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ENABLE_RX_TD_ECRC_TRIM : boolean := FALSE;
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ENTER_RVRY_EI_L0 : boolean := TRUE;
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EXPANSION_ROM : bit_vector := X"FFFFF001";
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EXT_CFG_CAP_PTR : bit_vector := X"3F";
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EXT_CFG_XP_CAP_PTR : bit_vector := X"3FF";
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HEADER_TYPE : bit_vector := X"00";
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INFER_EI : bit_vector := X"00";
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INTERRUPT_PIN : bit_vector := X"01";
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IS_SWITCH : boolean := FALSE;
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LAST_CONFIG_DWORD : bit_vector := X"042";
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LINK_CAP_ASPM_SUPPORT : integer := 1;
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LINK_CAP_CLOCK_POWER_MANAGEMENT : boolean := FALSE;
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LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP : boolean := FALSE;
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LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 : integer := 7;
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LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 : integer := 7;
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LINK_CAP_L0S_EXIT_LATENCY_GEN1 : integer := 7;
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LINK_CAP_L0S_EXIT_LATENCY_GEN2 : integer := 7;
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LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 : integer := 7;
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LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 : integer := 7;
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LINK_CAP_L1_EXIT_LATENCY_GEN1 : integer := 7;
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LINK_CAP_L1_EXIT_LATENCY_GEN2 : integer := 7;
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LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP : boolean := FALSE;
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LINK_CAP_MAX_LINK_SPEED : bit_vector := X"1";
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LINK_CAP_MAX_LINK_WIDTH : bit_vector := X"08";
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LINK_CAP_RSVD_23_22 : integer := 0;
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LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE : boolean := FALSE;
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LINK_CONTROL_RCB : integer := 0;
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LINK_CTRL2_DEEMPHASIS : boolean := FALSE;
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LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE : boolean := FALSE;
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LINK_CTRL2_TARGET_LINK_SPEED : bit_vector := X"2";
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LINK_STATUS_SLOT_CLOCK_CONFIG : boolean := TRUE;
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LL_ACK_TIMEOUT : bit_vector := X"0000";
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LL_ACK_TIMEOUT_EN : boolean := FALSE;
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LL_ACK_TIMEOUT_FUNC : integer := 0;
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LL_REPLAY_TIMEOUT : bit_vector := X"0000";
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LL_REPLAY_TIMEOUT_EN : boolean := FALSE;
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LL_REPLAY_TIMEOUT_FUNC : integer := 0;
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LTSSM_MAX_LINK_WIDTH : bit_vector := X"01";
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MSI_BASE_PTR : bit_vector := X"48";
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MSI_CAP_ID : bit_vector := X"05";
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MSI_CAP_MULTIMSGCAP : integer := 0;
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MSI_CAP_MULTIMSG_EXTENSION : integer := 0;
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MSI_CAP_NEXTPTR : bit_vector := X"60";
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MSI_CAP_ON : boolean := FALSE;
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MSI_CAP_PER_VECTOR_MASKING_CAPABLE : boolean := TRUE;
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MSI_CAP_64_BIT_ADDR_CAPABLE : boolean := TRUE;
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MSIX_BASE_PTR : bit_vector := X"9C";
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MSIX_CAP_ID : bit_vector := X"11";
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MSIX_CAP_NEXTPTR : bit_vector := X"00";
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MSIX_CAP_ON : boolean := FALSE;
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MSIX_CAP_PBA_BIR : integer := 0;
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MSIX_CAP_PBA_OFFSET : bit_vector := X"00000050";
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MSIX_CAP_TABLE_BIR : integer := 0;
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MSIX_CAP_TABLE_OFFSET : bit_vector := X"00000040";
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MSIX_CAP_TABLE_SIZE : bit_vector := X"000";
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N_FTS_COMCLK_GEN1 : integer := 255;
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N_FTS_COMCLK_GEN2 : integer := 255;
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N_FTS_GEN1 : integer := 255;
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N_FTS_GEN2 : integer := 255;
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PCIE_BASE_PTR : bit_vector := X"60";
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PCIE_CAP_CAPABILITY_ID : bit_vector := X"10";
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PCIE_CAP_CAPABILITY_VERSION : bit_vector := X"2";
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PCIE_CAP_DEVICE_PORT_TYPE : bit_vector := X"0";
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PCIE_CAP_INT_MSG_NUM : bit_vector := X"00";
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PCIE_CAP_NEXTPTR : bit_vector := X"00";
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PCIE_CAP_ON : boolean := TRUE;
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PCIE_CAP_RSVD_15_14 : integer := 0;
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PCIE_CAP_SLOT_IMPLEMENTED : boolean := FALSE;
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PCIE_REVISION : integer := 2;
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PGL0_LANE : integer := 0;
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PGL1_LANE : integer := 1;
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PGL2_LANE : integer := 2;
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PGL3_LANE : integer := 3;
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PGL4_LANE : integer := 4;
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PGL5_LANE : integer := 5;
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PGL6_LANE : integer := 6;
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PGL7_LANE : integer := 7;
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PL_AUTO_CONFIG : integer := 0;
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PL_FAST_TRAIN : boolean := FALSE;
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PM_BASE_PTR : bit_vector := X"40";
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PM_CAP_AUXCURRENT : integer := 0;
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PM_CAP_DSI : boolean := FALSE;
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PM_CAP_D1SUPPORT : boolean := TRUE;
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PM_CAP_D2SUPPORT : boolean := TRUE;
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PM_CAP_ID : bit_vector := X"11";
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PM_CAP_NEXTPTR : bit_vector := X"48";
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PM_CAP_ON : boolean := TRUE;
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PM_CAP_PME_CLOCK : boolean := FALSE;
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PM_CAP_PMESUPPORT : bit_vector := X"0F";
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PM_CAP_RSVD_04 : integer := 0;
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PM_CAP_VERSION : integer := 3;
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PM_CSR_BPCCEN : boolean := FALSE;
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PM_CSR_B2B3 : boolean := FALSE;
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PM_CSR_NOSOFTRST : boolean := TRUE;
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PM_DATA0 : bit_vector := X"01";
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PM_DATA1 : bit_vector := X"01";
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PM_DATA2 : bit_vector := X"01";
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PM_DATA3 : bit_vector := X"01";
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PM_DATA4 : bit_vector := X"01";
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PM_DATA5 : bit_vector := X"01";
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PM_DATA6 : bit_vector := X"01";
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PM_DATA7 : bit_vector := X"01";
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PM_DATA_SCALE0 : bit_vector := X"1";
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227 |
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PM_DATA_SCALE1 : bit_vector := X"1";
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228 |
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PM_DATA_SCALE2 : bit_vector := X"1";
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229 |
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PM_DATA_SCALE3 : bit_vector := X"1";
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230 |
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PM_DATA_SCALE4 : bit_vector := X"1";
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PM_DATA_SCALE5 : bit_vector := X"1";
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232 |
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PM_DATA_SCALE6 : bit_vector := X"1";
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233 |
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PM_DATA_SCALE7 : bit_vector := X"1";
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234 |
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RECRC_CHK : integer := 0;
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235 |
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RECRC_CHK_TRIM : boolean := FALSE;
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236 |
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REVISION_ID : bit_vector := X"00";
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237 |
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ROOT_CAP_CRS_SW_VISIBILITY : boolean := FALSE;
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238 |
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SELECT_DLL_IF : boolean := FALSE;
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239 |
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SLOT_CAP_ATT_BUTTON_PRESENT : boolean := FALSE;
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240 |
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SLOT_CAP_ATT_INDICATOR_PRESENT : boolean := FALSE;
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241 |
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SLOT_CAP_ELEC_INTERLOCK_PRESENT : boolean := FALSE;
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242 |
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SLOT_CAP_HOTPLUG_CAPABLE : boolean := FALSE;
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243 |
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SLOT_CAP_HOTPLUG_SURPRISE : boolean := FALSE;
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244 |
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SLOT_CAP_MRL_SENSOR_PRESENT : boolean := FALSE;
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245 |
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SLOT_CAP_NO_CMD_COMPLETED_SUPPORT : boolean := FALSE;
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246 |
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SLOT_CAP_PHYSICAL_SLOT_NUM : bit_vector := X"0000";
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247 |
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SLOT_CAP_POWER_CONTROLLER_PRESENT : boolean := FALSE;
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248 |
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SLOT_CAP_POWER_INDICATOR_PRESENT : boolean := FALSE;
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249 |
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SLOT_CAP_SLOT_POWER_LIMIT_SCALE : integer := 0;
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250 |
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SLOT_CAP_SLOT_POWER_LIMIT_VALUE : bit_vector := X"00";
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251 |
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SPARE_BIT0 : integer := 0;
|
252 |
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SPARE_BIT1 : integer := 0;
|
253 |
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SPARE_BIT2 : integer := 0;
|
254 |
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SPARE_BIT3 : integer := 0;
|
255 |
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SPARE_BIT4 : integer := 0;
|
256 |
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SPARE_BIT5 : integer := 0;
|
257 |
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SPARE_BIT6 : integer := 0;
|
258 |
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SPARE_BIT7 : integer := 0;
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259 |
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SPARE_BIT8 : integer := 0;
|
260 |
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SPARE_BYTE0 : bit_vector := X"00";
|
261 |
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SPARE_BYTE1 : bit_vector := X"00";
|
262 |
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SPARE_BYTE2 : bit_vector := X"00";
|
263 |
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SPARE_BYTE3 : bit_vector := X"00";
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264 |
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SPARE_WORD0 : bit_vector := X"00000000";
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265 |
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SPARE_WORD1 : bit_vector := X"00000000";
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266 |
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SPARE_WORD2 : bit_vector := X"00000000";
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267 |
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SPARE_WORD3 : bit_vector := X"00000000";
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268 |
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SUBSYSTEM_ID : bit_vector := X"0007";
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269 |
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SUBSYSTEM_VENDOR_ID : bit_vector := X"10EE";
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270 |
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TL_RBYPASS : boolean := FALSE;
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271 |
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TL_RX_RAM_RADDR_LATENCY : integer := 0;
|
272 |
|
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TL_RX_RAM_RDATA_LATENCY : integer := 2;
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273 |
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TL_RX_RAM_WRITE_LATENCY : integer := 0;
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274 |
|
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TL_TFC_DISABLE : boolean := FALSE;
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275 |
|
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TL_TX_CHECKS_DISABLE : boolean := FALSE;
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276 |
|
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TL_TX_RAM_RADDR_LATENCY : integer := 0;
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277 |
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TL_TX_RAM_RDATA_LATENCY : integer := 2;
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278 |
|
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TL_TX_RAM_WRITE_LATENCY : integer := 0;
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279 |
|
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UPCONFIG_CAPABLE : boolean := TRUE;
|
280 |
|
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UPSTREAM_FACING : boolean := TRUE;
|
281 |
|
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UR_INV_REQ : boolean := TRUE;
|
282 |
|
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USER_CLK_FREQ : integer := 3;
|
283 |
|
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EXIT_LOOPBACK_ON_EI : boolean := TRUE;
|
284 |
|
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VC_BASE_PTR : bit_vector := X"10C";
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285 |
|
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VC_CAP_ID : bit_vector := X"0002";
|
286 |
|
|
VC_CAP_NEXTPTR : bit_vector := X"000";
|
287 |
|
|
VC_CAP_ON : boolean := FALSE;
|
288 |
|
|
VC_CAP_REJECT_SNOOP_TRANSACTIONS : boolean := FALSE;
|
289 |
|
|
VC_CAP_VERSION : bit_vector := X"1";
|
290 |
|
|
VC0_CPL_INFINITE : boolean := TRUE;
|
291 |
|
|
VC0_RX_RAM_LIMIT : bit_vector := X"03FF";
|
292 |
|
|
VC0_TOTAL_CREDITS_CD : integer := 127;
|
293 |
|
|
VC0_TOTAL_CREDITS_CH : integer := 31;
|
294 |
|
|
VC0_TOTAL_CREDITS_NPH : integer := 12;
|
295 |
|
|
VC0_TOTAL_CREDITS_PD : integer := 288;
|
296 |
|
|
VC0_TOTAL_CREDITS_PH : integer := 32;
|
297 |
|
|
VC0_TX_LASTPACKET : integer := 31;
|
298 |
|
|
VENDOR_ID : bit_vector := X"10EE";
|
299 |
|
|
VSEC_BASE_PTR : bit_vector := X"160";
|
300 |
|
|
VSEC_CAP_HDR_ID : bit_vector := X"1234";
|
301 |
|
|
VSEC_CAP_HDR_LENGTH : bit_vector := X"018";
|
302 |
|
|
VSEC_CAP_HDR_REVISION : bit_vector := X"1";
|
303 |
|
|
VSEC_CAP_ID : bit_vector := X"000B";
|
304 |
|
|
VSEC_CAP_IS_LINK_VISIBLE : boolean := TRUE;
|
305 |
|
|
VSEC_CAP_NEXTPTR : bit_vector := X"000";
|
306 |
|
|
VSEC_CAP_ON : boolean := FALSE;
|
307 |
|
|
VSEC_CAP_VERSION : bit_vector := X"1"
|
308 |
|
|
);
|
309 |
|
|
port (
|
310 |
|
|
|
311 |
|
|
PCIEXPRXN : in std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);
|
312 |
|
|
PCIEXPRXP : in std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);
|
313 |
|
|
PCIEXPTXN : out std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);
|
314 |
|
|
PCIEXPTXP : out std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);
|
315 |
|
|
|
316 |
|
|
SYSCLK : in std_logic;
|
317 |
|
|
FUNDRSTN : in std_logic;
|
318 |
|
|
|
319 |
|
|
TRNLNKUPN : out std_logic;
|
320 |
|
|
TRNCLK : out std_logic;
|
321 |
|
|
|
322 |
|
|
PHYRDYN : out std_logic;
|
323 |
|
|
USERRSTN : out std_logic;
|
324 |
|
|
RECEIVEDFUNCLVLRSTN : out std_logic;
|
325 |
|
|
LNKCLKEN : out std_logic;
|
326 |
|
|
SYSRSTN : in std_logic;
|
327 |
|
|
PLRSTN : in std_logic;
|
328 |
|
|
DLRSTN : in std_logic;
|
329 |
|
|
TLRSTN : in std_logic;
|
330 |
|
|
FUNCLVLRSTN : in std_logic;
|
331 |
|
|
CMRSTN : in std_logic;
|
332 |
|
|
CMSTICKYRSTN : in std_logic;
|
333 |
|
|
|
334 |
|
|
TRNRBARHITN : out std_logic_vector(6 downto 0);
|
335 |
|
|
TRNRD : out std_logic_vector(63 downto 0);
|
336 |
|
|
TRNRECRCERRN : out std_logic;
|
337 |
|
|
TRNREOFN : out std_logic;
|
338 |
|
|
|
339 |
|
|
TRNRERRFWDN : out std_logic;
|
340 |
|
|
TRNRREMN : out std_logic;
|
341 |
|
|
TRNRSOFN : out std_logic;
|
342 |
|
|
TRNRSRCDSCN : out std_logic;
|
343 |
|
|
TRNRSRCRDYN : out std_logic;
|
344 |
|
|
TRNRDSTRDYN : in std_logic;
|
345 |
|
|
TRNRNPOKN : in std_logic;
|
346 |
|
|
|
347 |
|
|
TRNTBUFAV : out std_logic_vector(5 downto 0);
|
348 |
|
|
TRNTCFGREQN : out std_logic;
|
349 |
|
|
|
350 |
|
|
TRNTDLLPDSTRDYN : out std_logic;
|
351 |
|
|
TRNTDSTRDYN : out std_logic;
|
352 |
|
|
|
353 |
|
|
TRNTERRDROPN : out std_logic;
|
354 |
|
|
|
355 |
|
|
TRNTCFGGNTN : in std_logic;
|
356 |
|
|
|
357 |
|
|
TRNTD : in std_logic_vector(63 downto 0);
|
358 |
|
|
TRNTDLLPDATA : in std_logic_vector(31 downto 0);
|
359 |
|
|
TRNTDLLPSRCRDYN : in std_logic;
|
360 |
|
|
TRNTECRCGENN : in std_logic;
|
361 |
|
|
TRNTEOFN : in std_logic;
|
362 |
|
|
|
363 |
|
|
TRNTERRFWDN : in std_logic;
|
364 |
|
|
TRNTREMN : in std_logic;
|
365 |
|
|
|
366 |
|
|
TRNTSOFN : in std_logic;
|
367 |
|
|
TRNTSRCDSCN : in std_logic;
|
368 |
|
|
TRNTSRCRDYN : in std_logic;
|
369 |
|
|
TRNTSTRN : in std_logic;
|
370 |
|
|
|
371 |
|
|
TRNFCCPLD : out std_logic_vector(11 downto 0);
|
372 |
|
|
TRNFCCPLH : out std_logic_vector(7 downto 0);
|
373 |
|
|
TRNFCNPD : out std_logic_vector(11 downto 0);
|
374 |
|
|
TRNFCNPH : out std_logic_vector(7 downto 0);
|
375 |
|
|
TRNFCPD : out std_logic_vector(11 downto 0);
|
376 |
|
|
TRNFCPH : out std_logic_vector(7 downto 0);
|
377 |
|
|
TRNFCSEL : in std_logic_vector(2 downto 0);
|
378 |
|
|
|
379 |
|
|
CFGAERECRCCHECKEN : out std_logic;
|
380 |
|
|
CFGAERECRCGENEN : out std_logic;
|
381 |
|
|
CFGCOMMANDBUSMASTERENABLE : out std_logic;
|
382 |
|
|
CFGCOMMANDINTERRUPTDISABLE : out std_logic;
|
383 |
|
|
CFGCOMMANDIOENABLE : out std_logic;
|
384 |
|
|
CFGCOMMANDMEMENABLE : out std_logic;
|
385 |
|
|
CFGCOMMANDSERREN : out std_logic;
|
386 |
|
|
CFGDEVCONTROLAUXPOWEREN : out std_logic;
|
387 |
|
|
CFGDEVCONTROLCORRERRREPORTINGEN : out std_logic;
|
388 |
|
|
CFGDEVCONTROLENABLERO : out std_logic;
|
389 |
|
|
CFGDEVCONTROLEXTTAGEN : out std_logic;
|
390 |
|
|
CFGDEVCONTROLFATALERRREPORTINGEN : out std_logic;
|
391 |
|
|
CFGDEVCONTROLMAXPAYLOAD : out std_logic_vector(2 downto 0);
|
392 |
|
|
CFGDEVCONTROLMAXREADREQ : out std_logic_vector(2 downto 0);
|
393 |
|
|
CFGDEVCONTROLNONFATALREPORTINGEN : out std_logic;
|
394 |
|
|
CFGDEVCONTROLNOSNOOPEN : out std_logic;
|
395 |
|
|
CFGDEVCONTROLPHANTOMEN : out std_logic;
|
396 |
|
|
CFGDEVCONTROLURERRREPORTINGEN : out std_logic;
|
397 |
|
|
CFGDEVCONTROL2CPLTIMEOUTDIS : out std_logic;
|
398 |
|
|
CFGDEVCONTROL2CPLTIMEOUTVAL : out std_logic_vector(3 downto 0);
|
399 |
|
|
CFGDEVSTATUSCORRERRDETECTED : out std_logic;
|
400 |
|
|
CFGDEVSTATUSFATALERRDETECTED : out std_logic;
|
401 |
|
|
CFGDEVSTATUSNONFATALERRDETECTED : out std_logic;
|
402 |
|
|
CFGDEVSTATUSURDETECTED : out std_logic;
|
403 |
|
|
CFGDO : out std_logic_vector(31 downto 0);
|
404 |
|
|
CFGERRAERHEADERLOGSETN : out std_logic;
|
405 |
|
|
CFGERRCPLRDYN : out std_logic;
|
406 |
|
|
CFGINTERRUPTDO : out std_logic_vector(7 downto 0);
|
407 |
|
|
CFGINTERRUPTMMENABLE : out std_logic_vector(2 downto 0);
|
408 |
|
|
CFGINTERRUPTMSIENABLE : out std_logic;
|
409 |
|
|
CFGINTERRUPTMSIXENABLE : out std_logic;
|
410 |
|
|
CFGINTERRUPTMSIXFM : out std_logic;
|
411 |
|
|
CFGINTERRUPTRDYN : out std_logic;
|
412 |
|
|
CFGLINKCONTROLRCB : out std_logic;
|
413 |
|
|
CFGLINKCONTROLASPMCONTROL : out std_logic_vector(1 downto 0);
|
414 |
|
|
CFGLINKCONTROLAUTOBANDWIDTHINTEN : out std_logic;
|
415 |
|
|
CFGLINKCONTROLBANDWIDTHINTEN : out std_logic;
|
416 |
|
|
CFGLINKCONTROLCLOCKPMEN : out std_logic;
|
417 |
|
|
CFGLINKCONTROLCOMMONCLOCK : out std_logic;
|
418 |
|
|
CFGLINKCONTROLEXTENDEDSYNC : out std_logic;
|
419 |
|
|
CFGLINKCONTROLHWAUTOWIDTHDIS : out std_logic;
|
420 |
|
|
CFGLINKCONTROLLINKDISABLE : out std_logic;
|
421 |
|
|
CFGLINKCONTROLRETRAINLINK : out std_logic;
|
422 |
|
|
CFGLINKSTATUSAUTOBANDWIDTHSTATUS : out std_logic;
|
423 |
|
|
CFGLINKSTATUSBANDWITHSTATUS : out std_logic;
|
424 |
|
|
CFGLINKSTATUSCURRENTSPEED : out std_logic_vector(1 downto 0);
|
425 |
|
|
CFGLINKSTATUSDLLACTIVE : out std_logic;
|
426 |
|
|
CFGLINKSTATUSLINKTRAINING : out std_logic;
|
427 |
|
|
CFGLINKSTATUSNEGOTIATEDWIDTH : out std_logic_vector(3 downto 0);
|
428 |
|
|
CFGMSGDATA : out std_logic_vector(15 downto 0);
|
429 |
|
|
CFGMSGRECEIVED : out std_logic;
|
430 |
|
|
CFGMSGRECEIVEDASSERTINTA : out std_logic;
|
431 |
|
|
CFGMSGRECEIVEDASSERTINTB : out std_logic;
|
432 |
|
|
CFGMSGRECEIVEDASSERTINTC : out std_logic;
|
433 |
|
|
CFGMSGRECEIVEDASSERTINTD : out std_logic;
|
434 |
|
|
CFGMSGRECEIVEDDEASSERTINTA : out std_logic;
|
435 |
|
|
CFGMSGRECEIVEDDEASSERTINTB : out std_logic;
|
436 |
|
|
CFGMSGRECEIVEDDEASSERTINTC : out std_logic;
|
437 |
|
|
CFGMSGRECEIVEDDEASSERTINTD : out std_logic;
|
438 |
|
|
CFGMSGRECEIVEDERRCOR : out std_logic;
|
439 |
|
|
CFGMSGRECEIVEDERRFATAL : out std_logic;
|
440 |
|
|
CFGMSGRECEIVEDERRNONFATAL : out std_logic;
|
441 |
|
|
CFGMSGRECEIVEDPMASNAK : out std_logic;
|
442 |
|
|
CFGMSGRECEIVEDPMETO : out std_logic;
|
443 |
|
|
CFGMSGRECEIVEDPMETOACK : out std_logic;
|
444 |
|
|
CFGMSGRECEIVEDPMPME : out std_logic;
|
445 |
|
|
CFGMSGRECEIVEDSETSLOTPOWERLIMIT : out std_logic;
|
446 |
|
|
CFGMSGRECEIVEDUNLOCK : out std_logic;
|
447 |
|
|
CFGPCIELINKSTATE : out std_logic_vector(2 downto 0);
|
448 |
|
|
CFGPMCSRPMEEN : out std_logic;
|
449 |
|
|
CFGPMCSRPMESTATUS : out std_logic;
|
450 |
|
|
CFGPMCSRPOWERSTATE : out std_logic_vector(1 downto 0);
|
451 |
|
|
CFGPMRCVASREQL1N : out std_logic;
|
452 |
|
|
CFGPMRCVENTERL1N : out std_logic;
|
453 |
|
|
CFGPMRCVENTERL23N : out std_logic;
|
454 |
|
|
CFGPMRCVREQACKN : out std_logic;
|
455 |
|
|
CFGRDWRDONEN : out std_logic;
|
456 |
|
|
CFGSLOTCONTROLELECTROMECHILCTLPULSE : out std_logic;
|
457 |
|
|
CFGTRANSACTION : out std_logic;
|
458 |
|
|
CFGTRANSACTIONADDR : out std_logic_vector(6 downto 0);
|
459 |
|
|
CFGTRANSACTIONTYPE : out std_logic;
|
460 |
|
|
CFGVCTCVCMAP : out std_logic_vector(6 downto 0);
|
461 |
|
|
CFGBYTEENN : in std_logic_vector(3 downto 0);
|
462 |
|
|
CFGDI : in std_logic_vector(31 downto 0);
|
463 |
|
|
CFGDSBUSNUMBER : in std_logic_vector(7 downto 0);
|
464 |
|
|
CFGDSDEVICENUMBER : in std_logic_vector(4 downto 0);
|
465 |
|
|
CFGDSFUNCTIONNUMBER : in std_logic_vector(2 downto 0);
|
466 |
|
|
CFGDSN : in std_logic_vector(63 downto 0);
|
467 |
|
|
CFGDWADDR : in std_logic_vector(9 downto 0);
|
468 |
|
|
CFGERRACSN : in std_logic;
|
469 |
|
|
CFGERRAERHEADERLOG : in std_logic_vector(127 downto 0);
|
470 |
|
|
CFGERRCORN : in std_logic;
|
471 |
|
|
CFGERRCPLABORTN : in std_logic;
|
472 |
|
|
CFGERRCPLTIMEOUTN : in std_logic;
|
473 |
|
|
CFGERRCPLUNEXPECTN : in std_logic;
|
474 |
|
|
CFGERRECRCN : in std_logic;
|
475 |
|
|
CFGERRLOCKEDN : in std_logic;
|
476 |
|
|
CFGERRPOSTEDN : in std_logic;
|
477 |
|
|
CFGERRTLPCPLHEADER : in std_logic_vector(47 downto 0);
|
478 |
|
|
CFGERRURN : in std_logic;
|
479 |
|
|
CFGINTERRUPTASSERTN : in std_logic;
|
480 |
|
|
CFGINTERRUPTDI : in std_logic_vector(7 downto 0);
|
481 |
|
|
CFGINTERRUPTN : in std_logic;
|
482 |
|
|
CFGPMDIRECTASPML1N : in std_logic;
|
483 |
|
|
CFGPMSENDPMACKN : in std_logic;
|
484 |
|
|
CFGPMSENDPMETON : in std_logic;
|
485 |
|
|
CFGPMSENDPMNAKN : in std_logic;
|
486 |
|
|
CFGPMTURNOFFOKN : in std_logic;
|
487 |
|
|
CFGPMWAKEN : in std_logic;
|
488 |
|
|
CFGPORTNUMBER : in std_logic_vector(7 downto 0);
|
489 |
|
|
CFGRDENN : in std_logic;
|
490 |
|
|
CFGTRNPENDINGN : in std_logic;
|
491 |
|
|
CFGWRENN : in std_logic;
|
492 |
|
|
CFGWRREADONLYN : in std_logic;
|
493 |
|
|
CFGWRRW1CASRWN : in std_logic;
|
494 |
|
|
|
495 |
|
|
PLINITIALLINKWIDTH : out std_logic_vector(2 downto 0);
|
496 |
|
|
PLLANEREVERSALMODE : out std_logic_vector(1 downto 0);
|
497 |
|
|
PLLINKGEN2CAP : out std_logic;
|
498 |
|
|
PLLINKPARTNERGEN2SUPPORTED : out std_logic;
|
499 |
|
|
PLLINKUPCFGCAP : out std_logic;
|
500 |
|
|
PLLTSSMSTATE : out std_logic_vector(5 downto 0);
|
501 |
|
|
PLPHYLNKUPN : out std_logic;
|
502 |
|
|
PLRECEIVEDHOTRST : out std_logic;
|
503 |
|
|
PLRXPMSTATE : out std_logic_vector(1 downto 0);
|
504 |
|
|
PLSELLNKRATE : out std_logic;
|
505 |
|
|
PLSELLNKWIDTH : out std_logic_vector(1 downto 0);
|
506 |
|
|
PLTXPMSTATE : out std_logic_vector(2 downto 0);
|
507 |
|
|
PLDIRECTEDLINKAUTON : in std_logic;
|
508 |
|
|
PLDIRECTEDLINKCHANGE : in std_logic_vector(1 downto 0);
|
509 |
|
|
PLDIRECTEDLINKSPEED : in std_logic;
|
510 |
|
|
PLDIRECTEDLINKWIDTH : in std_logic_vector(1 downto 0);
|
511 |
|
|
PLDOWNSTREAMDEEMPHSOURCE : in std_logic;
|
512 |
|
|
PLUPSTREAMPREFERDEEMPH : in std_logic;
|
513 |
|
|
PLTRANSMITHOTRST : in std_logic;
|
514 |
|
|
|
515 |
|
|
DBGSCLRA : out std_logic;
|
516 |
|
|
DBGSCLRB : out std_logic;
|
517 |
|
|
DBGSCLRC : out std_logic;
|
518 |
|
|
DBGSCLRD : out std_logic;
|
519 |
|
|
DBGSCLRE : out std_logic;
|
520 |
|
|
DBGSCLRF : out std_logic;
|
521 |
|
|
DBGSCLRG : out std_logic;
|
522 |
|
|
DBGSCLRH : out std_logic;
|
523 |
|
|
DBGSCLRI : out std_logic;
|
524 |
|
|
DBGSCLRJ : out std_logic;
|
525 |
|
|
DBGSCLRK : out std_logic;
|
526 |
|
|
DBGVECA : out std_logic_vector(63 downto 0);
|
527 |
|
|
DBGVECB : out std_logic_vector(63 downto 0);
|
528 |
|
|
DBGVECC : out std_logic_vector(11 downto 0);
|
529 |
|
|
PLDBGVEC : out std_logic_vector(11 downto 0);
|
530 |
|
|
DBGMODE : in std_logic_vector(1 downto 0);
|
531 |
|
|
DBGSUBMODE : in std_logic;
|
532 |
|
|
PLDBGMODE : in std_logic_vector(2 downto 0);
|
533 |
|
|
PCIEDRPDO : out std_logic_vector(15 downto 0);
|
534 |
|
|
PCIEDRPDRDY : out std_logic;
|
535 |
|
|
PCIEDRPCLK : in std_logic;
|
536 |
|
|
PCIEDRPDADDR : in std_logic_vector(8 downto 0);
|
537 |
|
|
PCIEDRPDEN : in std_logic;
|
538 |
|
|
PCIEDRPDI : in std_logic_vector(15 downto 0);
|
539 |
|
|
PCIEDRPDWE : in std_logic;
|
540 |
|
|
|
541 |
|
|
GTPLLLOCK : out std_logic;
|
542 |
|
|
PIPECLK : in std_logic;
|
543 |
|
|
|
544 |
|
|
USERCLK : in std_logic;
|
545 |
|
|
DRPCLK : in std_logic;
|
546 |
|
|
CLOCKLOCKED : in std_logic;
|
547 |
|
|
|
548 |
|
|
TxOutClk : out std_logic
|
549 |
|
|
);
|
550 |
|
|
end pcie_2_0_v6_rp;
|
551 |
|
|
|
552 |
|
|
architecture v6_pcie of pcie_2_0_v6_rp is
|
553 |
|
|
|
554 |
|
|
component pcie_pipe_v6
|
555 |
|
|
generic (
|
556 |
|
|
NO_OF_LANES : integer;
|
557 |
|
|
LINK_CAP_MAX_LINK_SPEED : bit_vector;
|
558 |
|
|
PIPE_PIPELINE_STAGES : integer);
|
559 |
|
|
port (
|
560 |
|
|
pipe_tx_rcvr_det_i : in std_logic;
|
561 |
|
|
pipe_tx_reset_i : in std_logic;
|
562 |
|
|
pipe_tx_rate_i : in std_logic;
|
563 |
|
|
pipe_tx_deemph_i : in std_logic;
|
564 |
|
|
pipe_tx_margin_i : in std_logic_vector(2 downto 0);
|
565 |
|
|
pipe_tx_swing_i : in std_logic;
|
566 |
|
|
pipe_tx_rcvr_det_o : out std_logic;
|
567 |
|
|
pipe_tx_reset_o : out std_logic;
|
568 |
|
|
pipe_tx_rate_o : out std_logic;
|
569 |
|
|
pipe_tx_deemph_o : out std_logic;
|
570 |
|
|
pipe_tx_margin_o : out std_logic_vector(2 downto 0);
|
571 |
|
|
pipe_tx_swing_o : out std_logic;
|
572 |
|
|
pipe_rx0_char_is_k_o : out std_logic_vector(1 downto 0);
|
573 |
|
|
pipe_rx0_data_o : out std_logic_vector(15 downto 0);
|
574 |
|
|
pipe_rx0_valid_o : out std_logic;
|
575 |
|
|
pipe_rx0_chanisaligned_o : out std_logic;
|
576 |
|
|
pipe_rx0_status_o : out std_logic_vector(2 downto 0);
|
577 |
|
|
pipe_rx0_phy_status_o : out std_logic;
|
578 |
|
|
pipe_rx0_elec_idle_o : out std_logic;
|
579 |
|
|
pipe_rx0_polarity_i : in std_logic;
|
580 |
|
|
pipe_tx0_compliance_i : in std_logic;
|
581 |
|
|
pipe_tx0_char_is_k_i : in std_logic_vector(1 downto 0);
|
582 |
|
|
pipe_tx0_data_i : in std_logic_vector(15 downto 0);
|
583 |
|
|
pipe_tx0_elec_idle_i : in std_logic;
|
584 |
|
|
pipe_tx0_powerdown_i : in std_logic_vector(1 downto 0);
|
585 |
|
|
pipe_rx0_char_is_k_i : in std_logic_vector(1 downto 0);
|
586 |
|
|
pipe_rx0_data_i : in std_logic_vector(15 downto 0);
|
587 |
|
|
pipe_rx0_valid_i : in std_logic;
|
588 |
|
|
pipe_rx0_chanisaligned_i : in std_logic;
|
589 |
|
|
pipe_rx0_status_i : in std_logic_vector(2 downto 0);
|
590 |
|
|
pipe_rx0_phy_status_i : in std_logic;
|
591 |
|
|
pipe_rx0_elec_idle_i : in std_logic;
|
592 |
|
|
pipe_rx0_polarity_o : out std_logic;
|
593 |
|
|
pipe_tx0_compliance_o : out std_logic;
|
594 |
|
|
pipe_tx0_char_is_k_o : out std_logic_vector(1 downto 0);
|
595 |
|
|
pipe_tx0_data_o : out std_logic_vector(15 downto 0);
|
596 |
|
|
pipe_tx0_elec_idle_o : out std_logic;
|
597 |
|
|
pipe_tx0_powerdown_o : out std_logic_vector(1 downto 0);
|
598 |
|
|
pipe_rx1_char_is_k_o : out std_logic_vector(1 downto 0);
|
599 |
|
|
pipe_rx1_data_o : out std_logic_vector(15 downto 0);
|
600 |
|
|
pipe_rx1_valid_o : out std_logic;
|
601 |
|
|
pipe_rx1_chanisaligned_o : out std_logic;
|
602 |
|
|
pipe_rx1_status_o : out std_logic_vector(2 downto 0);
|
603 |
|
|
pipe_rx1_phy_status_o : out std_logic;
|
604 |
|
|
pipe_rx1_elec_idle_o : out std_logic;
|
605 |
|
|
pipe_rx1_polarity_i : in std_logic;
|
606 |
|
|
pipe_tx1_compliance_i : in std_logic;
|
607 |
|
|
pipe_tx1_char_is_k_i : in std_logic_vector(1 downto 0);
|
608 |
|
|
pipe_tx1_data_i : in std_logic_vector(15 downto 0);
|
609 |
|
|
pipe_tx1_elec_idle_i : in std_logic;
|
610 |
|
|
pipe_tx1_powerdown_i : in std_logic_vector(1 downto 0);
|
611 |
|
|
pipe_rx1_char_is_k_i : in std_logic_vector(1 downto 0);
|
612 |
|
|
pipe_rx1_data_i : in std_logic_vector(15 downto 0);
|
613 |
|
|
pipe_rx1_valid_i : in std_logic;
|
614 |
|
|
pipe_rx1_chanisaligned_i : in std_logic;
|
615 |
|
|
pipe_rx1_status_i : in std_logic_vector(2 downto 0);
|
616 |
|
|
pipe_rx1_phy_status_i : in std_logic;
|
617 |
|
|
pipe_rx1_elec_idle_i : in std_logic;
|
618 |
|
|
pipe_rx1_polarity_o : out std_logic;
|
619 |
|
|
pipe_tx1_compliance_o : out std_logic;
|
620 |
|
|
pipe_tx1_char_is_k_o : out std_logic_vector(1 downto 0);
|
621 |
|
|
pipe_tx1_data_o : out std_logic_vector(15 downto 0);
|
622 |
|
|
pipe_tx1_elec_idle_o : out std_logic;
|
623 |
|
|
pipe_tx1_powerdown_o : out std_logic_vector(1 downto 0);
|
624 |
|
|
pipe_rx2_char_is_k_o : out std_logic_vector(1 downto 0);
|
625 |
|
|
pipe_rx2_data_o : out std_logic_vector(15 downto 0);
|
626 |
|
|
pipe_rx2_valid_o : out std_logic;
|
627 |
|
|
pipe_rx2_chanisaligned_o : out std_logic;
|
628 |
|
|
pipe_rx2_status_o : out std_logic_vector(2 downto 0);
|
629 |
|
|
pipe_rx2_phy_status_o : out std_logic;
|
630 |
|
|
pipe_rx2_elec_idle_o : out std_logic;
|
631 |
|
|
pipe_rx2_polarity_i : in std_logic;
|
632 |
|
|
pipe_tx2_compliance_i : in std_logic;
|
633 |
|
|
pipe_tx2_char_is_k_i : in std_logic_vector(1 downto 0);
|
634 |
|
|
pipe_tx2_data_i : in std_logic_vector(15 downto 0);
|
635 |
|
|
pipe_tx2_elec_idle_i : in std_logic;
|
636 |
|
|
pipe_tx2_powerdown_i : in std_logic_vector(1 downto 0);
|
637 |
|
|
pipe_rx2_char_is_k_i : in std_logic_vector(1 downto 0);
|
638 |
|
|
pipe_rx2_data_i : in std_logic_vector(15 downto 0);
|
639 |
|
|
pipe_rx2_valid_i : in std_logic;
|
640 |
|
|
pipe_rx2_chanisaligned_i : in std_logic;
|
641 |
|
|
pipe_rx2_status_i : in std_logic_vector(2 downto 0);
|
642 |
|
|
pipe_rx2_phy_status_i : in std_logic;
|
643 |
|
|
pipe_rx2_elec_idle_i : in std_logic;
|
644 |
|
|
pipe_rx2_polarity_o : out std_logic;
|
645 |
|
|
pipe_tx2_compliance_o : out std_logic;
|
646 |
|
|
pipe_tx2_char_is_k_o : out std_logic_vector(1 downto 0);
|
647 |
|
|
pipe_tx2_data_o : out std_logic_vector(15 downto 0);
|
648 |
|
|
pipe_tx2_elec_idle_o : out std_logic;
|
649 |
|
|
pipe_tx2_powerdown_o : out std_logic_vector(1 downto 0);
|
650 |
|
|
pipe_rx3_char_is_k_o : out std_logic_vector(1 downto 0);
|
651 |
|
|
pipe_rx3_data_o : out std_logic_vector(15 downto 0);
|
652 |
|
|
pipe_rx3_valid_o : out std_logic;
|
653 |
|
|
pipe_rx3_chanisaligned_o : out std_logic;
|
654 |
|
|
pipe_rx3_status_o : out std_logic_vector(2 downto 0);
|
655 |
|
|
pipe_rx3_phy_status_o : out std_logic;
|
656 |
|
|
pipe_rx3_elec_idle_o : out std_logic;
|
657 |
|
|
pipe_rx3_polarity_i : in std_logic;
|
658 |
|
|
pipe_tx3_compliance_i : in std_logic;
|
659 |
|
|
pipe_tx3_char_is_k_i : in std_logic_vector(1 downto 0);
|
660 |
|
|
pipe_tx3_data_i : in std_logic_vector(15 downto 0);
|
661 |
|
|
pipe_tx3_elec_idle_i : in std_logic;
|
662 |
|
|
pipe_tx3_powerdown_i : in std_logic_vector(1 downto 0);
|
663 |
|
|
pipe_rx3_char_is_k_i : in std_logic_vector(1 downto 0);
|
664 |
|
|
pipe_rx3_data_i : in std_logic_vector(15 downto 0);
|
665 |
|
|
pipe_rx3_valid_i : in std_logic;
|
666 |
|
|
pipe_rx3_chanisaligned_i : in std_logic;
|
667 |
|
|
pipe_rx3_status_i : in std_logic_vector(2 downto 0);
|
668 |
|
|
pipe_rx3_phy_status_i : in std_logic;
|
669 |
|
|
pipe_rx3_elec_idle_i : in std_logic;
|
670 |
|
|
pipe_rx3_polarity_o : out std_logic;
|
671 |
|
|
pipe_tx3_compliance_o : out std_logic;
|
672 |
|
|
pipe_tx3_char_is_k_o : out std_logic_vector(1 downto 0);
|
673 |
|
|
pipe_tx3_data_o : out std_logic_vector(15 downto 0);
|
674 |
|
|
pipe_tx3_elec_idle_o : out std_logic;
|
675 |
|
|
pipe_tx3_powerdown_o : out std_logic_vector(1 downto 0);
|
676 |
|
|
pipe_rx4_char_is_k_o : out std_logic_vector(1 downto 0);
|
677 |
|
|
pipe_rx4_data_o : out std_logic_vector(15 downto 0);
|
678 |
|
|
pipe_rx4_valid_o : out std_logic;
|
679 |
|
|
pipe_rx4_chanisaligned_o : out std_logic;
|
680 |
|
|
pipe_rx4_status_o : out std_logic_vector(2 downto 0);
|
681 |
|
|
pipe_rx4_phy_status_o : out std_logic;
|
682 |
|
|
pipe_rx4_elec_idle_o : out std_logic;
|
683 |
|
|
pipe_rx4_polarity_i : in std_logic;
|
684 |
|
|
pipe_tx4_compliance_i : in std_logic;
|
685 |
|
|
pipe_tx4_char_is_k_i : in std_logic_vector(1 downto 0);
|
686 |
|
|
pipe_tx4_data_i : in std_logic_vector(15 downto 0);
|
687 |
|
|
pipe_tx4_elec_idle_i : in std_logic;
|
688 |
|
|
pipe_tx4_powerdown_i : in std_logic_vector(1 downto 0);
|
689 |
|
|
pipe_rx4_char_is_k_i : in std_logic_vector(1 downto 0);
|
690 |
|
|
pipe_rx4_data_i : in std_logic_vector(15 downto 0);
|
691 |
|
|
pipe_rx4_valid_i : in std_logic;
|
692 |
|
|
pipe_rx4_chanisaligned_i : in std_logic;
|
693 |
|
|
pipe_rx4_status_i : in std_logic_vector(2 downto 0);
|
694 |
|
|
pipe_rx4_phy_status_i : in std_logic;
|
695 |
|
|
pipe_rx4_elec_idle_i : in std_logic;
|
696 |
|
|
pipe_rx4_polarity_o : out std_logic;
|
697 |
|
|
pipe_tx4_compliance_o : out std_logic;
|
698 |
|
|
pipe_tx4_char_is_k_o : out std_logic_vector(1 downto 0);
|
699 |
|
|
pipe_tx4_data_o : out std_logic_vector(15 downto 0);
|
700 |
|
|
pipe_tx4_elec_idle_o : out std_logic;
|
701 |
|
|
pipe_tx4_powerdown_o : out std_logic_vector(1 downto 0);
|
702 |
|
|
pipe_rx5_char_is_k_o : out std_logic_vector(1 downto 0);
|
703 |
|
|
pipe_rx5_data_o : out std_logic_vector(15 downto 0);
|
704 |
|
|
pipe_rx5_valid_o : out std_logic;
|
705 |
|
|
pipe_rx5_chanisaligned_o : out std_logic;
|
706 |
|
|
pipe_rx5_status_o : out std_logic_vector(2 downto 0);
|
707 |
|
|
pipe_rx5_phy_status_o : out std_logic;
|
708 |
|
|
pipe_rx5_elec_idle_o : out std_logic;
|
709 |
|
|
pipe_rx5_polarity_i : in std_logic;
|
710 |
|
|
pipe_tx5_compliance_i : in std_logic;
|
711 |
|
|
pipe_tx5_char_is_k_i : in std_logic_vector(1 downto 0);
|
712 |
|
|
pipe_tx5_data_i : in std_logic_vector(15 downto 0);
|
713 |
|
|
pipe_tx5_elec_idle_i : in std_logic;
|
714 |
|
|
pipe_tx5_powerdown_i : in std_logic_vector(1 downto 0);
|
715 |
|
|
pipe_rx5_char_is_k_i : in std_logic_vector(1 downto 0);
|
716 |
|
|
pipe_rx5_data_i : in std_logic_vector(15 downto 0);
|
717 |
|
|
pipe_rx5_valid_i : in std_logic;
|
718 |
|
|
pipe_rx5_chanisaligned_i : in std_logic;
|
719 |
|
|
pipe_rx5_status_i : in std_logic_vector(2 downto 0);
|
720 |
|
|
pipe_rx5_phy_status_i : in std_logic;
|
721 |
|
|
pipe_rx5_elec_idle_i : in std_logic;
|
722 |
|
|
pipe_rx5_polarity_o : out std_logic;
|
723 |
|
|
pipe_tx5_compliance_o : out std_logic;
|
724 |
|
|
pipe_tx5_char_is_k_o : out std_logic_vector(1 downto 0);
|
725 |
|
|
pipe_tx5_data_o : out std_logic_vector(15 downto 0);
|
726 |
|
|
pipe_tx5_elec_idle_o : out std_logic;
|
727 |
|
|
pipe_tx5_powerdown_o : out std_logic_vector(1 downto 0);
|
728 |
|
|
pipe_rx6_char_is_k_o : out std_logic_vector(1 downto 0);
|
729 |
|
|
pipe_rx6_data_o : out std_logic_vector(15 downto 0);
|
730 |
|
|
pipe_rx6_valid_o : out std_logic;
|
731 |
|
|
pipe_rx6_chanisaligned_o : out std_logic;
|
732 |
|
|
pipe_rx6_status_o : out std_logic_vector(2 downto 0);
|
733 |
|
|
pipe_rx6_phy_status_o : out std_logic;
|
734 |
|
|
pipe_rx6_elec_idle_o : out std_logic;
|
735 |
|
|
pipe_rx6_polarity_i : in std_logic;
|
736 |
|
|
pipe_tx6_compliance_i : in std_logic;
|
737 |
|
|
pipe_tx6_char_is_k_i : in std_logic_vector(1 downto 0);
|
738 |
|
|
pipe_tx6_data_i : in std_logic_vector(15 downto 0);
|
739 |
|
|
pipe_tx6_elec_idle_i : in std_logic;
|
740 |
|
|
pipe_tx6_powerdown_i : in std_logic_vector(1 downto 0);
|
741 |
|
|
pipe_rx6_char_is_k_i : in std_logic_vector(1 downto 0);
|
742 |
|
|
pipe_rx6_data_i : in std_logic_vector(15 downto 0);
|
743 |
|
|
pipe_rx6_valid_i : in std_logic;
|
744 |
|
|
pipe_rx6_chanisaligned_i : in std_logic;
|
745 |
|
|
pipe_rx6_status_i : in std_logic_vector(2 downto 0);
|
746 |
|
|
pipe_rx6_phy_status_i : in std_logic;
|
747 |
|
|
pipe_rx6_elec_idle_i : in std_logic;
|
748 |
|
|
pipe_rx6_polarity_o : out std_logic;
|
749 |
|
|
pipe_tx6_compliance_o : out std_logic;
|
750 |
|
|
pipe_tx6_char_is_k_o : out std_logic_vector(1 downto 0);
|
751 |
|
|
pipe_tx6_data_o : out std_logic_vector(15 downto 0);
|
752 |
|
|
pipe_tx6_elec_idle_o : out std_logic;
|
753 |
|
|
pipe_tx6_powerdown_o : out std_logic_vector(1 downto 0);
|
754 |
|
|
pipe_rx7_char_is_k_o : out std_logic_vector(1 downto 0);
|
755 |
|
|
pipe_rx7_data_o : out std_logic_vector(15 downto 0);
|
756 |
|
|
pipe_rx7_valid_o : out std_logic;
|
757 |
|
|
pipe_rx7_chanisaligned_o : out std_logic;
|
758 |
|
|
pipe_rx7_status_o : out std_logic_vector(2 downto 0);
|
759 |
|
|
pipe_rx7_phy_status_o : out std_logic;
|
760 |
|
|
pipe_rx7_elec_idle_o : out std_logic;
|
761 |
|
|
pipe_rx7_polarity_i : in std_logic;
|
762 |
|
|
pipe_tx7_compliance_i : in std_logic;
|
763 |
|
|
pipe_tx7_char_is_k_i : in std_logic_vector(1 downto 0);
|
764 |
|
|
pipe_tx7_data_i : in std_logic_vector(15 downto 0);
|
765 |
|
|
pipe_tx7_elec_idle_i : in std_logic;
|
766 |
|
|
pipe_tx7_powerdown_i : in std_logic_vector(1 downto 0);
|
767 |
|
|
pipe_rx7_char_is_k_i : in std_logic_vector(1 downto 0);
|
768 |
|
|
pipe_rx7_data_i : in std_logic_vector(15 downto 0);
|
769 |
|
|
pipe_rx7_valid_i : in std_logic;
|
770 |
|
|
pipe_rx7_chanisaligned_i : in std_logic;
|
771 |
|
|
pipe_rx7_status_i : in std_logic_vector(2 downto 0);
|
772 |
|
|
pipe_rx7_phy_status_i : in std_logic;
|
773 |
|
|
pipe_rx7_elec_idle_i : in std_logic;
|
774 |
|
|
pipe_rx7_polarity_o : out std_logic;
|
775 |
|
|
pipe_tx7_compliance_o : out std_logic;
|
776 |
|
|
pipe_tx7_char_is_k_o : out std_logic_vector(1 downto 0);
|
777 |
|
|
pipe_tx7_data_o : out std_logic_vector(15 downto 0);
|
778 |
|
|
pipe_tx7_elec_idle_o : out std_logic;
|
779 |
|
|
pipe_tx7_powerdown_o : out std_logic_vector(1 downto 0);
|
780 |
|
|
pl_ltssm_state : in std_logic_vector(5 downto 0);
|
781 |
|
|
pipe_clk : in std_logic;
|
782 |
|
|
rst_n : in std_logic);
|
783 |
|
|
end component;
|
784 |
|
|
|
785 |
|
|
component pcie_gtx_v6
|
786 |
|
|
generic (
|
787 |
|
|
NO_OF_LANES : integer;
|
788 |
|
|
LINK_CAP_MAX_LINK_SPEED : bit_vector;
|
789 |
|
|
REF_CLK_FREQ : integer;
|
790 |
|
|
PL_FAST_TRAIN : boolean);
|
791 |
|
|
port (
|
792 |
|
|
pipe_tx_rcvr_det : in std_logic;
|
793 |
|
|
pipe_tx_reset : in std_logic;
|
794 |
|
|
pipe_tx_rate : in std_logic;
|
795 |
|
|
pipe_tx_deemph : in std_logic;
|
796 |
|
|
pipe_tx_margin : in std_logic_vector(2 downto 0);
|
797 |
|
|
pipe_tx_swing : in std_logic;
|
798 |
|
|
pipe_rx0_char_is_k : out std_logic_vector(1 downto 0);
|
799 |
|
|
pipe_rx0_data : out std_logic_vector(15 downto 0);
|
800 |
|
|
pipe_rx0_valid : out std_logic;
|
801 |
|
|
pipe_rx0_chanisaligned : out std_logic;
|
802 |
|
|
pipe_rx0_status : out std_logic_vector(2 downto 0);
|
803 |
|
|
pipe_rx0_phy_status : out std_logic;
|
804 |
|
|
pipe_rx0_elec_idle : out std_logic;
|
805 |
|
|
pipe_rx0_polarity : in std_logic;
|
806 |
|
|
pipe_tx0_compliance : in std_logic;
|
807 |
|
|
pipe_tx0_char_is_k : in std_logic_vector(1 downto 0);
|
808 |
|
|
pipe_tx0_data : in std_logic_vector(15 downto 0);
|
809 |
|
|
pipe_tx0_elec_idle : in std_logic;
|
810 |
|
|
pipe_tx0_powerdown : in std_logic_vector(1 downto 0);
|
811 |
|
|
pipe_rx1_char_is_k : out std_logic_vector(1 downto 0);
|
812 |
|
|
pipe_rx1_data : out std_logic_vector(15 downto 0);
|
813 |
|
|
pipe_rx1_valid : out std_logic;
|
814 |
|
|
pipe_rx1_chanisaligned : out std_logic;
|
815 |
|
|
pipe_rx1_status : out std_logic_vector(2 downto 0);
|
816 |
|
|
pipe_rx1_phy_status : out std_logic;
|
817 |
|
|
pipe_rx1_elec_idle : out std_logic;
|
818 |
|
|
pipe_rx1_polarity : in std_logic;
|
819 |
|
|
pipe_tx1_compliance : in std_logic;
|
820 |
|
|
pipe_tx1_char_is_k : in std_logic_vector(1 downto 0);
|
821 |
|
|
pipe_tx1_data : in std_logic_vector(15 downto 0);
|
822 |
|
|
pipe_tx1_elec_idle : in std_logic;
|
823 |
|
|
pipe_tx1_powerdown : in std_logic_vector(1 downto 0);
|
824 |
|
|
pipe_rx2_char_is_k : out std_logic_vector(1 downto 0);
|
825 |
|
|
pipe_rx2_data : out std_logic_vector(15 downto 0);
|
826 |
|
|
pipe_rx2_valid : out std_logic;
|
827 |
|
|
pipe_rx2_chanisaligned : out std_logic;
|
828 |
|
|
pipe_rx2_status : out std_logic_vector(2 downto 0);
|
829 |
|
|
pipe_rx2_phy_status : out std_logic;
|
830 |
|
|
pipe_rx2_elec_idle : out std_logic;
|
831 |
|
|
pipe_rx2_polarity : in std_logic;
|
832 |
|
|
pipe_tx2_compliance : in std_logic;
|
833 |
|
|
pipe_tx2_char_is_k : in std_logic_vector(1 downto 0);
|
834 |
|
|
pipe_tx2_data : in std_logic_vector(15 downto 0);
|
835 |
|
|
pipe_tx2_elec_idle : in std_logic;
|
836 |
|
|
pipe_tx2_powerdown : in std_logic_vector(1 downto 0);
|
837 |
|
|
pipe_rx3_char_is_k : out std_logic_vector(1 downto 0);
|
838 |
|
|
pipe_rx3_data : out std_logic_vector(15 downto 0);
|
839 |
|
|
pipe_rx3_valid : out std_logic;
|
840 |
|
|
pipe_rx3_chanisaligned : out std_logic;
|
841 |
|
|
pipe_rx3_status : out std_logic_vector(2 downto 0);
|
842 |
|
|
pipe_rx3_phy_status : out std_logic;
|
843 |
|
|
pipe_rx3_elec_idle : out std_logic;
|
844 |
|
|
pipe_rx3_polarity : in std_logic;
|
845 |
|
|
pipe_tx3_compliance : in std_logic;
|
846 |
|
|
pipe_tx3_char_is_k : in std_logic_vector(1 downto 0);
|
847 |
|
|
pipe_tx3_data : in std_logic_vector(15 downto 0);
|
848 |
|
|
pipe_tx3_elec_idle : in std_logic;
|
849 |
|
|
pipe_tx3_powerdown : in std_logic_vector(1 downto 0);
|
850 |
|
|
pipe_rx4_char_is_k : out std_logic_vector(1 downto 0);
|
851 |
|
|
pipe_rx4_data : out std_logic_vector(15 downto 0);
|
852 |
|
|
pipe_rx4_valid : out std_logic;
|
853 |
|
|
pipe_rx4_chanisaligned : out std_logic;
|
854 |
|
|
pipe_rx4_status : out std_logic_vector(2 downto 0);
|
855 |
|
|
pipe_rx4_phy_status : out std_logic;
|
856 |
|
|
pipe_rx4_elec_idle : out std_logic;
|
857 |
|
|
pipe_rx4_polarity : in std_logic;
|
858 |
|
|
pipe_tx4_compliance : in std_logic;
|
859 |
|
|
pipe_tx4_char_is_k : in std_logic_vector(1 downto 0);
|
860 |
|
|
pipe_tx4_data : in std_logic_vector(15 downto 0);
|
861 |
|
|
pipe_tx4_elec_idle : in std_logic;
|
862 |
|
|
pipe_tx4_powerdown : in std_logic_vector(1 downto 0);
|
863 |
|
|
pipe_rx5_char_is_k : out std_logic_vector(1 downto 0);
|
864 |
|
|
pipe_rx5_data : out std_logic_vector(15 downto 0);
|
865 |
|
|
pipe_rx5_valid : out std_logic;
|
866 |
|
|
pipe_rx5_chanisaligned : out std_logic;
|
867 |
|
|
pipe_rx5_status : out std_logic_vector(2 downto 0);
|
868 |
|
|
pipe_rx5_phy_status : out std_logic;
|
869 |
|
|
pipe_rx5_elec_idle : out std_logic;
|
870 |
|
|
pipe_rx5_polarity : in std_logic;
|
871 |
|
|
pipe_tx5_compliance : in std_logic;
|
872 |
|
|
pipe_tx5_char_is_k : in std_logic_vector(1 downto 0);
|
873 |
|
|
pipe_tx5_data : in std_logic_vector(15 downto 0);
|
874 |
|
|
pipe_tx5_elec_idle : in std_logic;
|
875 |
|
|
pipe_tx5_powerdown : in std_logic_vector(1 downto 0);
|
876 |
|
|
pipe_rx6_char_is_k : out std_logic_vector(1 downto 0);
|
877 |
|
|
pipe_rx6_data : out std_logic_vector(15 downto 0);
|
878 |
|
|
pipe_rx6_valid : out std_logic;
|
879 |
|
|
pipe_rx6_chanisaligned : out std_logic;
|
880 |
|
|
pipe_rx6_status : out std_logic_vector(2 downto 0);
|
881 |
|
|
pipe_rx6_phy_status : out std_logic;
|
882 |
|
|
pipe_rx6_elec_idle : out std_logic;
|
883 |
|
|
pipe_rx6_polarity : in std_logic;
|
884 |
|
|
pipe_tx6_compliance : in std_logic;
|
885 |
|
|
pipe_tx6_char_is_k : in std_logic_vector(1 downto 0);
|
886 |
|
|
pipe_tx6_data : in std_logic_vector(15 downto 0);
|
887 |
|
|
pipe_tx6_elec_idle : in std_logic;
|
888 |
|
|
pipe_tx6_powerdown : in std_logic_vector(1 downto 0);
|
889 |
|
|
pipe_rx7_char_is_k : out std_logic_vector(1 downto 0);
|
890 |
|
|
pipe_rx7_data : out std_logic_vector(15 downto 0);
|
891 |
|
|
pipe_rx7_valid : out std_logic;
|
892 |
|
|
pipe_rx7_chanisaligned : out std_logic;
|
893 |
|
|
pipe_rx7_status : out std_logic_vector(2 downto 0);
|
894 |
|
|
pipe_rx7_phy_status : out std_logic;
|
895 |
|
|
pipe_rx7_elec_idle : out std_logic;
|
896 |
|
|
pipe_rx7_polarity : in std_logic;
|
897 |
|
|
pipe_tx7_compliance : in std_logic;
|
898 |
|
|
pipe_tx7_char_is_k : in std_logic_vector(1 downto 0);
|
899 |
|
|
pipe_tx7_data : in std_logic_vector(15 downto 0);
|
900 |
|
|
pipe_tx7_elec_idle : in std_logic;
|
901 |
|
|
pipe_tx7_powerdown : in std_logic_vector(1 downto 0);
|
902 |
|
|
pci_exp_txn : out std_logic_vector((NO_OF_LANES - 1) downto 0);
|
903 |
|
|
pci_exp_txp : out std_logic_vector((NO_OF_LANES - 1) downto 0);
|
904 |
|
|
pci_exp_rxn : in std_logic_vector((NO_OF_LANES - 1) downto 0);
|
905 |
|
|
pci_exp_rxp : in std_logic_vector((NO_OF_LANES - 1) downto 0);
|
906 |
|
|
sys_clk : in std_logic;
|
907 |
|
|
sys_rst_n : in std_logic;
|
908 |
|
|
pipe_clk : in std_logic;
|
909 |
|
|
drp_clk : in std_logic;
|
910 |
|
|
clock_locked : in std_logic;
|
911 |
|
|
gt_pll_lock : out std_logic;
|
912 |
|
|
pl_ltssm_state : in std_logic_vector(5 downto 0);
|
913 |
|
|
phy_rdy_n : out std_logic;
|
914 |
|
|
TxOutClk : out std_logic);
|
915 |
|
|
end component;
|
916 |
|
|
|
917 |
|
|
component pcie_bram_top_v6
|
918 |
|
|
generic (
|
919 |
|
|
DEV_CAP_MAX_PAYLOAD_SUPPORTED : integer;
|
920 |
|
|
VC0_TX_LASTPACKET : integer;
|
921 |
|
|
TL_TX_RAM_RADDR_LATENCY : integer;
|
922 |
|
|
TL_TX_RAM_RDATA_LATENCY : integer;
|
923 |
|
|
TL_TX_RAM_WRITE_LATENCY : integer;
|
924 |
|
|
VC0_RX_LIMIT : bit_vector;
|
925 |
|
|
TL_RX_RAM_RADDR_LATENCY : integer;
|
926 |
|
|
TL_RX_RAM_RDATA_LATENCY : integer;
|
927 |
|
|
TL_RX_RAM_WRITE_LATENCY : integer);
|
928 |
|
|
port (
|
929 |
|
|
user_clk_i : in std_logic;
|
930 |
|
|
reset_i : in std_logic;
|
931 |
|
|
mim_tx_wen : in std_logic;
|
932 |
|
|
mim_tx_waddr : in std_logic_vector(12 downto 0);
|
933 |
|
|
mim_tx_wdata : in std_logic_vector(71 downto 0);
|
934 |
|
|
mim_tx_ren : in std_logic;
|
935 |
|
|
mim_tx_rce : in std_logic;
|
936 |
|
|
mim_tx_raddr : in std_logic_vector(12 downto 0);
|
937 |
|
|
mim_tx_rdata : out std_logic_vector(71 downto 0);
|
938 |
|
|
mim_rx_wen : in std_logic;
|
939 |
|
|
mim_rx_waddr : in std_logic_vector(12 downto 0);
|
940 |
|
|
mim_rx_wdata : in std_logic_vector(71 downto 0);
|
941 |
|
|
mim_rx_ren : in std_logic;
|
942 |
|
|
mim_rx_rce : in std_logic;
|
943 |
|
|
mim_rx_raddr : in std_logic_vector(12 downto 0);
|
944 |
|
|
mim_rx_rdata : out std_logic_vector(71 downto 0));
|
945 |
|
|
end component;
|
946 |
|
|
|
947 |
|
|
component pcie_upconfig_fix_3451_v6
|
948 |
|
|
generic (
|
949 |
|
|
UPSTREAM_FACING : boolean;
|
950 |
|
|
PL_FAST_TRAIN : boolean;
|
951 |
|
|
LINK_CAP_MAX_LINK_WIDTH : bit_vector);
|
952 |
|
|
port (
|
953 |
|
|
pipe_clk : in std_logic;
|
954 |
|
|
pl_phy_lnkup_n : in std_logic;
|
955 |
|
|
pl_ltssm_state : in std_logic_vector(5 downto 0);
|
956 |
|
|
pl_sel_lnk_rate : in std_logic;
|
957 |
|
|
pl_directed_link_change : in std_logic_vector(1 downto 0);
|
958 |
|
|
cfg_link_status_negotiated_width : in std_logic_vector(3 downto 0);
|
959 |
|
|
pipe_rx0_data : in std_logic_vector(15 downto 0);
|
960 |
|
|
pipe_rx0_char_isk : in std_logic_vector(1 downto 0);
|
961 |
|
|
filter_pipe : out std_logic);
|
962 |
|
|
end component;
|
963 |
|
|
|
964 |
|
|
-- wire declarations
|
965 |
|
|
|
966 |
|
|
signal LL2BADDLLPERRN : std_logic;
|
967 |
|
|
signal LL2BADTLPERRN : std_logic;
|
968 |
|
|
signal LL2PROTOCOLERRN : std_logic;
|
969 |
|
|
signal LL2REPLAYROERRN : std_logic;
|
970 |
|
|
signal LL2REPLAYTOERRN : std_logic;
|
971 |
|
|
signal LL2SUSPENDOKN : std_logic;
|
972 |
|
|
signal LL2TFCINIT1SEQN : std_logic;
|
973 |
|
|
signal LL2TFCINIT2SEQN : std_logic;
|
974 |
|
|
signal MIMRXRADDR : std_logic_vector(12 downto 0);
|
975 |
|
|
signal MIMRXRCE : std_logic;
|
976 |
|
|
signal MIMRXREN : std_logic;
|
977 |
|
|
signal MIMRXWADDR : std_logic_vector(12 downto 0);
|
978 |
|
|
signal MIMRXWDATA : std_logic_vector(67 downto 0);
|
979 |
|
|
signal MIMRXWDATA_tmp : std_logic_vector(71 downto 0);
|
980 |
|
|
signal MIMRXWEN : std_logic;
|
981 |
|
|
signal MIMTXRADDR : std_logic_vector(12 downto 0);
|
982 |
|
|
signal MIMTXRCE : std_logic;
|
983 |
|
|
signal MIMTXREN : std_logic;
|
984 |
|
|
signal MIMTXWADDR : std_logic_vector(12 downto 0);
|
985 |
|
|
signal MIMTXWDATA : std_logic_vector(68 downto 0);
|
986 |
|
|
signal MIMTXWDATA_tmp : std_logic_vector(71 downto 0);
|
987 |
|
|
signal MIMTXWEN : std_logic;
|
988 |
|
|
signal PIPERX0POLARITY : std_logic;
|
989 |
|
|
signal PIPERX1POLARITY : std_logic;
|
990 |
|
|
signal PIPERX2POLARITY : std_logic;
|
991 |
|
|
signal PIPERX3POLARITY : std_logic;
|
992 |
|
|
signal PIPERX4POLARITY : std_logic;
|
993 |
|
|
signal PIPERX5POLARITY : std_logic;
|
994 |
|
|
signal PIPERX6POLARITY : std_logic;
|
995 |
|
|
signal PIPERX7POLARITY : std_logic;
|
996 |
|
|
signal PIPETXDEEMPH : std_logic;
|
997 |
|
|
signal PIPETXMARGIN : std_logic_vector(2 downto 0);
|
998 |
|
|
signal PIPETXRATE : std_logic;
|
999 |
|
|
signal PIPETXRCVRDET : std_logic;
|
1000 |
|
|
signal PIPETXRESET : std_logic;
|
1001 |
|
|
signal PIPETX0CHARISK : std_logic_vector(1 downto 0);
|
1002 |
|
|
signal PIPETX0COMPLIANCE : std_logic;
|
1003 |
|
|
signal PIPETX0DATA : std_logic_vector(15 downto 0);
|
1004 |
|
|
signal PIPETX0ELECIDLE : std_logic;
|
1005 |
|
|
signal PIPETX0POWERDOWN : std_logic_vector(1 downto 0);
|
1006 |
|
|
signal PIPETX1CHARISK : std_logic_vector(1 downto 0);
|
1007 |
|
|
signal PIPETX1COMPLIANCE : std_logic;
|
1008 |
|
|
signal PIPETX1DATA : std_logic_vector(15 downto 0);
|
1009 |
|
|
signal PIPETX1ELECIDLE : std_logic;
|
1010 |
|
|
signal PIPETX1POWERDOWN : std_logic_vector(1 downto 0);
|
1011 |
|
|
signal PIPETX2CHARISK : std_logic_vector(1 downto 0);
|
1012 |
|
|
signal PIPETX2COMPLIANCE : std_logic;
|
1013 |
|
|
signal PIPETX2DATA : std_logic_vector(15 downto 0);
|
1014 |
|
|
signal PIPETX2ELECIDLE : std_logic;
|
1015 |
|
|
signal PIPETX2POWERDOWN : std_logic_vector(1 downto 0);
|
1016 |
|
|
signal PIPETX3CHARISK : std_logic_vector(1 downto 0);
|
1017 |
|
|
signal PIPETX3COMPLIANCE : std_logic;
|
1018 |
|
|
signal PIPETX3DATA : std_logic_vector(15 downto 0);
|
1019 |
|
|
signal PIPETX3ELECIDLE : std_logic;
|
1020 |
|
|
signal PIPETX3POWERDOWN : std_logic_vector(1 downto 0);
|
1021 |
|
|
signal PIPETX4CHARISK : std_logic_vector(1 downto 0);
|
1022 |
|
|
signal PIPETX4COMPLIANCE : std_logic;
|
1023 |
|
|
signal PIPETX4DATA : std_logic_vector(15 downto 0);
|
1024 |
|
|
signal PIPETX4ELECIDLE : std_logic;
|
1025 |
|
|
signal PIPETX4POWERDOWN : std_logic_vector(1 downto 0);
|
1026 |
|
|
signal PIPETX5CHARISK : std_logic_vector(1 downto 0);
|
1027 |
|
|
signal PIPETX5COMPLIANCE : std_logic;
|
1028 |
|
|
signal PIPETX5DATA : std_logic_vector(15 downto 0);
|
1029 |
|
|
signal PIPETX5ELECIDLE : std_logic;
|
1030 |
|
|
signal PIPETX5POWERDOWN : std_logic_vector(1 downto 0);
|
1031 |
|
|
signal PIPETX6CHARISK : std_logic_vector(1 downto 0);
|
1032 |
|
|
signal PIPETX6COMPLIANCE : std_logic;
|
1033 |
|
|
signal PIPETX6DATA : std_logic_vector(15 downto 0);
|
1034 |
|
|
signal PIPETX6ELECIDLE : std_logic;
|
1035 |
|
|
signal PIPETX6POWERDOWN : std_logic_vector(1 downto 0);
|
1036 |
|
|
signal PIPETX7CHARISK : std_logic_vector(1 downto 0);
|
1037 |
|
|
signal PIPETX7COMPLIANCE : std_logic;
|
1038 |
|
|
signal PIPETX7DATA : std_logic_vector(15 downto 0);
|
1039 |
|
|
signal PIPETX7ELECIDLE : std_logic;
|
1040 |
|
|
signal PIPETX7POWERDOWN : std_logic_vector(1 downto 0);
|
1041 |
|
|
signal PL2LINKUPN : std_logic;
|
1042 |
|
|
signal PL2RECEIVERERRN : std_logic;
|
1043 |
|
|
signal PL2RECOVERYN : std_logic;
|
1044 |
|
|
signal PL2RXELECIDLE : std_logic;
|
1045 |
|
|
signal PL2SUSPENDOK : std_logic;
|
1046 |
|
|
signal TL2ASPMSUSPENDCREDITCHECKOKN : std_logic;
|
1047 |
|
|
signal TL2ASPMSUSPENDREQN : std_logic;
|
1048 |
|
|
signal TL2PPMSUSPENDOKN : std_logic;
|
1049 |
|
|
signal LL2SENDASREQL1N : std_logic;
|
1050 |
|
|
signal LL2SENDENTERL1N : std_logic;
|
1051 |
|
|
signal LL2SENDENTERL23N : std_logic;
|
1052 |
|
|
signal LL2SUSPENDNOWN : std_logic;
|
1053 |
|
|
signal LL2TLPRCVN : std_logic;
|
1054 |
|
|
signal MIMRXRDATA : std_logic_vector(71 downto 0);
|
1055 |
|
|
signal MIMTXRDATA : std_logic_vector(71 downto 0);
|
1056 |
|
|
signal PL2DIRECTEDLSTATE : std_logic_vector(4 downto 0);
|
1057 |
|
|
signal TL2ASPMSUSPENDCREDITCHECKN : std_logic;
|
1058 |
|
|
signal TL2PPMSUSPENDREQN : std_logic;
|
1059 |
|
|
signal PIPERX0CHANISALIGNED : std_logic;
|
1060 |
|
|
signal PIPERX0CHARISK : std_logic_vector(1 downto 0);
|
1061 |
|
|
signal PIPERX0DATA : std_logic_vector(15 downto 0);
|
1062 |
|
|
signal PIPERX0ELECIDLE : std_logic;
|
1063 |
|
|
signal PIPERX0PHYSTATUS : std_logic;
|
1064 |
|
|
signal PIPERX0STATUS : std_logic_vector(2 downto 0);
|
1065 |
|
|
signal PIPERX0VALID : std_logic;
|
1066 |
|
|
signal PIPERX1CHANISALIGNED : std_logic;
|
1067 |
|
|
signal PIPERX1CHARISK : std_logic_vector(1 downto 0);
|
1068 |
|
|
signal PIPERX1DATA : std_logic_vector(15 downto 0);
|
1069 |
|
|
signal PIPERX1ELECIDLE : std_logic;
|
1070 |
|
|
signal PIPERX1PHYSTATUS : std_logic;
|
1071 |
|
|
signal PIPERX1STATUS : std_logic_vector(2 downto 0);
|
1072 |
|
|
signal PIPERX1VALID : std_logic;
|
1073 |
|
|
signal PIPERX2CHANISALIGNED : std_logic;
|
1074 |
|
|
signal PIPERX2CHARISK : std_logic_vector(1 downto 0);
|
1075 |
|
|
signal PIPERX2DATA : std_logic_vector(15 downto 0);
|
1076 |
|
|
signal PIPERX2ELECIDLE : std_logic;
|
1077 |
|
|
signal PIPERX2PHYSTATUS : std_logic;
|
1078 |
|
|
signal PIPERX2STATUS : std_logic_vector(2 downto 0);
|
1079 |
|
|
signal PIPERX2VALID : std_logic;
|
1080 |
|
|
signal PIPERX3CHANISALIGNED : std_logic;
|
1081 |
|
|
signal PIPERX3CHARISK : std_logic_vector(1 downto 0);
|
1082 |
|
|
signal PIPERX3DATA : std_logic_vector(15 downto 0);
|
1083 |
|
|
signal PIPERX3ELECIDLE : std_logic;
|
1084 |
|
|
signal PIPERX3PHYSTATUS : std_logic;
|
1085 |
|
|
signal PIPERX3STATUS : std_logic_vector(2 downto 0);
|
1086 |
|
|
signal PIPERX3VALID : std_logic;
|
1087 |
|
|
signal PIPERX4CHANISALIGNED : std_logic;
|
1088 |
|
|
signal PIPERX4CHARISK : std_logic_vector(1 downto 0);
|
1089 |
|
|
signal PIPERX4DATA : std_logic_vector(15 downto 0);
|
1090 |
|
|
signal PIPERX4ELECIDLE : std_logic;
|
1091 |
|
|
signal PIPERX4PHYSTATUS : std_logic;
|
1092 |
|
|
signal PIPERX4STATUS : std_logic_vector(2 downto 0);
|
1093 |
|
|
signal PIPERX4VALID : std_logic;
|
1094 |
|
|
signal PIPERX5CHANISALIGNED : std_logic;
|
1095 |
|
|
signal PIPERX5CHARISK : std_logic_vector(1 downto 0);
|
1096 |
|
|
signal PIPERX5DATA : std_logic_vector(15 downto 0);
|
1097 |
|
|
signal PIPERX5ELECIDLE : std_logic;
|
1098 |
|
|
signal PIPERX5PHYSTATUS : std_logic;
|
1099 |
|
|
signal PIPERX5STATUS : std_logic_vector(2 downto 0);
|
1100 |
|
|
signal PIPERX5VALID : std_logic;
|
1101 |
|
|
signal PIPERX6CHANISALIGNED : std_logic;
|
1102 |
|
|
signal PIPERX6CHARISK : std_logic_vector(1 downto 0);
|
1103 |
|
|
signal PIPERX6DATA : std_logic_vector(15 downto 0);
|
1104 |
|
|
signal PIPERX6ELECIDLE : std_logic;
|
1105 |
|
|
signal PIPERX6PHYSTATUS : std_logic;
|
1106 |
|
|
signal PIPERX6STATUS : std_logic_vector(2 downto 0);
|
1107 |
|
|
signal PIPERX6VALID : std_logic;
|
1108 |
|
|
signal PIPERX7CHANISALIGNED : std_logic;
|
1109 |
|
|
signal PIPERX7CHARISK : std_logic_vector(1 downto 0);
|
1110 |
|
|
signal PIPERX7DATA : std_logic_vector(15 downto 0);
|
1111 |
|
|
signal PIPERX7ELECIDLE : std_logic;
|
1112 |
|
|
signal PIPERX7PHYSTATUS : std_logic;
|
1113 |
|
|
signal PIPERX7STATUS : std_logic_vector(2 downto 0);
|
1114 |
|
|
signal PIPERX7VALID : std_logic;
|
1115 |
|
|
|
1116 |
|
|
signal PIPERX0POLARITYGT : std_logic;
|
1117 |
|
|
signal PIPERX1POLARITYGT : std_logic;
|
1118 |
|
|
signal PIPERX2POLARITYGT : std_logic;
|
1119 |
|
|
signal PIPERX3POLARITYGT : std_logic;
|
1120 |
|
|
signal PIPERX4POLARITYGT : std_logic;
|
1121 |
|
|
signal PIPERX5POLARITYGT : std_logic;
|
1122 |
|
|
signal PIPERX6POLARITYGT : std_logic;
|
1123 |
|
|
signal PIPERX7POLARITYGT : std_logic;
|
1124 |
|
|
signal PIPETXDEEMPHGT : std_logic;
|
1125 |
|
|
signal PIPETXMARGINGT : std_logic_vector(2 downto 0);
|
1126 |
|
|
signal PIPETXRATEGT : std_logic;
|
1127 |
|
|
signal PIPETXRCVRDETGT : std_logic;
|
1128 |
|
|
signal PIPETX0CHARISKGT : std_logic_vector(1 downto 0);
|
1129 |
|
|
signal PIPETX0COMPLIANCEGT : std_logic;
|
1130 |
|
|
signal PIPETX0DATAGT : std_logic_vector(15 downto 0);
|
1131 |
|
|
signal PIPETX0ELECIDLEGT : std_logic;
|
1132 |
|
|
signal PIPETX0POWERDOWNGT : std_logic_vector(1 downto 0);
|
1133 |
|
|
signal PIPETX1CHARISKGT : std_logic_vector(1 downto 0);
|
1134 |
|
|
signal PIPETX1COMPLIANCEGT : std_logic;
|
1135 |
|
|
signal PIPETX1DATAGT : std_logic_vector(15 downto 0);
|
1136 |
|
|
signal PIPETX1ELECIDLEGT : std_logic;
|
1137 |
|
|
signal PIPETX1POWERDOWNGT : std_logic_vector(1 downto 0);
|
1138 |
|
|
signal PIPETX2CHARISKGT : std_logic_vector(1 downto 0);
|
1139 |
|
|
signal PIPETX2COMPLIANCEGT : std_logic;
|
1140 |
|
|
signal PIPETX2DATAGT : std_logic_vector(15 downto 0);
|
1141 |
|
|
signal PIPETX2ELECIDLEGT : std_logic;
|
1142 |
|
|
signal PIPETX2POWERDOWNGT : std_logic_vector(1 downto 0);
|
1143 |
|
|
signal PIPETX3CHARISKGT : std_logic_vector(1 downto 0);
|
1144 |
|
|
signal PIPETX3COMPLIANCEGT : std_logic;
|
1145 |
|
|
signal PIPETX3DATAGT : std_logic_vector(15 downto 0);
|
1146 |
|
|
signal PIPETX3ELECIDLEGT : std_logic;
|
1147 |
|
|
signal PIPETX3POWERDOWNGT : std_logic_vector(1 downto 0);
|
1148 |
|
|
signal PIPETX4CHARISKGT : std_logic_vector(1 downto 0);
|
1149 |
|
|
signal PIPETX4COMPLIANCEGT : std_logic;
|
1150 |
|
|
signal PIPETX4DATAGT : std_logic_vector(15 downto 0);
|
1151 |
|
|
signal PIPETX4ELECIDLEGT : std_logic;
|
1152 |
|
|
signal PIPETX4POWERDOWNGT : std_logic_vector(1 downto 0);
|
1153 |
|
|
signal PIPETX5CHARISKGT : std_logic_vector(1 downto 0);
|
1154 |
|
|
signal PIPETX5COMPLIANCEGT : std_logic;
|
1155 |
|
|
signal PIPETX5DATAGT : std_logic_vector(15 downto 0);
|
1156 |
|
|
signal PIPETX5ELECIDLEGT : std_logic;
|
1157 |
|
|
signal PIPETX5POWERDOWNGT : std_logic_vector(1 downto 0);
|
1158 |
|
|
signal PIPETX6CHARISKGT : std_logic_vector(1 downto 0);
|
1159 |
|
|
signal PIPETX6COMPLIANCEGT : std_logic;
|
1160 |
|
|
signal PIPETX6DATAGT : std_logic_vector(15 downto 0);
|
1161 |
|
|
signal PIPETX6ELECIDLEGT : std_logic;
|
1162 |
|
|
signal PIPETX6POWERDOWNGT : std_logic_vector(1 downto 0);
|
1163 |
|
|
signal PIPETX7CHARISKGT : std_logic_vector(1 downto 0);
|
1164 |
|
|
signal PIPETX7COMPLIANCEGT : std_logic;
|
1165 |
|
|
signal PIPETX7DATAGT : std_logic_vector(15 downto 0);
|
1166 |
|
|
signal PIPETX7ELECIDLEGT : std_logic;
|
1167 |
|
|
signal PIPETX7POWERDOWNGT : std_logic_vector(1 downto 0);
|
1168 |
|
|
|
1169 |
|
|
signal PIPERX0CHANISALIGNEDGT : std_logic;
|
1170 |
|
|
signal PIPERX0CHARISKGT : std_logic_vector(1 downto 0);
|
1171 |
|
|
signal PIPERX0DATAGT : std_logic_vector(15 downto 0);
|
1172 |
|
|
signal PIPERX0ELECIDLEGT : std_logic;
|
1173 |
|
|
signal PIPERX0PHYSTATUSGT : std_logic;
|
1174 |
|
|
signal PIPERX0STATUSGT : std_logic_vector(2 downto 0);
|
1175 |
|
|
signal PIPERX0VALIDGT : std_logic;
|
1176 |
|
|
signal PIPERX1CHANISALIGNEDGT : std_logic;
|
1177 |
|
|
signal PIPERX1CHARISKGT : std_logic_vector(1 downto 0);
|
1178 |
|
|
signal PIPERX1DATAGT : std_logic_vector(15 downto 0);
|
1179 |
|
|
signal PIPERX1ELECIDLEGT : std_logic;
|
1180 |
|
|
signal PIPERX1PHYSTATUSGT : std_logic;
|
1181 |
|
|
signal PIPERX1STATUSGT : std_logic_vector(2 downto 0);
|
1182 |
|
|
signal PIPERX1VALIDGT : std_logic;
|
1183 |
|
|
signal PIPERX2CHANISALIGNEDGT : std_logic;
|
1184 |
|
|
signal PIPERX2CHARISKGT : std_logic_vector(1 downto 0);
|
1185 |
|
|
signal PIPERX2DATAGT : std_logic_vector(15 downto 0);
|
1186 |
|
|
signal PIPERX2ELECIDLEGT : std_logic;
|
1187 |
|
|
signal PIPERX2PHYSTATUSGT : std_logic;
|
1188 |
|
|
signal PIPERX2STATUSGT : std_logic_vector(2 downto 0);
|
1189 |
|
|
signal PIPERX2VALIDGT : std_logic;
|
1190 |
|
|
signal PIPERX3CHANISALIGNEDGT : std_logic;
|
1191 |
|
|
signal PIPERX3CHARISKGT : std_logic_vector(1 downto 0);
|
1192 |
|
|
signal PIPERX3DATAGT : std_logic_vector(15 downto 0);
|
1193 |
|
|
signal PIPERX3ELECIDLEGT : std_logic;
|
1194 |
|
|
signal PIPERX3PHYSTATUSGT : std_logic;
|
1195 |
|
|
signal PIPERX3STATUSGT : std_logic_vector(2 downto 0);
|
1196 |
|
|
signal PIPERX3VALIDGT : std_logic;
|
1197 |
|
|
signal PIPERX4CHANISALIGNEDGT : std_logic;
|
1198 |
|
|
signal PIPERX4CHARISKGT : std_logic_vector(1 downto 0);
|
1199 |
|
|
signal PIPERX4DATAGT : std_logic_vector(15 downto 0);
|
1200 |
|
|
signal PIPERX4ELECIDLEGT : std_logic;
|
1201 |
|
|
signal PIPERX4PHYSTATUSGT : std_logic;
|
1202 |
|
|
signal PIPERX4STATUSGT : std_logic_vector(2 downto 0);
|
1203 |
|
|
signal PIPERX4VALIDGT : std_logic;
|
1204 |
|
|
signal PIPERX5CHANISALIGNEDGT : std_logic;
|
1205 |
|
|
signal PIPERX5CHARISKGT : std_logic_vector(1 downto 0);
|
1206 |
|
|
signal PIPERX5DATAGT : std_logic_vector(15 downto 0);
|
1207 |
|
|
signal PIPERX5ELECIDLEGT : std_logic;
|
1208 |
|
|
signal PIPERX5PHYSTATUSGT : std_logic;
|
1209 |
|
|
signal PIPERX5STATUSGT : std_logic_vector(2 downto 0);
|
1210 |
|
|
signal PIPERX5VALIDGT : std_logic;
|
1211 |
|
|
signal PIPERX6CHANISALIGNEDGT : std_logic;
|
1212 |
|
|
signal PIPERX6CHARISKGT : std_logic_vector(1 downto 0);
|
1213 |
|
|
signal PIPERX6DATAGT : std_logic_vector(15 downto 0);
|
1214 |
|
|
signal PIPERX6ELECIDLEGT : std_logic;
|
1215 |
|
|
signal PIPERX6PHYSTATUSGT : std_logic;
|
1216 |
|
|
signal PIPERX6STATUSGT : std_logic_vector(2 downto 0);
|
1217 |
|
|
signal PIPERX6VALIDGT : std_logic;
|
1218 |
|
|
signal PIPERX7CHANISALIGNEDGT : std_logic;
|
1219 |
|
|
signal PIPERX7CHARISKGT : std_logic_vector(1 downto 0);
|
1220 |
|
|
signal PIPERX7DATAGT : std_logic_vector(15 downto 0);
|
1221 |
|
|
signal PIPERX7ELECIDLEGT : std_logic;
|
1222 |
|
|
signal PIPERX7PHYSTATUSGT : std_logic;
|
1223 |
|
|
signal PIPERX7STATUSGT : std_logic_vector(2 downto 0);
|
1224 |
|
|
signal PIPERX7VALIDGT : std_logic;
|
1225 |
|
|
|
1226 |
|
|
signal filter_pipe_upconfig_fix_3451 : std_logic;
|
1227 |
|
|
|
1228 |
|
|
signal TRNRDLLPSRCRDYN : std_logic;
|
1229 |
|
|
|
1230 |
|
|
-- Declare intermediate signals for referenced outputs
|
1231 |
|
|
signal PCIEXPTXN_v6pcie100 : std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);
|
1232 |
|
|
signal PCIEXPTXP_v6pcie101 : std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);
|
1233 |
|
|
signal TRNLNKUPN_v6pcie123 : std_logic;
|
1234 |
|
|
signal PHYRDYN_v6pcie102 : std_logic;
|
1235 |
|
|
signal USERRSTN_v6pcie139 : std_logic;
|
1236 |
|
|
signal RECEIVEDFUNCLVLRSTN_v6pcie116 : std_logic;
|
1237 |
|
|
signal LNKCLKEN_v6pcie97 : std_logic;
|
1238 |
|
|
signal TRNRBARHITN_v6pcie124 : std_logic_vector(6 downto 0);
|
1239 |
|
|
signal TRNRD_v6pcie125 : std_logic_vector(63 downto 0);
|
1240 |
|
|
signal TRNRECRCERRN_v6pcie126 : std_logic;
|
1241 |
|
|
signal TRNREOFN_v6pcie127 : std_logic;
|
1242 |
|
|
signal TRNRERRFWDN_v6pcie128 : std_logic;
|
1243 |
|
|
signal TRNRREMN_v6pcie129 : std_logic;
|
1244 |
|
|
signal TRNRSOFN_v6pcie130 : std_logic;
|
1245 |
|
|
signal TRNRSRCDSCN_v6pcie131 : std_logic;
|
1246 |
|
|
signal TRNRSRCRDYN_v6pcie132 : std_logic;
|
1247 |
|
|
signal TRNTBUFAV_v6pcie133 : std_logic_vector(5 downto 0);
|
1248 |
|
|
signal TRNTCFGREQN_v6pcie134 : std_logic;
|
1249 |
|
|
signal TRNTDLLPDSTRDYN_v6pcie135 : std_logic;
|
1250 |
|
|
signal TRNTDSTRDYN_v6pcie136 : std_logic;
|
1251 |
|
|
signal TRNTERRDROPN_v6pcie137 : std_logic;
|
1252 |
|
|
signal TRNFCCPLD_v6pcie117 : std_logic_vector(11 downto 0);
|
1253 |
|
|
signal TRNFCCPLH_v6pcie118 : std_logic_vector(7 downto 0);
|
1254 |
|
|
signal TRNFCNPD_v6pcie119 : std_logic_vector(11 downto 0);
|
1255 |
|
|
signal TRNFCNPH_v6pcie120 : std_logic_vector(7 downto 0);
|
1256 |
|
|
signal TRNFCPD_v6pcie121 : std_logic_vector(11 downto 0);
|
1257 |
|
|
signal TRNFCPH_v6pcie122 : std_logic_vector(7 downto 0);
|
1258 |
|
|
signal CFGAERECRCCHECKEN_v6pcie0 : std_logic;
|
1259 |
|
|
signal CFGAERECRCGENEN_v6pcie1 : std_logic;
|
1260 |
|
|
signal CFGCOMMANDBUSMASTERENABLE_v6pcie2 : std_logic;
|
1261 |
|
|
signal CFGCOMMANDINTERRUPTDISABLE_v6pcie3 : std_logic;
|
1262 |
|
|
signal CFGCOMMANDIOENABLE_v6pcie4 : std_logic;
|
1263 |
|
|
signal CFGCOMMANDMEMENABLE_v6pcie5 : std_logic;
|
1264 |
|
|
signal CFGCOMMANDSERREN_v6pcie6 : std_logic;
|
1265 |
|
|
signal CFGDEVCONTROLAUXPOWEREN_v6pcie9 : std_logic;
|
1266 |
|
|
signal CFGDEVCONTROLCORRERRREPORTINGEN_v6pcie10 : std_logic;
|
1267 |
|
|
signal CFGDEVCONTROLENABLERO_v6pcie11 : std_logic;
|
1268 |
|
|
signal CFGDEVCONTROLEXTTAGEN_v6pcie12 : std_logic;
|
1269 |
|
|
signal CFGDEVCONTROLFATALERRREPORTINGEN_v6pcie13 : std_logic;
|
1270 |
|
|
signal CFGDEVCONTROLMAXPAYLOAD_v6pcie14 : std_logic_vector(2 downto 0);
|
1271 |
|
|
signal CFGDEVCONTROLMAXREADREQ_v6pcie15 : std_logic_vector(2 downto 0);
|
1272 |
|
|
signal CFGDEVCONTROLNONFATALREPORTINGEN_v6pcie16 : std_logic;
|
1273 |
|
|
signal CFGDEVCONTROLNOSNOOPEN_v6pcie17 : std_logic;
|
1274 |
|
|
signal CFGDEVCONTROLPHANTOMEN_v6pcie18 : std_logic;
|
1275 |
|
|
signal CFGDEVCONTROLURERRREPORTINGEN_v6pcie19 : std_logic;
|
1276 |
|
|
signal CFGDEVCONTROL2CPLTIMEOUTDIS_v6pcie7 : std_logic;
|
1277 |
|
|
signal CFGDEVCONTROL2CPLTIMEOUTVAL_v6pcie8 : std_logic_vector(3 downto 0);
|
1278 |
|
|
signal CFGDEVSTATUSCORRERRDETECTED_v6pcie20 : std_logic;
|
1279 |
|
|
signal CFGDEVSTATUSFATALERRDETECTED_v6pcie21 : std_logic;
|
1280 |
|
|
signal CFGDEVSTATUSNONFATALERRDETECTED_v6pcie22 : std_logic;
|
1281 |
|
|
signal CFGDEVSTATUSURDETECTED_v6pcie23 : std_logic;
|
1282 |
|
|
signal CFGDO_v6pcie24 : std_logic_vector(31 downto 0);
|
1283 |
|
|
signal CFGERRAERHEADERLOGSETN_v6pcie25 : std_logic;
|
1284 |
|
|
signal CFGERRCPLRDYN_v6pcie26 : std_logic;
|
1285 |
|
|
signal CFGINTERRUPTDO_v6pcie27 : std_logic_vector(7 downto 0);
|
1286 |
|
|
signal CFGINTERRUPTMMENABLE_v6pcie28 : std_logic_vector(2 downto 0);
|
1287 |
|
|
signal CFGINTERRUPTMSIENABLE_v6pcie29 : std_logic;
|
1288 |
|
|
signal CFGINTERRUPTMSIXENABLE_v6pcie30 : std_logic;
|
1289 |
|
|
signal CFGINTERRUPTMSIXFM_v6pcie31 : std_logic;
|
1290 |
|
|
signal CFGINTERRUPTRDYN_v6pcie32 : std_logic;
|
1291 |
|
|
signal CFGLINKCONTROLRCB_v6pcie41 : std_logic;
|
1292 |
|
|
signal CFGLINKCONTROLASPMCONTROL_v6pcie33 : std_logic_vector(1 downto 0);
|
1293 |
|
|
signal CFGLINKCONTROLAUTOBANDWIDTHINTEN_v6pcie34 : std_logic;
|
1294 |
|
|
signal CFGLINKCONTROLBANDWIDTHINTEN_v6pcie35 : std_logic;
|
1295 |
|
|
signal CFGLINKCONTROLCLOCKPMEN_v6pcie36 : std_logic;
|
1296 |
|
|
signal CFGLINKCONTROLCOMMONCLOCK_v6pcie37 : std_logic;
|
1297 |
|
|
signal CFGLINKCONTROLEXTENDEDSYNC_v6pcie38 : std_logic;
|
1298 |
|
|
signal CFGLINKCONTROLHWAUTOWIDTHDIS_v6pcie39 : std_logic;
|
1299 |
|
|
signal CFGLINKCONTROLLINKDISABLE_v6pcie40 : std_logic;
|
1300 |
|
|
signal CFGLINKCONTROLRETRAINLINK_v6pcie42 : std_logic;
|
1301 |
|
|
signal CFGLINKSTATUSAUTOBANDWIDTHSTATUS_v6pcie43 : std_logic;
|
1302 |
|
|
signal CFGLINKSTATUSBANDWITHSTATUS_v6pcie44 : std_logic;
|
1303 |
|
|
signal CFGLINKSTATUSCURRENTSPEED_v6pcie45 : std_logic_vector(1 downto 0);
|
1304 |
|
|
signal CFGLINKSTATUSDLLACTIVE_v6pcie46 : std_logic;
|
1305 |
|
|
signal CFGLINKSTATUSLINKTRAINING_v6pcie47 : std_logic;
|
1306 |
|
|
signal CFGLINKSTATUSNEGOTIATEDWIDTH_v6pcie48 : std_logic_vector(3 downto 0);
|
1307 |
|
|
signal CFGMSGDATA_v6pcie49 : std_logic_vector(15 downto 0);
|
1308 |
|
|
signal CFGMSGRECEIVED_v6pcie50 : std_logic;
|
1309 |
|
|
signal CFGMSGRECEIVEDASSERTINTA_v6pcie51 : std_logic;
|
1310 |
|
|
signal CFGMSGRECEIVEDASSERTINTB_v6pcie52 : std_logic;
|
1311 |
|
|
signal CFGMSGRECEIVEDASSERTINTC_v6pcie53 : std_logic;
|
1312 |
|
|
signal CFGMSGRECEIVEDASSERTINTD_v6pcie54 : std_logic;
|
1313 |
|
|
signal CFGMSGRECEIVEDDEASSERTINTA_v6pcie55 : std_logic;
|
1314 |
|
|
signal CFGMSGRECEIVEDDEASSERTINTB_v6pcie56 : std_logic;
|
1315 |
|
|
signal CFGMSGRECEIVEDDEASSERTINTC_v6pcie57 : std_logic;
|
1316 |
|
|
signal CFGMSGRECEIVEDDEASSERTINTD_v6pcie58 : std_logic;
|
1317 |
|
|
signal CFGMSGRECEIVEDERRCOR_v6pcie59 : std_logic;
|
1318 |
|
|
signal CFGMSGRECEIVEDERRFATAL_v6pcie60 : std_logic;
|
1319 |
|
|
signal CFGMSGRECEIVEDERRNONFATAL_v6pcie61 : std_logic;
|
1320 |
|
|
signal CFGMSGRECEIVEDPMASNAK_v6pcie62 : std_logic;
|
1321 |
|
|
signal CFGMSGRECEIVEDPMETO_v6pcie63 : std_logic;
|
1322 |
|
|
signal CFGMSGRECEIVEDPMETOACK_v6pcie64 : std_logic;
|
1323 |
|
|
signal CFGMSGRECEIVEDPMPME_v6pcie65 : std_logic;
|
1324 |
|
|
signal CFGMSGRECEIVEDSETSLOTPOWERLIMIT_v6pcie66 : std_logic;
|
1325 |
|
|
signal CFGMSGRECEIVEDUNLOCK_v6pcie67 : std_logic;
|
1326 |
|
|
signal CFGPCIELINKSTATE_v6pcie68 : std_logic_vector(2 downto 0);
|
1327 |
|
|
signal CFGPMCSRPMEEN_v6pcie69 : std_logic;
|
1328 |
|
|
signal CFGPMCSRPMESTATUS_v6pcie70 : std_logic;
|
1329 |
|
|
signal CFGPMCSRPOWERSTATE_v6pcie71 : std_logic_vector(1 downto 0);
|
1330 |
|
|
signal CFGPMRCVASREQL1N_v6pcie72 : std_logic;
|
1331 |
|
|
signal CFGPMRCVENTERL1N_v6pcie73 : std_logic;
|
1332 |
|
|
signal CFGPMRCVENTERL23N_v6pcie74 : std_logic;
|
1333 |
|
|
signal CFGPMRCVREQACKN_v6pcie75 : std_logic;
|
1334 |
|
|
signal CFGRDWRDONEN_v6pcie76 : std_logic;
|
1335 |
|
|
signal CFGSLOTCONTROLELECTROMECHILCTLPULSE_v6pcie77 : std_logic;
|
1336 |
|
|
signal CFGTRANSACTION_v6pcie78 : std_logic;
|
1337 |
|
|
signal CFGTRANSACTIONADDR_v6pcie79 : std_logic_vector(6 downto 0);
|
1338 |
|
|
signal CFGTRANSACTIONTYPE_v6pcie80 : std_logic;
|
1339 |
|
|
signal CFGVCTCVCMAP_v6pcie81 : std_logic_vector(6 downto 0);
|
1340 |
|
|
signal PLINITIALLINKWIDTH_v6pcie104 : std_logic_vector(2 downto 0);
|
1341 |
|
|
signal PLLANEREVERSALMODE_v6pcie105 : std_logic_vector(1 downto 0);
|
1342 |
|
|
signal PLLINKGEN2CAP_v6pcie106 : std_logic;
|
1343 |
|
|
signal PLLINKPARTNERGEN2SUPPORTED_v6pcie107 : std_logic;
|
1344 |
|
|
signal PLLINKUPCFGCAP_v6pcie108 : std_logic;
|
1345 |
|
|
signal PLLTSSMSTATE_v6pcie109 : std_logic_vector(5 downto 0);
|
1346 |
|
|
signal PLPHYLNKUPN_v6pcie110 : std_logic;
|
1347 |
|
|
signal PLRECEIVEDHOTRST_v6pcie111 : std_logic;
|
1348 |
|
|
signal PLRXPMSTATE_v6pcie112 : std_logic_vector(1 downto 0);
|
1349 |
|
|
signal PLSELLNKRATE_v6pcie113 : std_logic;
|
1350 |
|
|
signal PLSELLNKWIDTH_v6pcie114 : std_logic_vector(1 downto 0);
|
1351 |
|
|
signal PLTXPMSTATE_v6pcie115 : std_logic_vector(2 downto 0);
|
1352 |
|
|
signal DBGSCLRA_v6pcie82 : std_logic;
|
1353 |
|
|
signal DBGSCLRB_v6pcie83 : std_logic;
|
1354 |
|
|
signal DBGSCLRC_v6pcie84 : std_logic;
|
1355 |
|
|
signal DBGSCLRD_v6pcie85 : std_logic;
|
1356 |
|
|
signal DBGSCLRE_v6pcie86 : std_logic;
|
1357 |
|
|
signal DBGSCLRF_v6pcie87 : std_logic;
|
1358 |
|
|
signal DBGSCLRG_v6pcie88 : std_logic;
|
1359 |
|
|
signal DBGSCLRH_v6pcie89 : std_logic;
|
1360 |
|
|
signal DBGSCLRI_v6pcie90 : std_logic;
|
1361 |
|
|
signal DBGSCLRJ_v6pcie91 : std_logic;
|
1362 |
|
|
signal DBGSCLRK_v6pcie92 : std_logic;
|
1363 |
|
|
signal DBGVECA_v6pcie93 : std_logic_vector(63 downto 0);
|
1364 |
|
|
signal DBGVECB_v6pcie94 : std_logic_vector(63 downto 0);
|
1365 |
|
|
signal DBGVECC_v6pcie95 : std_logic_vector(11 downto 0);
|
1366 |
|
|
signal PLDBGVEC_v6pcie103 : std_logic_vector(11 downto 0);
|
1367 |
|
|
signal PCIEDRPDO_v6pcie98 : std_logic_vector(15 downto 0);
|
1368 |
|
|
signal PCIEDRPDRDY_v6pcie99 : std_logic;
|
1369 |
|
|
signal GTPLLLOCK_v6pcie96 : std_logic;
|
1370 |
|
|
signal TxOutClk_v6pcie138 : std_logic;
|
1371 |
|
|
|
1372 |
|
|
signal PIPERX0CHARISK_v6pcie : std_logic_vector(1 downto 0);
|
1373 |
|
|
signal PIPERX1CHARISK_v6pcie : std_logic_vector(1 downto 0);
|
1374 |
|
|
signal PIPERX2CHARISK_v6pcie : std_logic_vector(1 downto 0);
|
1375 |
|
|
signal PIPERX3CHARISK_v6pcie : std_logic_vector(1 downto 0);
|
1376 |
|
|
signal PIPERX4CHARISK_v6pcie : std_logic_vector(1 downto 0);
|
1377 |
|
|
signal PIPERX5CHARISK_v6pcie : std_logic_vector(1 downto 0);
|
1378 |
|
|
signal PIPERX6CHARISK_v6pcie : std_logic_vector(1 downto 0);
|
1379 |
|
|
signal PIPERX7CHARISK_v6pcie : std_logic_vector(1 downto 0);
|
1380 |
|
|
|
1381 |
|
|
begin
|
1382 |
|
|
-- Drive referenced outputs
|
1383 |
|
|
PCIEXPTXN <= PCIEXPTXN_v6pcie100;
|
1384 |
|
|
PCIEXPTXP <= PCIEXPTXP_v6pcie101;
|
1385 |
|
|
TRNLNKUPN <= TRNLNKUPN_v6pcie123;
|
1386 |
|
|
PHYRDYN <= PHYRDYN_v6pcie102;
|
1387 |
|
|
USERRSTN <= USERRSTN_v6pcie139;
|
1388 |
|
|
RECEIVEDFUNCLVLRSTN <= RECEIVEDFUNCLVLRSTN_v6pcie116;
|
1389 |
|
|
LNKCLKEN <= LNKCLKEN_v6pcie97;
|
1390 |
|
|
TRNRBARHITN <= TRNRBARHITN_v6pcie124;
|
1391 |
|
|
TRNRD <= TRNRD_v6pcie125;
|
1392 |
|
|
TRNRECRCERRN <= TRNRECRCERRN_v6pcie126;
|
1393 |
|
|
TRNREOFN <= TRNREOFN_v6pcie127;
|
1394 |
|
|
TRNRERRFWDN <= TRNRERRFWDN_v6pcie128;
|
1395 |
|
|
TRNRREMN <= TRNRREMN_v6pcie129;
|
1396 |
|
|
TRNRSOFN <= TRNRSOFN_v6pcie130;
|
1397 |
|
|
TRNRSRCDSCN <= TRNRSRCDSCN_v6pcie131;
|
1398 |
|
|
TRNRSRCRDYN <= TRNRSRCRDYN_v6pcie132;
|
1399 |
|
|
TRNTBUFAV <= TRNTBUFAV_v6pcie133;
|
1400 |
|
|
TRNTCFGREQN <= TRNTCFGREQN_v6pcie134;
|
1401 |
|
|
TRNTDLLPDSTRDYN <= TRNTDLLPDSTRDYN_v6pcie135;
|
1402 |
|
|
TRNTDSTRDYN <= TRNTDSTRDYN_v6pcie136;
|
1403 |
|
|
TRNTERRDROPN <= TRNTERRDROPN_v6pcie137;
|
1404 |
|
|
TRNFCCPLD <= TRNFCCPLD_v6pcie117;
|
1405 |
|
|
TRNFCCPLH <= TRNFCCPLH_v6pcie118;
|
1406 |
|
|
TRNFCNPD <= TRNFCNPD_v6pcie119;
|
1407 |
|
|
TRNFCNPH <= TRNFCNPH_v6pcie120;
|
1408 |
|
|
TRNFCPD <= TRNFCPD_v6pcie121;
|
1409 |
|
|
TRNFCPH <= TRNFCPH_v6pcie122;
|
1410 |
|
|
CFGAERECRCCHECKEN <= CFGAERECRCCHECKEN_v6pcie0;
|
1411 |
|
|
CFGAERECRCGENEN <= CFGAERECRCGENEN_v6pcie1;
|
1412 |
|
|
CFGCOMMANDBUSMASTERENABLE <= CFGCOMMANDBUSMASTERENABLE_v6pcie2;
|
1413 |
|
|
CFGCOMMANDINTERRUPTDISABLE <= CFGCOMMANDINTERRUPTDISABLE_v6pcie3;
|
1414 |
|
|
CFGCOMMANDIOENABLE <= CFGCOMMANDIOENABLE_v6pcie4;
|
1415 |
|
|
CFGCOMMANDMEMENABLE <= CFGCOMMANDMEMENABLE_v6pcie5;
|
1416 |
|
|
CFGCOMMANDSERREN <= CFGCOMMANDSERREN_v6pcie6;
|
1417 |
|
|
CFGDEVCONTROLAUXPOWEREN <= CFGDEVCONTROLAUXPOWEREN_v6pcie9;
|
1418 |
|
|
CFGDEVCONTROLCORRERRREPORTINGEN <= CFGDEVCONTROLCORRERRREPORTINGEN_v6pcie10;
|
1419 |
|
|
CFGDEVCONTROLENABLERO <= CFGDEVCONTROLENABLERO_v6pcie11;
|
1420 |
|
|
CFGDEVCONTROLEXTTAGEN <= CFGDEVCONTROLEXTTAGEN_v6pcie12;
|
1421 |
|
|
CFGDEVCONTROLFATALERRREPORTINGEN <= CFGDEVCONTROLFATALERRREPORTINGEN_v6pcie13;
|
1422 |
|
|
CFGDEVCONTROLMAXPAYLOAD <= CFGDEVCONTROLMAXPAYLOAD_v6pcie14;
|
1423 |
|
|
CFGDEVCONTROLMAXREADREQ <= CFGDEVCONTROLMAXREADREQ_v6pcie15;
|
1424 |
|
|
CFGDEVCONTROLNONFATALREPORTINGEN <= CFGDEVCONTROLNONFATALREPORTINGEN_v6pcie16;
|
1425 |
|
|
CFGDEVCONTROLNOSNOOPEN <= CFGDEVCONTROLNOSNOOPEN_v6pcie17;
|
1426 |
|
|
CFGDEVCONTROLPHANTOMEN <= CFGDEVCONTROLPHANTOMEN_v6pcie18;
|
1427 |
|
|
CFGDEVCONTROLURERRREPORTINGEN <= CFGDEVCONTROLURERRREPORTINGEN_v6pcie19;
|
1428 |
|
|
CFGDEVCONTROL2CPLTIMEOUTDIS <= CFGDEVCONTROL2CPLTIMEOUTDIS_v6pcie7;
|
1429 |
|
|
CFGDEVCONTROL2CPLTIMEOUTVAL <= CFGDEVCONTROL2CPLTIMEOUTVAL_v6pcie8;
|
1430 |
|
|
CFGDEVSTATUSCORRERRDETECTED <= CFGDEVSTATUSCORRERRDETECTED_v6pcie20;
|
1431 |
|
|
CFGDEVSTATUSFATALERRDETECTED <= CFGDEVSTATUSFATALERRDETECTED_v6pcie21;
|
1432 |
|
|
CFGDEVSTATUSNONFATALERRDETECTED <= CFGDEVSTATUSNONFATALERRDETECTED_v6pcie22;
|
1433 |
|
|
CFGDEVSTATUSURDETECTED <= CFGDEVSTATUSURDETECTED_v6pcie23;
|
1434 |
|
|
CFGDO <= CFGDO_v6pcie24;
|
1435 |
|
|
CFGERRAERHEADERLOGSETN <= CFGERRAERHEADERLOGSETN_v6pcie25;
|
1436 |
|
|
CFGERRCPLRDYN <= CFGERRCPLRDYN_v6pcie26;
|
1437 |
|
|
CFGINTERRUPTDO <= CFGINTERRUPTDO_v6pcie27;
|
1438 |
|
|
CFGINTERRUPTMMENABLE <= CFGINTERRUPTMMENABLE_v6pcie28;
|
1439 |
|
|
CFGINTERRUPTMSIENABLE <= CFGINTERRUPTMSIENABLE_v6pcie29;
|
1440 |
|
|
CFGINTERRUPTMSIXENABLE <= CFGINTERRUPTMSIXENABLE_v6pcie30;
|
1441 |
|
|
CFGINTERRUPTMSIXFM <= CFGINTERRUPTMSIXFM_v6pcie31;
|
1442 |
|
|
CFGINTERRUPTRDYN <= CFGINTERRUPTRDYN_v6pcie32;
|
1443 |
|
|
CFGLINKCONTROLRCB <= CFGLINKCONTROLRCB_v6pcie41;
|
1444 |
|
|
CFGLINKCONTROLASPMCONTROL <= CFGLINKCONTROLASPMCONTROL_v6pcie33;
|
1445 |
|
|
CFGLINKCONTROLAUTOBANDWIDTHINTEN <= CFGLINKCONTROLAUTOBANDWIDTHINTEN_v6pcie34;
|
1446 |
|
|
CFGLINKCONTROLBANDWIDTHINTEN <= CFGLINKCONTROLBANDWIDTHINTEN_v6pcie35;
|
1447 |
|
|
CFGLINKCONTROLCLOCKPMEN <= CFGLINKCONTROLCLOCKPMEN_v6pcie36;
|
1448 |
|
|
CFGLINKCONTROLCOMMONCLOCK <= CFGLINKCONTROLCOMMONCLOCK_v6pcie37;
|
1449 |
|
|
CFGLINKCONTROLEXTENDEDSYNC <= CFGLINKCONTROLEXTENDEDSYNC_v6pcie38;
|
1450 |
|
|
CFGLINKCONTROLHWAUTOWIDTHDIS <= CFGLINKCONTROLHWAUTOWIDTHDIS_v6pcie39;
|
1451 |
|
|
CFGLINKCONTROLLINKDISABLE <= CFGLINKCONTROLLINKDISABLE_v6pcie40;
|
1452 |
|
|
CFGLINKCONTROLRETRAINLINK <= CFGLINKCONTROLRETRAINLINK_v6pcie42;
|
1453 |
|
|
CFGLINKSTATUSAUTOBANDWIDTHSTATUS <= CFGLINKSTATUSAUTOBANDWIDTHSTATUS_v6pcie43;
|
1454 |
|
|
CFGLINKSTATUSBANDWITHSTATUS <= CFGLINKSTATUSBANDWITHSTATUS_v6pcie44;
|
1455 |
|
|
CFGLINKSTATUSCURRENTSPEED <= CFGLINKSTATUSCURRENTSPEED_v6pcie45;
|
1456 |
|
|
CFGLINKSTATUSDLLACTIVE <= CFGLINKSTATUSDLLACTIVE_v6pcie46;
|
1457 |
|
|
CFGLINKSTATUSLINKTRAINING <= CFGLINKSTATUSLINKTRAINING_v6pcie47;
|
1458 |
|
|
CFGLINKSTATUSNEGOTIATEDWIDTH <= CFGLINKSTATUSNEGOTIATEDWIDTH_v6pcie48;
|
1459 |
|
|
CFGMSGDATA <= CFGMSGDATA_v6pcie49;
|
1460 |
|
|
CFGMSGRECEIVED <= CFGMSGRECEIVED_v6pcie50;
|
1461 |
|
|
CFGMSGRECEIVEDASSERTINTA <= CFGMSGRECEIVEDASSERTINTA_v6pcie51;
|
1462 |
|
|
CFGMSGRECEIVEDASSERTINTB <= CFGMSGRECEIVEDASSERTINTB_v6pcie52;
|
1463 |
|
|
CFGMSGRECEIVEDASSERTINTC <= CFGMSGRECEIVEDASSERTINTC_v6pcie53;
|
1464 |
|
|
CFGMSGRECEIVEDASSERTINTD <= CFGMSGRECEIVEDASSERTINTD_v6pcie54;
|
1465 |
|
|
CFGMSGRECEIVEDDEASSERTINTA <= CFGMSGRECEIVEDDEASSERTINTA_v6pcie55;
|
1466 |
|
|
CFGMSGRECEIVEDDEASSERTINTB <= CFGMSGRECEIVEDDEASSERTINTB_v6pcie56;
|
1467 |
|
|
CFGMSGRECEIVEDDEASSERTINTC <= CFGMSGRECEIVEDDEASSERTINTC_v6pcie57;
|
1468 |
|
|
CFGMSGRECEIVEDDEASSERTINTD <= CFGMSGRECEIVEDDEASSERTINTD_v6pcie58;
|
1469 |
|
|
CFGMSGRECEIVEDERRCOR <= CFGMSGRECEIVEDERRCOR_v6pcie59;
|
1470 |
|
|
CFGMSGRECEIVEDERRFATAL <= CFGMSGRECEIVEDERRFATAL_v6pcie60;
|
1471 |
|
|
CFGMSGRECEIVEDERRNONFATAL <= CFGMSGRECEIVEDERRNONFATAL_v6pcie61;
|
1472 |
|
|
CFGMSGRECEIVEDPMASNAK <= CFGMSGRECEIVEDPMASNAK_v6pcie62;
|
1473 |
|
|
CFGMSGRECEIVEDPMETO <= CFGMSGRECEIVEDPMETO_v6pcie63;
|
1474 |
|
|
CFGMSGRECEIVEDPMETOACK <= CFGMSGRECEIVEDPMETOACK_v6pcie64;
|
1475 |
|
|
CFGMSGRECEIVEDPMPME <= CFGMSGRECEIVEDPMPME_v6pcie65;
|
1476 |
|
|
CFGMSGRECEIVEDSETSLOTPOWERLIMIT <= CFGMSGRECEIVEDSETSLOTPOWERLIMIT_v6pcie66;
|
1477 |
|
|
CFGMSGRECEIVEDUNLOCK <= CFGMSGRECEIVEDUNLOCK_v6pcie67;
|
1478 |
|
|
CFGPCIELINKSTATE <= CFGPCIELINKSTATE_v6pcie68;
|
1479 |
|
|
CFGPMCSRPMEEN <= CFGPMCSRPMEEN_v6pcie69;
|
1480 |
|
|
CFGPMCSRPMESTATUS <= CFGPMCSRPMESTATUS_v6pcie70;
|
1481 |
|
|
CFGPMCSRPOWERSTATE <= CFGPMCSRPOWERSTATE_v6pcie71;
|
1482 |
|
|
CFGPMRCVASREQL1N <= CFGPMRCVASREQL1N_v6pcie72;
|
1483 |
|
|
CFGPMRCVENTERL1N <= CFGPMRCVENTERL1N_v6pcie73;
|
1484 |
|
|
CFGPMRCVENTERL23N <= CFGPMRCVENTERL23N_v6pcie74;
|
1485 |
|
|
CFGPMRCVREQACKN <= CFGPMRCVREQACKN_v6pcie75;
|
1486 |
|
|
CFGRDWRDONEN <= CFGRDWRDONEN_v6pcie76;
|
1487 |
|
|
CFGSLOTCONTROLELECTROMECHILCTLPULSE <= CFGSLOTCONTROLELECTROMECHILCTLPULSE_v6pcie77;
|
1488 |
|
|
CFGTRANSACTION <= CFGTRANSACTION_v6pcie78;
|
1489 |
|
|
CFGTRANSACTIONADDR <= CFGTRANSACTIONADDR_v6pcie79;
|
1490 |
|
|
CFGTRANSACTIONTYPE <= CFGTRANSACTIONTYPE_v6pcie80;
|
1491 |
|
|
CFGVCTCVCMAP <= CFGVCTCVCMAP_v6pcie81;
|
1492 |
|
|
PLINITIALLINKWIDTH <= PLINITIALLINKWIDTH_v6pcie104;
|
1493 |
|
|
PLLANEREVERSALMODE <= PLLANEREVERSALMODE_v6pcie105;
|
1494 |
|
|
PLLINKGEN2CAP <= PLLINKGEN2CAP_v6pcie106;
|
1495 |
|
|
PLLINKPARTNERGEN2SUPPORTED <= PLLINKPARTNERGEN2SUPPORTED_v6pcie107;
|
1496 |
|
|
PLLINKUPCFGCAP <= PLLINKUPCFGCAP_v6pcie108;
|
1497 |
|
|
PLLTSSMSTATE <= PLLTSSMSTATE_v6pcie109;
|
1498 |
|
|
PLPHYLNKUPN <= PLPHYLNKUPN_v6pcie110;
|
1499 |
|
|
PLRECEIVEDHOTRST <= PLRECEIVEDHOTRST_v6pcie111;
|
1500 |
|
|
PLRXPMSTATE <= PLRXPMSTATE_v6pcie112;
|
1501 |
|
|
PLSELLNKRATE <= PLSELLNKRATE_v6pcie113;
|
1502 |
|
|
PLSELLNKWIDTH <= PLSELLNKWIDTH_v6pcie114;
|
1503 |
|
|
PLTXPMSTATE <= PLTXPMSTATE_v6pcie115;
|
1504 |
|
|
DBGSCLRA <= DBGSCLRA_v6pcie82;
|
1505 |
|
|
DBGSCLRB <= DBGSCLRB_v6pcie83;
|
1506 |
|
|
DBGSCLRC <= DBGSCLRC_v6pcie84;
|
1507 |
|
|
DBGSCLRD <= DBGSCLRD_v6pcie85;
|
1508 |
|
|
DBGSCLRE <= DBGSCLRE_v6pcie86;
|
1509 |
|
|
DBGSCLRF <= DBGSCLRF_v6pcie87;
|
1510 |
|
|
DBGSCLRG <= DBGSCLRG_v6pcie88;
|
1511 |
|
|
DBGSCLRH <= DBGSCLRH_v6pcie89;
|
1512 |
|
|
DBGSCLRI <= DBGSCLRI_v6pcie90;
|
1513 |
|
|
DBGSCLRJ <= DBGSCLRJ_v6pcie91;
|
1514 |
|
|
DBGSCLRK <= DBGSCLRK_v6pcie92;
|
1515 |
|
|
DBGVECA <= DBGVECA_v6pcie93;
|
1516 |
|
|
DBGVECB <= DBGVECB_v6pcie94;
|
1517 |
|
|
DBGVECC <= DBGVECC_v6pcie95;
|
1518 |
|
|
PLDBGVEC <= PLDBGVEC_v6pcie103;
|
1519 |
|
|
PCIEDRPDO <= PCIEDRPDO_v6pcie98;
|
1520 |
|
|
PCIEDRPDRDY <= PCIEDRPDRDY_v6pcie99;
|
1521 |
|
|
GTPLLLOCK <= GTPLLLOCK_v6pcie96;
|
1522 |
|
|
TxOutClk <= TxOutClk_v6pcie138;
|
1523 |
|
|
LL2SENDASREQL1N <= '1';
|
1524 |
|
|
LL2SENDENTERL1N <= '1';
|
1525 |
|
|
LL2SENDENTERL23N <= '1';
|
1526 |
|
|
LL2SUSPENDNOWN <= '1';
|
1527 |
|
|
LL2TLPRCVN <= '1';
|
1528 |
|
|
PL2DIRECTEDLSTATE <= "00000";
|
1529 |
|
|
|
1530 |
|
|
-- Assignments to outputs
|
1531 |
|
|
|
1532 |
|
|
TRNCLK <= USERCLK;
|
1533 |
|
|
|
1534 |
|
|
PIPERX0CHARISK_v6pcie <= "11" when (filter_pipe_upconfig_fix_3451 = '1') else
|
1535 |
|
|
PIPERX0CHARISK;
|
1536 |
|
|
PIPERX1CHARISK_v6pcie <= "11" when (filter_pipe_upconfig_fix_3451 = '1') else
|
1537 |
|
|
PIPERX1CHARISK;
|
1538 |
|
|
PIPERX2CHARISK_v6pcie <= "11" when (filter_pipe_upconfig_fix_3451 = '1') else
|
1539 |
|
|
PIPERX2CHARISK;
|
1540 |
|
|
PIPERX3CHARISK_v6pcie <= "11" when (filter_pipe_upconfig_fix_3451 = '1') else
|
1541 |
|
|
PIPERX3CHARISK;
|
1542 |
|
|
PIPERX4CHARISK_v6pcie <= "11" when (filter_pipe_upconfig_fix_3451 = '1') else
|
1543 |
|
|
PIPERX4CHARISK;
|
1544 |
|
|
PIPERX5CHARISK_v6pcie <= "11" when (filter_pipe_upconfig_fix_3451 = '1') else
|
1545 |
|
|
PIPERX5CHARISK;
|
1546 |
|
|
PIPERX6CHARISK_v6pcie <= "11" when (filter_pipe_upconfig_fix_3451 = '1') else
|
1547 |
|
|
PIPERX6CHARISK;
|
1548 |
|
|
PIPERX7CHARISK_v6pcie <= "11" when (filter_pipe_upconfig_fix_3451 = '1') else
|
1549 |
|
|
PIPERX7CHARISK;
|
1550 |
|
|
|
1551 |
|
|
---------------------------------------------------------
|
1552 |
|
|
-- Virtex6 PCI Express Block Module
|
1553 |
|
|
---------------------------------------------------------
|
1554 |
|
|
|
1555 |
|
|
pcie_block_i : PCIE_2_0
|
1556 |
|
|
generic map (
|
1557 |
|
|
AER_BASE_PTR => AER_BASE_PTR,
|
1558 |
|
|
AER_CAP_ECRC_CHECK_CAPABLE => AER_CAP_ECRC_CHECK_CAPABLE,
|
1559 |
|
|
AER_CAP_ECRC_GEN_CAPABLE => AER_CAP_ECRC_GEN_CAPABLE,
|
1560 |
|
|
AER_CAP_ID => AER_CAP_ID,
|
1561 |
|
|
AER_CAP_INT_MSG_NUM_MSI => AER_CAP_INT_MSG_NUM_MSI,
|
1562 |
|
|
AER_CAP_INT_MSG_NUM_MSIX => AER_CAP_INT_MSG_NUM_MSIX,
|
1563 |
|
|
AER_CAP_NEXTPTR => AER_CAP_NEXTPTR,
|
1564 |
|
|
AER_CAP_ON => AER_CAP_ON,
|
1565 |
|
|
AER_CAP_PERMIT_ROOTERR_UPDATE => AER_CAP_PERMIT_ROOTERR_UPDATE,
|
1566 |
|
|
AER_CAP_VERSION => AER_CAP_VERSION,
|
1567 |
|
|
ALLOW_X8_GEN2 => ALLOW_X8_GEN2,
|
1568 |
|
|
BAR0 => BAR0,
|
1569 |
|
|
BAR1 => BAR1,
|
1570 |
|
|
BAR2 => BAR2,
|
1571 |
|
|
BAR3 => BAR3,
|
1572 |
|
|
BAR4 => BAR4,
|
1573 |
|
|
BAR5 => BAR5,
|
1574 |
|
|
CAPABILITIES_PTR => CAPABILITIES_PTR,
|
1575 |
|
|
CARDBUS_CIS_POINTER => CARDBUS_CIS_POINTER,
|
1576 |
|
|
CLASS_CODE => CLASS_CODE,
|
1577 |
|
|
CMD_INTX_IMPLEMENTED => CMD_INTX_IMPLEMENTED,
|
1578 |
|
|
CPL_TIMEOUT_DISABLE_SUPPORTED => CPL_TIMEOUT_DISABLE_SUPPORTED,
|
1579 |
|
|
CPL_TIMEOUT_RANGES_SUPPORTED => CPL_TIMEOUT_RANGES_SUPPORTED,
|
1580 |
|
|
CRM_MODULE_RSTS => CRM_MODULE_RSTS,
|
1581 |
|
|
DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE => DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE,
|
1582 |
|
|
DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE => DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE,
|
1583 |
|
|
DEV_CAP_ENDPOINT_L0S_LATENCY => DEV_CAP_ENDPOINT_L0S_LATENCY,
|
1584 |
|
|
DEV_CAP_ENDPOINT_L1_LATENCY => DEV_CAP_ENDPOINT_L1_LATENCY,
|
1585 |
|
|
DEV_CAP_EXT_TAG_SUPPORTED => DEV_CAP_EXT_TAG_SUPPORTED,
|
1586 |
|
|
DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE => DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE,
|
1587 |
|
|
DEV_CAP_MAX_PAYLOAD_SUPPORTED => DEV_CAP_MAX_PAYLOAD_SUPPORTED,
|
1588 |
|
|
DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT => DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT,
|
1589 |
|
|
DEV_CAP_ROLE_BASED_ERROR => DEV_CAP_ROLE_BASED_ERROR,
|
1590 |
|
|
DEV_CAP_RSVD_14_12 => DEV_CAP_RSVD_14_12,
|
1591 |
|
|
DEV_CAP_RSVD_17_16 => DEV_CAP_RSVD_17_16,
|
1592 |
|
|
DEV_CAP_RSVD_31_29 => DEV_CAP_RSVD_31_29,
|
1593 |
|
|
DEV_CONTROL_AUX_POWER_SUPPORTED => DEV_CONTROL_AUX_POWER_SUPPORTED,
|
1594 |
|
|
DEVICE_ID => DEVICE_ID,
|
1595 |
|
|
DISABLE_ASPM_L1_TIMER => DISABLE_ASPM_L1_TIMER,
|
1596 |
|
|
DISABLE_BAR_FILTERING => DISABLE_BAR_FILTERING,
|
1597 |
|
|
DISABLE_ID_CHECK => DISABLE_ID_CHECK,
|
1598 |
|
|
DISABLE_LANE_REVERSAL => DISABLE_LANE_REVERSAL,
|
1599 |
|
|
DISABLE_RX_TC_FILTER => DISABLE_RX_TC_FILTER,
|
1600 |
|
|
DISABLE_SCRAMBLING => DISABLE_SCRAMBLING,
|
1601 |
|
|
DNSTREAM_LINK_NUM => DNSTREAM_LINK_NUM,
|
1602 |
|
|
DSN_BASE_PTR => DSN_BASE_PTR,
|
1603 |
|
|
DSN_CAP_ID => DSN_CAP_ID,
|
1604 |
|
|
DSN_CAP_NEXTPTR => DSN_CAP_NEXTPTR,
|
1605 |
|
|
DSN_CAP_ON => DSN_CAP_ON,
|
1606 |
|
|
DSN_CAP_VERSION => DSN_CAP_VERSION,
|
1607 |
|
|
ENABLE_MSG_ROUTE => ENABLE_MSG_ROUTE,
|
1608 |
|
|
ENABLE_RX_TD_ECRC_TRIM => ENABLE_RX_TD_ECRC_TRIM,
|
1609 |
|
|
ENTER_RVRY_EI_L0 => ENTER_RVRY_EI_L0,
|
1610 |
|
|
EXPANSION_ROM => EXPANSION_ROM,
|
1611 |
|
|
EXT_CFG_CAP_PTR => EXT_CFG_CAP_PTR,
|
1612 |
|
|
EXT_CFG_XP_CAP_PTR => EXT_CFG_XP_CAP_PTR,
|
1613 |
|
|
HEADER_TYPE => HEADER_TYPE,
|
1614 |
|
|
INFER_EI => INFER_EI,
|
1615 |
|
|
INTERRUPT_PIN => INTERRUPT_PIN,
|
1616 |
|
|
IS_SWITCH => IS_SWITCH,
|
1617 |
|
|
LAST_CONFIG_DWORD => LAST_CONFIG_DWORD,
|
1618 |
|
|
LINK_CAP_ASPM_SUPPORT => LINK_CAP_ASPM_SUPPORT,
|
1619 |
|
|
LINK_CAP_CLOCK_POWER_MANAGEMENT => LINK_CAP_CLOCK_POWER_MANAGEMENT,
|
1620 |
|
|
LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP => LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP,
|
1621 |
|
|
LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP => LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP,
|
1622 |
|
|
LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 => LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1,
|
1623 |
|
|
LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 => LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2,
|
1624 |
|
|
LINK_CAP_L0S_EXIT_LATENCY_GEN1 => LINK_CAP_L0S_EXIT_LATENCY_GEN1,
|
1625 |
|
|
LINK_CAP_L0S_EXIT_LATENCY_GEN2 => LINK_CAP_L0S_EXIT_LATENCY_GEN2,
|
1626 |
|
|
LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 => LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1,
|
1627 |
|
|
LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 => LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2,
|
1628 |
|
|
LINK_CAP_L1_EXIT_LATENCY_GEN1 => LINK_CAP_L1_EXIT_LATENCY_GEN1,
|
1629 |
|
|
LINK_CAP_L1_EXIT_LATENCY_GEN2 => LINK_CAP_L1_EXIT_LATENCY_GEN2,
|
1630 |
|
|
LINK_CAP_MAX_LINK_SPEED => LINK_CAP_MAX_LINK_SPEED,
|
1631 |
|
|
LINK_CAP_MAX_LINK_WIDTH => LINK_CAP_MAX_LINK_WIDTH,
|
1632 |
|
|
LINK_CAP_RSVD_23_22 => LINK_CAP_RSVD_23_22,
|
1633 |
|
|
LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE => LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE,
|
1634 |
|
|
LINK_CONTROL_RCB => LINK_CONTROL_RCB,
|
1635 |
|
|
LINK_CTRL2_DEEMPHASIS => LINK_CTRL2_DEEMPHASIS,
|
1636 |
|
|
LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE => LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE,
|
1637 |
|
|
LINK_CTRL2_TARGET_LINK_SPEED => LINK_CTRL2_TARGET_LINK_SPEED,
|
1638 |
|
|
LINK_STATUS_SLOT_CLOCK_CONFIG => LINK_STATUS_SLOT_CLOCK_CONFIG,
|
1639 |
|
|
LL_ACK_TIMEOUT => LL_ACK_TIMEOUT,
|
1640 |
|
|
LL_ACK_TIMEOUT_EN => LL_ACK_TIMEOUT_EN,
|
1641 |
|
|
LL_ACK_TIMEOUT_FUNC => LL_ACK_TIMEOUT_FUNC,
|
1642 |
|
|
LL_REPLAY_TIMEOUT => LL_REPLAY_TIMEOUT,
|
1643 |
|
|
LL_REPLAY_TIMEOUT_EN => LL_REPLAY_TIMEOUT_EN,
|
1644 |
|
|
LL_REPLAY_TIMEOUT_FUNC => LL_REPLAY_TIMEOUT_FUNC,
|
1645 |
|
|
LTSSM_MAX_LINK_WIDTH => LTSSM_MAX_LINK_WIDTH,
|
1646 |
|
|
MSI_BASE_PTR => MSI_BASE_PTR,
|
1647 |
|
|
MSI_CAP_ID => MSI_CAP_ID,
|
1648 |
|
|
MSI_CAP_MULTIMSGCAP => MSI_CAP_MULTIMSGCAP,
|
1649 |
|
|
MSI_CAP_MULTIMSG_EXTENSION => MSI_CAP_MULTIMSG_EXTENSION,
|
1650 |
|
|
MSI_CAP_NEXTPTR => MSI_CAP_NEXTPTR,
|
1651 |
|
|
MSI_CAP_ON => MSI_CAP_ON,
|
1652 |
|
|
MSI_CAP_PER_VECTOR_MASKING_CAPABLE => MSI_CAP_PER_VECTOR_MASKING_CAPABLE,
|
1653 |
|
|
MSI_CAP_64_BIT_ADDR_CAPABLE => MSI_CAP_64_BIT_ADDR_CAPABLE,
|
1654 |
|
|
MSIX_BASE_PTR => MSIX_BASE_PTR,
|
1655 |
|
|
MSIX_CAP_ID => MSIX_CAP_ID,
|
1656 |
|
|
MSIX_CAP_NEXTPTR => MSIX_CAP_NEXTPTR,
|
1657 |
|
|
MSIX_CAP_ON => MSIX_CAP_ON,
|
1658 |
|
|
MSIX_CAP_PBA_BIR => MSIX_CAP_PBA_BIR,
|
1659 |
|
|
MSIX_CAP_PBA_OFFSET => MSIX_CAP_PBA_OFFSET,
|
1660 |
|
|
MSIX_CAP_TABLE_BIR => MSIX_CAP_TABLE_BIR,
|
1661 |
|
|
MSIX_CAP_TABLE_OFFSET => MSIX_CAP_TABLE_OFFSET,
|
1662 |
|
|
MSIX_CAP_TABLE_SIZE => MSIX_CAP_TABLE_SIZE,
|
1663 |
|
|
N_FTS_COMCLK_GEN1 => N_FTS_COMCLK_GEN1,
|
1664 |
|
|
N_FTS_COMCLK_GEN2 => N_FTS_COMCLK_GEN2,
|
1665 |
|
|
N_FTS_GEN1 => N_FTS_GEN1,
|
1666 |
|
|
N_FTS_GEN2 => N_FTS_GEN2,
|
1667 |
|
|
PCIE_BASE_PTR => PCIE_BASE_PTR,
|
1668 |
|
|
PCIE_CAP_CAPABILITY_ID => PCIE_CAP_CAPABILITY_ID,
|
1669 |
|
|
PCIE_CAP_CAPABILITY_VERSION => PCIE_CAP_CAPABILITY_VERSION,
|
1670 |
|
|
PCIE_CAP_DEVICE_PORT_TYPE => PCIE_CAP_DEVICE_PORT_TYPE,
|
1671 |
|
|
PCIE_CAP_INT_MSG_NUM => PCIE_CAP_INT_MSG_NUM,
|
1672 |
|
|
PCIE_CAP_NEXTPTR => PCIE_CAP_NEXTPTR,
|
1673 |
|
|
PCIE_CAP_ON => PCIE_CAP_ON,
|
1674 |
|
|
PCIE_CAP_RSVD_15_14 => PCIE_CAP_RSVD_15_14,
|
1675 |
|
|
PCIE_CAP_SLOT_IMPLEMENTED => PCIE_CAP_SLOT_IMPLEMENTED,
|
1676 |
|
|
PCIE_REVISION => PCIE_REVISION,
|
1677 |
|
|
PGL0_LANE => PGL0_LANE,
|
1678 |
|
|
PGL1_LANE => PGL1_LANE,
|
1679 |
|
|
PGL2_LANE => PGL2_LANE,
|
1680 |
|
|
PGL3_LANE => PGL3_LANE,
|
1681 |
|
|
PGL4_LANE => PGL4_LANE,
|
1682 |
|
|
PGL5_LANE => PGL5_LANE,
|
1683 |
|
|
PGL6_LANE => PGL6_LANE,
|
1684 |
|
|
PGL7_LANE => PGL7_LANE,
|
1685 |
|
|
PL_AUTO_CONFIG => PL_AUTO_CONFIG,
|
1686 |
|
|
PL_FAST_TRAIN => PL_FAST_TRAIN,
|
1687 |
|
|
PM_BASE_PTR => PM_BASE_PTR,
|
1688 |
|
|
PM_CAP_AUXCURRENT => PM_CAP_AUXCURRENT,
|
1689 |
|
|
PM_CAP_DSI => PM_CAP_DSI,
|
1690 |
|
|
PM_CAP_D1SUPPORT => PM_CAP_D1SUPPORT,
|
1691 |
|
|
PM_CAP_D2SUPPORT => PM_CAP_D2SUPPORT,
|
1692 |
|
|
PM_CAP_ID => PM_CAP_ID,
|
1693 |
|
|
PM_CAP_NEXTPTR => PM_CAP_NEXTPTR,
|
1694 |
|
|
PM_CAP_ON => PM_CAP_ON,
|
1695 |
|
|
PM_CAP_PME_CLOCK => PM_CAP_PME_CLOCK,
|
1696 |
|
|
PM_CAP_PMESUPPORT => PM_CAP_PMESUPPORT,
|
1697 |
|
|
PM_CAP_RSVD_04 => PM_CAP_RSVD_04,
|
1698 |
|
|
PM_CAP_VERSION => PM_CAP_VERSION,
|
1699 |
|
|
PM_CSR_BPCCEN => PM_CSR_BPCCEN,
|
1700 |
|
|
PM_CSR_B2B3 => PM_CSR_B2B3,
|
1701 |
|
|
PM_CSR_NOSOFTRST => PM_CSR_NOSOFTRST,
|
1702 |
|
|
PM_DATA_SCALE0 => PM_DATA_SCALE0,
|
1703 |
|
|
PM_DATA_SCALE1 => PM_DATA_SCALE1,
|
1704 |
|
|
PM_DATA_SCALE2 => PM_DATA_SCALE2,
|
1705 |
|
|
PM_DATA_SCALE3 => PM_DATA_SCALE3,
|
1706 |
|
|
PM_DATA_SCALE4 => PM_DATA_SCALE4,
|
1707 |
|
|
PM_DATA_SCALE5 => PM_DATA_SCALE5,
|
1708 |
|
|
PM_DATA_SCALE6 => PM_DATA_SCALE6,
|
1709 |
|
|
PM_DATA_SCALE7 => PM_DATA_SCALE7,
|
1710 |
|
|
PM_DATA0 => PM_DATA0,
|
1711 |
|
|
PM_DATA1 => PM_DATA1,
|
1712 |
|
|
PM_DATA2 => PM_DATA2,
|
1713 |
|
|
PM_DATA3 => PM_DATA3,
|
1714 |
|
|
PM_DATA4 => PM_DATA4,
|
1715 |
|
|
PM_DATA5 => PM_DATA5,
|
1716 |
|
|
PM_DATA6 => PM_DATA6,
|
1717 |
|
|
PM_DATA7 => PM_DATA7,
|
1718 |
|
|
RECRC_CHK => RECRC_CHK,
|
1719 |
|
|
RECRC_CHK_TRIM => RECRC_CHK_TRIM,
|
1720 |
|
|
REVISION_ID => REVISION_ID,
|
1721 |
|
|
ROOT_CAP_CRS_SW_VISIBILITY => ROOT_CAP_CRS_SW_VISIBILITY,
|
1722 |
|
|
SELECT_DLL_IF => SELECT_DLL_IF,
|
1723 |
|
|
SLOT_CAP_ATT_BUTTON_PRESENT => SLOT_CAP_ATT_BUTTON_PRESENT,
|
1724 |
|
|
SLOT_CAP_ATT_INDICATOR_PRESENT => SLOT_CAP_ATT_INDICATOR_PRESENT,
|
1725 |
|
|
SLOT_CAP_ELEC_INTERLOCK_PRESENT => SLOT_CAP_ELEC_INTERLOCK_PRESENT,
|
1726 |
|
|
SLOT_CAP_HOTPLUG_CAPABLE => SLOT_CAP_HOTPLUG_CAPABLE,
|
1727 |
|
|
SLOT_CAP_HOTPLUG_SURPRISE => SLOT_CAP_HOTPLUG_SURPRISE,
|
1728 |
|
|
SLOT_CAP_MRL_SENSOR_PRESENT => SLOT_CAP_MRL_SENSOR_PRESENT,
|
1729 |
|
|
SLOT_CAP_NO_CMD_COMPLETED_SUPPORT => SLOT_CAP_NO_CMD_COMPLETED_SUPPORT,
|
1730 |
|
|
SLOT_CAP_PHYSICAL_SLOT_NUM => SLOT_CAP_PHYSICAL_SLOT_NUM,
|
1731 |
|
|
SLOT_CAP_POWER_CONTROLLER_PRESENT => SLOT_CAP_POWER_CONTROLLER_PRESENT,
|
1732 |
|
|
SLOT_CAP_POWER_INDICATOR_PRESENT => SLOT_CAP_POWER_INDICATOR_PRESENT,
|
1733 |
|
|
SLOT_CAP_SLOT_POWER_LIMIT_SCALE => SLOT_CAP_SLOT_POWER_LIMIT_SCALE,
|
1734 |
|
|
SLOT_CAP_SLOT_POWER_LIMIT_VALUE => SLOT_CAP_SLOT_POWER_LIMIT_VALUE,
|
1735 |
|
|
SPARE_BIT0 => SPARE_BIT0,
|
1736 |
|
|
SPARE_BIT1 => SPARE_BIT1,
|
1737 |
|
|
SPARE_BIT2 => SPARE_BIT2,
|
1738 |
|
|
SPARE_BIT3 => SPARE_BIT3,
|
1739 |
|
|
SPARE_BIT4 => SPARE_BIT4,
|
1740 |
|
|
SPARE_BIT5 => SPARE_BIT5,
|
1741 |
|
|
SPARE_BIT6 => SPARE_BIT6,
|
1742 |
|
|
SPARE_BIT7 => SPARE_BIT7,
|
1743 |
|
|
SPARE_BIT8 => SPARE_BIT8,
|
1744 |
|
|
SPARE_BYTE0 => SPARE_BYTE0,
|
1745 |
|
|
SPARE_BYTE1 => SPARE_BYTE1,
|
1746 |
|
|
SPARE_BYTE2 => SPARE_BYTE2,
|
1747 |
|
|
SPARE_BYTE3 => SPARE_BYTE3,
|
1748 |
|
|
SPARE_WORD0 => SPARE_WORD0,
|
1749 |
|
|
SPARE_WORD1 => SPARE_WORD1,
|
1750 |
|
|
SPARE_WORD2 => SPARE_WORD2,
|
1751 |
|
|
SPARE_WORD3 => SPARE_WORD3,
|
1752 |
|
|
SUBSYSTEM_ID => SUBSYSTEM_ID,
|
1753 |
|
|
SUBSYSTEM_VENDOR_ID => SUBSYSTEM_VENDOR_ID,
|
1754 |
|
|
TL_RBYPASS => TL_RBYPASS,
|
1755 |
|
|
TL_RX_RAM_RADDR_LATENCY => TL_RX_RAM_RADDR_LATENCY,
|
1756 |
|
|
TL_RX_RAM_RDATA_LATENCY => TL_RX_RAM_RDATA_LATENCY,
|
1757 |
|
|
TL_RX_RAM_WRITE_LATENCY => TL_RX_RAM_WRITE_LATENCY,
|
1758 |
|
|
TL_TFC_DISABLE => TL_TFC_DISABLE,
|
1759 |
|
|
TL_TX_CHECKS_DISABLE => TL_TX_CHECKS_DISABLE,
|
1760 |
|
|
TL_TX_RAM_RADDR_LATENCY => TL_TX_RAM_RADDR_LATENCY,
|
1761 |
|
|
TL_TX_RAM_RDATA_LATENCY => TL_TX_RAM_RDATA_LATENCY,
|
1762 |
|
|
TL_TX_RAM_WRITE_LATENCY => TL_TX_RAM_WRITE_LATENCY,
|
1763 |
|
|
UPCONFIG_CAPABLE => UPCONFIG_CAPABLE,
|
1764 |
|
|
UPSTREAM_FACING => UPSTREAM_FACING,
|
1765 |
|
|
EXIT_LOOPBACK_ON_EI => EXIT_LOOPBACK_ON_EI,
|
1766 |
|
|
UR_INV_REQ => UR_INV_REQ,
|
1767 |
|
|
USER_CLK_FREQ => USER_CLK_FREQ,
|
1768 |
|
|
VC_BASE_PTR => VC_BASE_PTR,
|
1769 |
|
|
VC_CAP_ID => VC_CAP_ID,
|
1770 |
|
|
VC_CAP_NEXTPTR => VC_CAP_NEXTPTR,
|
1771 |
|
|
VC_CAP_ON => VC_CAP_ON,
|
1772 |
|
|
VC_CAP_REJECT_SNOOP_TRANSACTIONS => VC_CAP_REJECT_SNOOP_TRANSACTIONS,
|
1773 |
|
|
VC_CAP_VERSION => VC_CAP_VERSION,
|
1774 |
|
|
VC0_CPL_INFINITE => VC0_CPL_INFINITE,
|
1775 |
|
|
VC0_RX_RAM_LIMIT => VC0_RX_RAM_LIMIT,
|
1776 |
|
|
VC0_TOTAL_CREDITS_CD => VC0_TOTAL_CREDITS_CD,
|
1777 |
|
|
VC0_TOTAL_CREDITS_CH => VC0_TOTAL_CREDITS_CH,
|
1778 |
|
|
VC0_TOTAL_CREDITS_NPH => VC0_TOTAL_CREDITS_NPH,
|
1779 |
|
|
VC0_TOTAL_CREDITS_PD => VC0_TOTAL_CREDITS_PD,
|
1780 |
|
|
VC0_TOTAL_CREDITS_PH => VC0_TOTAL_CREDITS_PH,
|
1781 |
|
|
VC0_TX_LASTPACKET => VC0_TX_LASTPACKET,
|
1782 |
|
|
VENDOR_ID => VENDOR_ID,
|
1783 |
|
|
VSEC_BASE_PTR => VSEC_BASE_PTR,
|
1784 |
|
|
VSEC_CAP_HDR_ID => VSEC_CAP_HDR_ID,
|
1785 |
|
|
VSEC_CAP_HDR_LENGTH => VSEC_CAP_HDR_LENGTH,
|
1786 |
|
|
VSEC_CAP_HDR_REVISION => VSEC_CAP_HDR_REVISION,
|
1787 |
|
|
VSEC_CAP_ID => VSEC_CAP_ID,
|
1788 |
|
|
VSEC_CAP_IS_LINK_VISIBLE => VSEC_CAP_IS_LINK_VISIBLE,
|
1789 |
|
|
VSEC_CAP_NEXTPTR => VSEC_CAP_NEXTPTR,
|
1790 |
|
|
VSEC_CAP_ON => VSEC_CAP_ON,
|
1791 |
|
|
VSEC_CAP_VERSION => VSEC_CAP_VERSION
|
1792 |
|
|
)
|
1793 |
|
|
port map (
|
1794 |
|
|
CFGAERECRCCHECKEN => CFGAERECRCCHECKEN_v6pcie0,
|
1795 |
|
|
CFGAERECRCGENEN => CFGAERECRCGENEN_v6pcie1,
|
1796 |
|
|
CFGCOMMANDBUSMASTERENABLE => CFGCOMMANDBUSMASTERENABLE_v6pcie2,
|
1797 |
|
|
CFGCOMMANDINTERRUPTDISABLE => CFGCOMMANDINTERRUPTDISABLE_v6pcie3,
|
1798 |
|
|
CFGCOMMANDIOENABLE => CFGCOMMANDIOENABLE_v6pcie4,
|
1799 |
|
|
CFGCOMMANDMEMENABLE => CFGCOMMANDMEMENABLE_v6pcie5,
|
1800 |
|
|
CFGCOMMANDSERREN => CFGCOMMANDSERREN_v6pcie6,
|
1801 |
|
|
CFGDEVCONTROLAUXPOWEREN => CFGDEVCONTROLAUXPOWEREN_v6pcie9,
|
1802 |
|
|
CFGDEVCONTROLCORRERRREPORTINGEN => CFGDEVCONTROLCORRERRREPORTINGEN_v6pcie10,
|
1803 |
|
|
CFGDEVCONTROLENABLERO => CFGDEVCONTROLENABLERO_v6pcie11,
|
1804 |
|
|
CFGDEVCONTROLEXTTAGEN => CFGDEVCONTROLEXTTAGEN_v6pcie12,
|
1805 |
|
|
CFGDEVCONTROLFATALERRREPORTINGEN => CFGDEVCONTROLFATALERRREPORTINGEN_v6pcie13,
|
1806 |
|
|
CFGDEVCONTROLMAXPAYLOAD => CFGDEVCONTROLMAXPAYLOAD_v6pcie14,
|
1807 |
|
|
CFGDEVCONTROLMAXREADREQ => CFGDEVCONTROLMAXREADREQ_v6pcie15,
|
1808 |
|
|
CFGDEVCONTROLNONFATALREPORTINGEN => CFGDEVCONTROLNONFATALREPORTINGEN_v6pcie16,
|
1809 |
|
|
CFGDEVCONTROLNOSNOOPEN => CFGDEVCONTROLNOSNOOPEN_v6pcie17,
|
1810 |
|
|
CFGDEVCONTROLPHANTOMEN => CFGDEVCONTROLPHANTOMEN_v6pcie18,
|
1811 |
|
|
CFGDEVCONTROLURERRREPORTINGEN => CFGDEVCONTROLURERRREPORTINGEN_v6pcie19,
|
1812 |
|
|
CFGDEVCONTROL2CPLTIMEOUTDIS => CFGDEVCONTROL2CPLTIMEOUTDIS_v6pcie7,
|
1813 |
|
|
CFGDEVCONTROL2CPLTIMEOUTVAL => CFGDEVCONTROL2CPLTIMEOUTVAL_v6pcie8,
|
1814 |
|
|
CFGDEVSTATUSCORRERRDETECTED => CFGDEVSTATUSCORRERRDETECTED_v6pcie20,
|
1815 |
|
|
CFGDEVSTATUSFATALERRDETECTED => CFGDEVSTATUSFATALERRDETECTED_v6pcie21,
|
1816 |
|
|
CFGDEVSTATUSNONFATALERRDETECTED => CFGDEVSTATUSNONFATALERRDETECTED_v6pcie22,
|
1817 |
|
|
CFGDEVSTATUSURDETECTED => CFGDEVSTATUSURDETECTED_v6pcie23,
|
1818 |
|
|
CFGDO => CFGDO_v6pcie24,
|
1819 |
|
|
CFGERRAERHEADERLOGSETN => CFGERRAERHEADERLOGSETN_v6pcie25,
|
1820 |
|
|
CFGERRCPLRDYN => CFGERRCPLRDYN_v6pcie26,
|
1821 |
|
|
CFGINTERRUPTDO => CFGINTERRUPTDO_v6pcie27,
|
1822 |
|
|
CFGINTERRUPTMMENABLE => CFGINTERRUPTMMENABLE_v6pcie28,
|
1823 |
|
|
CFGINTERRUPTMSIENABLE => CFGINTERRUPTMSIENABLE_v6pcie29,
|
1824 |
|
|
CFGINTERRUPTMSIXENABLE => CFGINTERRUPTMSIXENABLE_v6pcie30,
|
1825 |
|
|
CFGINTERRUPTMSIXFM => CFGINTERRUPTMSIXFM_v6pcie31,
|
1826 |
|
|
CFGINTERRUPTRDYN => CFGINTERRUPTRDYN_v6pcie32,
|
1827 |
|
|
CFGLINKCONTROLRCB => CFGLINKCONTROLRCB_v6pcie41,
|
1828 |
|
|
CFGLINKCONTROLASPMCONTROL => CFGLINKCONTROLASPMCONTROL_v6pcie33,
|
1829 |
|
|
CFGLINKCONTROLAUTOBANDWIDTHINTEN => CFGLINKCONTROLAUTOBANDWIDTHINTEN_v6pcie34,
|
1830 |
|
|
CFGLINKCONTROLBANDWIDTHINTEN => CFGLINKCONTROLBANDWIDTHINTEN_v6pcie35,
|
1831 |
|
|
CFGLINKCONTROLCLOCKPMEN => CFGLINKCONTROLCLOCKPMEN_v6pcie36,
|
1832 |
|
|
CFGLINKCONTROLCOMMONCLOCK => CFGLINKCONTROLCOMMONCLOCK_v6pcie37,
|
1833 |
|
|
CFGLINKCONTROLEXTENDEDSYNC => CFGLINKCONTROLEXTENDEDSYNC_v6pcie38,
|
1834 |
|
|
CFGLINKCONTROLHWAUTOWIDTHDIS => CFGLINKCONTROLHWAUTOWIDTHDIS_v6pcie39,
|
1835 |
|
|
CFGLINKCONTROLLINKDISABLE => CFGLINKCONTROLLINKDISABLE_v6pcie40,
|
1836 |
|
|
CFGLINKCONTROLRETRAINLINK => CFGLINKCONTROLRETRAINLINK_v6pcie42,
|
1837 |
|
|
CFGLINKSTATUSAUTOBANDWIDTHSTATUS => CFGLINKSTATUSAUTOBANDWIDTHSTATUS_v6pcie43,
|
1838 |
|
|
CFGLINKSTATUSBANDWITHSTATUS => CFGLINKSTATUSBANDWITHSTATUS_v6pcie44,
|
1839 |
|
|
CFGLINKSTATUSCURRENTSPEED => CFGLINKSTATUSCURRENTSPEED_v6pcie45,
|
1840 |
|
|
CFGLINKSTATUSDLLACTIVE => CFGLINKSTATUSDLLACTIVE_v6pcie46,
|
1841 |
|
|
CFGLINKSTATUSLINKTRAINING => CFGLINKSTATUSLINKTRAINING_v6pcie47,
|
1842 |
|
|
CFGLINKSTATUSNEGOTIATEDWIDTH => CFGLINKSTATUSNEGOTIATEDWIDTH_v6pcie48,
|
1843 |
|
|
CFGMSGDATA => CFGMSGDATA_v6pcie49,
|
1844 |
|
|
CFGMSGRECEIVED => CFGMSGRECEIVED_v6pcie50,
|
1845 |
|
|
CFGMSGRECEIVEDASSERTINTA => CFGMSGRECEIVEDASSERTINTA_v6pcie51,
|
1846 |
|
|
CFGMSGRECEIVEDASSERTINTB => CFGMSGRECEIVEDASSERTINTB_v6pcie52,
|
1847 |
|
|
CFGMSGRECEIVEDASSERTINTC => CFGMSGRECEIVEDASSERTINTC_v6pcie53,
|
1848 |
|
|
CFGMSGRECEIVEDASSERTINTD => CFGMSGRECEIVEDASSERTINTD_v6pcie54,
|
1849 |
|
|
CFGMSGRECEIVEDDEASSERTINTA => CFGMSGRECEIVEDDEASSERTINTA_v6pcie55,
|
1850 |
|
|
CFGMSGRECEIVEDDEASSERTINTB => CFGMSGRECEIVEDDEASSERTINTB_v6pcie56,
|
1851 |
|
|
CFGMSGRECEIVEDDEASSERTINTC => CFGMSGRECEIVEDDEASSERTINTC_v6pcie57,
|
1852 |
|
|
CFGMSGRECEIVEDDEASSERTINTD => CFGMSGRECEIVEDDEASSERTINTD_v6pcie58,
|
1853 |
|
|
CFGMSGRECEIVEDERRCOR => CFGMSGRECEIVEDERRCOR_v6pcie59,
|
1854 |
|
|
CFGMSGRECEIVEDERRFATAL => CFGMSGRECEIVEDERRFATAL_v6pcie60,
|
1855 |
|
|
CFGMSGRECEIVEDERRNONFATAL => CFGMSGRECEIVEDERRNONFATAL_v6pcie61,
|
1856 |
|
|
CFGMSGRECEIVEDPMASNAK => CFGMSGRECEIVEDPMASNAK_v6pcie62,
|
1857 |
|
|
CFGMSGRECEIVEDPMETO => CFGMSGRECEIVEDPMETO_v6pcie63,
|
1858 |
|
|
CFGMSGRECEIVEDPMETOACK => CFGMSGRECEIVEDPMETOACK_v6pcie64,
|
1859 |
|
|
CFGMSGRECEIVEDPMPME => CFGMSGRECEIVEDPMPME_v6pcie65,
|
1860 |
|
|
CFGMSGRECEIVEDSETSLOTPOWERLIMIT => CFGMSGRECEIVEDSETSLOTPOWERLIMIT_v6pcie66,
|
1861 |
|
|
CFGMSGRECEIVEDUNLOCK => CFGMSGRECEIVEDUNLOCK_v6pcie67,
|
1862 |
|
|
CFGPCIELINKSTATE => CFGPCIELINKSTATE_v6pcie68,
|
1863 |
|
|
CFGPMRCVASREQL1N => CFGPMRCVASREQL1N_v6pcie72,
|
1864 |
|
|
CFGPMRCVENTERL1N => CFGPMRCVENTERL1N_v6pcie73,
|
1865 |
|
|
CFGPMRCVENTERL23N => CFGPMRCVENTERL23N_v6pcie74,
|
1866 |
|
|
CFGPMRCVREQACKN => CFGPMRCVREQACKN_v6pcie75,
|
1867 |
|
|
CFGPMCSRPMEEN => CFGPMCSRPMEEN_v6pcie69,
|
1868 |
|
|
CFGPMCSRPMESTATUS => CFGPMCSRPMESTATUS_v6pcie70,
|
1869 |
|
|
CFGPMCSRPOWERSTATE => CFGPMCSRPOWERSTATE_v6pcie71,
|
1870 |
|
|
CFGRDWRDONEN => CFGRDWRDONEN_v6pcie76,
|
1871 |
|
|
CFGSLOTCONTROLELECTROMECHILCTLPULSE => CFGSLOTCONTROLELECTROMECHILCTLPULSE_v6pcie77,
|
1872 |
|
|
CFGTRANSACTION => CFGTRANSACTION_v6pcie78,
|
1873 |
|
|
CFGTRANSACTIONADDR => CFGTRANSACTIONADDR_v6pcie79,
|
1874 |
|
|
CFGTRANSACTIONTYPE => CFGTRANSACTIONTYPE_v6pcie80,
|
1875 |
|
|
CFGVCTCVCMAP => CFGVCTCVCMAP_v6pcie81,
|
1876 |
|
|
DBGSCLRA => DBGSCLRA_v6pcie82,
|
1877 |
|
|
DBGSCLRB => DBGSCLRB_v6pcie83,
|
1878 |
|
|
DBGSCLRC => DBGSCLRC_v6pcie84,
|
1879 |
|
|
DBGSCLRD => DBGSCLRD_v6pcie85,
|
1880 |
|
|
DBGSCLRE => DBGSCLRE_v6pcie86,
|
1881 |
|
|
DBGSCLRF => DBGSCLRF_v6pcie87,
|
1882 |
|
|
DBGSCLRG => DBGSCLRG_v6pcie88,
|
1883 |
|
|
DBGSCLRH => DBGSCLRH_v6pcie89,
|
1884 |
|
|
DBGSCLRI => DBGSCLRI_v6pcie90,
|
1885 |
|
|
DBGSCLRJ => DBGSCLRJ_v6pcie91,
|
1886 |
|
|
DBGSCLRK => DBGSCLRK_v6pcie92,
|
1887 |
|
|
DBGVECA => DBGVECA_v6pcie93,
|
1888 |
|
|
DBGVECB => DBGVECB_v6pcie94,
|
1889 |
|
|
DBGVECC => DBGVECC_v6pcie95,
|
1890 |
|
|
DRPDO => PCIEDRPDO_v6pcie98,
|
1891 |
|
|
DRPDRDY => PCIEDRPDRDY_v6pcie99,
|
1892 |
|
|
LL2BADDLLPERRN => LL2BADDLLPERRN,
|
1893 |
|
|
LL2BADTLPERRN => LL2BADTLPERRN,
|
1894 |
|
|
LL2PROTOCOLERRN => LL2PROTOCOLERRN,
|
1895 |
|
|
LL2REPLAYROERRN => LL2REPLAYROERRN,
|
1896 |
|
|
LL2REPLAYTOERRN => LL2REPLAYTOERRN,
|
1897 |
|
|
LL2SUSPENDOKN => LL2SUSPENDOKN,
|
1898 |
|
|
LL2TFCINIT1SEQN => LL2TFCINIT1SEQN,
|
1899 |
|
|
LL2TFCINIT2SEQN => LL2TFCINIT2SEQN,
|
1900 |
|
|
MIMRXRADDR => MIMRXRADDR,
|
1901 |
|
|
MIMRXRCE => MIMRXRCE,
|
1902 |
|
|
MIMRXREN => MIMRXREN,
|
1903 |
|
|
MIMRXWADDR => MIMRXWADDR,
|
1904 |
|
|
MIMRXWDATA => MIMRXWDATA,
|
1905 |
|
|
MIMRXWEN => MIMRXWEN,
|
1906 |
|
|
MIMTXRADDR => MIMTXRADDR,
|
1907 |
|
|
MIMTXRCE => MIMTXRCE,
|
1908 |
|
|
MIMTXREN => MIMTXREN,
|
1909 |
|
|
MIMTXWADDR => MIMTXWADDR,
|
1910 |
|
|
MIMTXWDATA => MIMTXWDATA,
|
1911 |
|
|
MIMTXWEN => MIMTXWEN,
|
1912 |
|
|
PIPERX0POLARITY => PIPERX0POLARITY,
|
1913 |
|
|
PIPERX1POLARITY => PIPERX1POLARITY,
|
1914 |
|
|
PIPERX2POLARITY => PIPERX2POLARITY,
|
1915 |
|
|
PIPERX3POLARITY => PIPERX3POLARITY,
|
1916 |
|
|
PIPERX4POLARITY => PIPERX4POLARITY,
|
1917 |
|
|
PIPERX5POLARITY => PIPERX5POLARITY,
|
1918 |
|
|
PIPERX6POLARITY => PIPERX6POLARITY,
|
1919 |
|
|
PIPERX7POLARITY => PIPERX7POLARITY,
|
1920 |
|
|
PIPETXDEEMPH => PIPETXDEEMPH,
|
1921 |
|
|
PIPETXMARGIN => PIPETXMARGIN,
|
1922 |
|
|
PIPETXRATE => PIPETXRATE,
|
1923 |
|
|
PIPETXRCVRDET => PIPETXRCVRDET,
|
1924 |
|
|
PIPETXRESET => PIPETXRESET,
|
1925 |
|
|
PIPETX0CHARISK => PIPETX0CHARISK,
|
1926 |
|
|
PIPETX0COMPLIANCE => PIPETX0COMPLIANCE,
|
1927 |
|
|
PIPETX0DATA => PIPETX0DATA,
|
1928 |
|
|
PIPETX0ELECIDLE => PIPETX0ELECIDLE,
|
1929 |
|
|
PIPETX0POWERDOWN => PIPETX0POWERDOWN,
|
1930 |
|
|
PIPETX1CHARISK => PIPETX1CHARISK,
|
1931 |
|
|
PIPETX1COMPLIANCE => PIPETX1COMPLIANCE,
|
1932 |
|
|
PIPETX1DATA => PIPETX1DATA,
|
1933 |
|
|
PIPETX1ELECIDLE => PIPETX1ELECIDLE,
|
1934 |
|
|
PIPETX1POWERDOWN => PIPETX1POWERDOWN,
|
1935 |
|
|
PIPETX2CHARISK => PIPETX2CHARISK,
|
1936 |
|
|
PIPETX2COMPLIANCE => PIPETX2COMPLIANCE,
|
1937 |
|
|
PIPETX2DATA => PIPETX2DATA,
|
1938 |
|
|
PIPETX2ELECIDLE => PIPETX2ELECIDLE,
|
1939 |
|
|
PIPETX2POWERDOWN => PIPETX2POWERDOWN,
|
1940 |
|
|
PIPETX3CHARISK => PIPETX3CHARISK,
|
1941 |
|
|
PIPETX3COMPLIANCE => PIPETX3COMPLIANCE,
|
1942 |
|
|
PIPETX3DATA => PIPETX3DATA,
|
1943 |
|
|
PIPETX3ELECIDLE => PIPETX3ELECIDLE,
|
1944 |
|
|
PIPETX3POWERDOWN => PIPETX3POWERDOWN,
|
1945 |
|
|
PIPETX4CHARISK => PIPETX4CHARISK,
|
1946 |
|
|
PIPETX4COMPLIANCE => PIPETX4COMPLIANCE,
|
1947 |
|
|
PIPETX4DATA => PIPETX4DATA,
|
1948 |
|
|
PIPETX4ELECIDLE => PIPETX4ELECIDLE,
|
1949 |
|
|
PIPETX4POWERDOWN => PIPETX4POWERDOWN,
|
1950 |
|
|
PIPETX5CHARISK => PIPETX5CHARISK,
|
1951 |
|
|
PIPETX5COMPLIANCE => PIPETX5COMPLIANCE,
|
1952 |
|
|
PIPETX5DATA => PIPETX5DATA,
|
1953 |
|
|
PIPETX5ELECIDLE => PIPETX5ELECIDLE,
|
1954 |
|
|
PIPETX5POWERDOWN => PIPETX5POWERDOWN,
|
1955 |
|
|
PIPETX6CHARISK => PIPETX6CHARISK,
|
1956 |
|
|
PIPETX6COMPLIANCE => PIPETX6COMPLIANCE,
|
1957 |
|
|
PIPETX6DATA => PIPETX6DATA,
|
1958 |
|
|
PIPETX6ELECIDLE => PIPETX6ELECIDLE,
|
1959 |
|
|
PIPETX6POWERDOWN => PIPETX6POWERDOWN,
|
1960 |
|
|
PIPETX7CHARISK => PIPETX7CHARISK,
|
1961 |
|
|
PIPETX7COMPLIANCE => PIPETX7COMPLIANCE,
|
1962 |
|
|
PIPETX7DATA => PIPETX7DATA,
|
1963 |
|
|
PIPETX7ELECIDLE => PIPETX7ELECIDLE,
|
1964 |
|
|
PIPETX7POWERDOWN => PIPETX7POWERDOWN,
|
1965 |
|
|
PLDBGVEC => PLDBGVEC_v6pcie103,
|
1966 |
|
|
PLINITIALLINKWIDTH => PLINITIALLINKWIDTH_v6pcie104,
|
1967 |
|
|
PLLANEREVERSALMODE => PLLANEREVERSALMODE_v6pcie105,
|
1968 |
|
|
PLLINKGEN2CAP => PLLINKGEN2CAP_v6pcie106,
|
1969 |
|
|
PLLINKPARTNERGEN2SUPPORTED => PLLINKPARTNERGEN2SUPPORTED_v6pcie107,
|
1970 |
|
|
PLLINKUPCFGCAP => PLLINKUPCFGCAP_v6pcie108,
|
1971 |
|
|
PLLTSSMSTATE => PLLTSSMSTATE_v6pcie109,
|
1972 |
|
|
PLPHYLNKUPN => PLPHYLNKUPN_v6pcie110,
|
1973 |
|
|
PLRECEIVEDHOTRST => PLRECEIVEDHOTRST_v6pcie111,
|
1974 |
|
|
PLRXPMSTATE => PLRXPMSTATE_v6pcie112,
|
1975 |
|
|
PLSELLNKRATE => PLSELLNKRATE_v6pcie113,
|
1976 |
|
|
PLSELLNKWIDTH => PLSELLNKWIDTH_v6pcie114,
|
1977 |
|
|
PLTXPMSTATE => PLTXPMSTATE_v6pcie115,
|
1978 |
|
|
PL2LINKUPN => PL2LINKUPN,
|
1979 |
|
|
PL2RECEIVERERRN => PL2RECEIVERERRN,
|
1980 |
|
|
PL2RECOVERYN => PL2RECOVERYN,
|
1981 |
|
|
PL2RXELECIDLE => PL2RXELECIDLE,
|
1982 |
|
|
PL2SUSPENDOK => PL2SUSPENDOK,
|
1983 |
|
|
RECEIVEDFUNCLVLRSTN => RECEIVEDFUNCLVLRSTN_v6pcie116,
|
1984 |
|
|
LNKCLKEN => LNKCLKEN_v6pcie97,
|
1985 |
|
|
TL2ASPMSUSPENDCREDITCHECKOKN => TL2ASPMSUSPENDCREDITCHECKOKN,
|
1986 |
|
|
TL2ASPMSUSPENDREQN => TL2ASPMSUSPENDREQN,
|
1987 |
|
|
TL2PPMSUSPENDOKN => TL2PPMSUSPENDOKN,
|
1988 |
|
|
TRNFCCPLD => TRNFCCPLD_v6pcie117,
|
1989 |
|
|
TRNFCCPLH => TRNFCCPLH_v6pcie118,
|
1990 |
|
|
TRNFCNPD => TRNFCNPD_v6pcie119,
|
1991 |
|
|
TRNFCNPH => TRNFCNPH_v6pcie120,
|
1992 |
|
|
TRNFCPD => TRNFCPD_v6pcie121,
|
1993 |
|
|
TRNFCPH => TRNFCPH_v6pcie122,
|
1994 |
|
|
TRNLNKUPN => TRNLNKUPN_v6pcie123,
|
1995 |
|
|
TRNRBARHITN => TRNRBARHITN_v6pcie124,
|
1996 |
|
|
TRNRD => TRNRD_v6pcie125,
|
1997 |
|
|
TRNRDLLPDATA => open,
|
1998 |
|
|
TRNRDLLPSRCRDYN => TRNRDLLPSRCRDYN,
|
1999 |
|
|
TRNRECRCERRN => TRNRECRCERRN_v6pcie126,
|
2000 |
|
|
TRNREOFN => TRNREOFN_v6pcie127,
|
2001 |
|
|
TRNRERRFWDN => TRNRERRFWDN_v6pcie128,
|
2002 |
|
|
TRNRREMN => TRNRREMN_v6pcie129,
|
2003 |
|
|
TRNRSOFN => TRNRSOFN_v6pcie130,
|
2004 |
|
|
TRNRSRCDSCN => TRNRSRCDSCN_v6pcie131,
|
2005 |
|
|
TRNRSRCRDYN => TRNRSRCRDYN_v6pcie132,
|
2006 |
|
|
TRNTBUFAV => TRNTBUFAV_v6pcie133,
|
2007 |
|
|
TRNTCFGREQN => TRNTCFGREQN_v6pcie134,
|
2008 |
|
|
|
2009 |
|
|
TRNTDLLPDSTRDYN => TRNTDLLPDSTRDYN_v6pcie135,
|
2010 |
|
|
TRNTDSTRDYN => TRNTDSTRDYN_v6pcie136,
|
2011 |
|
|
TRNTERRDROPN => TRNTERRDROPN_v6pcie137,
|
2012 |
|
|
|
2013 |
|
|
USERRSTN => USERRSTN_v6pcie139,
|
2014 |
|
|
|
2015 |
|
|
CFGBYTEENN => CFGBYTEENN,
|
2016 |
|
|
CFGDI => CFGDI,
|
2017 |
|
|
|
2018 |
|
|
CFGDSBUSNUMBER => CFGDSBUSNUMBER,
|
2019 |
|
|
CFGDSDEVICENUMBER => CFGDSDEVICENUMBER,
|
2020 |
|
|
|
2021 |
|
|
CFGDSFUNCTIONNUMBER => CFGDSFUNCTIONNUMBER,
|
2022 |
|
|
CFGDSN => CFGDSN,
|
2023 |
|
|
CFGDWADDR => CFGDWADDR,
|
2024 |
|
|
CFGERRACSN => CFGERRACSN,
|
2025 |
|
|
|
2026 |
|
|
CFGERRAERHEADERLOG => CFGERRAERHEADERLOG,
|
2027 |
|
|
CFGERRCORN => CFGERRCORN,
|
2028 |
|
|
CFGERRCPLABORTN => CFGERRCPLABORTN,
|
2029 |
|
|
CFGERRCPLTIMEOUTN => CFGERRCPLTIMEOUTN,
|
2030 |
|
|
CFGERRCPLUNEXPECTN => CFGERRCPLUNEXPECTN,
|
2031 |
|
|
CFGERRECRCN => CFGERRECRCN,
|
2032 |
|
|
CFGERRLOCKEDN => CFGERRLOCKEDN,
|
2033 |
|
|
CFGERRPOSTEDN => CFGERRPOSTEDN,
|
2034 |
|
|
CFGERRTLPCPLHEADER => CFGERRTLPCPLHEADER,
|
2035 |
|
|
CFGERRURN => CFGERRURN,
|
2036 |
|
|
CFGINTERRUPTASSERTN => CFGINTERRUPTASSERTN,
|
2037 |
|
|
CFGINTERRUPTDI => CFGINTERRUPTDI,
|
2038 |
|
|
CFGINTERRUPTN => CFGINTERRUPTN,
|
2039 |
|
|
CFGPMDIRECTASPML1N => CFGPMDIRECTASPML1N,
|
2040 |
|
|
CFGPMSENDPMACKN => CFGPMSENDPMACKN,
|
2041 |
|
|
CFGPMSENDPMETON => CFGPMSENDPMETON,
|
2042 |
|
|
CFGPMSENDPMNAKN => CFGPMSENDPMNAKN,
|
2043 |
|
|
CFGPMTURNOFFOKN => CFGPMTURNOFFOKN,
|
2044 |
|
|
CFGPMWAKEN => CFGPMWAKEN,
|
2045 |
|
|
CFGPORTNUMBER => CFGPORTNUMBER,
|
2046 |
|
|
CFGRDENN => CFGRDENN,
|
2047 |
|
|
CFGTRNPENDINGN => CFGTRNPENDINGN,
|
2048 |
|
|
CFGWRENN => CFGWRENN,
|
2049 |
|
|
CFGWRREADONLYN => CFGWRREADONLYN,
|
2050 |
|
|
CFGWRRW1CASRWN => CFGWRRW1CASRWN,
|
2051 |
|
|
CMRSTN => CMRSTN,
|
2052 |
|
|
CMSTICKYRSTN => CMSTICKYRSTN,
|
2053 |
|
|
DBGMODE => DBGMODE,
|
2054 |
|
|
DBGSUBMODE => DBGSUBMODE,
|
2055 |
|
|
DLRSTN => DLRSTN,
|
2056 |
|
|
DRPCLK => PCIEDRPCLK,
|
2057 |
|
|
DRPDADDR => PCIEDRPDADDR,
|
2058 |
|
|
DRPDEN => PCIEDRPDEN,
|
2059 |
|
|
DRPDI => PCIEDRPDI,
|
2060 |
|
|
DRPDWE => PCIEDRPDWE,
|
2061 |
|
|
FUNCLVLRSTN => FUNCLVLRSTN,
|
2062 |
|
|
LL2SENDASREQL1N => LL2SENDASREQL1N,
|
2063 |
|
|
LL2SENDENTERL1N => LL2SENDENTERL1N,
|
2064 |
|
|
LL2SENDENTERL23N => LL2SENDENTERL23N,
|
2065 |
|
|
LL2SUSPENDNOWN => LL2SUSPENDNOWN,
|
2066 |
|
|
LL2TLPRCVN => LL2TLPRCVN,
|
2067 |
|
|
MIMRXRDATA => MIMRXRDATA(67 downto 0),
|
2068 |
|
|
MIMTXRDATA => MIMTXRDATA(68 downto 0),
|
2069 |
|
|
PIPECLK => PIPECLK,
|
2070 |
|
|
PIPERX0CHANISALIGNED => PIPERX0CHANISALIGNED,
|
2071 |
|
|
PIPERX0CHARISK => PIPERX0CHARISK_v6pcie,
|
2072 |
|
|
PIPERX0DATA => PIPERX0DATA,
|
2073 |
|
|
PIPERX0ELECIDLE => PIPERX0ELECIDLE,
|
2074 |
|
|
PIPERX0PHYSTATUS => PIPERX0PHYSTATUS,
|
2075 |
|
|
PIPERX0STATUS => PIPERX0STATUS,
|
2076 |
|
|
PIPERX0VALID => PIPERX0VALID,
|
2077 |
|
|
PIPERX1CHANISALIGNED => PIPERX1CHANISALIGNED,
|
2078 |
|
|
PIPERX1CHARISK => PIPERX1CHARISK_v6pcie,
|
2079 |
|
|
PIPERX1DATA => PIPERX1DATA,
|
2080 |
|
|
PIPERX1ELECIDLE => PIPERX1ELECIDLE,
|
2081 |
|
|
PIPERX1PHYSTATUS => PIPERX1PHYSTATUS,
|
2082 |
|
|
PIPERX1STATUS => PIPERX1STATUS,
|
2083 |
|
|
PIPERX1VALID => PIPERX1VALID,
|
2084 |
|
|
PIPERX2CHANISALIGNED => PIPERX2CHANISALIGNED,
|
2085 |
|
|
PIPERX2CHARISK => PIPERX2CHARISK_v6pcie,
|
2086 |
|
|
PIPERX2DATA => PIPERX2DATA,
|
2087 |
|
|
PIPERX2ELECIDLE => PIPERX2ELECIDLE,
|
2088 |
|
|
PIPERX2PHYSTATUS => PIPERX2PHYSTATUS,
|
2089 |
|
|
PIPERX2STATUS => PIPERX2STATUS,
|
2090 |
|
|
PIPERX2VALID => PIPERX2VALID,
|
2091 |
|
|
PIPERX3CHANISALIGNED => PIPERX3CHANISALIGNED,
|
2092 |
|
|
PIPERX3CHARISK => PIPERX3CHARISK_v6pcie,
|
2093 |
|
|
PIPERX3DATA => PIPERX3DATA,
|
2094 |
|
|
PIPERX3ELECIDLE => PIPERX3ELECIDLE,
|
2095 |
|
|
PIPERX3PHYSTATUS => PIPERX3PHYSTATUS,
|
2096 |
|
|
PIPERX3STATUS => PIPERX3STATUS,
|
2097 |
|
|
PIPERX3VALID => PIPERX3VALID,
|
2098 |
|
|
PIPERX4CHANISALIGNED => PIPERX4CHANISALIGNED,
|
2099 |
|
|
PIPERX4CHARISK => PIPERX4CHARISK_v6pcie,
|
2100 |
|
|
PIPERX4DATA => PIPERX4DATA,
|
2101 |
|
|
PIPERX4ELECIDLE => PIPERX4ELECIDLE,
|
2102 |
|
|
PIPERX4PHYSTATUS => PIPERX4PHYSTATUS,
|
2103 |
|
|
PIPERX4STATUS => PIPERX4STATUS,
|
2104 |
|
|
PIPERX4VALID => PIPERX4VALID,
|
2105 |
|
|
PIPERX5CHANISALIGNED => PIPERX5CHANISALIGNED,
|
2106 |
|
|
PIPERX5CHARISK => PIPERX5CHARISK_v6pcie,
|
2107 |
|
|
PIPERX5DATA => PIPERX5DATA,
|
2108 |
|
|
PIPERX5ELECIDLE => PIPERX5ELECIDLE,
|
2109 |
|
|
PIPERX5PHYSTATUS => PIPERX5PHYSTATUS,
|
2110 |
|
|
PIPERX5STATUS => PIPERX5STATUS,
|
2111 |
|
|
PIPERX5VALID => PIPERX5VALID,
|
2112 |
|
|
PIPERX6CHANISALIGNED => PIPERX6CHANISALIGNED,
|
2113 |
|
|
PIPERX6CHARISK => PIPERX6CHARISK_v6pcie,
|
2114 |
|
|
PIPERX6DATA => PIPERX6DATA,
|
2115 |
|
|
PIPERX6ELECIDLE => PIPERX6ELECIDLE,
|
2116 |
|
|
PIPERX6PHYSTATUS => PIPERX6PHYSTATUS,
|
2117 |
|
|
PIPERX6STATUS => PIPERX6STATUS,
|
2118 |
|
|
PIPERX6VALID => PIPERX6VALID,
|
2119 |
|
|
PIPERX7CHANISALIGNED => PIPERX7CHANISALIGNED,
|
2120 |
|
|
PIPERX7CHARISK => PIPERX7CHARISK_v6pcie,
|
2121 |
|
|
PIPERX7DATA => PIPERX7DATA,
|
2122 |
|
|
PIPERX7ELECIDLE => PIPERX7ELECIDLE,
|
2123 |
|
|
PIPERX7PHYSTATUS => PIPERX7PHYSTATUS,
|
2124 |
|
|
PIPERX7STATUS => PIPERX7STATUS,
|
2125 |
|
|
PIPERX7VALID => PIPERX7VALID,
|
2126 |
|
|
PLDBGMODE => PLDBGMODE,
|
2127 |
|
|
PLDIRECTEDLINKAUTON => PLDIRECTEDLINKAUTON,
|
2128 |
|
|
PLDIRECTEDLINKCHANGE => PLDIRECTEDLINKCHANGE,
|
2129 |
|
|
PLDIRECTEDLINKSPEED => PLDIRECTEDLINKSPEED,
|
2130 |
|
|
PLDIRECTEDLINKWIDTH => PLDIRECTEDLINKWIDTH,
|
2131 |
|
|
PLDOWNSTREAMDEEMPHSOURCE => PLDOWNSTREAMDEEMPHSOURCE,
|
2132 |
|
|
PLRSTN => PLRSTN,
|
2133 |
|
|
PLTRANSMITHOTRST => PLTRANSMITHOTRST,
|
2134 |
|
|
PLUPSTREAMPREFERDEEMPH => PLUPSTREAMPREFERDEEMPH,
|
2135 |
|
|
PL2DIRECTEDLSTATE => PL2DIRECTEDLSTATE,
|
2136 |
|
|
SYSRSTN => SYSRSTN,
|
2137 |
|
|
TLRSTN => TLRSTN,
|
2138 |
|
|
TL2ASPMSUSPENDCREDITCHECKN => '1',
|
2139 |
|
|
TL2PPMSUSPENDREQN => '1',
|
2140 |
|
|
|
2141 |
|
|
TRNFCSEL => TRNFCSEL,
|
2142 |
|
|
TRNRDSTRDYN => TRNRDSTRDYN,
|
2143 |
|
|
TRNRNPOKN => TRNRNPOKN,
|
2144 |
|
|
TRNTCFGGNTN => TRNTCFGGNTN,
|
2145 |
|
|
TRNTD => TRNTD,
|
2146 |
|
|
TRNTDLLPDATA => TRNTDLLPDATA,
|
2147 |
|
|
|
2148 |
|
|
TRNTDLLPSRCRDYN => TRNTDLLPSRCRDYN,
|
2149 |
|
|
TRNTECRCGENN => TRNTECRCGENN,
|
2150 |
|
|
TRNTEOFN => TRNTEOFN,
|
2151 |
|
|
TRNTERRFWDN => TRNTERRFWDN,
|
2152 |
|
|
TRNTREMN => TRNTREMN,
|
2153 |
|
|
TRNTSOFN => TRNTSOFN,
|
2154 |
|
|
TRNTSRCDSCN => TRNTSRCDSCN,
|
2155 |
|
|
TRNTSRCRDYN => TRNTSRCRDYN,
|
2156 |
|
|
TRNTSTRN => TRNTSTRN,
|
2157 |
|
|
USERCLK => USERCLK
|
2158 |
|
|
);
|
2159 |
|
|
|
2160 |
|
|
---------------------------------------------------------
|
2161 |
|
|
-- Virtex6 PIPE Module
|
2162 |
|
|
---------------------------------------------------------
|
2163 |
|
|
|
2164 |
|
|
|
2165 |
|
|
|
2166 |
|
|
pcie_pipe_i : pcie_pipe_v6
|
2167 |
|
|
generic map (
|
2168 |
|
|
NO_OF_LANES => LINK_CAP_MAX_LINK_WIDTH_int,
|
2169 |
|
|
LINK_CAP_MAX_LINK_SPEED => LINK_CAP_MAX_LINK_SPEED,
|
2170 |
|
|
PIPE_PIPELINE_STAGES => PIPE_PIPELINE_STAGES
|
2171 |
|
|
)
|
2172 |
|
|
port map (
|
2173 |
|
|
|
2174 |
|
|
-- Pipe Per-Link Signals
|
2175 |
|
|
pipe_tx_rcvr_det_i => PIPETXRCVRDET,
|
2176 |
|
|
pipe_tx_reset_i => PIPETXRESET,
|
2177 |
|
|
pipe_tx_rate_i => PIPETXRATE,
|
2178 |
|
|
pipe_tx_deemph_i => PIPETXDEEMPH,
|
2179 |
|
|
pipe_tx_margin_i => PIPETXMARGIN,
|
2180 |
|
|
pipe_tx_swing_i => '0',
|
2181 |
|
|
|
2182 |
|
|
pipe_tx_rcvr_det_o => PIPETXRCVRDETGT,
|
2183 |
|
|
pipe_tx_reset_o => open,
|
2184 |
|
|
pipe_tx_rate_o => PIPETXRATEGT,
|
2185 |
|
|
pipe_tx_deemph_o => PIPETXDEEMPHGT,
|
2186 |
|
|
pipe_tx_margin_o => PIPETXMARGINGT,
|
2187 |
|
|
pipe_tx_swing_o => open,
|
2188 |
|
|
|
2189 |
|
|
-- Pipe Per-Lane Signals - Lane 0
|
2190 |
|
|
pipe_rx0_char_is_k_o => PIPERX0CHARISK,
|
2191 |
|
|
pipe_rx0_data_o => PIPERX0DATA,
|
2192 |
|
|
pipe_rx0_valid_o => PIPERX0VALID,
|
2193 |
|
|
pipe_rx0_chanisaligned_o => PIPERX0CHANISALIGNED,
|
2194 |
|
|
pipe_rx0_status_o => PIPERX0STATUS,
|
2195 |
|
|
pipe_rx0_phy_status_o => PIPERX0PHYSTATUS,
|
2196 |
|
|
pipe_rx0_elec_idle_i => PIPERX0ELECIDLEGT,
|
2197 |
|
|
pipe_rx0_polarity_i => PIPERX0POLARITY,
|
2198 |
|
|
pipe_tx0_compliance_i => PIPETX0COMPLIANCE,
|
2199 |
|
|
pipe_tx0_char_is_k_i => PIPETX0CHARISK,
|
2200 |
|
|
pipe_tx0_data_i => PIPETX0DATA,
|
2201 |
|
|
pipe_tx0_elec_idle_i => PIPETX0ELECIDLE,
|
2202 |
|
|
pipe_tx0_powerdown_i => PIPETX0POWERDOWN,
|
2203 |
|
|
|
2204 |
|
|
pipe_rx0_char_is_k_i => PIPERX0CHARISKGT,
|
2205 |
|
|
pipe_rx0_data_i => PIPERX0DATAGT,
|
2206 |
|
|
pipe_rx0_valid_i => PIPERX0VALIDGT,
|
2207 |
|
|
pipe_rx0_chanisaligned_i => PIPERX0CHANISALIGNEDGT,
|
2208 |
|
|
pipe_rx0_status_i => PIPERX0STATUSGT,
|
2209 |
|
|
pipe_rx0_phy_status_i => PIPERX0PHYSTATUSGT,
|
2210 |
|
|
pipe_rx0_elec_idle_o => PIPERX0ELECIDLE,
|
2211 |
|
|
pipe_rx0_polarity_o => PIPERX0POLARITYGT,
|
2212 |
|
|
pipe_tx0_compliance_o => PIPETX0COMPLIANCEGT,
|
2213 |
|
|
pipe_tx0_char_is_k_o => PIPETX0CHARISKGT,
|
2214 |
|
|
pipe_tx0_data_o => PIPETX0DATAGT,
|
2215 |
|
|
pipe_tx0_elec_idle_o => PIPETX0ELECIDLEGT,
|
2216 |
|
|
pipe_tx0_powerdown_o => PIPETX0POWERDOWNGT,
|
2217 |
|
|
|
2218 |
|
|
-- Pipe Per-Lane Signals - Lane 1
|
2219 |
|
|
pipe_rx1_char_is_k_o => PIPERX1CHARISK,
|
2220 |
|
|
pipe_rx1_data_o => PIPERX1DATA,
|
2221 |
|
|
pipe_rx1_valid_o => PIPERX1VALID,
|
2222 |
|
|
pipe_rx1_chanisaligned_o => PIPERX1CHANISALIGNED,
|
2223 |
|
|
pipe_rx1_status_o => PIPERX1STATUS,
|
2224 |
|
|
pipe_rx1_phy_status_o => PIPERX1PHYSTATUS,
|
2225 |
|
|
pipe_rx1_elec_idle_i => PIPERX1ELECIDLEGT,
|
2226 |
|
|
pipe_rx1_polarity_i => PIPERX1POLARITY,
|
2227 |
|
|
pipe_tx1_compliance_i => PIPETX1COMPLIANCE,
|
2228 |
|
|
pipe_tx1_char_is_k_i => PIPETX1CHARISK,
|
2229 |
|
|
pipe_tx1_data_i => PIPETX1DATA,
|
2230 |
|
|
pipe_tx1_elec_idle_i => PIPETX1ELECIDLE,
|
2231 |
|
|
pipe_tx1_powerdown_i => PIPETX1POWERDOWN,
|
2232 |
|
|
|
2233 |
|
|
pipe_rx1_char_is_k_i => PIPERX1CHARISKGT,
|
2234 |
|
|
pipe_rx1_data_i => PIPERX1DATAGT,
|
2235 |
|
|
pipe_rx1_valid_i => PIPERX1VALIDGT,
|
2236 |
|
|
pipe_rx1_chanisaligned_i => PIPERX1CHANISALIGNEDGT,
|
2237 |
|
|
pipe_rx1_status_i => PIPERX1STATUSGT,
|
2238 |
|
|
pipe_rx1_phy_status_i => PIPERX1PHYSTATUSGT,
|
2239 |
|
|
pipe_rx1_elec_idle_o => PIPERX1ELECIDLE,
|
2240 |
|
|
pipe_rx1_polarity_o => PIPERX1POLARITYGT,
|
2241 |
|
|
pipe_tx1_compliance_o => PIPETX1COMPLIANCEGT,
|
2242 |
|
|
pipe_tx1_char_is_k_o => PIPETX1CHARISKGT,
|
2243 |
|
|
pipe_tx1_data_o => PIPETX1DATAGT,
|
2244 |
|
|
pipe_tx1_elec_idle_o => PIPETX1ELECIDLEGT,
|
2245 |
|
|
pipe_tx1_powerdown_o => PIPETX1POWERDOWNGT,
|
2246 |
|
|
|
2247 |
|
|
-- Pipe Per-Lane Signals - Lane 2
|
2248 |
|
|
pipe_rx2_char_is_k_o => PIPERX2CHARISK,
|
2249 |
|
|
pipe_rx2_data_o => PIPERX2DATA,
|
2250 |
|
|
pipe_rx2_valid_o => PIPERX2VALID,
|
2251 |
|
|
pipe_rx2_chanisaligned_o => PIPERX2CHANISALIGNED,
|
2252 |
|
|
pipe_rx2_status_o => PIPERX2STATUS,
|
2253 |
|
|
pipe_rx2_phy_status_o => PIPERX2PHYSTATUS,
|
2254 |
|
|
pipe_rx2_elec_idle_i => PIPERX2ELECIDLEGT,
|
2255 |
|
|
pipe_rx2_polarity_i => PIPERX2POLARITY,
|
2256 |
|
|
pipe_tx2_compliance_i => PIPETX2COMPLIANCE,
|
2257 |
|
|
pipe_tx2_char_is_k_i => PIPETX2CHARISK,
|
2258 |
|
|
pipe_tx2_data_i => PIPETX2DATA,
|
2259 |
|
|
pipe_tx2_elec_idle_i => PIPETX2ELECIDLE,
|
2260 |
|
|
pipe_tx2_powerdown_i => PIPETX2POWERDOWN,
|
2261 |
|
|
|
2262 |
|
|
pipe_rx2_char_is_k_i => PIPERX2CHARISKGT,
|
2263 |
|
|
pipe_rx2_data_i => PIPERX2DATAGT,
|
2264 |
|
|
pipe_rx2_valid_i => PIPERX2VALIDGT,
|
2265 |
|
|
pipe_rx2_chanisaligned_i => PIPERX2CHANISALIGNEDGT,
|
2266 |
|
|
pipe_rx2_status_i => PIPERX2STATUSGT,
|
2267 |
|
|
pipe_rx2_phy_status_i => PIPERX2PHYSTATUSGT,
|
2268 |
|
|
pipe_rx2_elec_idle_o => PIPERX2ELECIDLE,
|
2269 |
|
|
pipe_rx2_polarity_o => PIPERX2POLARITYGT,
|
2270 |
|
|
pipe_tx2_compliance_o => PIPETX2COMPLIANCEGT,
|
2271 |
|
|
pipe_tx2_char_is_k_o => PIPETX2CHARISKGT,
|
2272 |
|
|
pipe_tx2_data_o => PIPETX2DATAGT,
|
2273 |
|
|
pipe_tx2_elec_idle_o => PIPETX2ELECIDLEGT,
|
2274 |
|
|
pipe_tx2_powerdown_o => PIPETX2POWERDOWNGT,
|
2275 |
|
|
|
2276 |
|
|
-- Pipe Per-Lane Signals - Lane 3
|
2277 |
|
|
pipe_rx3_char_is_k_o => PIPERX3CHARISK,
|
2278 |
|
|
pipe_rx3_data_o => PIPERX3DATA,
|
2279 |
|
|
pipe_rx3_valid_o => PIPERX3VALID,
|
2280 |
|
|
pipe_rx3_chanisaligned_o => PIPERX3CHANISALIGNED,
|
2281 |
|
|
pipe_rx3_status_o => PIPERX3STATUS,
|
2282 |
|
|
pipe_rx3_phy_status_o => PIPERX3PHYSTATUS,
|
2283 |
|
|
pipe_rx3_elec_idle_i => PIPERX3ELECIDLEGT,
|
2284 |
|
|
pipe_rx3_polarity_i => PIPERX3POLARITY,
|
2285 |
|
|
pipe_tx3_compliance_i => PIPETX3COMPLIANCE,
|
2286 |
|
|
pipe_tx3_char_is_k_i => PIPETX3CHARISK,
|
2287 |
|
|
pipe_tx3_data_i => PIPETX3DATA,
|
2288 |
|
|
pipe_tx3_elec_idle_i => PIPETX3ELECIDLE,
|
2289 |
|
|
pipe_tx3_powerdown_i => PIPETX3POWERDOWN,
|
2290 |
|
|
|
2291 |
|
|
pipe_rx3_char_is_k_i => PIPERX3CHARISKGT,
|
2292 |
|
|
pipe_rx3_data_i => PIPERX3DATAGT,
|
2293 |
|
|
pipe_rx3_valid_i => PIPERX3VALIDGT,
|
2294 |
|
|
pipe_rx3_chanisaligned_i => PIPERX3CHANISALIGNEDGT,
|
2295 |
|
|
pipe_rx3_status_i => PIPERX3STATUSGT,
|
2296 |
|
|
pipe_rx3_phy_status_i => PIPERX3PHYSTATUSGT,
|
2297 |
|
|
pipe_rx3_elec_idle_o => PIPERX3ELECIDLE,
|
2298 |
|
|
pipe_rx3_polarity_o => PIPERX3POLARITYGT,
|
2299 |
|
|
pipe_tx3_compliance_o => PIPETX3COMPLIANCEGT,
|
2300 |
|
|
pipe_tx3_char_is_k_o => PIPETX3CHARISKGT,
|
2301 |
|
|
pipe_tx3_data_o => PIPETX3DATAGT,
|
2302 |
|
|
pipe_tx3_elec_idle_o => PIPETX3ELECIDLEGT,
|
2303 |
|
|
pipe_tx3_powerdown_o => PIPETX3POWERDOWNGT,
|
2304 |
|
|
|
2305 |
|
|
-- Pipe Per-Lane Signals - Lane 4
|
2306 |
|
|
pipe_rx4_char_is_k_o => PIPERX4CHARISK,
|
2307 |
|
|
pipe_rx4_data_o => PIPERX4DATA,
|
2308 |
|
|
pipe_rx4_valid_o => PIPERX4VALID,
|
2309 |
|
|
pipe_rx4_chanisaligned_o => PIPERX4CHANISALIGNED,
|
2310 |
|
|
pipe_rx4_status_o => PIPERX4STATUS,
|
2311 |
|
|
pipe_rx4_phy_status_o => PIPERX4PHYSTATUS,
|
2312 |
|
|
pipe_rx4_elec_idle_i => PIPERX4ELECIDLEGT,
|
2313 |
|
|
pipe_rx4_polarity_i => PIPERX4POLARITY,
|
2314 |
|
|
pipe_tx4_compliance_i => PIPETX4COMPLIANCE,
|
2315 |
|
|
pipe_tx4_char_is_k_i => PIPETX4CHARISK,
|
2316 |
|
|
pipe_tx4_data_i => PIPETX4DATA,
|
2317 |
|
|
pipe_tx4_elec_idle_i => PIPETX4ELECIDLE,
|
2318 |
|
|
pipe_tx4_powerdown_i => PIPETX4POWERDOWN,
|
2319 |
|
|
|
2320 |
|
|
pipe_rx4_char_is_k_i => PIPERX4CHARISKGT,
|
2321 |
|
|
pipe_rx4_data_i => PIPERX4DATAGT,
|
2322 |
|
|
pipe_rx4_valid_i => PIPERX4VALIDGT,
|
2323 |
|
|
pipe_rx4_chanisaligned_i => PIPERX4CHANISALIGNEDGT,
|
2324 |
|
|
pipe_rx4_status_i => PIPERX4STATUSGT,
|
2325 |
|
|
pipe_rx4_phy_status_i => PIPERX4PHYSTATUSGT,
|
2326 |
|
|
pipe_rx4_elec_idle_o => PIPERX4ELECIDLE,
|
2327 |
|
|
pipe_rx4_polarity_o => PIPERX4POLARITYGT,
|
2328 |
|
|
pipe_tx4_compliance_o => PIPETX4COMPLIANCEGT,
|
2329 |
|
|
pipe_tx4_char_is_k_o => PIPETX4CHARISKGT,
|
2330 |
|
|
pipe_tx4_data_o => PIPETX4DATAGT,
|
2331 |
|
|
pipe_tx4_elec_idle_o => PIPETX4ELECIDLEGT,
|
2332 |
|
|
pipe_tx4_powerdown_o => PIPETX4POWERDOWNGT,
|
2333 |
|
|
|
2334 |
|
|
-- Pipe Per-Lane Signals - Lane 5
|
2335 |
|
|
pipe_rx5_char_is_k_o => PIPERX5CHARISK,
|
2336 |
|
|
pipe_rx5_data_o => PIPERX5DATA,
|
2337 |
|
|
pipe_rx5_valid_o => PIPERX5VALID,
|
2338 |
|
|
pipe_rx5_chanisaligned_o => PIPERX5CHANISALIGNED,
|
2339 |
|
|
pipe_rx5_status_o => PIPERX5STATUS,
|
2340 |
|
|
pipe_rx5_phy_status_o => PIPERX5PHYSTATUS,
|
2341 |
|
|
pipe_rx5_elec_idle_i => PIPERX5ELECIDLEGT,
|
2342 |
|
|
pipe_rx5_polarity_i => PIPERX5POLARITY,
|
2343 |
|
|
pipe_tx5_compliance_i => PIPETX5COMPLIANCE,
|
2344 |
|
|
pipe_tx5_char_is_k_i => PIPETX5CHARISK,
|
2345 |
|
|
pipe_tx5_data_i => PIPETX5DATA,
|
2346 |
|
|
pipe_tx5_elec_idle_i => PIPETX5ELECIDLE,
|
2347 |
|
|
pipe_tx5_powerdown_i => PIPETX5POWERDOWN,
|
2348 |
|
|
|
2349 |
|
|
pipe_rx5_char_is_k_i => PIPERX5CHARISKGT,
|
2350 |
|
|
pipe_rx5_data_i => PIPERX5DATAGT,
|
2351 |
|
|
pipe_rx5_valid_i => PIPERX5VALIDGT,
|
2352 |
|
|
pipe_rx5_chanisaligned_i => PIPERX5CHANISALIGNEDGT,
|
2353 |
|
|
pipe_rx5_status_i => PIPERX5STATUSGT,
|
2354 |
|
|
pipe_rx5_phy_status_i => PIPERX5PHYSTATUSGT,
|
2355 |
|
|
pipe_rx5_elec_idle_o => PIPERX5ELECIDLE,
|
2356 |
|
|
pipe_rx5_polarity_o => PIPERX5POLARITYGT,
|
2357 |
|
|
pipe_tx5_compliance_o => PIPETX5COMPLIANCEGT,
|
2358 |
|
|
pipe_tx5_char_is_k_o => PIPETX5CHARISKGT,
|
2359 |
|
|
pipe_tx5_data_o => PIPETX5DATAGT,
|
2360 |
|
|
pipe_tx5_elec_idle_o => PIPETX5ELECIDLEGT,
|
2361 |
|
|
pipe_tx5_powerdown_o => PIPETX5POWERDOWNGT,
|
2362 |
|
|
|
2363 |
|
|
-- Pipe Per-Lane Signals - Lane 6
|
2364 |
|
|
pipe_rx6_char_is_k_o => PIPERX6CHARISK,
|
2365 |
|
|
pipe_rx6_data_o => PIPERX6DATA,
|
2366 |
|
|
pipe_rx6_valid_o => PIPERX6VALID,
|
2367 |
|
|
pipe_rx6_chanisaligned_o => PIPERX6CHANISALIGNED,
|
2368 |
|
|
pipe_rx6_status_o => PIPERX6STATUS,
|
2369 |
|
|
pipe_rx6_phy_status_o => PIPERX6PHYSTATUS,
|
2370 |
|
|
pipe_rx6_elec_idle_i => PIPERX6ELECIDLEGT,
|
2371 |
|
|
pipe_rx6_polarity_i => PIPERX6POLARITY,
|
2372 |
|
|
pipe_tx6_compliance_i => PIPETX6COMPLIANCE,
|
2373 |
|
|
pipe_tx6_char_is_k_i => PIPETX6CHARISK,
|
2374 |
|
|
pipe_tx6_data_i => PIPETX6DATA,
|
2375 |
|
|
pipe_tx6_elec_idle_i => PIPETX6ELECIDLE,
|
2376 |
|
|
pipe_tx6_powerdown_i => PIPETX6POWERDOWN,
|
2377 |
|
|
|
2378 |
|
|
pipe_rx6_char_is_k_i => PIPERX6CHARISKGT,
|
2379 |
|
|
pipe_rx6_data_i => PIPERX6DATAGT,
|
2380 |
|
|
pipe_rx6_valid_i => PIPERX6VALIDGT,
|
2381 |
|
|
pipe_rx6_chanisaligned_i => PIPERX6CHANISALIGNEDGT,
|
2382 |
|
|
pipe_rx6_status_i => PIPERX6STATUSGT,
|
2383 |
|
|
pipe_rx6_phy_status_i => PIPERX6PHYSTATUSGT,
|
2384 |
|
|
pipe_rx6_elec_idle_o => PIPERX6ELECIDLE,
|
2385 |
|
|
pipe_rx6_polarity_o => PIPERX6POLARITYGT,
|
2386 |
|
|
pipe_tx6_compliance_o => PIPETX6COMPLIANCEGT,
|
2387 |
|
|
pipe_tx6_char_is_k_o => PIPETX6CHARISKGT,
|
2388 |
|
|
pipe_tx6_data_o => PIPETX6DATAGT,
|
2389 |
|
|
pipe_tx6_elec_idle_o => PIPETX6ELECIDLEGT,
|
2390 |
|
|
pipe_tx6_powerdown_o => PIPETX6POWERDOWNGT,
|
2391 |
|
|
|
2392 |
|
|
-- Pipe Per-Lane Signals - Lane 7
|
2393 |
|
|
pipe_rx7_char_is_k_o => PIPERX7CHARISK,
|
2394 |
|
|
pipe_rx7_data_o => PIPERX7DATA,
|
2395 |
|
|
pipe_rx7_valid_o => PIPERX7VALID,
|
2396 |
|
|
pipe_rx7_chanisaligned_o => PIPERX7CHANISALIGNED,
|
2397 |
|
|
pipe_rx7_status_o => PIPERX7STATUS,
|
2398 |
|
|
pipe_rx7_phy_status_o => PIPERX7PHYSTATUS,
|
2399 |
|
|
pipe_rx7_elec_idle_i => PIPERX7ELECIDLEGT,
|
2400 |
|
|
pipe_rx7_polarity_i => PIPERX7POLARITY,
|
2401 |
|
|
pipe_tx7_compliance_i => PIPETX7COMPLIANCE,
|
2402 |
|
|
pipe_tx7_char_is_k_i => PIPETX7CHARISK,
|
2403 |
|
|
pipe_tx7_data_i => PIPETX7DATA,
|
2404 |
|
|
pipe_tx7_elec_idle_i => PIPETX7ELECIDLE,
|
2405 |
|
|
pipe_tx7_powerdown_i => PIPETX7POWERDOWN,
|
2406 |
|
|
|
2407 |
|
|
pipe_rx7_char_is_k_i => PIPERX7CHARISKGT,
|
2408 |
|
|
pipe_rx7_data_i => PIPERX7DATAGT,
|
2409 |
|
|
pipe_rx7_valid_i => PIPERX7VALIDGT,
|
2410 |
|
|
pipe_rx7_chanisaligned_i => PIPERX7CHANISALIGNEDGT,
|
2411 |
|
|
pipe_rx7_status_i => PIPERX7STATUSGT,
|
2412 |
|
|
pipe_rx7_phy_status_i => PIPERX7PHYSTATUSGT,
|
2413 |
|
|
pipe_rx7_elec_idle_o => PIPERX7ELECIDLE,
|
2414 |
|
|
pipe_rx7_polarity_o => PIPERX7POLARITYGT,
|
2415 |
|
|
pipe_tx7_compliance_o => PIPETX7COMPLIANCEGT,
|
2416 |
|
|
pipe_tx7_char_is_k_o => PIPETX7CHARISKGT,
|
2417 |
|
|
pipe_tx7_data_o => PIPETX7DATAGT,
|
2418 |
|
|
pipe_tx7_elec_idle_o => PIPETX7ELECIDLEGT,
|
2419 |
|
|
pipe_tx7_powerdown_o => PIPETX7POWERDOWNGT,
|
2420 |
|
|
|
2421 |
|
|
-- Non PIPE signals
|
2422 |
|
|
pl_ltssm_state => PLLTSSMSTATE_v6pcie109,
|
2423 |
|
|
pipe_clk => PIPECLK,
|
2424 |
|
|
rst_n => PHYRDYN_v6pcie102
|
2425 |
|
|
);
|
2426 |
|
|
|
2427 |
|
|
---------------------------------------------------------
|
2428 |
|
|
-- Virtex6 GTX Module
|
2429 |
|
|
---------------------------------------------------------
|
2430 |
|
|
|
2431 |
|
|
|
2432 |
|
|
|
2433 |
|
|
pcie_gt_i : pcie_gtx_v6
|
2434 |
|
|
generic map (
|
2435 |
|
|
NO_OF_LANES => LINK_CAP_MAX_LINK_WIDTH_int,
|
2436 |
|
|
LINK_CAP_MAX_LINK_SPEED => LINK_CAP_MAX_LINK_SPEED,
|
2437 |
|
|
REF_CLK_FREQ => REF_CLK_FREQ,
|
2438 |
|
|
PL_FAST_TRAIN => PL_FAST_TRAIN
|
2439 |
|
|
)
|
2440 |
|
|
port map (
|
2441 |
|
|
|
2442 |
|
|
-- Pipe Common Signals
|
2443 |
|
|
pipe_tx_rcvr_det => PIPETXRCVRDETGT,
|
2444 |
|
|
pipe_tx_reset => '0',
|
2445 |
|
|
pipe_tx_rate => PIPETXRATEGT,
|
2446 |
|
|
pipe_tx_deemph => PIPETXDEEMPHGT,
|
2447 |
|
|
pipe_tx_margin => PIPETXMARGINGT,
|
2448 |
|
|
pipe_tx_swing => '0',
|
2449 |
|
|
|
2450 |
|
|
-- Pipe Per-Lane Signals - Lane 0
|
2451 |
|
|
pipe_rx0_char_is_k => PIPERX0CHARISKGT,
|
2452 |
|
|
pipe_rx0_data => PIPERX0DATAGT,
|
2453 |
|
|
pipe_rx0_valid => PIPERX0VALIDGT,
|
2454 |
|
|
pipe_rx0_chanisaligned => PIPERX0CHANISALIGNEDGT,
|
2455 |
|
|
pipe_rx0_status => PIPERX0STATUSGT,
|
2456 |
|
|
pipe_rx0_phy_status => PIPERX0PHYSTATUSGT,
|
2457 |
|
|
pipe_rx0_elec_idle => PIPERX0ELECIDLEGT,
|
2458 |
|
|
pipe_rx0_polarity => PIPERX0POLARITYGT,
|
2459 |
|
|
pipe_tx0_compliance => PIPETX0COMPLIANCEGT,
|
2460 |
|
|
pipe_tx0_char_is_k => PIPETX0CHARISKGT,
|
2461 |
|
|
pipe_tx0_data => PIPETX0DATAGT,
|
2462 |
|
|
pipe_tx0_elec_idle => PIPETX0ELECIDLEGT,
|
2463 |
|
|
pipe_tx0_powerdown => PIPETX0POWERDOWNGT,
|
2464 |
|
|
|
2465 |
|
|
-- Pipe Per-Lane Signals - Lane 1
|
2466 |
|
|
pipe_rx1_char_is_k => PIPERX1CHARISKGT,
|
2467 |
|
|
pipe_rx1_data => PIPERX1DATAGT,
|
2468 |
|
|
pipe_rx1_valid => PIPERX1VALIDGT,
|
2469 |
|
|
pipe_rx1_chanisaligned => PIPERX1CHANISALIGNEDGT,
|
2470 |
|
|
pipe_rx1_status => PIPERX1STATUSGT,
|
2471 |
|
|
pipe_rx1_phy_status => PIPERX1PHYSTATUSGT,
|
2472 |
|
|
pipe_rx1_elec_idle => PIPERX1ELECIDLEGT,
|
2473 |
|
|
pipe_rx1_polarity => PIPERX1POLARITYGT,
|
2474 |
|
|
pipe_tx1_compliance => PIPETX1COMPLIANCEGT,
|
2475 |
|
|
pipe_tx1_char_is_k => PIPETX1CHARISKGT,
|
2476 |
|
|
pipe_tx1_data => PIPETX1DATAGT,
|
2477 |
|
|
pipe_tx1_elec_idle => PIPETX1ELECIDLEGT,
|
2478 |
|
|
pipe_tx1_powerdown => PIPETX1POWERDOWNGT,
|
2479 |
|
|
|
2480 |
|
|
-- Pipe Per-Lane Signals - Lane 2
|
2481 |
|
|
pipe_rx2_char_is_k => PIPERX2CHARISKGT,
|
2482 |
|
|
pipe_rx2_data => PIPERX2DATAGT,
|
2483 |
|
|
pipe_rx2_valid => PIPERX2VALIDGT,
|
2484 |
|
|
pipe_rx2_chanisaligned => PIPERX2CHANISALIGNEDGT,
|
2485 |
|
|
pipe_rx2_status => PIPERX2STATUSGT,
|
2486 |
|
|
pipe_rx2_phy_status => PIPERX2PHYSTATUSGT,
|
2487 |
|
|
pipe_rx2_elec_idle => PIPERX2ELECIDLEGT,
|
2488 |
|
|
pipe_rx2_polarity => PIPERX2POLARITYGT,
|
2489 |
|
|
pipe_tx2_compliance => PIPETX2COMPLIANCEGT,
|
2490 |
|
|
pipe_tx2_char_is_k => PIPETX2CHARISKGT,
|
2491 |
|
|
pipe_tx2_data => PIPETX2DATAGT,
|
2492 |
|
|
pipe_tx2_elec_idle => PIPETX2ELECIDLEGT,
|
2493 |
|
|
pipe_tx2_powerdown => PIPETX2POWERDOWNGT,
|
2494 |
|
|
|
2495 |
|
|
-- Pipe Per-Lane Signals - Lane 3
|
2496 |
|
|
pipe_rx3_char_is_k => PIPERX3CHARISKGT,
|
2497 |
|
|
pipe_rx3_data => PIPERX3DATAGT,
|
2498 |
|
|
pipe_rx3_valid => PIPERX3VALIDGT,
|
2499 |
|
|
pipe_rx3_chanisaligned => PIPERX3CHANISALIGNEDGT,
|
2500 |
|
|
pipe_rx3_status => PIPERX3STATUSGT,
|
2501 |
|
|
pipe_rx3_phy_status => PIPERX3PHYSTATUSGT,
|
2502 |
|
|
pipe_rx3_elec_idle => PIPERX3ELECIDLEGT,
|
2503 |
|
|
pipe_rx3_polarity => PIPERX3POLARITYGT,
|
2504 |
|
|
pipe_tx3_compliance => PIPETX3COMPLIANCEGT,
|
2505 |
|
|
pipe_tx3_char_is_k => PIPETX3CHARISKGT,
|
2506 |
|
|
pipe_tx3_data => PIPETX3DATAGT,
|
2507 |
|
|
pipe_tx3_elec_idle => PIPETX3ELECIDLEGT,
|
2508 |
|
|
pipe_tx3_powerdown => PIPETX3POWERDOWNGT,
|
2509 |
|
|
|
2510 |
|
|
-- Pipe Per-Lane Signals - Lane 4
|
2511 |
|
|
pipe_rx4_char_is_k => PIPERX4CHARISKGT,
|
2512 |
|
|
pipe_rx4_data => PIPERX4DATAGT,
|
2513 |
|
|
pipe_rx4_valid => PIPERX4VALIDGT,
|
2514 |
|
|
pipe_rx4_chanisaligned => PIPERX4CHANISALIGNEDGT,
|
2515 |
|
|
pipe_rx4_status => PIPERX4STATUSGT,
|
2516 |
|
|
pipe_rx4_phy_status => PIPERX4PHYSTATUSGT,
|
2517 |
|
|
pipe_rx4_elec_idle => PIPERX4ELECIDLEGT,
|
2518 |
|
|
pipe_rx4_polarity => PIPERX4POLARITYGT,
|
2519 |
|
|
pipe_tx4_compliance => PIPETX4COMPLIANCEGT,
|
2520 |
|
|
pipe_tx4_char_is_k => PIPETX4CHARISKGT,
|
2521 |
|
|
pipe_tx4_data => PIPETX4DATAGT,
|
2522 |
|
|
pipe_tx4_elec_idle => PIPETX4ELECIDLEGT,
|
2523 |
|
|
pipe_tx4_powerdown => PIPETX4POWERDOWNGT,
|
2524 |
|
|
|
2525 |
|
|
-- Pipe Per-Lane Signals - Lane 5
|
2526 |
|
|
pipe_rx5_char_is_k => PIPERX5CHARISKGT,
|
2527 |
|
|
pipe_rx5_data => PIPERX5DATAGT,
|
2528 |
|
|
pipe_rx5_valid => PIPERX5VALIDGT,
|
2529 |
|
|
pipe_rx5_chanisaligned => PIPERX5CHANISALIGNEDGT,
|
2530 |
|
|
pipe_rx5_status => PIPERX5STATUSGT,
|
2531 |
|
|
pipe_rx5_phy_status => PIPERX5PHYSTATUSGT,
|
2532 |
|
|
pipe_rx5_elec_idle => PIPERX5ELECIDLEGT,
|
2533 |
|
|
pipe_rx5_polarity => PIPERX5POLARITYGT,
|
2534 |
|
|
pipe_tx5_compliance => PIPETX5COMPLIANCEGT,
|
2535 |
|
|
pipe_tx5_char_is_k => PIPETX5CHARISKGT,
|
2536 |
|
|
pipe_tx5_data => PIPETX5DATAGT,
|
2537 |
|
|
pipe_tx5_elec_idle => PIPETX5ELECIDLEGT,
|
2538 |
|
|
pipe_tx5_powerdown => PIPETX5POWERDOWNGT,
|
2539 |
|
|
|
2540 |
|
|
-- Pipe Per-Lane Signals - Lane 6
|
2541 |
|
|
pipe_rx6_char_is_k => PIPERX6CHARISKGT,
|
2542 |
|
|
pipe_rx6_data => PIPERX6DATAGT,
|
2543 |
|
|
pipe_rx6_valid => PIPERX6VALIDGT,
|
2544 |
|
|
pipe_rx6_chanisaligned => PIPERX6CHANISALIGNEDGT,
|
2545 |
|
|
pipe_rx6_status => PIPERX6STATUSGT,
|
2546 |
|
|
pipe_rx6_phy_status => PIPERX6PHYSTATUSGT,
|
2547 |
|
|
pipe_rx6_elec_idle => PIPERX6ELECIDLEGT,
|
2548 |
|
|
pipe_rx6_polarity => PIPERX6POLARITYGT,
|
2549 |
|
|
pipe_tx6_compliance => PIPETX6COMPLIANCEGT,
|
2550 |
|
|
pipe_tx6_char_is_k => PIPETX6CHARISKGT,
|
2551 |
|
|
pipe_tx6_data => PIPETX6DATAGT,
|
2552 |
|
|
pipe_tx6_elec_idle => PIPETX6ELECIDLEGT,
|
2553 |
|
|
pipe_tx6_powerdown => PIPETX6POWERDOWNGT,
|
2554 |
|
|
|
2555 |
|
|
-- Pipe Per-Lane Signals - Lane 7
|
2556 |
|
|
pipe_rx7_char_is_k => PIPERX7CHARISKGT,
|
2557 |
|
|
pipe_rx7_data => PIPERX7DATAGT,
|
2558 |
|
|
pipe_rx7_valid => PIPERX7VALIDGT,
|
2559 |
|
|
pipe_rx7_chanisaligned => PIPERX7CHANISALIGNEDGT,
|
2560 |
|
|
pipe_rx7_status => PIPERX7STATUSGT,
|
2561 |
|
|
pipe_rx7_phy_status => PIPERX7PHYSTATUSGT,
|
2562 |
|
|
pipe_rx7_elec_idle => PIPERX7ELECIDLEGT,
|
2563 |
|
|
pipe_rx7_polarity => PIPERX7POLARITYGT,
|
2564 |
|
|
pipe_tx7_compliance => PIPETX7COMPLIANCEGT,
|
2565 |
|
|
pipe_tx7_char_is_k => PIPETX7CHARISKGT,
|
2566 |
|
|
pipe_tx7_data => PIPETX7DATAGT,
|
2567 |
|
|
pipe_tx7_elec_idle => PIPETX7ELECIDLEGT,
|
2568 |
|
|
pipe_tx7_powerdown => PIPETX7POWERDOWNGT,
|
2569 |
|
|
|
2570 |
|
|
-- PCI Express Signals
|
2571 |
|
|
pci_exp_txn => PCIEXPTXN_v6pcie100,
|
2572 |
|
|
pci_exp_txp => PCIEXPTXP_v6pcie101,
|
2573 |
|
|
pci_exp_rxn => PCIEXPRXN,
|
2574 |
|
|
pci_exp_rxp => PCIEXPRXP,
|
2575 |
|
|
|
2576 |
|
|
-- Non PIPE Signals
|
2577 |
|
|
sys_clk => SYSCLK,
|
2578 |
|
|
sys_rst_n => FUNDRSTN,
|
2579 |
|
|
pipe_clk => PIPECLK,
|
2580 |
|
|
drp_clk => DRPCLK,
|
2581 |
|
|
clock_locked => CLOCKLOCKED,
|
2582 |
|
|
pl_ltssm_state => PLLTSSMSTATE_v6pcie109,
|
2583 |
|
|
|
2584 |
|
|
gt_pll_lock => GTPLLLOCK_v6pcie96,
|
2585 |
|
|
phy_rdy_n => PHYRDYN_v6pcie102,
|
2586 |
|
|
txoutclk => TxOutClk_v6pcie138
|
2587 |
|
|
);
|
2588 |
|
|
|
2589 |
|
|
---------------------------------------------------------
|
2590 |
|
|
-- PCI Express BRAM Module
|
2591 |
|
|
---------------------------------------------------------
|
2592 |
|
|
|
2593 |
|
|
|
2594 |
|
|
|
2595 |
|
|
MIMTXWDATA_tmp <= "000" & MIMTXWDATA;
|
2596 |
|
|
MIMRXWDATA_tmp <= "0000" & MIMRXWDATA;
|
2597 |
|
|
|
2598 |
|
|
pcie_bram_i : pcie_bram_top_v6
|
2599 |
|
|
generic map (
|
2600 |
|
|
DEV_CAP_MAX_PAYLOAD_SUPPORTED => DEV_CAP_MAX_PAYLOAD_SUPPORTED,
|
2601 |
|
|
VC0_TX_LASTPACKET => VC0_TX_LASTPACKET,
|
2602 |
|
|
TL_TX_RAM_RADDR_LATENCY => TL_TX_RAM_RADDR_LATENCY,
|
2603 |
|
|
TL_TX_RAM_RDATA_LATENCY => TL_TX_RAM_RDATA_LATENCY,
|
2604 |
|
|
TL_TX_RAM_WRITE_LATENCY => TL_TX_RAM_WRITE_LATENCY,
|
2605 |
|
|
VC0_RX_LIMIT => VC0_RX_RAM_LIMIT,
|
2606 |
|
|
TL_RX_RAM_RADDR_LATENCY => TL_RX_RAM_RADDR_LATENCY,
|
2607 |
|
|
TL_RX_RAM_RDATA_LATENCY => TL_RX_RAM_RDATA_LATENCY,
|
2608 |
|
|
TL_RX_RAM_WRITE_LATENCY => TL_RX_RAM_WRITE_LATENCY
|
2609 |
|
|
)
|
2610 |
|
|
port map (
|
2611 |
|
|
|
2612 |
|
|
-- elseEN_128B_INT
|
2613 |
|
|
user_clk_i => USERCLK,
|
2614 |
|
|
reset_i => PHYRDYN_v6pcie102,
|
2615 |
|
|
-- endifEN_128B_INT
|
2616 |
|
|
|
2617 |
|
|
mim_tx_waddr => MIMTXWADDR,
|
2618 |
|
|
mim_tx_wen => MIMTXWEN,
|
2619 |
|
|
mim_tx_ren => MIMTXREN,
|
2620 |
|
|
mim_tx_rce => MIMTXRCE,
|
2621 |
|
|
mim_tx_wdata => MIMTXWDATA_tmp,
|
2622 |
|
|
mim_tx_raddr => MIMTXRADDR,
|
2623 |
|
|
mim_tx_rdata => MIMTXRDATA,
|
2624 |
|
|
|
2625 |
|
|
mim_rx_waddr => MIMRXWADDR,
|
2626 |
|
|
mim_rx_wen => MIMRXWEN,
|
2627 |
|
|
mim_rx_ren => MIMRXREN,
|
2628 |
|
|
mim_rx_rce => MIMRXRCE,
|
2629 |
|
|
mim_rx_wdata => MIMRXWDATA_tmp,
|
2630 |
|
|
mim_rx_raddr => MIMRXRADDR,
|
2631 |
|
|
mim_rx_rdata => MIMRXRDATA
|
2632 |
|
|
);
|
2633 |
|
|
|
2634 |
|
|
---------------------------------------------------------
|
2635 |
|
|
-- PCI Express Port Workarounds
|
2636 |
|
|
---------------------------------------------------------
|
2637 |
|
|
|
2638 |
|
|
|
2639 |
|
|
|
2640 |
|
|
pcie_upconfig_fix_3451_v6_i : pcie_upconfig_fix_3451_v6
|
2641 |
|
|
generic map (
|
2642 |
|
|
UPSTREAM_FACING => UPSTREAM_FACING,
|
2643 |
|
|
PL_FAST_TRAIN => PL_FAST_TRAIN,
|
2644 |
|
|
LINK_CAP_MAX_LINK_WIDTH => LINK_CAP_MAX_LINK_WIDTH
|
2645 |
|
|
)
|
2646 |
|
|
port map (
|
2647 |
|
|
|
2648 |
|
|
pipe_clk => PIPECLK,
|
2649 |
|
|
pl_phy_lnkup_n => PLPHYLNKUPN_v6pcie110,
|
2650 |
|
|
|
2651 |
|
|
pl_ltssm_state => PLLTSSMSTATE_v6pcie109,
|
2652 |
|
|
pl_sel_lnk_rate => PLSELLNKRATE_v6pcie113,
|
2653 |
|
|
pl_directed_link_change => PLDIRECTEDLINKCHANGE,
|
2654 |
|
|
|
2655 |
|
|
cfg_link_status_negotiated_width => CFGLINKSTATUSNEGOTIATEDWIDTH_v6pcie48,
|
2656 |
|
|
pipe_rx0_data => PIPERX0DATAGT(15 downto 0),
|
2657 |
|
|
pipe_rx0_char_isk => PIPERX0CHARISKGT(1 downto 0),
|
2658 |
|
|
|
2659 |
|
|
filter_pipe => filter_pipe_upconfig_fix_3451
|
2660 |
|
|
);
|
2661 |
|
|
|
2662 |
|
|
end v6_pcie;
|
2663 |
|
|
|
2664 |
|
|
|
2665 |
|
|
|