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[/] [pcie_ds_dma/] [trunk/] [core/] [ds_dma64/] [pcie_src/] [pcie_sim/] [dsport/] [test_interface.vhd] - Blame information for rev 2

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-------------------------------------------------------------------------------
2 
--
3 
-- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
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--
5 
-- This file contains confidential and proprietary information
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-- of Xilinx, Inc. and is protected under U.S. and
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-- international copyright and other intellectual property
8 
-- laws.
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--
10 
-- DISCLAIMER
11 
-- This disclaimer is not a license and does not grant any
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-- rights to the materials distributed herewith. Except as
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-- otherwise provided in a valid license issued to you by
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-- Xilinx, and to the maximum extent permitted by applicable
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-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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-- (2) Xilinx shall not be liable (whether in contract or tort,
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-- including negligence, or under any other theory of
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-- liability) for any loss or damage of any kind or nature
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-- related to, arising under or in connection with these
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-- materials, including for any direct, or any indirect,
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-- special, incidental, or consequential loss or damage
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-- (including loss of data, profits, goodwill, or any type of
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-- loss or damage suffered as a result of any action brought
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-- by a third party) even if such damage or loss was
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-- reasonably foreseeable or Xilinx had been advised of the
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-- possibility of the same.
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--
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-- CRITICAL APPLICATIONS
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-- Xilinx products are not designed or intended to be fail-
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-- safe, or for use in any application requiring fail-safe
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-- performance, such as life-support or safety devices or
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-- systems, Class III medical devices, nuclear facilities,
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-- applications related to the deployment of airbags, or any
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-- other applications that could lead to death, personal
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-- injury, or severe property or environmental damage
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-- (individually and collectively, "Critical
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-- Applications"). Customer assumes the sole risk and
42 
-- liability of any use of Xilinx products in Critical
43 
-- Applications, subject only to applicable laws and
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-- regulations governing limitations on product liability.
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--
46 
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
47 
-- PART OF THIS FILE AT ALL TIMES.
48 
--
49 
-------------------------------------------------------------------------------
50 
-- Project    : Virtex-6 Integrated Block for PCI Express
51 
-- File       : test_interface.vhd
52 
-- Version    : 2.3
53 
---- Description:  Procedures invoked by the test program file.
54 
----
55 
----
56 
--------------------------------------------------------------------------------
57 
 
58 
library ieee;
59 
use ieee.std_logic_1164.all;
60 
use ieee.std_logic_textio.all;
61 
use ieee.numeric_std.all;
62 
 
63 
library std;
64 
use std.textio.all;
65 
 
66 
-- Package Declaration
67 
 
68 
package test_interface is
69 
 
70 
type BYTE_ARRAY             is array (999 downto 0) of std_logic_vector(7 downto 0);
71 
type DATA_ARRAY             is array (499 downto 0) of std_logic_vector(7 downto 0);
72 
type THIRTY_THREE_BIT_ARRAY is array (6 downto 0) of std_logic_vector((33 - 1) downto 0);
73 
type DWORD_ARRAY            is array (6 downto 0) of std_logic_vector((32 - 1) downto 0);
74 
type ENABLE_ARRAY           is array (6 downto 0) of INTEGER;
75 
 
76 
constant PCI_EXP_MEM_READ32            : std_logic_vector(6 downto 0) := "0000000";
77 
constant PCI_EXP_IO_READ               : std_logic_vector(6 downto 0) := "0000010";
78 
constant PCI_EXP_CFG_READ0             : std_logic_vector(6 downto 0) := "0000100";
79 
constant PCI_EXP_COMPLETION_WO_DATA    : std_logic_vector(6 downto 0) := "0001010";
80 
constant PCI_EXP_MEM_READ64            : std_logic_vector(6 downto 0) := "0100000";
81 
constant PCI_EXP_MSG_NODATA            : std_logic_vector(6 downto 3) := "0110";
82 
constant PCI_EXP_MEM_WRITE32           : std_logic_vector(6 downto 0) := "1000000";
83 
constant PCI_EXP_IO_WRITE              : std_logic_vector(6 downto 0) := "1000010";
84 
constant PCI_EXP_CFG_WRITE0            : std_logic_vector(6 downto 0) := "1000100";
85 
constant PCI_EXP_COMPLETION_DATA       : std_logic_vector(6 downto 0) := "1001010";
86 
constant PCI_EXP_MEM_WRITE64           : std_logic_vector(6 downto 0) := "1100000";
87 
constant PCI_EXP_MSG_DATA              : std_logic_vector(6 downto 3) := "1110";
88 
 
89 
constant COMPLETER_ID_CFG              : std_logic_vector(15 downto 0) := X"01A0";
90 
 
91 
constant DEV_ID                        : std_logic_vector(15 downto 0) := X"6011";
92 
constant VEN_ID                        : std_logic_vector(15 downto 0) := X"10EE";
93 
constant DEV_VEN_ID                    : std_logic_vector(31 downto 0) := (DEV_ID & VEN_ID);
94 
constant MAX_LINK_SPEED                : integer := 1;
95 
 
96 
signal trn_trem_n_c    : std_logic_vector ((8  - 1) downto 0 );
97 
signal trn_td_c        : std_logic_vector ((64 - 1) downto 0 );
98 
 
99 
shared variable frame_store_tx          : BYTE_ARRAY;
100 
shared variable frame_store_tx_idx      : INTEGER;
101 
shared variable DATA_STORE              : DATA_ARRAY;
102 
shared variable P_READ_DATA             : std_logic_vector(31 downto 0);
103 
shared variable Lglobal                 : line;
104 
shared variable BAR_RANGE               : DWORD_ARRAY;
105 
shared variable BAR                     : THIRTY_THREE_BIT_ARRAY;
106 
shared variable NUMBER_OF_IO_BARS       : INTEGER;
107 
shared variable NUMBER_OF_MEM64_BARS    : INTEGER;
108 
shared variable NUMBER_OF_MEM32_BARS    : INTEGER;
109 
shared variable BAR_ENABLED             : ENABLE_ARRAY;
110 
shared variable pio_check_design : boolean;
111 
shared variable i                       : INTEGER;
112 
shared variable success                 : boolean;
113 
 
114 
-- Cfg Rd/Wr interface signals
115 
type cfg_rdwr_sigs is record
116 
  trn_clk          : std_logic;
117 
  trn_reset_n      : std_logic;
118 
  cfg_rd_wr_done_n : std_logic;
119 
  cfg_dwaddr       : std_logic_vector(9 downto 0);
120 
  cfg_di           : std_logic_vector(31 downto 0);
121 
  cfg_do           : std_logic_vector(31 downto 0);
122 
  cfg_byte_en_n    : std_logic_vector(3 downto 0);
123 
  cfg_wr_en_n      : std_logic;
124 
  cfg_rd_en_n      : std_logic;
125 
end record;
126 
signal cfg_rdwr_int : cfg_rdwr_sigs := (trn_clk => 'Z', trn_reset_n => 'Z', cfg_rd_wr_done_n => '1', cfg_dwaddr => (OTHERS => '0'), cfg_di => x"00000000", cfg_do => x"00000000", cfg_byte_en_n => "1111", cfg_wr_en_n => '1', cfg_rd_en_n => '1');
127 
 
128 
 
129 
file tx_file : TEXT open write_mode is "tx.dat";
130 
 
131 
procedure writeNowToTx (  text_string     : in string);
132 
 
133 
procedure writeHexToTx (  text_string     : in string;
134 
                                               hexValue        : in std_logic_vector);
135 
 
136 
procedure writeNowToScreen (text_string     : in string);
137 
 
138 
 
139 
procedure FINISH;
140 
 
141 
procedure FINISH_FAILURE;
142 
 
143 
procedure PROC_TX_SYNCHRONIZE (
144 
 
145 
  first : in INTEGER;
146 
  last_call: in INTEGER;
147 
  signal trn_lnk_up_n : in std_logic;
148 
  signal trn_tdst_rdy_n : in std_logic;
149 
  signal trn_clk : in std_logic
150 
 
151 
);
152 
 
153 
procedure PROC_TX_TYPE0_CONFIGURATION_READ (
154 
 
155 
  tag                      : in std_logic_vector (7 downto 0);
156 
  reg_addr                 : in std_logic_vector (11 downto 0);
157 
  first_dw_be              : in std_logic_vector (3 downto 0);
158 
  signal trn_td_c          : out std_logic_vector(63 downto 0);
159 
  signal trn_tsof_n        : out std_logic;
160 
  signal trn_teof_n        : out std_logic;
161 
  signal trn_trem_n_c      : out std_logic_vector(7 downto 0);
162 
  signal trn_tsrc_rdy_n    : out std_logic;
163 
  signal trn_lnk_up_n : in std_logic;
164 
  signal trn_tdst_rdy_n : in std_logic;
165 
  signal trn_clk : in std_logic
166 
 
167 
);
168 
 
169 
 
170 
procedure PROC_TX_TYPE0_CONFIGURATION_WRITE (
171 
 
172 
  tag                      : in std_logic_vector (7 downto 0);
173 
  reg_addr                 : in std_logic_vector (11 downto 0);
174 
  reg_data                 : in std_logic_vector (31 downto 0);
175 
  first_dw_be              : in std_logic_vector (3 downto 0);
176 
  signal trn_td_c          : out std_logic_vector(63 downto 0);
177 
  signal trn_tsof_n        : out std_logic;
178 
  signal trn_teof_n        : out std_logic;
179 
  signal trn_trem_n_c      : out std_logic_vector(7 downto 0);
180 
  signal trn_tsrc_rdy_n    : out std_logic;
181 
  signal trn_lnk_up_n : in std_logic;
182 
  signal trn_tdst_rdy_n : in std_logic;
183 
  signal trn_clk : in std_logic
184 
 
185 
);
186 
 
187 
procedure PROC_TX_TYPE1_CONFIGURATION_READ (
188 
 
189 
  tag                      : in std_logic_vector (7 downto 0);
190 
  reg_addr                 : in std_logic_vector (11 downto 0);
191 
  first_dw_be              : in std_logic_vector (3 downto 0);
192 
  signal trn_td_c          : out std_logic_vector(63 downto 0);
193 
  signal trn_tsof_n        : out std_logic;
194 
  signal trn_teof_n        : out std_logic;
195 
  signal trn_trem_n_c      : out std_logic_vector(7 downto 0);
196 
  signal trn_tsrc_rdy_n    : out std_logic;
197 
  signal trn_lnk_up_n : in std_logic;
198 
  signal trn_tdst_rdy_n : in std_logic;
199 
  signal trn_clk : in std_logic
200 
 
201 
);
202 
 
203 
procedure PROC_TX_TYPE1_CONFIGURATION_WRITE (
204 
 
205 
  tag                      : in std_logic_vector (7 downto 0);
206 
  reg_addr                 : in std_logic_vector (11 downto 0);
207 
  reg_data                 : in std_logic_vector (31 downto 0);
208 
  first_dw_be              : in std_logic_vector (3 downto 0);
209 
  signal trn_td_c          : out std_logic_vector(63 downto 0);
210 
  signal trn_tsof_n        : out std_logic;
211 
  signal trn_teof_n        : out std_logic;
212 
  signal trn_trem_n_c      : out std_logic_vector(7 downto 0);
213 
  signal trn_tsrc_rdy_n    : out std_logic;
214 
  signal trn_lnk_up_n : in std_logic;
215 
  signal trn_tdst_rdy_n : in std_logic;
216 
  signal trn_clk : in std_logic
217 
 
218 
);
219 
 
220 
procedure PROC_TX_MEMORY_READ_32 (
221 
 
222 
  tag                      : in std_logic_vector (7 downto 0);
223 
  tc                       : in std_logic_vector (2 downto 0);
224 
  len                      : in std_logic_vector (9 downto 0);
225 
  addr                     : in std_logic_vector (31 downto 0);
226 
  last_dw_be               : in std_logic_vector (3 downto 0);
227 
  first_dw_be              : in std_logic_vector (3 downto 0);
228 
  signal trn_td_c          : out std_logic_vector(63 downto 0);
229 
  signal trn_tsof_n        : out std_logic;
230 
  signal trn_teof_n        : out std_logic;
231 
  signal trn_trem_n_c      : out std_logic_vector(7 downto 0);
232 
  signal trn_tsrc_rdy_n    : out std_logic;
233 
  signal trn_lnk_up_n : in std_logic;
234 
  signal trn_tdst_rdy_n : in std_logic;
235 
  signal trn_clk : in std_logic
236 
 
237 
 
238 
);
239 
 
240 
procedure PROC_TX_MEMORY_READ_64 (
241 
 
242 
  tag                      : in std_logic_vector (7 downto 0);
243 
  tc                       : in std_logic_vector (2 downto 0);
244 
  len                      : in std_logic_vector (9 downto 0);
245 
  addr                     : in std_logic_vector (63 downto 0);
246 
  last_dw_be               : in std_logic_vector (3 downto 0);
247 
  first_dw_be              : in std_logic_vector (3 downto 0);
248 
  signal trn_td_c          : out std_logic_vector(63 downto 0);
249 
  signal trn_tsof_n        : out std_logic;
250 
  signal trn_teof_n        : out std_logic;
251 
  signal trn_trem_n_c      : out std_logic_vector(7 downto 0);
252 
  signal trn_tsrc_rdy_n    : out std_logic;
253 
  signal trn_lnk_up_n : in std_logic;
254 
  signal trn_tdst_rdy_n : in std_logic;
255 
  signal trn_clk : in std_logic
256 
 
257 
 
258 
);
259 
 
260 
procedure PROC_TX_MEMORY_WRITE_32 (
261 
 
262 
  tag                         : in std_logic_vector (7 downto 0);
263 
  tc                          : in std_logic_vector (2 downto 0);
264 
  len                         : in std_logic_vector (9 downto 0);
265 
  addr                        : in std_logic_vector (31 downto 0);
266 
  last_dw_be                  : in std_logic_vector (3 downto 0);
267 
  first_dw_be                 : in std_logic_vector (3 downto 0);
268 
  ep                          : in std_logic;
269 
  signal trn_td_c             : out std_logic_vector(63 downto 0);
270 
  signal trn_tsof_n           : out std_logic;
271 
  signal trn_teof_n           : out std_logic;
272 
  signal trn_trem_n_c         : out std_logic_vector(7 downto 0);
273 
  signal trn_tsrc_rdy_n       : out std_logic;
274 
  signal trn_terrfwd_n        : out std_logic;
275 
  signal trn_lnk_up_n : in std_logic;
276 
  signal trn_tdst_rdy_n : in std_logic;
277 
  signal trn_clk : in std_logic
278 
 
279 
 
280 
);
281 
 
282 
 
283 
procedure PROC_TX_MEMORY_WRITE_64 (
284 
 
285 
  tag                         : in std_logic_vector (7 downto 0);
286 
  tc                          : in std_logic_vector (2 downto 0);
287 
  len                         : in std_logic_vector (9 downto 0);
288 
  addr                        : in std_logic_vector (63 downto 0);
289 
  last_dw_be                  : in std_logic_vector (3 downto 0);
290 
  first_dw_be                 : in std_logic_vector (3 downto 0);
291 
  ep                          : in std_logic;
292 
  signal trn_td_c             : out std_logic_vector(63 downto 0);
293 
  signal trn_tsof_n           : out std_logic;
294 
  signal trn_teof_n           : out std_logic;
295 
  signal trn_trem_n_c         : out std_logic_vector(7 downto 0);
296 
  signal trn_tsrc_rdy_n       : out std_logic;
297 
  signal trn_terrfwd_n        : out std_logic;
298 
  signal trn_lnk_up_n : in std_logic;
299 
  signal trn_tdst_rdy_n : in std_logic;
300 
  signal trn_clk : in std_logic
301 
 
302 
 
303 
);
304 
 
305 
 
306 
procedure PROC_TX_COMPLETION (
307 
 
308 
  tag                      : in std_logic_vector (7 downto 0);
309 
  tc                       : in std_logic_vector (2 downto 0);
310 
  len                      : in std_logic_vector (9 downto 0);
311 
  comp_status              : in std_logic_vector (2 downto 0);
312 
  signal trn_td_c          : out std_logic_vector(63 downto 0);
313 
  signal trn_tsof_n        : out std_logic;
314 
  signal trn_teof_n        : out std_logic;
315 
  signal trn_trem_n_c      : out std_logic_vector(7 downto 0);
316 
  signal trn_tsrc_rdy_n    : out std_logic;
317 
  signal trn_lnk_up_n : in std_logic;
318 
  signal trn_tdst_rdy_n : in std_logic;
319 
  signal trn_clk : in std_logic
320 
 
321 
);
322 
 
323 
procedure PROC_TX_COMPLETION_DATA (
324 
 
325 
  tag                      : in std_logic_vector (7 downto 0);
326 
  tc                       : in std_logic_vector (2 downto 0);
327 
  len                      : in std_logic_vector (9 downto 0);
328 
  byte_count               : in std_logic_vector (11 downto 0);
329 
  lower_addr               : in std_logic_vector (6 downto 0);
330 
  comp_status              : in std_logic_vector (2 downto 0);
331 
  ep                       : in std_logic;
332 
  signal trn_td_c          : out std_logic_vector(63 downto 0);
333 
  signal trn_tsof_n        : out std_logic;
334 
  signal trn_teof_n        : out std_logic;
335 
  signal trn_trem_n_c      : out std_logic_vector(7 downto 0);
336 
  signal trn_tsrc_rdy_n    : out std_logic;
337 
  signal trn_terrfwd_n     : out std_logic;
338 
  signal trn_lnk_up_n : in std_logic;
339 
  signal trn_tdst_rdy_n : in std_logic;
340 
  signal trn_clk : in std_logic
341 
 
342 
);
343 
 
344 
procedure PROC_TX_MESSAGE (
345 
 
346 
  tag                      : in std_logic_vector (7 downto 0);
347 
  tc                       : in std_logic_vector (2 downto 0);
348 
  len                      : in std_logic_vector (9 downto 0);
349 
  data                     : in std_logic_vector (63 downto 0);
350 
  message_rtg              : in std_logic_vector (2 downto 0);
351 
  message_code             : in std_logic_vector (7 downto 0);
352 
  signal trn_td_c          : out std_logic_vector(63 downto 0);
353 
  signal trn_tsof_n        : out std_logic;
354 
  signal trn_teof_n        : out std_logic;
355 
  signal trn_trem_n_c      : out std_logic_vector(7 downto 0);
356 
  signal trn_tsrc_rdy_n    : out std_logic;
357 
  signal trn_lnk_up_n : in std_logic;
358 
  signal trn_tdst_rdy_n : in std_logic;
359 
  signal trn_clk : in std_logic
360 
 
361 
);
362 
 
363 
procedure PROC_TX_MESSAGE_DATA (
364 
 
365 
  tag                      : in std_logic_vector (7 downto 0);
366 
  tc                       : in std_logic_vector (2 downto 0);
367 
  len                      : in std_logic_vector (9 downto 0);
368 
  data                     : in std_logic_vector (63 downto 0);
369 
  message_rtg              : in std_logic_vector (2 downto 0);
370 
  message_code             : in std_logic_vector (7 downto 0);
371 
  signal trn_td_c          : out std_logic_vector(63 downto 0);
372 
  signal trn_tsof_n        : out std_logic;
373 
  signal trn_teof_n        : out std_logic;
374 
  signal trn_trem_n_c      : out std_logic_vector(7 downto 0);
375 
  signal trn_tsrc_rdy_n    : out std_logic;
376 
  signal trn_lnk_up_n : in std_logic;
377 
  signal trn_tdst_rdy_n : in std_logic;
378 
  signal trn_clk : in std_logic
379 
 
380 
);
381 
 
382 
procedure PROC_TX_IO_READ (
383 
 
384 
  tag                      : in std_logic_vector (7 downto 0);
385 
  addr                     : in std_logic_vector (31 downto 0);
386 
  first_dw_be              : in std_logic_vector (3 downto 0);
387 
  signal trn_td_c          : out std_logic_vector(63 downto 0);
388 
  signal trn_tsof_n        : out std_logic;
389 
  signal trn_teof_n        : out std_logic;
390 
  signal trn_trem_n_c      : out std_logic_vector(7 downto 0);
391 
  signal trn_tsrc_rdy_n    : out std_logic;
392 
  signal trn_lnk_up_n : in std_logic;
393 
  signal trn_tdst_rdy_n : in std_logic;
394 
  signal trn_clk : in std_logic
395 
 
396 
);
397 
 
398 
procedure PROC_TX_IO_WRITE (
399 
 
400 
  tag                      : in std_logic_vector (7 downto 0);
401 
  addr                     : in std_logic_vector (31 downto 0);
402 
  first_dw_be              : in std_logic_vector (3 downto 0);
403 
  data                     : in std_logic_vector(31 downto 0);
404 
  signal trn_td_c          : out std_logic_vector(63 downto 0);
405 
  signal trn_tsof_n        : out std_logic;
406 
  signal trn_teof_n        : out std_logic;
407 
  signal trn_trem_n_c      : out std_logic_vector(7 downto 0);
408 
  signal trn_tsrc_rdy_n    : out std_logic;
409 
  signal trn_lnk_up_n : in std_logic;
410 
  signal trn_tdst_rdy_n : in std_logic;
411 
  signal trn_clk : in std_logic
412 
 
413 
);
414 
 
415 
procedure PROC_USR_DATA_SETUP_SEQ;
416 
 
417 
procedure PROC_TX_CLK_EAT  (
418 
 
419 
  clock_count : in INTEGER;
420 
  signal trn_clk : in std_logic
421 
 
422 
);
423 
 
424 
procedure PROC_SET_READ_DATA  (
425 
 
426 
  be     : in std_logic_vector(3 downto 0);
427 
  data   : in std_logic_vector(31 downto 0)
428 
 
429 
);
430 
 
431 
procedure PROC_WAIT_FOR_READ_DATA  (
432 
 
433 
  signal tx_rx_read_data_valid    : out std_logic;
434 
  signal rx_tx_read_data_valid    : in std_logic;
435 
  signal rx_tx_read_data : in std_logic_vector(31 downto 0);
436 
  signal trn_clk : in std_logic
437 
 
438 
);
439 
 
440 
procedure PROC_DISPLAY_PCIE_MAP  (
441 
 
442 
  BAR            : THIRTY_THREE_BIT_ARRAY;
443 
  BAR_ENABLED    : ENABLE_ARRAY;
444 
  BAR_RANGE      : DWORD_ARRAY
445 
 
446 
);
447 
 
448 
procedure PROC_BUILD_PCIE_MAP
449 
;
450 
 
451 
procedure PROC_BAR_SCAN  (
452 
 
453 
  signal tx_rx_read_data_valid : out std_logic;
454 
  signal rx_tx_read_data_valid : in std_logic;
455 
  signal rx_tx_read_data : in std_logic_vector (31 downto 0);
456 
  signal trn_td_c : out std_logic_vector(63 downto 0);
457 
  signal trn_tsof_n : out std_logic;
458 
  signal trn_teof_n : out std_logic;
459 
  signal trn_trem_n_c : out std_logic_vector(7 downto 0);
460 
  signal trn_tsrc_rdy_n : out std_logic;
461 
  signal trn_lnk_up_n : in std_logic;
462 
  signal trn_tdst_rdy_n : in std_logic;
463 
  signal trn_clk : in std_logic
464 
 
465 
);
466 
 
467 
procedure PROC_BAR_PROGRAM  (
468 
 
469 
  signal trn_td_c          : out std_logic_vector(63 downto 0);
470 
  signal trn_tsof_n        : out std_logic;
471 
  signal trn_teof_n        : out std_logic;
472 
  signal trn_trem_n_c      : out std_logic_vector(7 downto 0);
473 
  signal trn_tsrc_rdy_n    : out std_logic;
474 
  signal trn_lnk_up_n : in std_logic;
475 
  signal trn_tdst_rdy_n : in std_logic;
476 
  signal trn_clk : in std_logic
477 
 
478 
);
479 
 
480 
procedure PROC_BAR_INIT  (
481 
 
482 
  signal tx_rx_read_data_valid : out std_logic;
483 
  signal rx_tx_read_data_valid : in std_logic;
484 
  signal rx_tx_read_data : in std_logic_vector (31 downto 0);
485 
  signal trn_td_c : out std_logic_vector(63 downto 0);
486 
  signal trn_tsof_n : out std_logic;
487 
  signal trn_teof_n : out std_logic;
488 
  signal trn_trem_n_c : out std_logic_vector(7 downto 0);
489 
  signal trn_tsrc_rdy_n : out std_logic;
490 
  signal trn_lnk_up_n : in std_logic;
491 
  signal trn_tdst_rdy_n : in std_logic;
492 
  signal trn_clk : in std_logic
493 
 
494 
 );
495 
 
496 
procedure PROC_SYSTEM_INITIALIZATION(
497 
     signal trn_reset_n: in std_logic;
498 
     signal trn_lnk_up_n: in std_logic;
499 
     signal speed_change_done_n : in std_logic
500 
);
501 
 
502 
 
503 
procedure PROC_READ_CFG_DW (
504 
  addr                : in    std_logic_vector(9 downto 0);
505 
  signal cfg_rdwr_int : inout cfg_rdwr_sigs
506 
);
507 
 
508 
procedure PROC_WRITE_CFG_DW (
509 
  addr                : in    std_logic_vector(9 downto 0);
510 
  data                : in    std_logic_vector(31 downto 0);
511 
  byte_en_n           : in    std_logic_vector(3 downto 0);
512 
  signal cfg_rdwr_int : inout cfg_rdwr_sigs
513 
);
514 
 
515 
end package test_interface;
516 
 
517 
 
518 
 
519 
-- Package Body
520 
 
521 
package body test_interface is
522 
 
523 
--************************************************************
524 
--     Proc : writeNowToTx
525 
--     Inputs : Text String
526 
--     Outputs : None
527 
--     Description : Displays text string to Tx file pre-appended with
528 
--         current simulation time..
529 
--*************************************************************
530 
 
531 
procedure writeNowToTx (
532 
 
533 
  text_string     : in string
534 
 
535 
) is
536 
 
537 
  variable L      : line;
538 
 
539 
begin
540 
 
541 
  write (L, String'("[ "));
542 
  write (L, now);
543 
  write (L, String'(" ] : "));
544 
  write (L, text_string);
545 
  writeline (tx_file, L);
546 
 
547 
end writeNowToTx;
548 
 
549 
 
550 
--************************************************************
551 
--     Proc : writeHexToTx
552 
--     Inputs : hex value with bit width that is multiple of 4
553 
--     Outputs : None
554 
--     Description : Displays nibble aligned hex value to Tx file
555 
--
556 
--*************************************************************
557 
 
558 
procedure writeHexToTx (
559 
 
560 
  text_string     : in string;
561 
  hexValue        : in std_logic_vector
562 
 
563 
) is
564 
 
565 
  variable L      : line;
566 
 
567 
begin
568 
 
569 
  write (L, text_string);
570 
  hwrite(L, hexValue);
571 
  writeline (tx_file, L);
572 
 
573 
end writeHexToTx;
574 
 
575 
 
576 
--************************************************************
577 
--     Proc : writeNowToScreen
578 
--     Inputs : Text String
579 
--     Outputs : None
580 
--     Description : Displays current simulation time and text string to
581 
--          standard output.
582 
--*************************************************************
583 
 
584 
procedure writeNowToScreen (
585 
 
586 
  text_string     : in string
587 
 
588 
) is
589 
 
590 
  variable L      : line;
591 
 
592 
begin
593 
 
594 
  write (L, String'("[ "));
595 
  write (L, now);
596 
  write (L, String'(" ] : "));
597 
  write (L, text_string);
598 
  writeline (output, L);
599 
 
600 
end writeNowToScreen;
601 
 
602 
 
603 
 
604 
--************************************************************
605 
--     Proc : PROC_READ_DATA
606 
--     Inputs : None
607 
--     Outputs : None
608 
--     Description : Consume clocks.
609 
--   *************************************************************/
610 
 
611 
procedure PROC_READ_DATA (
612 
 
613 
  last                  : in INTEGER;
614 
  trn_d                 : in std_logic_vector (63 downto 0);
615 
  trn_rem               : in std_logic_vector (7 downto 0)
616 
 
617 
) is
618 
 
619 
  variable i            : INTEGER;
620 
  variable data_byte    : std_logic_vector (7 downto 0);
621 
  variable remain       : INTEGER;
622 
  variable hi_index     : INTEGER;
623 
  variable low_index    : INTEGER;
624 
  variable my_line      : line;
625 
 
626 
begin
627 
 
628 
  hi_index := 63;
629 
  low_index := 56;
630 
  if (last = 1) then
631 
 
632 
    if (trn_rem = X"0F") then
633 
 
634 
      remain := 4;
635 
 
636 
    else remain := 8;
637 
 
638 
    end if;
639 
 
640 
  else
641 
 
642 
    remain := 8;
643 
 
644 
  end if;
645 
  for i in 0 to (remain - 1) loop
646 
 
647 
    data_byte := trn_d( hi_index downto low_index);
648 
    hi_index := hi_index - 8;
649 
    low_index := low_index - 8;
650 
    frame_store_tx(frame_store_tx_idx) := data_byte;
651 
    frame_store_tx_idx := frame_store_tx_idx + 1;
652 
 
653 
  end loop;
654 
 
655 
end PROC_READ_DATA;
656 
 
657 
 
658 
--************************************************************
659 
--  Proc : PROC_DECIPHER_FRAME
660 
--  Inputs : None
661 
-- Outputs : fmt, tlp_type, traffic_class, td, ep, attr, length
662 
--  Description : Deciphers frame
663 
--  *************************************************************/
664 
 
665 
 
666 
procedure PROC_DECIPHER_FRAME (
667 
 
668 
  fmt                   : out std_logic_vector (1 downto 0);
669 
  tlp_type              : out std_logic_vector (4 downto 0);
670 
  traffic_class         : out std_logic_vector (2 downto 0);
671 
  td                    : out std_logic;
672 
  ep                    : out std_logic;
673 
  attr                  : out std_logic_vector (1 downto 0);
674 
  length                : out std_logic_vector (9 downto 0)
675 
 
676 
) is
677 
 
678 
begin
679 
 
680 
  fmt := frame_store_tx(0)(6 downto 5);
681 
  tlp_type := frame_store_tx(0)(4 downto 0);
682 
  traffic_class := frame_store_tx(1)(6 downto 4);
683 
  td := frame_store_tx(2)(7);
684 
  ep := frame_store_tx(2)(6);
685 
  attr := frame_store_tx(2)(5 downto 4);
686 
  length(9 downto 8) := frame_store_tx(2)(1 downto 0);
687 
  length(7 downto 0) := frame_store_tx(3);
688 
 
689 
end PROC_DECIPHER_FRAME;
690 
 
691 
 
692 
-- ************************************************************
693 
--  Proc : PROC_3DW
694 
--  Inputs : fmt, type, traffic_class, td, ep, attr, length,
695 
--  payload,
696 
--  Outputs : None
697 
--  Description : Gets variables and prints frame
698 
--  *************************************************************/
699 
 
700 
 
701 
procedure PROC_3DW (
702 
 
703 
  fmt              : in std_logic_vector (1 downto 0);
704 
  tlp_type         : in std_logic_vector (4 downto 0);
705 
  traffic_class    : in std_logic_vector (2 downto 0);
706 
  td               : in std_logic;
707 
  ep               : in std_logic;
708 
  attr             : in std_logic_vector (1 downto 0);
709 
  length           : in std_logic_vector (9 downto 0);
710 
  payload          : in INTEGER
711 
 
712 
) is
713 
 
714 
  variable requester_id         : std_logic_vector (15 downto 0);
715 
  variable tag                  : std_logic_vector (7 downto 0);
716 
  variable byte_enables         : std_logic_vector (7 downto 0);
717 
  variable address_low          : std_logic_vector (31 downto 0);
718 
  variable completer_id         : std_logic_vector (15 downto 0);
719 
  variable register_address     : std_logic_vector (9 downto 0);
720 
  variable completion_status    : std_logic_vector (2 downto 0);
721 
  variable i                    : INTEGER;
722 
  variable L                    : line;
723 
  variable fmt_type             : std_logic_vector (6 downto 0);
724 
 
725 
begin
726 
 
727 
  writeHexToTx (String'("     Traffic Class: 0x"), '0' & traffic_class);
728 
  write (L, String'("     TD: ")); write(L,  td); writeline (tx_file, L);
729 
  write (L, String'("     EP: ")); write(L, ep); writeline (tx_file, L);
730 
  writeHexToTx (String'("     Attributes: 0x"), "00" & attr);
731 
  writeHexToTx (String'("     Length: 0x"), "00" & length);
732 
 
733 
  fmt_type := fmt & tlp_type;
734 
  case (fmt_type) is
735 
 
736 
    when PCI_EXP_CFG_READ0 | PCI_EXP_CFG_WRITE0 =>
737 
 
738 
      requester_id := frame_store_tx(4) & frame_store_tx(5);
739 
      tag := frame_store_tx(6);
740 
      byte_enables := frame_store_tx(7);
741 
      completer_id := frame_store_tx(8) & frame_store_tx(9);
742 
      register_address(9 downto 8) := frame_store_tx(10)(1 downto 0);
743 
      register_address(7 downto 0) := frame_store_tx(11);
744 
 
745 
      writeHexToTx ( String'("     Requester Id: 0x"), requester_id);
746 
      writeHexToTx ( String'("     Tag: 0x"), tag);
747 
      writeHexToTx ( String'("     Last and First Byte Enables: 0x"), byte_enables);
748 
      writeHexToTx ( String'("     Completer Id: 0x"), completer_id);
749 
      writeHexToTx ( String'("     Register Address: 0x"), "00" & register_address);
750 
 
751 
      if (payload = 1) then
752 
 
753 
        write (L, String'("")); writeline(tx_file, L);
754 
        for i in 12 to (frame_store_tx_idx - 1) loop
755 
 
756 
          writeHexToTx ( String'("     0x"), frame_store_tx(i));
757 
 
758 
        end loop;
759 
 
760 
      end if;
761 
      write (L, String'("")); writeline(tx_file, L);
762 
 
763 
    when PCI_EXP_COMPLETION_WO_DATA | PCI_EXP_COMPLETION_DATA=>
764 
 
765 
      completer_id := frame_store_tx(4) & frame_store_tx(5);
766 
      completion_status(2 downto 0) := frame_store_tx(6)(7 downto 5);
767 
      requester_id := frame_store_tx(8) & frame_store_tx(9);
768 
      tag := frame_store_tx(10);
769 
 
770 
      writeHexToTx ( String'("     Completer Id: 0x"), completer_id);
771 
      writeHexToTx ( String'("     Completion Status: 0x"), '0' & completion_status);
772 
      writeHexToTx ( String'("     Requester Id: 0x"), requester_id);
773 
      writeHexToTx ( String'("     Tag: 0x"), tag);
774 
 
775 
      if (payload = 1) then
776 
 
777 
        write (L, String'("")); writeline(tx_file, L);
778 
        for i in 12 to (frame_store_tx_idx - 1) loop
779 
 
780 
                    writeHexToTx ( String'("     0x"), frame_store_tx(i));
781 
 
782 
        end loop;
783 
 
784 
      end if;
785 
      write (L, String'("")); writeline(tx_file, L);
786 
 
787 
    when others =>
788 
 
789 
      requester_id := frame_store_tx(4) & frame_store_tx(5);
790 
      tag := frame_store_tx(6);
791 
      byte_enables := frame_store_tx(7);
792 
      address_low(31 downto 24) := frame_store_tx(8);
793 
      address_low(23 downto 16) := frame_store_tx(9);
794 
      address_low(15 downto 8) := frame_store_tx(10);
795 
      address_low( 7 downto 0) := frame_store_tx(11);
796 
 
797 
      writeHexToTx ( String'("     Requester Id: 0x"), requester_id);
798 
      writeHexToTx ( String'("     Tag: 0x"), tag);
799 
      writeHexToTx ( String'("     Last and First Byte Enables: 0x"), byte_enables);
800 
      writeHexToTx ( String'("     Address Low: 0x"), address_low);
801 
 
802 
      if (payload = 1) then
803 
 
804 
        write (L, String'("")); writeline(tx_file, L);
805 
        for i in 12 to (frame_store_tx_idx - 1) loop
806 
 
807 
          writeHexToTx ( String'("     0x"), frame_store_tx(i));
808 
 
809 
        end loop;
810 
 
811 
      end if;
812 
      write (L, String'("")); writeline(tx_file, L);
813 
 
814 
  end  case;
815 
 
816 
end PROC_3DW;
817 
 
818 
 
819 
-- ************************************************************
820 
--  Proc : PROC_4DW
821 
--  Inputs : fmt, type, traffic_class, td, ep, attr, length
822 
--  payload
823 
--  Outputs : None
824 
--  Description : Gets variables and prints frame
825 
--  *************************************************************/
826 
 
827 
 
828 
procedure PROC_4DW (
829 
 
830 
  fmt              : in std_logic_vector (1 downto 0);
831 
  tlp_type         : in std_logic_vector (4 downto 0);
832 
  traffic_class    : in std_logic_vector (2 downto 0);
833 
  td               : in std_logic;
834 
  ep               : in std_logic;
835 
  attr             : in std_logic_vector (1 downto 0);
836 
  length           : in std_logic_vector (9 downto 0);
837 
  payload          : in INTEGER
838 
 
839 
) is
840 
 
841 
  variable requester_id    : std_logic_vector (15 downto 0);
842 
  variable tag             : std_logic_vector (7 downto 0);
843 
  variable byte_enables    : std_logic_vector (7 downto 0);
844 
  variable message_code    : std_logic_vector (7 downto 0);
845 
  variable address_high    : std_logic_vector (31 downto 0);
846 
  variable address_low     : std_logic_vector (31 downto 0);
847 
  variable msg_type        : std_logic_vector (2 downto 0);
848 
  variable i               : INTEGER;
849 
  variable L               : line;
850 
  variable fmt_type        : std_logic_vector (6 downto 0);
851 
 
852 
begin
853 
 
854 
  writeHexToTx (String'("     Traffic Class: 0x"), '0' & traffic_class);
855 
  write (L, String'("     TD: ")); write(L,  td); writeline (tx_file, L);
856 
  write (L, String'("     EP: ")); write(L, ep); writeline (tx_file, L);
857 
  writeHexToTx (String'("     Attributes: 0x"), "00" & attr);
858 
  writeHexToTx (String'("     Length: 0x"), "00" & length);
859 
 
860 
  requester_id := frame_store_tx(4) & frame_store_tx(5);
861 
  tag := frame_store_tx(6);
862 
  byte_enables := frame_store_tx(7);
863 
  message_code := frame_store_tx(7);
864 
  address_high(31 downto 24) := frame_store_tx(8);
865 
  address_high(23 downto 16) := frame_store_tx(9) ;
866 
  address_high(15 downto 8) := frame_store_tx(10);
867 
  address_high(7 downto 0) := frame_store_tx(11);
868 
  address_low(31 downto 24) := frame_store_tx(12);
869 
  address_low(23 downto 16) := frame_store_tx(13);
870 
  address_low(15 downto 8) := frame_store_tx(14) ;
871 
  address_low(7 downto 0) := frame_store_tx(15);
872 
 
873 
  writeHexToTx ( String'("     Requester Id: 0x"), requester_id);
874 
  writeHexToTx ( String'("     Tag: 0x"), tag);
875 
 
876 
  fmt_type := fmt & tlp_type;
877 
 
878 
  if ((fmt_type(6 downto 3) = PCI_EXP_MSG_NODATA)
879 
     or (fmt_type(6 downto 3) = PCI_EXP_MSG_DATA)) then
880 
 
881 
    msg_type := tlp_type(2 downto 0);
882 
    writeHexToTx ( String'("     Message Type: 0x"), '0' & msg_type);
883 
    writeHexToTx ( String'("     Message Code: 0x"), message_code);
884 
    writeHexToTx ( String'("     Address High: 0x"), address_high);
885 
    writeHexToTx ( String'("     Address Low:  0x"), address_low);
886 
 
887 
    if (payload = 1) then
888 
 
889 
      write (L, String'("")); writeline(tx_file, L);
890 
      for i in 16 to (frame_store_tx_idx - 1) loop
891 
 
892 
        writeHexToTx ( String'("     0x"), frame_store_tx(i));
893 
 
894 
      end loop;
895 
 
896 
    end if;
897 
    write (L, String'("")); writeline(tx_file, L);
898 
 
899 
  else
900 
 
901 
    case (fmt_type) is
902 
 
903 
      when PCI_EXP_MEM_READ64 | PCI_EXP_MEM_WRITE64 =>
904 
 
905 
        writeHexToTx ( String'("     Last and First Byte Enables: 0x"), byte_enables);
906 
        writeHexToTx ( String'("     Address High: 0x"), address_high);
907 
        writeHexToTx ( String'("     Address Low:  0x"), address_low);
908 
 
909 
        if (payload = 1) then
910 
 
911 
          write (L, String'("")); writeline(tx_file, L);
912 
          for i in 16 to (frame_store_tx_idx - 1) loop
913 
 
914 
            writeHexToTx ( String'("     0x"), frame_store_tx(i));
915 
 
916 
          end loop;
917 
 
918 
        end if;
919 
 
920 
        write (L, String'("")); writeline(tx_file, L);
921 
 
922 
      when others =>
923 
 
924 
        write (L, String'(": Not a vaild frame")); writeline (tx_file, L); write (L, String'("")); writeline(tx_file, L);
925 
        assert (false)
926 
          report "Simulation Ended"
927 
          severity failure;
928 
 
929 
    end  case; -- (fmt_type)
930 
 
931 
  end if;
932 
 
933 
end PROC_4DW;
934 
 
935 
 
936 
--************************************************************
937 
--  Proc : PROC_PARSE_FRAME
938 
--  Inputs : None
939 
--  Outputs : None
940 
--  Description : Parse frame data
941 
--  *************************************************************/
942 
 
943 
procedure PROC_PARSE_FRAME is
944 
 
945 
  variable fmt                  : std_logic_vector (1 downto 0);
946 
  variable tlp_type             : std_logic_vector (4 downto 0);
947 
  variable traffic_class        : std_logic_vector (2 downto 0);
948 
  variable td                   : std_logic;
949 
  variable ep                   : std_logic;
950 
  variable attr                 : std_logic_vector (1 downto 0);
951 
  variable length               : std_logic_vector (9 downto 0);
952 
  variable payload              : INTEGER;
953 
  variable reqester_id          : std_logic_vector(15 downto 0);
954 
  variable completer_id         : std_logic_vector(15 downto 0);
955 
  variable tag                  : std_logic_vector(7 downto 0);
956 
  variable byte_enables         : std_logic_vector(7 downto 0);
957 
  variable message_code         : std_logic_vector(7 downto 0);
958 
  variable address_low          : std_logic_vector(31 downto 0);
959 
  variable address_high         : std_logic_vector(31 downto 0);
960 
  variable register_address     : std_logic_vector (9 downto 0);
961 
  variable completion_status    : std_logic_vector (2 downto 0);
962 
  variable log_file_ptr         : std_logic_vector (31 downto 0);
963 
  variable frame_store_idx      : INTEGER;
964 
  variable fmt_type             : std_logic_vector (6 downto 0);
965 
  variable L                    : line;
966 
 
967 
begin
968 
 
969 
  writeNowToScreen ( String'("PROC_PARSE_FRAME on Transmit"));
970 
  PROC_DECIPHER_FRAME (fmt, tlp_type, traffic_class, td, ep, attr, length);
971 
 
972 
  -- decode the packets received based on fmt and type
973 
  fmt_type := fmt & tlp_type;
974 
 
975 
  if (fmt_type(6 downto 3) = PCI_EXP_MSG_NODATA) then
976 
 
977 
    writeNowToTx("Message With No Data Frame");
978 
    payload := 0;
979 
    PROC_4DW(fmt, tlp_type, traffic_class, td, ep, attr, length, payload);
980 
 
981 
  elsif (fmt_type(6 downto 3) = PCI_EXP_MSG_DATA) then
982 
 
983 
    writeNowToTx("Message With Data Frame");
984 
    payload := 1;
985 
    PROC_4DW(fmt, tlp_type, traffic_class, td, ep, attr, length, payload);
986 
 
987 
  else
988 
 
989 
    case (fmt_type) is
990 
 
991 
      when PCI_EXP_MEM_READ32 =>
992 
 
993 
        writeNowToTx("Memory Read-32 Frame");
994 
        payload := 0;
995 
        PROC_3DW(fmt, tlp_type, traffic_class, td, ep, attr, length, payload);
996 
 
997 
      when PCI_EXP_IO_READ =>
998 
 
999 
        writeNowToTx("IO Read Frame");
1000 
        payload := 0;
1001 
        PROC_3DW(fmt, tlp_type, traffic_class, td, ep, attr, length, payload);
1002 
 
1003 
      when PCI_EXP_CFG_READ0 =>
1004 
 
1005 
        writeNowToTx("Config Read Type 0 Frame");
1006 
        payload := 0;
1007 
        PROC_3DW(fmt, tlp_type, traffic_class, td, ep, attr, length, payload);
1008 
 
1009 
      when PCI_EXP_COMPLETION_WO_DATA =>
1010 
 
1011 
        writeNowToTx("Completion Without Data Frame");
1012 
        payload := 0;
1013 
        PROC_3DW(fmt, tlp_type, traffic_class, td, ep, attr, length, payload);
1014 
 
1015 
      when PCI_EXP_MEM_READ64 =>
1016 
 
1017 
        writeNowToTx("Memory Read-64 Frame");
1018 
        payload := 0;
1019 
        PROC_4DW(fmt, tlp_type, traffic_class, td, ep, attr, length, payload);
1020 
 
1021 
      when PCI_EXP_MEM_WRITE32 =>
1022 
 
1023 
        writeNowToTx("Memory Write-32 Frame");
1024 
        payload := 1;
1025 
        PROC_3DW(fmt, tlp_type, traffic_class, td, ep, attr, length, payload);
1026 
 
1027 
      when PCI_EXP_IO_WRITE =>
1028 
 
1029 
        writeNowToTx("IO Write Frame");
1030 
        payload := 1;
1031 
        PROC_3DW(fmt, tlp_type, traffic_class, td, ep, attr, length, payload);
1032 
 
1033 
      when PCI_EXP_CFG_WRITE0 =>
1034 
 
1035 
        writeNowToTx("Config Write Type 0 Frame");
1036 
        payload := 1;
1037 
        PROC_3DW(fmt, tlp_type, traffic_class, td, ep, attr, length, payload);
1038 
 
1039 
      when PCI_EXP_COMPLETION_DATA =>
1040 
 
1041 
        writeNowToTx("Completion With Data Frame");
1042 
        payload := 1;
1043 
        PROC_3DW(fmt, tlp_type, traffic_class, td, ep, attr, length, payload);
1044 
 
1045 
      when PCI_EXP_MEM_WRITE64 =>
1046 
 
1047 
        writeNowToTx("Memory Write-64 Frame");
1048 
        payload := 1;
1049 
        PROC_4DW(fmt, tlp_type, traffic_class, td, ep, attr, length, payload);
1050 
 
1051 
      when others =>
1052 
 
1053 
        writeNowToTx("Not a vaild frame. fmt_type = ");
1054 
        write (L, fmt_type);
1055 
        writeline (tx_file, L);
1056 
        assert (false)
1057 
          report "Simulation Ended"
1058 
          severity failure;
1059 
 
1060 
    end  case;
1061 
 
1062 
  end if;
1063 
 
1064 
  frame_store_tx_idx := 0; -- reset frame pointer
1065 
 
1066 
end PROC_PARSE_FRAME;
1067 
 
1068 
--************************************************************
1069 
--  Proc : FINISH
1070 
--  Inputs : None
1071 
--  Outputs : None
1072 
--  Description : Ends simulation with successful message
1073 
--*************************************************************/
1074 
 
1075 
procedure FINISH is
1076 
 
1077 
  variable  L : line;
1078 
 
1079 
begin
1080 
 
1081 
  assert (false)
1082 
    report "Simulation Stopped."
1083 
    severity failure;
1084 
 
1085 
end FINISH;
1086 
 
1087 
 
1088 
--************************************************************
1089 
--  Proc : FINISH_FAILURE
1090 
--  Inputs : None
1091 
--  Outputs : None
1092 
--  Description : Ends simulation with failure message
1093 
--*************************************************************/
1094 
 
1095 
procedure FINISH_FAILURE is
1096 
 
1097 
  variable  L : line;
1098 
 
1099 
begin
1100 
 
1101 
  assert (false)
1102 
    report "Simulation Ended With 1 or more failures"
1103 
    severity failure;
1104 
 
1105 
end FINISH_FAILURE;
1106 
 
1107 
 
1108 
--************************************************************
1109 
--    Proc : PROC_TX_CLK_EAT
1110 
--    Inputs : None
1111 
--    Outputs : None
1112 
--    Description : Consume clocks.
1113 
--*************************************************************/
1114 
 
1115 
procedure PROC_TX_CLK_EAT  (
1116 
 
1117 
  clock_count : in INTEGER;
1118 
  signal trn_clk : in std_logic
1119 
 
1120 
) is
1121 
 
1122 
  variable i  : INTEGER;
1123 
 
1124 
begin
1125 
 
1126 
  for i in 0 to (clock_count - 1) loop
1127 
 
1128 
    wait until (trn_clk'event and trn_clk = '1');
1129 
 
1130 
  end loop;
1131 
 
1132 
end PROC_TX_CLK_EAT;
1133 
 
1134 
 
1135 
--************************************************************
1136 
--    Proc : PROC_TX_SYNCHRONIZE
1137 
--    Inputs : first_, last_call_
1138 
--    Outputs : None
1139 
--    Description : Synchronize with tx clock and handshake signals
1140 
--*************************************************************/
1141 
 
1142 
procedure PROC_TX_SYNCHRONIZE (
1143 
 
1144 
  first : in INTEGER;
1145 
  last_call: in INTEGER;
1146 
  signal trn_lnk_up_n : in std_logic;
1147 
  signal trn_tdst_rdy_n : in std_logic;
1148 
  signal trn_clk : in std_logic
1149 
 
1150 
) is
1151 
 
1152 
  variable last  : INTEGER;
1153 
 
1154 
begin
1155 
 
1156 
  assert (trn_lnk_up_n = '0')
1157 
    report "TX Trn interface is MIA"
1158 
    severity failure;
1159 
 
1160 
  wait until (trn_clk'event and trn_clk = '1');
1161 
 
1162 
  if ((trn_tdst_rdy_n = '1') and (first = 1)) then
1163 
 
1164 
    while (trn_tdst_rdy_n = '1') loop
1165 
 
1166 
      wait until (trn_clk'event and trn_clk = '1');
1167 
 
1168 
    end loop;
1169 
 
1170 
  end if;
1171 
  if (first = 1) then
1172 
 
1173 
    if (trn_trem_n_c = X"00") then --"00000000") then
1174 
 
1175 
      last := 0;
1176 
 
1177 
    else
1178 
 
1179 
      last := 1;
1180 
 
1181 
    end if;
1182 
 
1183 
    PROC_READ_DATA(last, trn_td_c, trn_trem_n_c);
1184 
 
1185 
  end if;
1186 
  if (last_call = 1) then
1187 
 
1188 
    PROC_PARSE_FRAME;
1189 
 
1190 
  end if;
1191 
 
1192 
end PROC_TX_SYNCHRONIZE;
1193 
 
1194 
 
1195 
 
1196 
--************************************************************
1197 
--    Proc : PROC_TX_TYPE0_CONFIGURATION_READ
1198 
--    Inputs : Tag, PCI/PCI-Express Reg Address, First BypeEn
1199 
--    Outputs : Transaction Tx Interface Signaling
1200 
--    Description : Generates a Type 0 Configuration Read TLP
1201 
--*************************************************************/
1202 
 
1203 
procedure PROC_TX_TYPE0_CONFIGURATION_READ (
1204 
 
1205 
  tag                      : in std_logic_vector (7 downto 0);
1206 
  reg_addr                 : in std_logic_vector (11 downto 0);
1207 
  first_dw_be              : in std_logic_vector (3 downto 0);
1208 
  signal trn_td_c          : out std_logic_vector(63 downto 0);
1209 
  signal trn_tsof_n        : out std_logic;
1210 
  signal trn_teof_n        : out std_logic;
1211 
  signal trn_trem_n_c      : out std_logic_vector(7 downto 0);
1212 
  signal trn_tsrc_rdy_n    : out std_logic;
1213 
  signal trn_lnk_up_n : in std_logic;
1214 
  signal trn_tdst_rdy_n : in std_logic;
1215 
  signal trn_clk : in std_logic
1216 
 
1217 
) is
1218 
 
1219 
begin
1220 
 
1221 
  assert (trn_lnk_up_n = '0')
1222 
    report "TX Trn interface is MIA"
1223 
    severity failure;
1224 
 
1225 
 
1226 
  PROC_TX_SYNCHRONIZE(0, 0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
1227 
 
1228 
  trn_td_c          <= '0' &
1229 
                       "00" &
1230 
                       "00100" &
1231 
                       '0' &
1232 
                       "000" &
1233 
                       "0000" &
1234 
                       '0' &
1235 
                       '0' &
1236 
                       "00" &
1237 
                       "00" &
1238 
                       "0000000001" &
1239 
                       COMPLETER_ID_CFG &
1240 
                       tag(7 downto 0) &
1241 
                       "0000" &
1242 
                       first_dw_be(3 downto 0);
1243 
  trn_tsof_n        <= '0';
1244 
  trn_teof_n        <= '1';
1245 
  trn_trem_n_c      <= X"00";
1246 
  trn_tsrc_rdy_n    <= '0';
1247 
 
1248 
  PROC_TX_SYNCHRONIZE(1,0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
1249 
 
1250 
  trn_td_c          <= COMPLETER_ID_CFG &
1251 
                       "0000" &
1252 
                       reg_addr(11 downto 2) &
1253 
                       "00" &
1254 
                       X"00000000";
1255 
  trn_tsof_n        <= '1';
1256 
  trn_teof_n        <= '0';
1257 
  trn_trem_n_c      <= X"0F";
1258 
  trn_tsrc_rdy_n    <= '0';
1259 
 
1260 
  PROC_TX_SYNCHRONIZE(1, 1, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
1261 
 
1262 
  trn_teof_n        <= '1';
1263 
  trn_trem_n_c      <= X"00";
1264 
  trn_tsrc_rdy_n    <= '1';
1265 
 
1266 
end PROC_TX_TYPE0_CONFIGURATION_READ;
1267 
 
1268 
 
1269 
--************************************************************
1270 
--    Proc : PROC_TX_TYPE0_CONFIGURATION_WRITE
1271 
--    Inputs : Tag, PCI/PCI-Express Reg Address, First BypeEn
1272 
--    Outputs : Transaction Tx Interface Signaling
1273 
--    Description : Generates a Type 0 Configuration Write TLP
1274 
--*************************************************************/
1275 
 
1276 
procedure PROC_TX_TYPE0_CONFIGURATION_WRITE (
1277 
 
1278 
  tag                      : in std_logic_vector (7 downto 0);
1279 
  reg_addr                 : in std_logic_vector (11 downto 0);
1280 
  reg_data                 : in std_logic_vector (31 downto 0);
1281 
  first_dw_be              : in std_logic_vector (3 downto 0);
1282 
  signal trn_td_c          : out std_logic_vector(63 downto 0);
1283 
  signal trn_tsof_n        : out std_logic;
1284 
  signal trn_teof_n        : out std_logic;
1285 
  signal trn_trem_n_c      : out std_logic_vector(7 downto 0);
1286 
  signal trn_tsrc_rdy_n    : out std_logic;
1287 
  signal trn_lnk_up_n : in std_logic;
1288 
  signal trn_tdst_rdy_n : in std_logic;
1289 
  signal trn_clk : in std_logic
1290 
 
1291 
) is
1292 
 
1293 
begin
1294 
 
1295 
  assert (trn_lnk_up_n = '0')
1296 
    report "TX Trn interface is MIA"
1297 
    severity failure;
1298 
 
1299 
 
1300 
  PROC_TX_SYNCHRONIZE(0, 0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
1301 
 
1302 
  trn_td_c <=          '0' &
1303 
                       "10" &
1304 
                       "00100" &
1305 
                       '0' &
1306 
                       "000" &
1307 
                       "0000" &
1308 
                       '0' &
1309 
                       '0' &
1310 
                       "00" &
1311 
                       "00" &
1312 
                       "0000000001" &
1313 
                       COMPLETER_ID_CFG &
1314 
                       tag(7 downto 0) &
1315 
                       "0000" &
1316 
                       first_dw_be(3 downto 0);
1317 
  trn_tsof_n        <= '0';
1318 
  trn_tsrc_rdy_n    <= '0';
1319 
 
1320 
  PROC_TX_SYNCHRONIZE(1,0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
1321 
 
1322 
  trn_td_c          <= COMPLETER_ID_CFG &
1323 
                       "0000" &
1324 
                       reg_addr(11 downto 2) &
1325 
                       "00" &
1326 
                       reg_data(7 downto 0) &
1327 
                       reg_data(15 downto 8) &
1328 
                       reg_data(23 downto 16) &
1329 
                       reg_data(31 downto 24);
1330 
  trn_tsof_n        <= '1';
1331 
  trn_teof_n        <= '0';
1332 
  trn_trem_n_c      <= X"00";
1333 
 
1334 
  PROC_TX_SYNCHRONIZE(1, 1, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
1335 
 
1336 
  trn_teof_n        <= '1';
1337 
  trn_tsrc_rdy_n    <= '1';
1338 
 
1339 
 
1340 
end PROC_TX_TYPE0_CONFIGURATION_WRITE;
1341 
 
1342 
 
1343 
--************************************************************
1344 
--    Proc : PROC_TX_TYPE1_CONFIGURATION_READ
1345 
--    Inputs : Tag, PCI/PCI-Express Reg Address, First BypeEn
1346 
--    Outputs : Transaction Tx Interface Signaling
1347 
--    Description : Generates a Type 1 Configuration Read TLP
1348 
--*************************************************************/
1349 
 
1350 
procedure PROC_TX_TYPE1_CONFIGURATION_READ (
1351 
 
1352 
  tag                      : in std_logic_vector (7 downto 0);
1353 
  reg_addr                 : in std_logic_vector (11 downto 0);
1354 
  first_dw_be              : in std_logic_vector (3 downto 0);
1355 
  signal trn_td_c          : out std_logic_vector(63 downto 0);
1356 
  signal trn_tsof_n        : out std_logic;
1357 
  signal trn_teof_n        : out std_logic;
1358 
  signal trn_trem_n_c      : out std_logic_vector(7 downto 0);
1359 
  signal trn_tsrc_rdy_n    : out std_logic;
1360 
  signal trn_lnk_up_n : in std_logic;
1361 
  signal trn_tdst_rdy_n : in std_logic;
1362 
  signal trn_clk : in std_logic
1363 
 
1364 
) is
1365 
 
1366 
begin
1367 
 
1368 
  assert (trn_lnk_up_n = '0')
1369 
    report "TX Trn interface is MIA"
1370 
    severity failure;
1371 
 
1372 
  PROC_TX_SYNCHRONIZE(0, 0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
1373 
 
1374 
  trn_td_c          <= '0' &
1375 
                       "00" &
1376 
                       "00101" &
1377 
                       '0' &
1378 
                       "000" &
1379 
                       "0000" &
1380 
                       '0' &
1381 
                       '0' &
1382 
                       "00" &
1383 
                       "00" &
1384 
                       "0000000001" &
1385 
                       COMPLETER_ID_CFG &
1386 
                       tag(7 downto 0) &
1387 
                       "0000" &
1388 
                       first_dw_be(3 downto 0);
1389 
  trn_tsof_n        <= '0';
1390 
  trn_teof_n        <= '1';
1391 
  trn_trem_n_c      <= X"00";
1392 
  trn_tsrc_rdy_n    <= '0';
1393 
 
1394 
  PROC_TX_SYNCHRONIZE(1,0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
1395 
 
1396 
  trn_td_c          <= COMPLETER_ID_CFG &
1397 
                       "0000" &
1398 
                       reg_addr(11 downto 2) &
1399 
                       "00" &
1400 
                       X"00000000";
1401 
                       trn_tsof_n <= '1';
1402 
                       trn_teof_n <= '0';
1403 
                       trn_trem_n_c <= X"0F";
1404 
                       trn_tsrc_rdy_n <= '0';
1405 
 
1406 
  PROC_TX_SYNCHRONIZE(1, 1, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
1407 
 
1408 
  trn_teof_n        <= '1';
1409 
  trn_trem_n_c      <= X"00";
1410 
  trn_tsrc_rdy_n    <= '1';
1411 
 
1412 
end PROC_TX_TYPE1_CONFIGURATION_READ;
1413 
 
1414 
 
1415 
--************************************************************
1416 
--    Proc : PROC_TX_TYPE1_CONFIGURATION_WRITE
1417 
--    Inputs : Tag, PCI/PCI-Express Reg Address, First BypeEn
1418 
--    Outputs : Transaction Tx Interface Signaling
1419 
--    Description : Generates a Type 1 Configuration Write TLP
1420 
--*************************************************************/
1421 
 
1422 
procedure PROC_TX_TYPE1_CONFIGURATION_WRITE (
1423 
 
1424 
  tag                      : in std_logic_vector (7 downto 0);
1425 
  reg_addr                 : in std_logic_vector (11 downto 0);
1426 
  reg_data                 : in std_logic_vector (31 downto 0);
1427 
  first_dw_be              : in std_logic_vector (3 downto 0);
1428 
  signal trn_td_c          : out std_logic_vector(63 downto 0);
1429 
  signal trn_tsof_n        : out std_logic;
1430 
  signal trn_teof_n        : out std_logic;
1431 
  signal trn_trem_n_c      : out std_logic_vector(7 downto 0);
1432 
  signal trn_tsrc_rdy_n    : out std_logic;
1433 
  signal trn_lnk_up_n : in std_logic;
1434 
  signal trn_tdst_rdy_n : in std_logic;
1435 
  signal trn_clk : in std_logic
1436 
 
1437 
) is
1438 
 
1439 
begin
1440 
 
1441 
  assert (trn_lnk_up_n = '0')
1442 
    report "TX Trn interface is MIA"
1443 
    severity failure;
1444 
 
1445 
  PROC_TX_SYNCHRONIZE(0, 0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
1446 
 
1447 
  trn_td_c          <= '0' &
1448 
                       "10" &
1449 
                       "00101" &
1450 
                       '0' &
1451 
                       "000" &
1452 
                       "0000" &
1453 
                       '0' &
1454 
                       '0' &
1455 
                       "00" &
1456 
                       "00" &
1457 
                       "0000000001" &
1458 
                       COMPLETER_ID_CFG &
1459 
                       tag(7 downto 0) &
1460 
                       "0000" &
1461 
                       first_dw_be(3 downto 0);
1462 
  trn_tsof_n        <= '0';
1463 
  trn_tsrc_rdy_n    <= '0';
1464 
 
1465 
  PROC_TX_SYNCHRONIZE(1,0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
1466 
 
1467 
  trn_td_c          <= COMPLETER_ID_CFG &
1468 
                       "0000" &
1469 
                       reg_addr(11 downto 2) &
1470 
                       "00" &
1471 
                       reg_data(7 downto 0) &
1472 
                       reg_data(15 downto 8) &
1473 
                       reg_data(23 downto 16) &
1474 
                       reg_data(31 downto 24);
1475 
 
1476 
  trn_tsof_n       <= '1';
1477 
  trn_teof_n       <= '0';
1478 
  trn_trem_n_c     <= X"00";
1479 
 
1480 
  PROC_TX_SYNCHRONIZE(1, 1, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
1481 
 
1482 
  trn_teof_n       <= '1';
1483 
  trn_tsrc_rdy_n   <= '1';
1484 
 
1485 
end PROC_TX_TYPE1_CONFIGURATION_WRITE;
1486 
 
1487 
 
1488 
--************************************************************
1489 
--  Procedure : PROC_TX_MEMORY_READ_32
1490 
--  Inputs : Tag, Length, Address, Last Byte En, First Byte En
1491 
--  Outputs : Transaction Tx Interface Signaling
1492 
--  Description : Generates a Memory Read 32 TLP
1493 
--*************************************************************/
1494 
 
1495 
procedure PROC_TX_MEMORY_READ_32 (
1496 
 
1497 
  tag                      : in std_logic_vector (7 downto 0);
1498 
  tc                       : in std_logic_vector (2 downto 0);
1499 
  len                      : in std_logic_vector (9 downto 0);
1500 
  addr                     : in std_logic_vector (31 downto 0);
1501 
  last_dw_be               : in std_logic_vector (3 downto 0);
1502 
  first_dw_be              : in std_logic_vector (3 downto 0);
1503 
  signal trn_td_c          : out std_logic_vector(63 downto 0);
1504 
  signal trn_tsof_n        : out std_logic;
1505 
  signal trn_teof_n        : out std_logic;
1506 
  signal trn_trem_n_c      : out std_logic_vector(7 downto 0);
1507 
  signal trn_tsrc_rdy_n    : out std_logic;
1508 
  signal trn_lnk_up_n : in std_logic;
1509 
  signal trn_tdst_rdy_n : in std_logic;
1510 
  signal trn_clk : in std_logic
1511 
 
1512 
 
1513 
) is
1514 
 
1515 
begin
1516 
 
1517 
  assert (trn_lnk_up_n = '0')
1518 
    report "TX Trn interface is MIA"
1519 
    severity failure;
1520 
 
1521 
 
1522 
  PROC_TX_SYNCHRONIZE(0, 0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
1523 
 
1524 
  trn_td_c <=          '0' &
1525 
                       "00" &
1526 
                       "00000" &
1527 
                       '0' &
1528 
                       tc(2 downto 0) &
1529 
                       "0000" &
1530 
                       '0' &
1531 
                       '0' &
1532 
                       "00" &
1533 
                       "00" &
1534 
                       len(9 downto 0) &
1535 
                       COMPLETER_ID_CFG &
1536 
                       tag(7 downto 0) &
1537 
                       last_dw_be(3 downto 0) &
1538 
                       first_dw_be(3 downto 0);
1539 
  trn_tsof_n        <= '0';
1540 
  trn_teof_n        <= '1';
1541 
  trn_trem_n_c      <= X"00";
1542 
  trn_tsrc_rdy_n    <= '0';
1543 
 
1544 
  PROC_TX_SYNCHRONIZE(1,0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
1545 
 
1546 
  trn_td_c          <= addr(31 downto 2) &
1547 
                       "00" &
1548 
                       X"00000000";
1549 
  trn_tsof_n        <= '1';
1550 
  trn_teof_n        <= '0';
1551 
  trn_trem_n_c      <= X"0F";
1552 
  trn_tsrc_rdy_n    <= '0';
1553 
 
1554 
  PROC_TX_SYNCHRONIZE(1, 1, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
1555 
 
1556 
  trn_teof_n        <= '1';
1557 
  trn_trem_n_c      <= X"00";
1558 
  trn_tsrc_rdy_n    <= '1';
1559 
 
1560 
end PROC_TX_MEMORY_READ_32;
1561 
 
1562 
 
1563 
--************************************************************
1564 
--  Proc : PROC_TX_MEMORY_READ_64
1565 
--  Inputs : Tag, Length, Address, Last Byte En, First Byte En
1566 
--  Outputs : Transaction Tx Interface Signaling
1567 
--  Description : Generates a Memory Read 64 TLP
1568 
--*************************************************************/
1569 
 
1570 
procedure PROC_TX_MEMORY_READ_64 (
1571 
 
1572 
  tag                      : in std_logic_vector (7 downto 0);
1573 
  tc                       : in std_logic_vector (2 downto 0);
1574 
  len                      : in std_logic_vector (9 downto 0);
1575 
  addr                     : in std_logic_vector (63 downto 0);
1576 
  last_dw_be               : in std_logic_vector (3 downto 0);
1577 
  first_dw_be              : in std_logic_vector (3 downto 0);
1578 
  signal trn_td_c          : out std_logic_vector(63 downto 0);
1579 
  signal trn_tsof_n        : out std_logic;
1580 
  signal trn_teof_n        : out std_logic;
1581 
  signal trn_trem_n_c      : out std_logic_vector(7 downto 0);
1582 
  signal trn_tsrc_rdy_n    : out std_logic;
1583 
  signal trn_lnk_up_n : in std_logic;
1584 
  signal trn_tdst_rdy_n : in std_logic;
1585 
  signal trn_clk : in std_logic
1586 
 
1587 
 
1588 
) is
1589 
 
1590 
begin
1591 
 
1592 
  assert (trn_lnk_up_n = '0')
1593 
    report "TX Trn interface is MIA"
1594 
    severity failure;
1595 
 
1596 
 
1597 
  PROC_TX_SYNCHRONIZE(0, 0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
1598 
 
1599 
  trn_td_c <=          '0' &
1600 
                       "01" &
1601 
                       "00000" &
1602 
                       '0' &
1603 
                       tc(2 downto 0) &
1604 
                       "0000" &
1605 
                       '0' &
1606 
                       '0' &
1607 
                       "00" &
1608 
                       "00" &
1609 
                       len(9 downto 0) &
1610 
                       COMPLETER_ID_CFG &
1611 
                       tag(7 downto 0) &
1612 
                       last_dw_be(3 downto 0) &
1613 
                       first_dw_be(3 downto 0);
1614 
  trn_tsof_n        <= '0';
1615 
  trn_teof_n        <= '1';
1616 
  trn_trem_n_c      <= X"00";
1617 
  trn_tsrc_rdy_n    <= '0';
1618 
 
1619 
  PROC_TX_SYNCHRONIZE(1,0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
1620 
 
1621 
  trn_td_c          <= addr(63 downto 2) &
1622 
                       "00";
1623 
  trn_tsof_n        <= '1';
1624 
  trn_teof_n        <= '0';
1625 
  trn_trem_n_c      <= X"00";
1626 
  trn_tsrc_rdy_n    <= '0';
1627 
 
1628 
  PROC_TX_SYNCHRONIZE(1, 1, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
1629 
 
1630 
  trn_teof_n        <= '1';
1631 
  trn_trem_n_c      <= X"00";
1632 
  trn_tsrc_rdy_n    <= '1';
1633 
 
1634 
end PROC_TX_MEMORY_READ_64;
1635 
 
1636 
 
1637 
--************************************************************
1638 
--    Proc : PROC_TX_MEMORY_WRITE_32
1639 
--    Inputs : Tag, Length, Address, Last Byte En, First Byte En
1640 
--    Outputs : Transaction Tx Interface Signaling
1641 
--    Description : Generates a Memory Write 32 TLP
1642 
--*************************************************************/
1643 
 
1644 
procedure PROC_TX_MEMORY_WRITE_32 (
1645 
 
1646 
  tag                         : in std_logic_vector (7 downto 0);
1647 
  tc                          : in std_logic_vector (2 downto 0);
1648 
  len                         : in std_logic_vector (9 downto 0);
1649 
  addr                        : in std_logic_vector (31 downto 0);
1650 
  last_dw_be                  : in std_logic_vector (3 downto 0);
1651 
  first_dw_be                 : in std_logic_vector (3 downto 0);
1652 
  ep                          : in std_logic;
1653 
  signal trn_td_c             : out std_logic_vector(63 downto 0);
1654 
  signal trn_tsof_n           : out std_logic;
1655 
  signal trn_teof_n           : out std_logic;
1656 
  signal trn_trem_n_c         : out std_logic_vector(7 downto 0);
1657 
  signal trn_tsrc_rdy_n       : out std_logic;
1658 
  signal trn_terrfwd_n        : out std_logic;
1659 
  signal trn_lnk_up_n : in std_logic;
1660 
  signal trn_tdst_rdy_n : in std_logic;
1661 
  signal trn_clk : in std_logic
1662 
 
1663 
 
1664 
) is
1665 
 
1666 
  variable length             : std_logic_vector(9 downto 0);
1667 
  variable i                  : INTEGER;
1668 
  variable int_length         : INTEGER;
1669 
  variable unsigned_length    : unsigned(9 downto 0);
1670 
 
1671 
begin
1672 
 
1673 
  assert (trn_lnk_up_n = '0')
1674 
    report "TX Trn interface is MIA"
1675 
    severity failure;
1676 
 
1677 
 
1678 
  if (len = "0000000000") then
1679 
 
1680 
    length := "1000000000"; --1024
1681 
 
1682 
  else
1683 
 
1684 
    length := len;
1685 
 
1686 
  end if;
1687 
 
1688 
  PROC_TX_SYNCHRONIZE(0, 0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
1689 
 
1690 
  trn_td_c                <= '0' &
1691 
                             "10" &
1692 
                             "00000" &
1693 
                             '0' &
1694 
                             tc(2 downto 0) &
1695 
                             "0000" &
1696 
                             '0' &
1697 
                             '0' &
1698 
                             "00" &
1699 
                             "00" &
1700 
                             len(9 downto 0) &
1701 
                             COMPLETER_ID_CFG &
1702 
                             tag(7 downto 0) &
1703 
                             last_dw_be(3 downto 0) &
1704 
                             first_dw_be(3 downto 0);
1705 
  trn_tsof_n              <= '0';
1706 
  trn_teof_n              <= '1';
1707 
  trn_trem_n_c            <= X"00";
1708 
  trn_tsrc_rdy_n          <= '0';
1709 
 
1710 
  PROC_TX_SYNCHRONIZE(1,0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
1711 
 
1712 
  trn_td_c                <= addr(31 downto 2) &
1713 
                             "00" &
1714 
                             DATA_STORE(0) &
1715 
                             DATA_STORE(1) &
1716 
                             DATA_STORE(2) &
1717 
                             DATA_STORE(3);
1718 
  trn_tsof_n              <= '1';
1719 
 
1720 
  if (length /= "0000000001") then
1721 
 
1722 
    unsigned_length := unsigned(length);
1723 
    int_length := to_integer( unsigned_length);
1724 
    i := 4;
1725 
    while (i < (int_length * 4)) loop
1726 
 
1727 
      PROC_TX_SYNCHRONIZE(1,0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
1728 
 
1729 
      trn_td_c            <= DATA_STORE(i+0) &
1730 
                             DATA_STORE(i+1) &
1731 
                             DATA_STORE(i+2) &
1732 
                             DATA_STORE(i+3) &
1733 
                             DATA_STORE(i+4) &
1734 
                             DATA_STORE(i+5) &
1735 
                             DATA_STORE(i+6) &
1736 
                             DATA_STORE(i+7);
1737 
 
1738 
      if ((i+7) >= ((int_length*4)-1) ) then
1739 
 
1740 
        trn_teof_n <= '0';
1741 
        if (ep = '1') then
1742 
 
1743 
          trn_terrfwd_n   <= '0';
1744 
 
1745 
        end if;
1746 
        if (((int_length - 1) mod 2) = 0) then
1747 
 
1748 
          trn_trem_n_c    <= X"00";
1749 
 
1750 
        else
1751 
 
1752 
          trn_trem_n_c    <= X"0F";
1753 
 
1754 
        end if;
1755 
 
1756 
      end if;
1757 
 
1758 
      i := i + 8;
1759 
 
1760 
    end loop;
1761 
 
1762 
  else
1763 
 
1764 
    trn_teof_n            <= '0';
1765 
    if (ep = '1') then
1766 
 
1767 
      trn_terrfwd_n       <= '0';
1768 
 
1769 
    end if;
1770 
 
1771 
    trn_trem_n_c          <= X"00";
1772 
 
1773 
  end if;
1774 
 
1775 
  PROC_TX_SYNCHRONIZE(1, 1, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
1776 
 
1777 
  trn_teof_n              <= '1';
1778 
  trn_trem_n_c            <= X"00";
1779 
  trn_terrfwd_n           <= '1';
1780 
  trn_tsrc_rdy_n          <= '1';
1781 
 
1782 
 
1783 
end PROC_TX_MEMORY_WRITE_32;
1784 
 
1785 
 
1786 
 
1787 
--************************************************************
1788 
--  Proc : PROC_TX_MEMORY_WRITE_64
1789 
--  Inputs : Tag, Length, Address, Last Byte En, First Byte En
1790 
--  Outputs : Transaction Tx Interface Signaling
1791 
--  Description : Generates a Memory Write 64 TLP
1792 
--*************************************************************/
1793 
 
1794 
procedure PROC_TX_MEMORY_WRITE_64 (
1795 
 
1796 
  tag                         : in std_logic_vector (7 downto 0);
1797 
  tc                          : in std_logic_vector (2 downto 0);
1798 
  len                         : in std_logic_vector (9 downto 0);
1799 
  addr                        : in std_logic_vector (63 downto 0);
1800 
  last_dw_be                  : in std_logic_vector (3 downto 0);
1801 
  first_dw_be                 : in std_logic_vector (3 downto 0);
1802 
  ep                          : in std_logic;
1803 
  signal trn_td_c             : out std_logic_vector(63 downto 0);
1804 
  signal trn_tsof_n           : out std_logic;
1805 
  signal trn_teof_n           : out std_logic;
1806 
  signal trn_trem_n_c         : out std_logic_vector(7 downto 0);
1807 
  signal trn_tsrc_rdy_n       : out std_logic;
1808 
  signal trn_terrfwd_n        : out std_logic;
1809 
  signal trn_lnk_up_n : in std_logic;
1810 
  signal trn_tdst_rdy_n : in std_logic;
1811 
  signal trn_clk : in std_logic
1812 
 
1813 
 
1814 
) is
1815 
 
1816 
  variable length             : std_logic_vector(9 downto 0);
1817 
  variable i                  : INTEGER;
1818 
  variable int_length         : INTEGER;
1819 
  variable unsigned_length    : unsigned(9 downto 0);
1820 
 
1821 
begin
1822 
 
1823 
  assert (trn_lnk_up_n = '0')
1824 
    report "TX Trn interface is MIA"
1825 
    severity failure;
1826 
 
1827 
 
1828 
  if (len = "0000000000") then
1829 
 
1830 
    length := "1000000000"; --1024
1831 
 
1832 
  else
1833 
 
1834 
    length := len;
1835 
 
1836 
  end if;
1837 
 
1838 
  PROC_TX_SYNCHRONIZE(0, 0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
1839 
 
1840 
  trn_td_c               <= '0' &
1841 
                            "11" &
1842 
                            "00000" &
1843 
                            '0' &
1844 
                            tc(2 downto 0) &
1845 
                            "0000" &
1846 
                            '0' &
1847 
                            '0' &
1848 
                            "00" &
1849 
                            "00" &
1850 
                            len(9 downto 0) &
1851 
                            COMPLETER_ID_CFG &
1852 
                            tag(7 downto 0) &
1853 
                            last_dw_be(3 downto 0) &
1854 
                            first_dw_be(3 downto 0);
1855 
  trn_tsof_n             <= '0';
1856 
  trn_teof_n             <= '1';
1857 
  trn_trem_n_c           <= X"00";
1858 
  trn_tsrc_rdy_n         <= '0';
1859 
 
1860 
  PROC_TX_SYNCHRONIZE(1,0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
1861 
 
1862 
  trn_td_c               <= addr(63 downto 2) &
1863 
                            "00" ;
1864 
  trn_tsof_n             <= '1';
1865 
 
1866 
  unsigned_length := unsigned(length);
1867 
  int_length := to_integer( unsigned_length);
1868 
  if (int_length = 1) then
1869 
 
1870 
    DATA_STORE(4) := X"00";
1871 
    DATA_STORE(5) := X"00";
1872 
    DATA_STORE(6) := X"00";
1873 
    DATA_STORE(7) := X"00";
1874 
 
1875 
  end if;
1876 
  i := 0;
1877 
  while (i < (int_length * 4)) loop
1878 
 
1879 
    PROC_TX_SYNCHRONIZE(1,0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
1880 
 
1881 
    trn_td_c             <= DATA_STORE(i+0) &
1882 
                            DATA_STORE(i+1) &
1883 
                            DATA_STORE(i+2) &
1884 
                            DATA_STORE(i+3) &
1885 
                            DATA_STORE(i+4) &
1886 
                            DATA_STORE(i+5) &
1887 
                            DATA_STORE(i+6) &
1888 
                            DATA_STORE(i+7);
1889 
 
1890 
    if ((i+7) >= ((int_length*4)-1) ) then
1891 
 
1892 
      trn_teof_n <= '0';
1893 
      if (ep = '1') then
1894 
 
1895 
        trn_terrfwd_n    <= '0';
1896 
 
1897 
      end if;
1898 
      if ((int_length mod 2) = 0) then
1899 
 
1900 
        trn_trem_n_c     <= X"00";
1901 
 
1902 
      else
1903 
 
1904 
        trn_trem_n_c     <= X"0F";
1905 
 
1906 
      end if;
1907 
 
1908 
    end if;
1909 
 
1910 
    i := i + 8;
1911 
 
1912 
  end loop;
1913 
 
1914 
  PROC_TX_SYNCHRONIZE(1, 1, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
1915 
 
1916 
  trn_teof_n             <= '1';
1917 
  trn_terrfwd_n          <= '1';
1918 
  trn_trem_n_c           <= X"00";
1919 
  trn_tsrc_rdy_n         <= '1';
1920 
 
1921 
 
1922 
end PROC_TX_MEMORY_WRITE_64;
1923 
 
1924 
 
1925 
--************************************************************
1926 
--  Proc : PROC_TX_COMPLETION_
1927 
--  Inputs : Tag, Tc, Length, Completion Status
1928 
--  Outputs : Transaction Tx Interface Signaling
1929 
--  Description : Generates a Completion TLP
1930 
--*************************************************************/
1931 
 
1932 
 
1933 
procedure PROC_TX_COMPLETION (
1934 
 
1935 
  tag                      : in std_logic_vector (7 downto 0);
1936 
  tc                       : in std_logic_vector (2 downto 0);
1937 
  len                      : in std_logic_vector (9 downto 0);
1938 
  comp_status              : in std_logic_vector (2 downto 0);
1939 
  signal trn_td_c          : out std_logic_vector(63 downto 0);
1940 
  signal trn_tsof_n        : out std_logic;
1941 
  signal trn_teof_n        : out std_logic;
1942 
  signal trn_trem_n_c      : out std_logic_vector(7 downto 0);
1943 
  signal trn_tsrc_rdy_n    : out std_logic;
1944 
  signal trn_lnk_up_n : in std_logic;
1945 
  signal trn_tdst_rdy_n : in std_logic;
1946 
  signal trn_clk : in std_logic
1947 
 
1948 
) is
1949 
 
1950 
begin
1951 
 
1952 
  assert (trn_lnk_up_n = '0')
1953 
  report "TX Trn interface is MIA"
1954 
    severity failure;
1955 
 
1956 
 
1957 
  PROC_TX_SYNCHRONIZE(0, 0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
1958 
 
1959 
  trn_td_c          <= '0' &
1960 
                       "00" &
1961 
                       "01010" &
1962 
                       '0' &
1963 
                       tc(2 downto 0) &
1964 
                       "0000" &
1965 
                       '0' &
1966 
                       '0' &
1967 
                       "00" &
1968 
                       "00" &
1969 
                       len(9 downto 0) &
1970 
                       COMPLETER_ID_CFG &
1971 
                       comp_status(2 downto 0) &
1972 
                       '0' &
1973 
                       X"000";
1974 
  trn_tsof_n        <= '0';
1975 
  trn_teof_n        <= '1';
1976 
  trn_trem_n_c      <= X"00";
1977 
  trn_tsrc_rdy_n    <= '0';
1978 
 
1979 
  PROC_TX_SYNCHRONIZE(1,0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
1980 
 
1981 
  trn_td_c          <= COMPLETER_ID_CFG &
1982 
                       tag(7 downto 0) &
1983 
                       X"00" &
1984 
                       X"00000000";
1985 
  trn_tsof_n        <= '1';
1986 
  trn_teof_n        <= '0';
1987 
  trn_trem_n_c      <= X"0F";
1988 
 
1989 
  PROC_TX_SYNCHRONIZE(1, 1, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
1990 
 
1991 
  trn_teof_n        <= '1';
1992 
  trn_trem_n_c      <= X"00";
1993 
  trn_tsrc_rdy_n    <= '1';
1994 
 
1995 
 
1996 
end PROC_TX_COMPLETION;
1997 
 
1998 
 
1999 
--************************************************************
2000 
--  Proc : PROC_TX_COMPLETION_DATA_
2001 
--  Inputs : Tag, Tc, Length, Completion Status
2002 
--  Outputs : Transaction Tx Interface Signaling
2003 
--  Description : Generates a Completion with Data TLP
2004 
--*************************************************************/
2005 
 
2006 
procedure PROC_TX_COMPLETION_DATA (
2007 
 
2008 
  tag                      : in std_logic_vector (7 downto 0);
2009 
  tc                       : in std_logic_vector (2 downto 0);
2010 
  len                      : in std_logic_vector (9 downto 0);
2011 
  byte_count               : in std_logic_vector (11 downto 0);
2012 
  lower_addr               : in std_logic_vector (6 downto 0);
2013 
  comp_status              : in std_logic_vector (2 downto 0);
2014 
  ep                       : in std_logic;
2015 
  signal trn_td_c          : out std_logic_vector(63 downto 0);
2016 
  signal trn_tsof_n        : out std_logic;
2017 
  signal trn_teof_n        : out std_logic;
2018 
  signal trn_trem_n_c      : out std_logic_vector(7 downto 0);
2019 
  signal trn_tsrc_rdy_n    : out std_logic;
2020 
  signal trn_terrfwd_n     : out std_logic;
2021 
  signal trn_lnk_up_n : in std_logic;
2022 
  signal trn_tdst_rdy_n : in std_logic;
2023 
  signal trn_clk : in std_logic
2024 
 
2025 
) is
2026 
 
2027 
  variable length : std_logic_vector(9 downto 0);
2028 
  variable i : INTEGER;
2029 
  variable int_length : INTEGER;
2030 
  variable unsigned_length : unsigned(9 downto 0);
2031 
 
2032 
begin
2033 
 
2034 
  assert (trn_lnk_up_n = '0')
2035 
  report "TX Trn interface is MIA"
2036 
    severity failure;
2037 
 
2038 
 
2039 
  if (len = "0000000000") then
2040 
 
2041 
    length := "1000000000"; --1024
2042 
 
2043 
  else
2044 
 
2045 
    length := len;
2046 
 
2047 
  end if;
2048 
 
2049 
  PROC_TX_SYNCHRONIZE(0, 0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
2050 
 
2051 
  trn_td_c                 <= '0' &
2052 
                              "10" &
2053 
                              "01010" &
2054 
                              '0' &
2055 
                              tc(2 downto 0) &
2056 
                              "0000" &
2057 
                              '0' &
2058 
                              '0' &
2059 
                              "00" &
2060 
                              "00" &
2061 
                              len(9 downto 0) &
2062 
                              COMPLETER_ID_CFG &
2063 
                              comp_status(2 downto 0) &
2064 
                              '0' &
2065 
                              byte_count(11 downto 0);
2066 
  trn_tsof_n               <= '0';
2067 
  trn_teof_n               <= '1';
2068 
  trn_trem_n_c             <= X"00";
2069 
  trn_tsrc_rdy_n           <= '0';
2070 
 
2071 
  PROC_TX_SYNCHRONIZE(1,0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
2072 
 
2073 
  trn_td_c                 <= COMPLETER_ID_CFG &
2074 
                              tag(7 downto 0) &
2075 
                              '0' &
2076 
                              lower_addr(6 downto 0) &
2077 
                              DATA_STORE(0) &
2078 
                              DATA_STORE(1) &
2079 
                              DATA_STORE(2) &
2080 
                              DATA_STORE(3);
2081 
  trn_tsof_n               <= '1';
2082 
 
2083 
  if (length /= "0000000001") then
2084 
 
2085 
    unsigned_length := unsigned(length);
2086 
    int_length := to_integer( unsigned_length);
2087 
    i := 4;
2088 
    while (i < (int_length * 4)) loop
2089 
 
2090 
      PROC_TX_SYNCHRONIZE(1,0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
2091 
      trn_td_c             <= DATA_STORE(i+0) &
2092 
                              DATA_STORE(i+1) &
2093 
                              DATA_STORE(i+2) &
2094 
                              DATA_STORE(i+3) &
2095 
                              DATA_STORE(i+4) &
2096 
                              DATA_STORE(i+5) &
2097 
                              DATA_STORE(i+6) &
2098 
                              DATA_STORE(i+7);
2099 
 
2100 
      if ((i+7) >= ((int_length*4)-1) ) then
2101 
 
2102 
        trn_teof_n         <= '0';
2103 
        if (ep = '1') then
2104 
 
2105 
          trn_terrfwd_n    <= '0';
2106 
 
2107 
        end if;
2108 
        if (((int_length - 1) mod 2) = 0) then
2109 
 
2110 
          trn_trem_n_c     <= X"00";
2111 
 
2112 
        else
2113 
 
2114 
          trn_trem_n_c     <= X"0F";
2115 
 
2116 
        end if;
2117 
 
2118 
      end if;
2119 
 
2120 
      i := i + 8;
2121 
 
2122 
    end loop;
2123 
 
2124 
  else
2125 
 
2126 
    trn_teof_n <= '0';
2127 
    if (ep = '1') then
2128 
 
2129 
      trn_terrfwd_n        <= '0';
2130 
 
2131 
    end if;
2132 
 
2133 
    trn_trem_n_c           <= X"00";
2134 
 
2135 
  end if;
2136 
 
2137 
  PROC_TX_SYNCHRONIZE(1, 1, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
2138 
 
2139 
  trn_teof_n               <= '1';
2140 
  trn_terrfwd_n            <= '1';
2141 
  trn_trem_n_c             <= X"00";
2142 
  trn_tsrc_rdy_n           <= '1';
2143 
 
2144 
 
2145 
end PROC_TX_COMPLETION_DATA;
2146 
 
2147 
 
2148 
--************************************************************
2149 
--    Proc : PROC_TX_MESSAGE
2150 
--    Inputs : Tag, TC, Address, Message Routing, Message Code
2151 
--    Outputs : Transaction Tx Interface Signaling
2152 
--    Description : Generates a Message TLP
2153 
--*************************************************************/
2154 
 
2155 
procedure PROC_TX_MESSAGE (
2156 
 
2157 
  tag                      : in std_logic_vector (7 downto 0);
2158 
  tc                       : in std_logic_vector (2 downto 0);
2159 
  len                      : in std_logic_vector (9 downto 0);
2160 
  data                     : in std_logic_vector (63 downto 0);
2161 
  message_rtg              : in std_logic_vector (2 downto 0);
2162 
  message_code             : in std_logic_vector (7 downto 0);
2163 
  signal trn_td_c          : out std_logic_vector(63 downto 0);
2164 
  signal trn_tsof_n        : out std_logic;
2165 
  signal trn_teof_n        : out std_logic;
2166 
  signal trn_trem_n_c      : out std_logic_vector(7 downto 0);
2167 
  signal trn_tsrc_rdy_n    : out std_logic;
2168 
  signal trn_lnk_up_n : in std_logic;
2169 
  signal trn_tdst_rdy_n : in std_logic;
2170 
  signal trn_clk : in std_logic
2171 
 
2172 
) is
2173 
 
2174 
begin
2175 
 
2176 
  assert (trn_lnk_up_n = '0')
2177 
    report "TX Trn interface is MIA"
2178 
    severity failure;
2179 
 
2180 
 
2181 
  PROC_TX_SYNCHRONIZE(0, 0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
2182 
 
2183 
  trn_td_c          <= '0' &
2184 
                       "01" &
2185 
                       "10" & message_rtg(2 downto 0) &
2186 
                       '0' &
2187 
                       tc(2 downto 0) &
2188 
                       "0000" &
2189 
                       '0' &
2190 
                       '0' &
2191 
                       "00" &
2192 
                       "00" &
2193 
                       "0000000000" &
2194 
                       COMPLETER_ID_CFG &
2195 
                       tag(7 downto 0) &
2196 
                       message_code(7 downto 0);
2197 
  trn_tsof_n        <= '0';
2198 
  trn_teof_n        <= '1';
2199 
  trn_trem_n_c      <= X"00";
2200 
  trn_tsrc_rdy_n    <= '0';
2201 
 
2202 
  PROC_TX_SYNCHRONIZE(1,0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
2203 
 
2204 
  trn_td_c          <= data;
2205 
  trn_tsof_n        <= '1';
2206 
  trn_teof_n        <= '0';
2207 
  trn_trem_n_c      <= X"00";
2208 
 
2209 
 
2210 
  PROC_TX_SYNCHRONIZE(1, 1, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
2211 
 
2212 
  trn_teof_n        <= '1';
2213 
  trn_trem_n_c      <= X"00";
2214 
  trn_tsrc_rdy_n    <= '1';
2215 
 
2216 
 
2217 
end PROC_TX_MESSAGE;
2218 
 
2219 
 
2220 
 
2221 
--************************************************************
2222 
--    Proc : PROC_TX_MESSAGE_DATA
2223 
--    Inputs : Tag, TC, Address, Message Routing, Message Code
2224 
--    Outputs : Transaction Tx Interface Signaling
2225 
--    Description : Generates a Message Data TLP
2226 
--*************************************************************/
2227 
 
2228 
procedure PROC_TX_MESSAGE_DATA (
2229 
 
2230 
  tag                      : in std_logic_vector (7 downto 0);
2231 
  tc                       : in std_logic_vector (2 downto 0);
2232 
  len                      : in std_logic_vector (9 downto 0);
2233 
  data                     : in std_logic_vector (63 downto 0);
2234 
  message_rtg              : in std_logic_vector (2 downto 0);
2235 
  message_code             : in std_logic_vector (7 downto 0);
2236 
  signal trn_td_c          : out std_logic_vector(63 downto 0);
2237 
  signal trn_tsof_n        : out std_logic;
2238 
  signal trn_teof_n        : out std_logic;
2239 
  signal trn_trem_n_c      : out std_logic_vector(7 downto 0);
2240 
  signal trn_tsrc_rdy_n    : out std_logic;
2241 
  signal trn_lnk_up_n : in std_logic;
2242 
  signal trn_tdst_rdy_n : in std_logic;
2243 
  signal trn_clk : in std_logic
2244 
 
2245 
) is
2246 
 
2247 
  variable length             : std_logic_vector(9 downto 0);
2248 
  variable i                  : INTEGER;
2249 
  variable int_length         : INTEGER;
2250 
  variable unsigned_length    : unsigned(9 downto 0);
2251 
 
2252 
begin
2253 
 
2254 
  assert (trn_lnk_up_n = '0')
2255 
  report "TX Trn interface is MIA"
2256 
    severity failure;
2257 
 
2258 
 
2259 
  if (len = "0000000000") then
2260 
 
2261 
    length := "1000000000"; --1024
2262 
 
2263 
  else
2264 
 
2265 
    length := len;
2266 
 
2267 
  end if;
2268 
 
2269 
  PROC_TX_SYNCHRONIZE(0, 0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
2270 
 
2271 
  trn_td_c              <= '0' &
2272 
                           "11" &
2273 
                           "10" & message_rtg(2 downto 0) &
2274 
                           '0' &
2275 
                           tc(2 downto 0) &
2276 
                           "0000" &
2277 
                           '0' &
2278 
                           '0' &
2279 
                           "00" &
2280 
                           "00" &
2281 
                           length(9 downto 0) &
2282 
                           COMPLETER_ID_CFG &
2283 
                           tag(7 downto 0) &
2284 
                           message_code(7 downto 0);
2285 
 
2286 
  trn_tsof_n            <= '0';
2287 
  trn_teof_n            <= '1';
2288 
  trn_trem_n_c          <= X"00";
2289 
  trn_tsrc_rdy_n        <= '0';
2290 
 
2291 
  PROC_TX_SYNCHRONIZE(1,0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
2292 
 
2293 
  trn_td_c              <= data;
2294 
  trn_tsof_n            <= '1';
2295 
 
2296 
  unsigned_length := unsigned(length);
2297 
  int_length := to_integer( unsigned_length);
2298 
  i := 0;
2299 
  while (i < (int_length * 4)) loop
2300 
 
2301 
    PROC_TX_SYNCHRONIZE(1,0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
2302 
 
2303 
    trn_td_c            <= DATA_STORE(i+0) &
2304 
                           DATA_STORE(i+1) &
2305 
                           DATA_STORE(i+2) &
2306 
                           DATA_STORE(i+3) &
2307 
                           DATA_STORE(i+4) &
2308 
                           DATA_STORE(i+5) &
2309 
                           DATA_STORE(i+6) &
2310 
                           DATA_STORE(i+7);
2311 
 
2312 
    if ((i+7) >= ((int_length*4)-1) ) then
2313 
 
2314 
      trn_teof_n        <= '0';
2315 
      if ((int_length mod 2) = 0) then
2316 
 
2317 
        trn_trem_n_c    <= X"00";
2318 
 
2319 
      else
2320 
 
2321 
        trn_trem_n_c    <= X"0F";
2322 
 
2323 
      end if;
2324 
 
2325 
    end if;
2326 
 
2327 
    i := i + 8;
2328 
 
2329 
  end loop;
2330 
 
2331 
  PROC_TX_SYNCHRONIZE(1, 1, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
2332 
 
2333 
  trn_teof_n            <= '1';
2334 
  trn_trem_n_c          <= X"00";
2335 
  trn_tsrc_rdy_n        <= '1';
2336 
 
2337 
 
2338 
end PROC_TX_MESSAGE_DATA;
2339 
 
2340 
 
2341 
 
2342 
--************************************************************
2343 
--    Proc : PROC_TX_IO_READ
2344 
--    Inputs : Tag, Address
2345 
--    Outputs : Transaction Tx Interface Signaling
2346 
--    Description : Generates a IO Read TLP
2347 
--*************************************************************/
2348 
 
2349 
procedure PROC_TX_IO_READ (
2350 
 
2351 
  tag                      : in std_logic_vector (7 downto 0);
2352 
  addr                     : in std_logic_vector (31 downto 0);
2353 
  first_dw_be              : in std_logic_vector (3 downto 0);
2354 
  signal trn_td_c          : out std_logic_vector(63 downto 0);
2355 
  signal trn_tsof_n        : out std_logic;
2356 
  signal trn_teof_n        : out std_logic;
2357 
  signal trn_trem_n_c      : out std_logic_vector(7 downto 0);
2358 
  signal trn_tsrc_rdy_n    : out std_logic;
2359 
  signal trn_lnk_up_n : in std_logic;
2360 
  signal trn_tdst_rdy_n : in std_logic;
2361 
  signal trn_clk : in std_logic
2362 
 
2363 
) is
2364 
 
2365 
begin
2366 
 
2367 
  assert (trn_lnk_up_n = '0')
2368 
    report "TX Trn interface is MIA"
2369 
    severity failure;
2370 
 
2371 
 
2372 
  PROC_TX_SYNCHRONIZE(0, 0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
2373 
 
2374 
  trn_td_c          <= '0' &
2375 
                       "00" &
2376 
                       "00010" &
2377 
                       '0' &
2378 
                       "000" &
2379 
                       "0000" &
2380 
                       '0' &
2381 
                       '0' &
2382 
                       "00" &
2383 
                       "00" &
2384 
                       "0000000001" &
2385 
                       COMPLETER_ID_CFG &
2386 
                       tag(7 downto 0) &
2387 
                       "0000" &
2388 
                       first_dw_be(3 downto 0);
2389 
  trn_tsof_n        <= '0';
2390 
  trn_teof_n        <= '1';
2391 
  trn_trem_n_c      <= X"00";
2392 
  trn_tsrc_rdy_n    <= '0';
2393 
 
2394 
  PROC_TX_SYNCHRONIZE(1,0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
2395 
 
2396 
  trn_td_c          <= addr(31 downto 2) &
2397 
                      "00" &
2398 
                       X"00000000";
2399 
  trn_tsof_n        <= '1';
2400 
  trn_teof_n        <= '0';
2401 
  trn_trem_n_c      <= X"0F";
2402 
  trn_tsrc_rdy_n    <= '0';
2403 
 
2404 
  PROC_TX_SYNCHRONIZE(1, 1, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
2405 
 
2406 
  trn_teof_n        <= '1';
2407 
  trn_trem_n_c      <= X"00";
2408 
  trn_tsrc_rdy_n    <= '1';
2409 
 
2410 
end PROC_TX_IO_READ;
2411 
 
2412 
 
2413 
--************************************************************
2414 
--    Proc : PROC_TX_IO_WRITE
2415 
--    Inputs : Tag, Address, Data
2416 
--    Outputs : Transaction Tx Interface Signaling
2417 
--    Description : Generates a IO Read TLP
2418 
--*************************************************************/
2419 
 
2420 
procedure PROC_TX_IO_WRITE (
2421 
 
2422 
  tag                      : in std_logic_vector (7 downto 0);
2423 
  addr                     : in std_logic_vector (31 downto 0);
2424 
  first_dw_be              : in std_logic_vector (3 downto 0);
2425 
  data                     : in std_logic_vector(31 downto 0);
2426 
  signal trn_td_c          : out std_logic_vector(63 downto 0);
2427 
  signal trn_tsof_n        : out std_logic;
2428 
  signal trn_teof_n        : out std_logic;
2429 
  signal trn_trem_n_c      : out std_logic_vector(7 downto 0);
2430 
  signal trn_tsrc_rdy_n    : out std_logic;
2431 
  signal trn_lnk_up_n : in std_logic;
2432 
  signal trn_tdst_rdy_n : in std_logic;
2433 
  signal trn_clk : in std_logic
2434 
 
2435 
) is
2436 
 
2437 
begin
2438 
 
2439 
  assert (trn_lnk_up_n = '0')
2440 
    report "TX Trn interface is MIA"
2441 
    severity failure;
2442 
 
2443 
 
2444 
  PROC_TX_SYNCHRONIZE(0, 0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
2445 
 
2446 
  trn_td_c          <= '0' &
2447 
                       "10" &
2448 
                       "00010" &
2449 
                       '0' &
2450 
                       "000" &
2451 
                       "0000" &
2452 
                       '0' &
2453 
                       '0' &
2454 
                       "00" &
2455 
                       "00" &
2456 
                       "0000000001" &
2457 
                       COMPLETER_ID_CFG &
2458 
                       tag(7 downto 0) &
2459 
                       "0000" &
2460 
                       first_dw_be(3 downto 0);
2461 
  trn_tsof_n        <= '0';
2462 
  trn_teof_n        <= '1';
2463 
  trn_trem_n_c      <= X"00";
2464 
  trn_tsrc_rdy_n    <= '0';
2465 
 
2466 
  PROC_TX_SYNCHRONIZE(1,0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
2467 
 
2468 
  trn_td_c          <= addr(31 downto 2) &
2469 
                       "00" &
2470 
                       data(7 downto 0) &
2471 
                       data(15 downto 8) &
2472 
                       data(23 downto 16) &
2473 
                       data(31 downto 24);
2474 
  trn_tsof_n        <= '1';
2475 
  trn_teof_n        <= '0';
2476 
  trn_trem_n_c      <= X"00";
2477 
 
2478 
  PROC_TX_SYNCHRONIZE(1, 1, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
2479 
 
2480 
  trn_teof_n        <= '1';
2481 
  trn_trem_n_c      <= X"00";
2482 
  trn_tsrc_rdy_n    <= '1';
2483 
 
2484 
 
2485 
end PROC_TX_IO_WRITE;
2486 
 
2487 
 
2488 
--************************************************************
2489 
--    Proc : PROC_USR_DATA_SETUP_SEQ
2490 
--    Inputs : None
2491 
--    Outputs : None
2492 
--    Description : Populates scratch pad data area with known good data.
2493 
--*************************************************************/
2494 
 
2495 
procedure PROC_USR_DATA_SETUP_SEQ is
2496 
 
2497 
  variable i             : INTEGER;
2498 
  variable unsigned_i    : unsigned(7 downto 0);
2499 
  variable vector_i      : std_logic_vector(7 downto 0);
2500 
 
2501 
begin
2502 
 
2503 
  for i in 0 to 4095 loop
2504 
 
2505 
    unsigned_i := to_unsigned(i, 8);
2506 
    vector_i := std_logic_vector(unsigned_i);
2507 
    DATA_STORE(i) := vector_i(7 downto 0);
2508 
 
2509 
  end loop;
2510 
 
2511 
end PROC_USR_DATA_SETUP_SEQ;
2512 
 
2513 
 
2514 
--************************************************************
2515 
--    Proc : PROC_SET_READ_DATA
2516 
--    Inputs : Data
2517 
--    Outputs : None
2518 
--    Description : Set read data to known value
2519 
--*************************************************************/
2520 
 
2521 
procedure PROC_SET_READ_DATA  (
2522 
 
2523 
  be     : in std_logic_vector(3 downto 0);
2524 
  data   : in std_logic_vector(31 downto 0)
2525 
 
2526 
) is
2527 
 
2528 
begin
2529 
 
2530 
  P_READ_DATA := data;
2531 
 
2532 
end PROC_SET_READ_DATA;
2533 
 
2534 
 
2535 
 
2536 
--************************************************************
2537 
--    Proc : PROC_WAIT_FOR_READ_DATA
2538 
--    Inputs : None
2539 
--    Outputs : Read data P_READ_DATA will be valid
2540 
--    Description : This task must be executed
2541 
--                  immediately following a read call
2542 
--                  in order for the read process to function
2543 
--                  correctly.
2544 
--*************************************************************/
2545 
 
2546 
procedure PROC_WAIT_FOR_READ_DATA  (
2547 
 
2548 
  signal tx_rx_read_data_valid    : out std_logic;
2549 
  signal rx_tx_read_data_valid    : in std_logic;
2550 
  signal rx_tx_read_data : in std_logic_vector(31 downto 0);
2551 
  signal trn_clk : in std_logic
2552 
 
2553 
) is
2554 
 
2555 
  variable j : INTEGER;
2556 
 
2557 
begin
2558 
 
2559 
  j := 10;
2560 
  tx_rx_read_data_valid <= '1';
2561 
  while (rx_tx_read_data_valid = '0') loop
2562 
 
2563 
    wait until (trn_clk'event and trn_clk = '1');
2564 
 
2565 
  end loop;
2566 
  P_READ_DATA := rx_tx_read_data;
2567 
  tx_rx_read_data_valid <= '0'; -- indicate to rx_app to make rx_tx_valid = 0
2568 
  wait until rx_tx_read_data_valid = '0';
2569 
 
2570 
end PROC_WAIT_FOR_READ_DATA;
2571 
 
2572 
 
2573 
--***********************************************************
2574 
--      Procedure : PROC_DISPLAY_PCIE_MAP
2575 
--      Inputs : none
2576 
--      Outputs : none
2577 
--      Description : Displays the Memory Manager's P_MAP calculations
2578 
--                    based on range values read from PCI_E device.
2579 
--*************************************************************/
2580 
 
2581 
procedure PROC_DISPLAY_PCIE_MAP  (
2582 
 
2583 
  BAR            : THIRTY_THREE_BIT_ARRAY;
2584 
  BAR_ENABLED    : ENABLE_ARRAY;
2585 
  BAR_RANGE      : DWORD_ARRAY
2586 
 
2587 
) is
2588 
 
2589 
  variable i              : INTEGER;
2590 
  variable L              : line;
2591 
  variable func_result    : std_logic_vector(31 downto 0);
2592 
 
2593 
begin
2594 
 
2595 
  for i in 0 to 6 loop
2596 
 
2597 
    write (L, String'("            BAR "));
2598 
    hwrite(L, std_logic_vector(to_unsigned(i, 4)));
2599 
    write (L, String'(" = 0x"));
2600 
    hwrite(L, BAR(i)(31 downto 0));
2601 
    write (L, String'(" RANGE = 0x"));
2602 
    hwrite(L, BAR_RANGE(i)(31 downto 0));
2603 
 
2604 
    case BAR_ENABLED(i) is
2605 
 
2606 
      when 1 => write (L, String'(" IO MAPPED"));
2607 
 
2608 
      when 2 => write (L, String'(" MEM32 MAPPED"));
2609 
 
2610 
      when 3 => write (L, String'(" MEM64 MAPPED"));
2611 
 
2612 
      when others => write (L, String'(" DISABLED"));
2613 
 
2614 
    end case;
2615 
    writeline (output, L);
2616 
 
2617 
  end loop;
2618 
 
2619 
end PROC_DISPLAY_PCIE_MAP;
2620 
 
2621 
 
2622 
 
2623 
--*************************************************************
2624 
--      Procedure : PROC_BUILD_PCIE_MAP
2625 
--      Inputs :
2626 
--      Outputs :
2627 
--      Description : Looks at range values read from config space and
2628 
--                    builds corresponding mem/io map
2629 
--*************************************************************/
2630 
 
2631 
procedure PROC_BUILD_PCIE_MAP
2632 
 
2633 
is
2634 
 
2635 
  variable i    : INTEGER;
2636 
  variable L    : line;
2637 
  variable RANGE_VALUE : std_logic_vector(31 downto 0);
2638 
 
2639 
begin
2640 
 
2641 
  writeNowToScreen(String'("PCI EXPRESS BAR MEMORY/IO MAPPING PROCESS BEGUN.."));
2642 
 
2643 
  BAR(0) := '0' & X"10000000";
2644 
  BAR(1) := '0' & X"20000000";
2645 
  BAR(2) := '0' & X"30000000";
2646 
  BAR(3) := '0' & X"40000000";
2647 
  BAR(4) := '0' & X"50000000";
2648 
  BAR(5) := '0' & X"60000000";
2649 
  BAR(6) := '0' & X"70000001";  -- bit 0 must be set to enable the EROM
2650 
 
2651 
 
2652 
  i := 0;
2653 
  while (i <= 6) loop
2654 
 
2655 
    RANGE_VALUE := BAR_RANGE(i);
2656 
 
2657 
    if (RANGE_VALUE = X"00000000") then
2658 
 
2659 
      BAR_ENABLED(i) := 0; -- Disabled
2660 
      BAR(i) := '0' & X"00000000";
2661 
 
2662 
    else
2663 
 
2664 
      if ((RANGE_VALUE(0) = '1') and (i /= 6)) then
2665 
 
2666 
        BAR_ENABLED(i) := 1; -- IO
2667 
        NUMBER_OF_IO_BARS := NUMBER_OF_IO_BARS + 1;
2668 
--        if (pio_check_design and (NUMBER_OF_IO_BARS >1)) then
2669 
--          write (L, String'("Warning: PIO design only supports 1 IO BAR. Testbench will disable BAR"));
2670 
--          hwrite(L, std_logic_vector(to_unsigned(i, 4)));
2671 
--          writeline (output, L);
2672 
--          BAR_ENABLED(i) := 0; -- Disabled
2673 
--        end if;
2674 
 
2675 
      else
2676 
 
2677 
        if (RANGE_VALUE(2) = '1') then
2678 
 
2679 
          BAR_ENABLED(i) := 3; -- Mem64
2680 
          BAR_ENABLED(i+1) := 0; -- Mem64 uses upper BAR so set as disabled
2681 
 
2682 
          NUMBER_OF_MEM64_BARS := NUMBER_OF_MEM64_BARS + 1;
2683 
          if (pio_check_design and (NUMBER_OF_MEM64_BARS >1)) then
2684 
            write (L, String'("Warning: PIO design only supports 1 MEM64 BAR. Testbench will disable BAR"));
2685 
            hwrite(L, std_logic_vector(to_unsigned(i, 4)));
2686 
            writeline (output, L);
2687 
            BAR_ENABLED(i) := 0; -- Disabled
2688 
          end if;
2689 
          i := i + 1;
2690 
 
2691 
        else
2692 
 
2693 
 
2694 
          if (i /= 6) then NUMBER_OF_MEM32_BARS := NUMBER_OF_MEM32_BARS + 1;
2695 
          end if;
2696 
          BAR_ENABLED(i) := 2; -- Mem32
2697 
--          if (pio_check_design and (NUMBER_OF_MEM32_BARS >1)) then
2698 
--            write (L, String'("Warning: PIO design only supports 1 MEM32 BAR. Testbench will disable BAR"));
2699 
--            hwrite(L, std_logic_vector(to_unsigned(i, 4)));
2700 
--            writeline (output, L);
2701 
--            BAR_ENABLED(i) := 0; -- Disabled
2702 
--          end if;
2703 
 
2704 
 
2705 
        end if;
2706 
 
2707 
      end if;
2708 
 
2709 
    end if;
2710 
 
2711 
    i := i + 1;
2712 
 
2713 
  end loop;
2714 
 
2715 
end PROC_BUILD_PCIE_MAP;
2716 
 
2717 
 
2718 
--***********************************************************
2719 
--        Proc : PROC_BAR_SCAN
2720 
--        Inputs : None
2721 
--        Outputs : None
2722 
--        Description : Scans PCI core's configuration registers.
2723 
--*************************************************************/
2724 
 
2725 
procedure PROC_BAR_SCAN  (
2726 
 
2727 
  signal tx_rx_read_data_valid : out std_logic;
2728 
  signal rx_tx_read_data_valid : in std_logic;
2729 
  signal rx_tx_read_data : in std_logic_vector (31 downto 0);
2730 
  signal trn_td_c : out std_logic_vector(63 downto 0);
2731 
  signal trn_tsof_n : out std_logic;
2732 
  signal trn_teof_n : out std_logic;
2733 
  signal trn_trem_n_c : out std_logic_vector(7 downto 0);
2734 
  signal trn_tsrc_rdy_n : out std_logic;
2735 
  signal trn_lnk_up_n : in std_logic;
2736 
  signal trn_tdst_rdy_n : in std_logic;
2737 
  signal trn_clk : in std_logic
2738 
 
2739 
) is
2740 
 
2741 
  variable P_ADDRESS_MASK : std_logic_vector((32 - 1) downto 0);
2742 
  variable L : line;
2743 
  variable DEFAULT_TAG : std_logic_vector(( 8 - 1) downto 0);
2744 
 
2745 
begin
2746 
 
2747 
 
2748 
-- TRN MODEL Initialization
2749 
  BAR_RANGE(0) := X"FFE00000";
2750 
  BAR_RANGE(1) := X"FFE00000";
2751 
  BAR_RANGE(2) := X"00000000";
2752 
  BAR_RANGE(3) := X"00000000";
2753 
  BAR_RANGE(4) := X"00000000";
2754 
  BAR_RANGE(5) := X"00000000";
2755 
  BAR_RANGE(6) := X"00000000";
2756 
 
2757 
 
2758 
end PROC_BAR_SCAN;
2759 
 
2760 
 
2761 
--************************************************************
2762 
--       Procedure : PROC_BAR_PROGRAM
2763 
--       Inputs : None
2764 
--       Outputs : None
2765 
--       Description : Program's PCI core's configuration registers.
2766 
-- ************************************************************/
2767 
 
2768 
procedure PROC_BAR_PROGRAM  (
2769 
 
2770 
  signal trn_td_c          : out std_logic_vector(63 downto 0);
2771 
  signal trn_tsof_n        : out std_logic;
2772 
  signal trn_teof_n        : out std_logic;
2773 
  signal trn_trem_n_c      : out std_logic_vector(7 downto 0);
2774 
  signal trn_tsrc_rdy_n    : out std_logic;
2775 
  signal trn_lnk_up_n : in std_logic;
2776 
  signal trn_tdst_rdy_n : in std_logic;
2777 
  signal trn_clk : in std_logic
2778 
 
2779 
) is
2780 
 
2781 
  variable L : line;
2782 
  variable DEFAULT_TAG : std_logic_vector(( 8 - 1) downto 0);
2783 
 
2784 
begin
2785 
 
2786 
  DEFAULT_TAG := X"0f";
2787 
 
2788 
  write (L, String'("[ ")); write (L, now);
2789 
  write (L, String'(" ] : Setting Core Configuration Space..."));
2790 
  writeline (output, L);
2791 
  PROC_TX_CLK_EAT(3000, trn_clk);
2792 
 
2793 
-- Program BAR0
2794 
 
2795 
  PROC_TX_TYPE0_CONFIGURATION_WRITE (
2796 
    DEFAULT_TAG, --tag :in std_logic_vector (7 downto 0);
2797 
    X"010",  --reg_addr 12'h10
2798 
    BAR(0)(31 downto 0), --reg_data : in std_logic_vector (31 downto 0);
2799 
    X"F", --first_dw_be : in std_logic_vector (3 downto 0);
2800 
    trn_td_c, trn_tsof_n,trn_teof_n,trn_trem_n_c, trn_tsrc_rdy_n, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
2801 
  DEFAULT_TAG := X"10";
2802 
  PROC_TX_CLK_EAT(100, trn_clk);
2803 
 
2804 
-- Program BAR1
2805 
 
2806 
  PROC_TX_TYPE0_CONFIGURATION_WRITE (
2807 
    DEFAULT_TAG, --tag :in std_logic_vector (7 downto 0);
2808 
    X"014", --reg_addr 12'h14
2809 
    BAR(1)(31 downto 0), --reg_data : in std_logic_vector (31 downto 0);
2810 
    X"F", --first_dw_be : in std_logic_vector (3 downto 0);
2811 
    trn_td_c, trn_tsof_n,trn_teof_n,trn_trem_n_c, trn_tsrc_rdy_n, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
2812 
  DEFAULT_TAG := X"11";
2813 
  PROC_TX_CLK_EAT(100, trn_clk);
2814 
 
2815 
-- Program BAR2
2816 
 
2817 
  PROC_TX_TYPE0_CONFIGURATION_WRITE (
2818 
    DEFAULT_TAG, --tag :in std_logic_vector (7 downto 0);
2819 
    X"018", --reg_addr 12'h18
2820 
    BAR(2)(31 downto 0), --reg_data : in std_logic_vector (31 downto 0);
2821 
    X"F", --first_dw_be : in std_logic_vector (3 downto 0);
2822 
    trn_td_c, trn_tsof_n,trn_teof_n,trn_trem_n_c, trn_tsrc_rdy_n, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
2823 
  DEFAULT_TAG := X"12";
2824 
  PROC_TX_CLK_EAT(100, trn_clk);
2825 
 
2826 
-- Program BAR3
2827 
 
2828 
  PROC_TX_TYPE0_CONFIGURATION_WRITE (
2829 
    DEFAULT_TAG, --tag :in std_logic_vector (7 downto 0);
2830 
    X"01C", --reg_addr 12'h1C
2831 
    BAR(3)(31 downto 0), --reg_data : in std_logic_vector (31 downto 0);
2832 
    X"F", --first_dw_be : in std_logic_vector (3 downto 0);
2833 
    trn_td_c, trn_tsof_n,trn_teof_n,trn_trem_n_c, trn_tsrc_rdy_n, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
2834 
  DEFAULT_TAG := X"13";
2835 
  PROC_TX_CLK_EAT(100, trn_clk);
2836 
 
2837 
-- Program BAR4
2838 
 
2839 
  PROC_TX_TYPE0_CONFIGURATION_WRITE (
2840 
    DEFAULT_TAG, --tag :in std_logic_vector (7 downto 0);
2841 
    X"020", --reg_addr 12'h20
2842 
    BAR(4)(31 downto 0), --reg_data : in std_logic_vector (31 downto 0);
2843 
    X"F", --first_dw_be : in std_logic_vector (3 downto 0);
2844 
    trn_td_c, trn_tsof_n,trn_teof_n,trn_trem_n_c, trn_tsrc_rdy_n, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
2845 
  DEFAULT_TAG := X"14";
2846 
  PROC_TX_CLK_EAT(100, trn_clk);
2847 
 
2848 
-- Program BAR5
2849 
 
2850 
  PROC_TX_TYPE0_CONFIGURATION_WRITE (
2851 
    DEFAULT_TAG, --tag :in std_logic_vector (7 downto 0);
2852 
    X"024", --reg_addr 12'h24
2853 
    BAR(5)(31 downto 0), --reg_data : in std_logic_vector (31 downto 0);
2854 
    X"F", --first_dw_be : in std_logic_vector (3 downto 0);
2855 
    trn_td_c, trn_tsof_n,trn_teof_n,trn_trem_n_c, trn_tsrc_rdy_n, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
2856 
  DEFAULT_TAG := X"15";
2857 
  PROC_TX_CLK_EAT(100, trn_clk);
2858 
 
2859 
-- Program Expansion ROM BAR
2860 
 
2861 
  PROC_TX_TYPE0_CONFIGURATION_WRITE (
2862 
    DEFAULT_TAG, --tag :in std_logic_vector (7 downto 0);
2863 
    X"030", --reg_addr 12'h30
2864 
    BAR(6)(31 downto 0), --reg_data : in std_logic_vector (31 downto 0);
2865 
    X"F", --first_dw_be : in std_logic_vector (3 downto 0);
2866 
    trn_td_c, trn_tsof_n,trn_teof_n,trn_trem_n_c, trn_tsrc_rdy_n, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
2867 
  DEFAULT_TAG := X"16";
2868 
  PROC_TX_CLK_EAT(100, trn_clk);
2869 
 
2870 
 
2871 
-- Program PCI Command Register
2872 
 
2873 
  PROC_TX_TYPE0_CONFIGURATION_WRITE (
2874 
    DEFAULT_TAG, --tag :in std_logic_vector (7 downto 0);
2875 
    X"004", --reg_addr 12'h04
2876 
    X"00000007", --reg_data : in std_logic_vector (31 downto 0);
2877 
    X"1", --first_dw_be : in std_logic_vector (3 downto 0);
2878 
    trn_td_c, trn_tsof_n,trn_teof_n,trn_trem_n_c, trn_tsrc_rdy_n, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
2879 
  DEFAULT_TAG := X"17";
2880 
  PROC_TX_CLK_EAT(100, trn_clk);
2881 
 
2882 
 
2883 
-- Program PCIe Device Control Register
2884 
 
2885 
  PROC_TX_TYPE0_CONFIGURATION_WRITE (
2886 
    DEFAULT_TAG, --tag :in std_logic_vector (7 downto 0);
2887 
    X"068", --reg_addr 12'h68
2888 
    X"0000005F", --reg_data : in std_logic_vector (31 downto 0);
2889 
    X"1", --first_dw_be : in std_logic_vector (3 downto 0);
2890 
    trn_td_c, trn_tsof_n,trn_teof_n,trn_trem_n_c, trn_tsrc_rdy_n, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
2891 
  DEFAULT_TAG := X"18";
2892 
  PROC_TX_CLK_EAT(1000, trn_clk);
2893 
 
2894 
end PROC_BAR_PROGRAM;
2895 
 
2896 
 
2897 
--   ***********************************************************
2898 
--      Procedure : PROC_BAR_INIT
2899 
--      Inputs : None
2900 
--      Outputs : None
2901 
--     Description : Initialize PCI core based on core's configuration.
2902 
--   *************************************************************/
2903 
 
2904 
procedure PROC_BAR_INIT  (
2905 
 
2906 
  signal tx_rx_read_data_valid : out std_logic;
2907 
  signal rx_tx_read_data_valid : in std_logic;
2908 
  signal rx_tx_read_data : in std_logic_vector (31 downto 0);
2909 
  signal trn_td_c : out std_logic_vector(63 downto 0);
2910 
  signal trn_tsof_n : out std_logic;
2911 
  signal trn_teof_n : out std_logic;
2912 
  signal trn_trem_n_c : out std_logic_vector(7 downto 0);
2913 
  signal trn_tsrc_rdy_n : out std_logic;
2914 
  signal trn_lnk_up_n : in std_logic;
2915 
  signal trn_tdst_rdy_n : in std_logic;
2916 
  signal trn_clk : in std_logic
2917 
 
2918 
) is
2919 
 
2920 
begin
2921 
 
2922 
  PROC_BAR_SCAN(tx_rx_read_data_valid, rx_tx_read_data_valid, rx_tx_read_data, trn_td_c, trn_tsof_n,
2923 
                trn_teof_n, trn_trem_n_c, trn_tsrc_rdy_n, trn_lnk_up_n, trn_tdst_rdy_n,trn_clk);
2924 
 
2925 
  PROC_BUILD_PCIE_MAP;
2926 
 
2927 
  PROC_DISPLAY_PCIE_MAP(BAR, BAR_ENABLED, BAR_RANGE );
2928 
 
2929 
  PROC_BAR_PROGRAM( trn_td_c, trn_tsof_n, trn_teof_n,
2930 
                    trn_trem_n_c, trn_tsrc_rdy_n, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
2931 
 
2932 
end PROC_BAR_INIT;
2933 
 
2934 
 
2935 
 
2936 
--************************************************************
2937 
--  Proc : PROC_SYSTEM_INITIALIZATION
2938 
--  Inputs : None
2939 
--  Outputs : None
2940 
--  Description : Waits for Reset to deassert and for Link up.
2941 
--*************************************************************/
2942 
 
2943 
procedure PROC_SYSTEM_INITIALIZATION(
2944 
   signal trn_reset_n: in std_logic;
2945 
   signal trn_lnk_up_n: in std_logic;
2946 
   signal speed_change_done_n : in std_logic )  is
2947 
 
2948 
  variable  L : line;
2949 
 
2950 
begin
2951 
 
2952 
--------------------------------------------------------------------------
2953 
-- Wait for Transaction reset to be de-asserted..
2954 
--------------------------------------------------------------------------
2955 
 
2956 
  wait until trn_reset_n = '1';
2957 
  writeNowToScreen ( String'("Transaction Reset is De-asserted"));
2958 
 
2959 
--------------------------------------------------------------------------
2960 
-- Wait for Transaction link to be asserted..
2961 
--------------------------------------------------------------------------
2962 
 
2963 
  if MAX_LINK_SPEED = 1 then
2964 
       wait until (trn_lnk_up_n = '0');
2965 
  else
2966 
       wait until (trn_lnk_up_n = '0');
2967 
       wait until (speed_change_done_n = '0');
2968 
  end if;
2969 
 
2970 
  writeNowToScreen ( String'("Transaction Link is Up"));
2971 
 
2972 
 
2973 
end PROC_SYSTEM_INITIALIZATION;
2974 
 
2975 
--************************************************************
2976 
--  Proc : PROC_READ_CFG_DW
2977 
--  Inputs : addr - 10-bit address
2978 
--  Outputs : None
2979 
--  Inouts : cfg_rdwr_int - configuration interface signals
2980 
--  Description : Read Configuration Space DW
2981 
--*************************************************************/
2982 
 
2983 
procedure PROC_READ_CFG_DW (
2984 
  addr                 : in    std_logic_vector(9 downto 0);
2985 
  signal cfg_rdwr_int  : inout cfg_rdwr_sigs
2986 
) is
2987 
    variable L : line;
2988 
  begin
2989 
 
2990 
    -- Because cfg_rdwr_int is an inout, we have to tri-state the sub-signals we want to read
2991 
    cfg_rdwr_int.cfg_rd_wr_done_n <= 'Z';
2992 
    cfg_rdwr_int.cfg_do <= (OTHERS => 'Z');
2993 
    cfg_rdwr_int.trn_clk <= 'Z';
2994 
    cfg_rdwr_int.trn_reset_n <= 'Z';
2995 
 
2996 
    assert (cfg_rdwr_int.trn_reset_n = '1')
2997 
    report "TX Reset is asserted"
2998 
    severity failure;
2999 
 
3000 
    if (cfg_rdwr_int.cfg_rd_wr_done_n /= '1') then
3001 
      wait until (rising_edge(cfg_rdwr_int.trn_clk) and cfg_rdwr_int.cfg_rd_wr_done_n = '1');
3002 
    end if;
3003 
 
3004 
    wait until (rising_edge(cfg_rdwr_int.trn_clk));
3005 
    cfg_rdwr_int.cfg_dwaddr <= addr;
3006 
    cfg_rdwr_int.cfg_wr_en_n <= '1';
3007 
    cfg_rdwr_int.cfg_rd_en_n <= '0';
3008 
    writeNowToScreen(String'("Reading Config space"));
3009 
    write (L, String'("  Addr: [0x"));
3010 
    hwrite(L, "00" & addr);
3011 
    write (L, String'("]"));
3012 
    writeline(output, L);
3013 
 
3014 
 
3015 
    wait until (rising_edge(cfg_rdwr_int.trn_clk) and cfg_rdwr_int.cfg_rd_wr_done_n = '0');
3016 
    cfg_rdwr_int.cfg_rd_en_n <= '1';
3017 
    write (L, String'("  Cfg Addr [0x"));
3018 
    hwrite(L, "00" & addr);
3019 
    write (L, String'("] -> Data [0x"));
3020 
    hwrite(L, cfg_rdwr_int.cfg_do);
3021 
    write (L, String'("]"));
3022 
    writeline(output, L);
3023 
 
3024 
  end PROC_READ_CFG_DW;
3025 
 
3026 
--************************************************************
3027 
--  Proc : PROC_WRITE_CFG_DW
3028 
--  Inputs : addr - 10-bit address
3029 
--           data - 32-bit data to write
3030 
--           byte_en_n - 4-bit active-low byte enable
3031 
--  Outputs : None
3032 
--  Inouts : cfg_rdwr_int - configuration interface signals
3033 
--  Description : Write Configuration Space DW
3034 
--*************************************************************/
3035 
 
3036 
procedure PROC_WRITE_CFG_DW (
3037 
  addr                : in    std_logic_vector(9 downto 0);
3038 
  data                : in    std_logic_vector(31 downto 0);
3039 
  byte_en_n           : in    std_logic_vector(3 downto 0);
3040 
  signal cfg_rdwr_int : inout cfg_rdwr_sigs
3041 
) is
3042 
    variable L : line;
3043 
  begin
3044 
 
3045 
    -- Because cfg_rdwr_int is an inout, we have to tri-state the sub-signals we want to read
3046 
    cfg_rdwr_int.cfg_rd_wr_done_n <= 'Z';
3047 
    cfg_rdwr_int.cfg_do <= (OTHERS => 'Z');
3048 
    cfg_rdwr_int.trn_clk <= 'Z';
3049 
    cfg_rdwr_int.trn_reset_n <= 'Z';
3050 
 
3051 
    assert (cfg_rdwr_int.trn_reset_n = '1')
3052 
    report "TX Reset is asserted"
3053 
    severity failure;
3054 
 
3055 
    if (cfg_rdwr_int.cfg_rd_wr_done_n /= '1') then
3056 
      wait until (rising_edge(cfg_rdwr_int.trn_clk) and cfg_rdwr_int.cfg_rd_wr_done_n = '1');
3057 
    end if;
3058 
 
3059 
    wait until (rising_edge(cfg_rdwr_int.trn_clk));
3060 
    cfg_rdwr_int.cfg_dwaddr <= addr;
3061 
    cfg_rdwr_int.cfg_wr_en_n <= '0';
3062 
    cfg_rdwr_int.cfg_rd_en_n <= '1';
3063 
    cfg_rdwr_int.cfg_di <= data;
3064 
    cfg_rdwr_int.cfg_byte_en_n <= byte_en_n;
3065 
    writeNowToScreen(String'("Writing Config space"));
3066 
    write (L, String'("  Addr: [0x"));
3067 
    hwrite(L, "00" & addr);
3068 
    write (L, String'("] -> Data [0x"));
3069 
    hwrite(L, data);
3070 
    write (L, String'("]"));
3071 
    writeline(output, L);
3072 
 
3073 
    wait until (rising_edge(cfg_rdwr_int.trn_clk) and cfg_rdwr_int.cfg_rd_wr_done_n = '0');
3074 
    cfg_rdwr_int.cfg_wr_en_n <= '1';
3075 
 
3076 
  end PROC_WRITE_CFG_DW;
3077 
 
3078 
 
3079 
end package body test_interface;

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