1 |
2 |
dsmv |
-------------------------------------------------------------------------------
|
2 |
|
|
--
|
3 |
|
|
-- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
|
4 |
|
|
--
|
5 |
|
|
-- This file contains confidential and proprietary information
|
6 |
|
|
-- of Xilinx, Inc. and is protected under U.S. and
|
7 |
|
|
-- international copyright and other intellectual property
|
8 |
|
|
-- laws.
|
9 |
|
|
--
|
10 |
|
|
-- DISCLAIMER
|
11 |
|
|
-- This disclaimer is not a license and does not grant any
|
12 |
|
|
-- rights to the materials distributed herewith. Except as
|
13 |
|
|
-- otherwise provided in a valid license issued to you by
|
14 |
|
|
-- Xilinx, and to the maximum extent permitted by applicable
|
15 |
|
|
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
16 |
|
|
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
17 |
|
|
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
18 |
|
|
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
19 |
|
|
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
20 |
|
|
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
21 |
|
|
-- including negligence, or under any other theory of
|
22 |
|
|
-- liability) for any loss or damage of any kind or nature
|
23 |
|
|
-- related to, arising under or in connection with these
|
24 |
|
|
-- materials, including for any direct, or any indirect,
|
25 |
|
|
-- special, incidental, or consequential loss or damage
|
26 |
|
|
-- (including loss of data, profits, goodwill, or any type of
|
27 |
|
|
-- loss or damage suffered as a result of any action brought
|
28 |
|
|
-- by a third party) even if such damage or loss was
|
29 |
|
|
-- reasonably foreseeable or Xilinx had been advised of the
|
30 |
|
|
-- possibility of the same.
|
31 |
|
|
--
|
32 |
|
|
-- CRITICAL APPLICATIONS
|
33 |
|
|
-- Xilinx products are not designed or intended to be fail-
|
34 |
|
|
-- safe, or for use in any application requiring fail-safe
|
35 |
|
|
-- performance, such as life-support or safety devices or
|
36 |
|
|
-- systems, Class III medical devices, nuclear facilities,
|
37 |
|
|
-- applications related to the deployment of airbags, or any
|
38 |
|
|
-- other applications that could lead to death, personal
|
39 |
|
|
-- injury, or severe property or environmental damage
|
40 |
|
|
-- (individually and collectively, "Critical
|
41 |
|
|
-- Applications"). Customer assumes the sole risk and
|
42 |
|
|
-- liability of any use of Xilinx products in Critical
|
43 |
|
|
-- Applications, subject only to applicable laws and
|
44 |
|
|
-- regulations governing limitations on product liability.
|
45 |
|
|
--
|
46 |
|
|
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
47 |
|
|
-- PART OF THIS FILE AT ALL TIMES.
|
48 |
|
|
--
|
49 |
|
|
-------------------------------------------------------------------------------
|
50 |
|
|
-- Project : Virtex-6 Integrated Block for PCI Express
|
51 |
|
|
-- File : xilinx_pcie_rport_m2.vhd
|
52 |
|
|
-- Version : 2.3
|
53 |
|
|
--
|
54 |
|
|
-- Description: PCI Express Root Port example FPGA design
|
55 |
|
|
--
|
56 |
|
|
------------------------------------------------------------------------------
|
57 |
|
|
|
58 |
|
|
|
59 |
|
|
library ieee;
|
60 |
|
|
use ieee.std_logic_1164.all;
|
61 |
|
|
|
62 |
|
|
library work;
|
63 |
|
|
use work.cmd_sim_pkg.all;
|
64 |
|
|
|
65 |
|
|
package xilinx_pcie_rport_m2_pkg is
|
66 |
|
|
|
67 |
|
|
component xilinx_pcie_rport_m2 is
|
68 |
|
|
generic (
|
69 |
|
|
REF_CLK_FREQ : integer := 0; -- 0 - 100MHz, 1 - 125 MHz, 2 - 250 MHz
|
70 |
|
|
ALLOW_X8_GEN2 : boolean := FALSE;
|
71 |
|
|
PL_FAST_TRAIN : boolean := FALSE;
|
72 |
|
|
LINK_CAP_MAX_LINK_SPEED : bit_vector := X"1";
|
73 |
|
|
DEVICE_ID : bit_vector := X"0007";
|
74 |
|
|
LINK_CAP_MAX_LINK_WIDTH : bit_vector := X"08";
|
75 |
|
|
LTSSM_MAX_LINK_WIDTH : bit_vector := X"08";
|
76 |
|
|
LINK_CAP_MAX_LINK_WIDTH_int : integer := 8;
|
77 |
|
|
LINK_CTRL2_TARGET_LINK_SPEED : bit_vector := X"2";
|
78 |
|
|
DEV_CAP_MAX_PAYLOAD_SUPPORTED : integer := 2;
|
79 |
|
|
USER_CLK_FREQ : integer := 3;
|
80 |
|
|
VC0_TX_LASTPACKET : integer := 31;
|
81 |
|
|
VC0_RX_RAM_LIMIT : bit_vector := X"03FF";
|
82 |
|
|
VC0_TOTAL_CREDITS_CD : integer := 154;
|
83 |
|
|
VC0_TOTAL_CREDITS_PD : integer := 154
|
84 |
|
|
);
|
85 |
|
|
port (
|
86 |
|
|
pci_exp_txp : out std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);
|
87 |
|
|
pci_exp_txn : out std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);
|
88 |
|
|
pci_exp_rxp : in std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);
|
89 |
|
|
pci_exp_rxn : in std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);
|
90 |
|
|
|
91 |
|
|
sys_clk : in std_logic;
|
92 |
|
|
sys_reset_n : in std_logic;
|
93 |
|
|
|
94 |
|
|
---- Test ----
|
95 |
|
|
cmd : in bh_cmd; -- êîìàíäà
|
96 |
|
|
ret : out bh_ret -- îòâåò
|
97 |
|
|
|
98 |
|
|
);
|
99 |
|
|
|
100 |
|
|
end component;
|
101 |
|
|
|
102 |
|
|
end package;
|
103 |
|
|
|
104 |
|
|
|
105 |
|
|
|
106 |
|
|
library ieee;
|
107 |
|
|
use ieee.std_logic_1164.all;
|
108 |
|
|
|
109 |
|
|
library work;
|
110 |
|
|
use work.cmd_sim_pkg.all;
|
111 |
|
|
|
112 |
|
|
|
113 |
|
|
use work.pci_exp_usrapp_tx_m2_pkg.all;
|
114 |
|
|
use work.pci_exp_usrapp_rx_m2_pkg.all;
|
115 |
|
|
|
116 |
|
|
entity xilinx_pcie_rport_m2 is
|
117 |
|
|
generic (
|
118 |
|
|
REF_CLK_FREQ : integer := 0; -- 0 - 100MHz, 1 - 125 MHz, 2 - 250 MHz
|
119 |
|
|
ALLOW_X8_GEN2 : boolean := FALSE;
|
120 |
|
|
PL_FAST_TRAIN : boolean := FALSE;
|
121 |
|
|
LINK_CAP_MAX_LINK_SPEED : bit_vector := X"1";
|
122 |
|
|
DEVICE_ID : bit_vector := X"0007";
|
123 |
|
|
LINK_CAP_MAX_LINK_WIDTH : bit_vector := X"08";
|
124 |
|
|
LTSSM_MAX_LINK_WIDTH : bit_vector := X"08";
|
125 |
|
|
LINK_CAP_MAX_LINK_WIDTH_int : integer := 8;
|
126 |
|
|
LINK_CTRL2_TARGET_LINK_SPEED : bit_vector := X"2";
|
127 |
|
|
DEV_CAP_MAX_PAYLOAD_SUPPORTED : integer := 2;
|
128 |
|
|
USER_CLK_FREQ : integer := 3;
|
129 |
|
|
VC0_TX_LASTPACKET : integer := 31;
|
130 |
|
|
VC0_RX_RAM_LIMIT : bit_vector := X"03FF";
|
131 |
|
|
VC0_TOTAL_CREDITS_CD : integer := 154;
|
132 |
|
|
VC0_TOTAL_CREDITS_PD : integer := 154
|
133 |
|
|
);
|
134 |
|
|
port (
|
135 |
|
|
pci_exp_txp : out std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);
|
136 |
|
|
pci_exp_txn : out std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);
|
137 |
|
|
pci_exp_rxp : in std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);
|
138 |
|
|
pci_exp_rxn : in std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);
|
139 |
|
|
|
140 |
|
|
sys_clk : in std_logic;
|
141 |
|
|
sys_reset_n : in std_logic;
|
142 |
|
|
|
143 |
|
|
---- Test ----
|
144 |
|
|
cmd : in bh_cmd; -- êîìàíäà
|
145 |
|
|
ret : out bh_ret -- îòâåò
|
146 |
|
|
|
147 |
|
|
);
|
148 |
|
|
|
149 |
|
|
end xilinx_pcie_rport_m2;
|
150 |
|
|
|
151 |
|
|
architecture rtl of xilinx_pcie_rport_m2 is
|
152 |
|
|
|
153 |
|
|
component pcie_2_0_rport_v6
|
154 |
|
|
generic (
|
155 |
|
|
REF_CLK_FREQ : integer;
|
156 |
|
|
ALLOW_X8_GEN2 : boolean;
|
157 |
|
|
PL_FAST_TRAIN : boolean;
|
158 |
|
|
LINK_CAP_MAX_LINK_SPEED : bit_vector;
|
159 |
|
|
DEVICE_ID : bit_vector;
|
160 |
|
|
LINK_CAP_MAX_LINK_WIDTH : bit_vector;
|
161 |
|
|
LINK_CAP_MAX_LINK_WIDTH_int : integer;
|
162 |
|
|
LINK_CTRL2_TARGET_LINK_SPEED : bit_vector;
|
163 |
|
|
LTSSM_MAX_LINK_WIDTH : bit_vector;
|
164 |
|
|
DEV_CAP_MAX_PAYLOAD_SUPPORTED : integer;
|
165 |
|
|
USER_CLK_FREQ : integer;
|
166 |
|
|
VC0_TX_LASTPACKET : integer;
|
167 |
|
|
VC0_RX_RAM_LIMIT : bit_vector;
|
168 |
|
|
VC0_TOTAL_CREDITS_CD : integer;
|
169 |
|
|
VC0_TOTAL_CREDITS_PD : integer
|
170 |
|
|
);
|
171 |
|
|
port (
|
172 |
|
|
pci_exp_txp : out std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);
|
173 |
|
|
pci_exp_txn : out std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);
|
174 |
|
|
pci_exp_rxp : in std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);
|
175 |
|
|
pci_exp_rxn : in std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);
|
176 |
|
|
trn_clk : out std_logic;
|
177 |
|
|
trn_reset_n : out std_logic;
|
178 |
|
|
trn_lnk_up_n : out std_logic;
|
179 |
|
|
trn_tbuf_av : out std_logic_vector(5 downto 0);
|
180 |
|
|
trn_tcfg_req_n : out std_logic;
|
181 |
|
|
trn_terr_drop_n : out std_logic;
|
182 |
|
|
trn_tdst_rdy_n : out std_logic;
|
183 |
|
|
trn_td : in std_logic_vector(63 downto 0);
|
184 |
|
|
trn_trem_n : in std_logic;
|
185 |
|
|
trn_tsof_n : in std_logic;
|
186 |
|
|
trn_teof_n : in std_logic;
|
187 |
|
|
trn_tsrc_rdy_n : in std_logic;
|
188 |
|
|
trn_tsrc_dsc_n : in std_logic;
|
189 |
|
|
trn_terrfwd_n : in std_logic;
|
190 |
|
|
trn_tcfg_gnt_n : in std_logic;
|
191 |
|
|
trn_tstr_n : in std_logic;
|
192 |
|
|
trn_rd : out std_logic_vector(63 downto 0);
|
193 |
|
|
trn_rrem_n : out std_logic;
|
194 |
|
|
trn_rsof_n : out std_logic;
|
195 |
|
|
trn_reof_n : out std_logic;
|
196 |
|
|
trn_rsrc_rdy_n : out std_logic;
|
197 |
|
|
trn_rsrc_dsc_n : out std_logic;
|
198 |
|
|
trn_rerrfwd_n : out std_logic;
|
199 |
|
|
trn_rbar_hit_n : out std_logic_vector(6 downto 0);
|
200 |
|
|
trn_rdst_rdy_n : in std_logic;
|
201 |
|
|
trn_rnp_ok_n : in std_logic;
|
202 |
|
|
trn_recrc_err_n : out std_logic;
|
203 |
|
|
trn_fc_cpld : out std_logic_vector(11 downto 0);
|
204 |
|
|
trn_fc_cplh : out std_logic_vector(7 downto 0);
|
205 |
|
|
trn_fc_npd : out std_logic_vector(11 downto 0);
|
206 |
|
|
trn_fc_nph : out std_logic_vector(7 downto 0);
|
207 |
|
|
trn_fc_pd : out std_logic_vector(11 downto 0);
|
208 |
|
|
trn_fc_ph : out std_logic_vector(7 downto 0);
|
209 |
|
|
trn_fc_sel : in std_logic_vector(2 downto 0);
|
210 |
|
|
cfg_do : out std_logic_vector(31 downto 0);
|
211 |
|
|
cfg_rd_wr_done_n : out std_logic;
|
212 |
|
|
cfg_di : in std_logic_vector(31 downto 0);
|
213 |
|
|
cfg_byte_en_n : in std_logic_vector(3 downto 0);
|
214 |
|
|
cfg_dwaddr : in std_logic_vector(9 downto 0);
|
215 |
|
|
cfg_wr_en_n : in std_logic;
|
216 |
|
|
cfg_wr_rw1c_as_rw_n : in std_logic;
|
217 |
|
|
cfg_rd_en_n : in std_logic;
|
218 |
|
|
cfg_err_cor_n : in std_logic;
|
219 |
|
|
cfg_err_ur_n : in std_logic;
|
220 |
|
|
cfg_err_ecrc_n : in std_logic;
|
221 |
|
|
cfg_err_cpl_timeout_n : in std_logic;
|
222 |
|
|
cfg_err_cpl_abort_n : in std_logic;
|
223 |
|
|
cfg_err_cpl_unexpect_n : in std_logic;
|
224 |
|
|
cfg_err_posted_n : in std_logic;
|
225 |
|
|
cfg_err_locked_n : in std_logic;
|
226 |
|
|
cfg_err_tlp_cpl_header : in std_logic_vector(47 downto 0);
|
227 |
|
|
cfg_err_cpl_rdy_n : out std_logic;
|
228 |
|
|
cfg_interrupt_n : in std_logic;
|
229 |
|
|
cfg_interrupt_rdy_n : out std_logic;
|
230 |
|
|
cfg_interrupt_assert_n : in std_logic;
|
231 |
|
|
cfg_interrupt_di : in std_logic_vector(7 downto 0);
|
232 |
|
|
cfg_interrupt_do : out std_logic_vector(7 downto 0);
|
233 |
|
|
cfg_interrupt_mmenable : out std_logic_vector(2 downto 0);
|
234 |
|
|
cfg_interrupt_msienable : out std_logic;
|
235 |
|
|
cfg_interrupt_msixenable : out std_logic;
|
236 |
|
|
cfg_interrupt_msixfm : out std_logic;
|
237 |
|
|
cfg_trn_pending_n : in std_logic;
|
238 |
|
|
cfg_pm_send_pme_to_n : in std_logic;
|
239 |
|
|
cfg_status : out std_logic_vector(15 downto 0);
|
240 |
|
|
cfg_command : out std_logic_vector(15 downto 0);
|
241 |
|
|
cfg_dstatus : out std_logic_vector(15 downto 0);
|
242 |
|
|
cfg_dcommand : out std_logic_vector(15 downto 0);
|
243 |
|
|
cfg_lstatus : out std_logic_vector(15 downto 0);
|
244 |
|
|
cfg_lcommand : out std_logic_vector(15 downto 0);
|
245 |
|
|
cfg_dcommand2 : out std_logic_vector(15 downto 0);
|
246 |
|
|
cfg_pcie_link_state_n : out std_logic_vector(2 downto 0);
|
247 |
|
|
cfg_dsn : in std_logic_vector(63 downto 0);
|
248 |
|
|
cfg_pmcsr_pme_en : out std_logic;
|
249 |
|
|
cfg_pmcsr_pme_status : out std_logic;
|
250 |
|
|
cfg_pmcsr_powerstate : out std_logic_vector(1 downto 0);
|
251 |
|
|
cfg_msg_received : out std_logic;
|
252 |
|
|
cfg_msg_data : out std_logic_vector(15 downto 0);
|
253 |
|
|
cfg_msg_received_err_cor : out std_logic;
|
254 |
|
|
cfg_msg_received_err_non_fatal : out std_logic;
|
255 |
|
|
cfg_msg_received_err_fatal : out std_logic;
|
256 |
|
|
cfg_msg_received_pme_to_ack : out std_logic;
|
257 |
|
|
cfg_msg_received_assert_inta : out std_logic;
|
258 |
|
|
cfg_msg_received_assert_intb : out std_logic;
|
259 |
|
|
cfg_msg_received_assert_intc : out std_logic;
|
260 |
|
|
cfg_msg_received_assert_intd : out std_logic;
|
261 |
|
|
cfg_msg_received_deassert_inta : out std_logic;
|
262 |
|
|
cfg_msg_received_deassert_intb : out std_logic;
|
263 |
|
|
cfg_msg_received_deassert_intc : out std_logic;
|
264 |
|
|
cfg_msg_received_deassert_intd : out std_logic;
|
265 |
|
|
cfg_ds_bus_number : in std_logic_vector(7 downto 0);
|
266 |
|
|
cfg_ds_device_number : in std_logic_vector(4 downto 0);
|
267 |
|
|
pl_initial_link_width : out std_logic_vector(2 downto 0);
|
268 |
|
|
pl_lane_reversal_mode : out std_logic_vector(1 downto 0);
|
269 |
|
|
pl_link_gen2_capable : out std_logic;
|
270 |
|
|
pl_link_partner_gen2_supported : out std_logic;
|
271 |
|
|
pl_link_upcfg_capable : out std_logic;
|
272 |
|
|
pl_ltssm_state : out std_logic_vector(5 downto 0);
|
273 |
|
|
pl_sel_link_rate : out std_logic;
|
274 |
|
|
pl_sel_link_width : out std_logic_vector(1 downto 0);
|
275 |
|
|
pl_directed_link_auton : in std_logic;
|
276 |
|
|
pl_directed_link_change : in std_logic_vector(1 downto 0);
|
277 |
|
|
pl_directed_link_speed : in std_logic;
|
278 |
|
|
pl_directed_link_width : in std_logic_vector(1 downto 0);
|
279 |
|
|
pl_upstream_prefer_deemph : in std_logic;
|
280 |
|
|
pl_transmit_hot_rst : in std_logic;
|
281 |
|
|
pcie_drp_clk : in std_logic;
|
282 |
|
|
pcie_drp_den : in std_logic;
|
283 |
|
|
pcie_drp_dwe : in std_logic;
|
284 |
|
|
pcie_drp_daddr : in std_logic_vector(8 downto 0);
|
285 |
|
|
pcie_drp_di : in std_logic_vector(15 downto 0);
|
286 |
|
|
pcie_drp_do : out std_logic_vector(15 downto 0);
|
287 |
|
|
pcie_drp_drdy : out std_logic;
|
288 |
|
|
sys_clk : in std_logic;
|
289 |
|
|
sys_reset_n : in std_logic);
|
290 |
|
|
end component;
|
291 |
|
|
|
292 |
|
|
component pci_exp_usrapp_cfg
|
293 |
|
|
port (
|
294 |
|
|
cfg_do : in std_logic_vector(31 downto 0);
|
295 |
|
|
cfg_di : out std_logic_vector(31 downto 0);
|
296 |
|
|
cfg_byte_en_n : out std_logic_vector(3 downto 0);
|
297 |
|
|
cfg_dwaddr : out std_logic_vector(9 downto 0);
|
298 |
|
|
cfg_wr_en_n : out std_logic;
|
299 |
|
|
cfg_rd_en_n : out std_logic;
|
300 |
|
|
cfg_rd_wr_done_n : in std_logic;
|
301 |
|
|
cfg_err_cor_n : out std_logic;
|
302 |
|
|
cfg_err_ur_n : out std_logic;
|
303 |
|
|
cfg_err_ecrc_n : out std_logic;
|
304 |
|
|
cfg_err_cpl_timeout_n : out std_logic;
|
305 |
|
|
cfg_err_cpl_abort_n : out std_logic;
|
306 |
|
|
cfg_err_cpl_unexpect_n : out std_logic;
|
307 |
|
|
cfg_err_posted_n : out std_logic;
|
308 |
|
|
cfg_err_tlp_cpl_header : out std_logic_vector(47 downto 0);
|
309 |
|
|
cfg_interrupt_n : out std_logic;
|
310 |
|
|
cfg_interrupt_rdy_n : in std_logic;
|
311 |
|
|
cfg_turnoff_ok_n : out std_logic;
|
312 |
|
|
cfg_to_turnoff_n : in std_logic;
|
313 |
|
|
cfg_pm_wake_n : out std_logic;
|
314 |
|
|
cfg_bus_number : in std_logic_vector((8 -1) downto 0);
|
315 |
|
|
cfg_device_number : in std_logic_vector((5 - 1) downto 0);
|
316 |
|
|
cfg_function_number : in std_logic_vector((3 - 1) downto 0);
|
317 |
|
|
cfg_status : in std_logic_vector((16 - 1) downto 0);
|
318 |
|
|
cfg_command : in std_logic_vector((16 - 1) downto 0);
|
319 |
|
|
cfg_dstatus : in std_logic_vector((16 - 1) downto 0);
|
320 |
|
|
cfg_dcommand : in std_logic_vector((16 - 1) downto 0);
|
321 |
|
|
cfg_lstatus : in std_logic_vector((16 - 1) downto 0);
|
322 |
|
|
cfg_lcommand : in std_logic_vector((16 - 1) downto 0);
|
323 |
|
|
cfg_pcie_link_state_n : in std_logic_vector((3 - 1) downto 0);
|
324 |
|
|
cfg_trn_pending_n : out std_logic;
|
325 |
|
|
trn_clk : in std_logic;
|
326 |
|
|
trn_reset_n : in std_logic);
|
327 |
|
|
end component;
|
328 |
|
|
|
329 |
|
|
|
330 |
|
|
|
331 |
|
|
|
332 |
|
|
component pci_exp_usrapp_pl
|
333 |
|
|
generic (
|
334 |
|
|
LINK_CAP_MAX_LINK_SPEED : integer);
|
335 |
|
|
port (
|
336 |
|
|
pl_initial_link_width : in std_logic_vector(2 downto 0);
|
337 |
|
|
pl_lane_reversal_mode : in std_logic_vector(1 downto 0);
|
338 |
|
|
pl_link_gen2_capable : in std_logic;
|
339 |
|
|
pl_link_partner_gen2_supported : in std_logic;
|
340 |
|
|
pl_link_upcfg_capable : in std_logic;
|
341 |
|
|
pl_ltssm_state : in std_logic_vector(5 downto 0);
|
342 |
|
|
pl_received_hot_rst : in std_logic;
|
343 |
|
|
pl_sel_link_rate : in std_logic;
|
344 |
|
|
pl_sel_link_width : in std_logic_vector(1 downto 0);
|
345 |
|
|
pl_directed_link_auton : out std_logic;
|
346 |
|
|
pl_directed_link_change : out std_logic_vector(1 downto 0);
|
347 |
|
|
pl_directed_link_speed : out std_logic;
|
348 |
|
|
pl_directed_link_width : out std_logic_vector(1 downto 0);
|
349 |
|
|
pl_upstream_prefer_deemph : out std_logic;
|
350 |
|
|
speed_change_done_n : out std_logic;
|
351 |
|
|
trn_lnk_up_n : in std_logic;
|
352 |
|
|
trn_clk : in std_logic;
|
353 |
|
|
trn_reset_n : in std_logic);
|
354 |
|
|
end component;
|
355 |
|
|
|
356 |
|
|
FUNCTION to_integer (
|
357 |
|
|
val_in : bit_vector) RETURN integer IS
|
358 |
|
|
|
359 |
|
|
CONSTANT vctr : bit_vector(val_in'high-val_in'low DOWNTO 0) := val_in;
|
360 |
|
|
VARIABLE ret : integer := 0;
|
361 |
|
|
BEGIN
|
362 |
|
|
FOR index IN vctr'RANGE LOOP
|
363 |
|
|
IF (vctr(index) = '1') THEN
|
364 |
|
|
ret := ret + (2**index);
|
365 |
|
|
END IF;
|
366 |
|
|
END LOOP;
|
367 |
|
|
RETURN(ret);
|
368 |
|
|
END to_integer;
|
369 |
|
|
|
370 |
|
|
constant LINK_CAP_MAX_LINK_SPEED_int : integer := to_integer(LINK_CAP_MAX_LINK_SPEED);
|
371 |
|
|
|
372 |
|
|
signal rx_tx_read_data : std_logic_vector(31 downto 0);
|
373 |
|
|
signal rx_tx_read_data_valid : std_logic;
|
374 |
|
|
signal tx_rx_read_data_valid : std_logic;
|
375 |
|
|
signal speed_change_done_n : std_logic;
|
376 |
|
|
|
377 |
|
|
-- Tx
|
378 |
|
|
signal trn_tbuf_av : std_logic_vector(5 downto 0);
|
379 |
|
|
signal trn_tdst_dsc_n : std_logic;
|
380 |
|
|
signal trn_tdst_rdy_n : std_logic;
|
381 |
|
|
signal trn_td : std_logic_vector(63 downto 0);
|
382 |
|
|
signal trn_trem_n : std_logic;
|
383 |
|
|
signal trn_trem_n_out : std_logic_vector(7 downto 0);
|
384 |
|
|
signal trn_tsof_n : std_logic;
|
385 |
|
|
signal trn_teof_n : std_logic;
|
386 |
|
|
signal trn_tsrc_rdy_n : std_logic;
|
387 |
|
|
signal trn_tsrc_dsc_n : std_logic;
|
388 |
|
|
signal trn_terrfwd_n : std_logic;
|
389 |
|
|
|
390 |
|
|
-- Rx
|
391 |
|
|
signal trn_rd : std_logic_vector(63 downto 0);
|
392 |
|
|
signal trn_rrem_n : std_logic;
|
393 |
|
|
signal trn_rrem_n_in : std_logic_vector(7 downto 0);
|
394 |
|
|
signal trn_rsof_n : std_logic;
|
395 |
|
|
signal trn_reof_n : std_logic;
|
396 |
|
|
signal trn_rsrc_rdy_n : std_logic;
|
397 |
|
|
signal trn_rsrc_dsc_n : std_logic;
|
398 |
|
|
signal trn_rerrfwd_n : std_logic;
|
399 |
|
|
signal trn_rbar_hit_n : std_logic_vector(6 downto 0);
|
400 |
|
|
signal trn_rdst_rdy_n : std_logic;
|
401 |
|
|
signal trn_rnp_ok_n : std_logic;
|
402 |
|
|
|
403 |
|
|
signal trn_clk : std_logic;
|
404 |
|
|
signal trn_reset_n : std_logic;
|
405 |
|
|
signal trn_lnk_up_n : std_logic;
|
406 |
|
|
|
407 |
|
|
---------------------------------------------------------
|
408 |
|
|
-- 3. Configuration (CFG) Interface
|
409 |
|
|
---------------------------------------------------------
|
410 |
|
|
|
411 |
|
|
signal cfg_do : std_logic_vector(31 downto 0);
|
412 |
|
|
signal cfg_rd_wr_done_n : std_logic;
|
413 |
|
|
signal cfg_di : std_logic_vector(31 downto 0);
|
414 |
|
|
signal cfg_byte_en_n : std_logic_vector(3 downto 0);
|
415 |
|
|
signal cfg_dwaddr : std_logic_vector(9 downto 0);
|
416 |
|
|
signal cfg_wr_en_n : std_logic;
|
417 |
|
|
signal cfg_rd_en_n : std_logic;
|
418 |
|
|
|
419 |
|
|
signal cfg_err_cor_n: std_logic;
|
420 |
|
|
signal cfg_err_ur_n : std_logic;
|
421 |
|
|
signal cfg_err_ecrc_n : std_logic;
|
422 |
|
|
signal cfg_err_cpl_timeout_n : std_logic;
|
423 |
|
|
signal cfg_err_cpl_abort_n : std_logic;
|
424 |
|
|
signal cfg_err_cpl_unexpect_n : std_logic;
|
425 |
|
|
signal cfg_err_posted_n : std_logic;
|
426 |
|
|
signal cfg_err_tlp_cpl_header : std_logic_vector(47 downto 0);
|
427 |
|
|
signal cfg_err_cpl_rdy_n : std_logic;
|
428 |
|
|
signal cfg_interrupt_n : std_logic;
|
429 |
|
|
signal cfg_interrupt_rdy_n : std_logic;
|
430 |
|
|
signal cfg_interrupt_mmenable : std_logic_vector(2 downto 0);
|
431 |
|
|
signal cfg_interrupt_msienable : std_logic;
|
432 |
|
|
signal cfg_interrupt_msixenable : std_logic;
|
433 |
|
|
signal cfg_interrupt_msixfm : std_logic;
|
434 |
|
|
signal cfg_trn_pending_n : std_logic;
|
435 |
|
|
signal cfg_status : std_logic_vector(15 downto 0);
|
436 |
|
|
signal cfg_command : std_logic_vector(15 downto 0);
|
437 |
|
|
signal cfg_dstatus : std_logic_vector(15 downto 0);
|
438 |
|
|
signal cfg_dcommand : std_logic_vector(15 downto 0);
|
439 |
|
|
signal cfg_lstatus : std_logic_vector(15 downto 0);
|
440 |
|
|
signal cfg_lcommand : std_logic_vector(15 downto 0);
|
441 |
|
|
signal cfg_pcie_link_state_n : std_logic_vector(2 downto 0);
|
442 |
|
|
|
443 |
|
|
signal cfg_msg_received : std_logic;
|
444 |
|
|
signal cfg_msg_data : std_logic_vector(15 downto 0);
|
445 |
|
|
signal cfg_msg_received_err_cor : std_logic;
|
446 |
|
|
signal cfg_msg_received_err_non_fatal : std_logic;
|
447 |
|
|
signal cfg_msg_received_err_fatal : std_logic;
|
448 |
|
|
signal cfg_msg_received_pme_to_ack : std_logic;
|
449 |
|
|
signal cfg_msg_received_assert_inta : std_logic;
|
450 |
|
|
signal cfg_msg_received_assert_intb : std_logic;
|
451 |
|
|
signal cfg_msg_received_assert_intc : std_logic;
|
452 |
|
|
signal cfg_msg_received_assert_intd : std_logic;
|
453 |
|
|
signal cfg_msg_received_deassert_inta : std_logic;
|
454 |
|
|
signal cfg_msg_received_deassert_intb : std_logic;
|
455 |
|
|
signal cfg_msg_received_deassert_intc : std_logic;
|
456 |
|
|
signal cfg_msg_received_deassert_intd : std_logic;
|
457 |
|
|
|
458 |
|
|
---------------------------------------------------------
|
459 |
|
|
-- 4. Physical Layer Control and Status (PL) Interface
|
460 |
|
|
---------------------------------------------------------
|
461 |
|
|
|
462 |
|
|
signal pl_initial_link_width : std_logic_vector(2 downto 0);
|
463 |
|
|
signal pl_lane_reversal_mode : std_logic_vector(1 downto 0);
|
464 |
|
|
signal pl_link_gen2_capable : std_logic;
|
465 |
|
|
signal pl_link_partner_gen2_supported : std_logic;
|
466 |
|
|
signal pl_link_upcfg_capable : std_logic;
|
467 |
|
|
signal pl_ltssm_state : std_logic_vector(5 downto 0);
|
468 |
|
|
signal pl_sel_link_rate : std_logic;
|
469 |
|
|
signal pl_sel_link_width : std_logic_vector(1 downto 0);
|
470 |
|
|
signal pl_directed_link_auton : std_logic;
|
471 |
|
|
signal pl_directed_link_change : std_logic_vector(1 downto 0);
|
472 |
|
|
signal pl_directed_link_speed : std_logic;
|
473 |
|
|
signal pl_directed_link_width : std_logic_vector(1 downto 0);
|
474 |
|
|
signal pl_upstream_prefer_deemph : std_logic;
|
475 |
|
|
|
476 |
|
|
-------------------------------------------------------
|
477 |
|
|
|
478 |
|
|
begin
|
479 |
|
|
|
480 |
|
|
trn_trem_n <= '1' when (trn_trem_n_out = X"0F") else
|
481 |
|
|
'0';
|
482 |
|
|
trn_rrem_n_in <= X"0F" when (trn_rrem_n = '1') else
|
483 |
|
|
X"00";
|
484 |
|
|
|
485 |
|
|
rport : pcie_2_0_rport_v6
|
486 |
|
|
generic map(
|
487 |
|
|
REF_CLK_FREQ => REF_CLK_FREQ,
|
488 |
|
|
ALLOW_X8_GEN2 => ALLOW_X8_GEN2,
|
489 |
|
|
PL_FAST_TRAIN => PL_FAST_TRAIN,
|
490 |
|
|
LINK_CAP_MAX_LINK_SPEED => LINK_CAP_MAX_LINK_SPEED,
|
491 |
|
|
DEVICE_ID => DEVICE_ID,
|
492 |
|
|
LINK_CAP_MAX_LINK_WIDTH => LINK_CAP_MAX_LINK_WIDTH,
|
493 |
|
|
LINK_CAP_MAX_LINK_WIDTH_int => LINK_CAP_MAX_LINK_WIDTH_int,
|
494 |
|
|
LINK_CTRL2_TARGET_LINK_SPEED => LINK_CTRL2_TARGET_LINK_SPEED,
|
495 |
|
|
LTSSM_MAX_LINK_WIDTH => LTSSM_MAX_LINK_WIDTH,
|
496 |
|
|
DEV_CAP_MAX_PAYLOAD_SUPPORTED => DEV_CAP_MAX_PAYLOAD_SUPPORTED,
|
497 |
|
|
USER_CLK_FREQ => USER_CLK_FREQ,
|
498 |
|
|
VC0_TX_LASTPACKET => VC0_TX_LASTPACKET,
|
499 |
|
|
VC0_RX_RAM_LIMIT => VC0_RX_RAM_LIMIT,
|
500 |
|
|
VC0_TOTAL_CREDITS_CD => VC0_TOTAL_CREDITS_CD,
|
501 |
|
|
VC0_TOTAL_CREDITS_PD => VC0_TOTAL_CREDITS_CD
|
502 |
|
|
)
|
503 |
|
|
port map(
|
504 |
|
|
pci_exp_txp => pci_exp_txp,
|
505 |
|
|
pci_exp_txn => pci_exp_txn,
|
506 |
|
|
pci_exp_rxp => pci_exp_rxp,
|
507 |
|
|
pci_exp_rxn => pci_exp_rxn,
|
508 |
|
|
trn_clk => trn_clk ,
|
509 |
|
|
trn_reset_n => trn_reset_n ,
|
510 |
|
|
trn_lnk_up_n => trn_lnk_up_n ,
|
511 |
|
|
trn_tbuf_av => trn_tbuf_av ,
|
512 |
|
|
trn_tcfg_req_n => open,
|
513 |
|
|
trn_terr_drop_n => trn_tdst_dsc_n ,
|
514 |
|
|
trn_tdst_rdy_n => trn_tdst_rdy_n ,
|
515 |
|
|
trn_td => trn_td ,
|
516 |
|
|
trn_trem_n => trn_trem_n,
|
517 |
|
|
trn_tsof_n => trn_tsof_n ,
|
518 |
|
|
trn_teof_n => trn_teof_n ,
|
519 |
|
|
trn_tsrc_rdy_n => trn_tsrc_rdy_n ,
|
520 |
|
|
trn_tsrc_dsc_n => trn_tsrc_dsc_n ,
|
521 |
|
|
trn_terrfwd_n => trn_terrfwd_n ,
|
522 |
|
|
trn_tcfg_gnt_n => '0' ,
|
523 |
|
|
trn_tstr_n => '1' ,
|
524 |
|
|
trn_rd => trn_rd ,
|
525 |
|
|
trn_rrem_n => trn_rrem_n ,
|
526 |
|
|
trn_rsof_n => trn_rsof_n ,
|
527 |
|
|
trn_reof_n => trn_reof_n ,
|
528 |
|
|
trn_rsrc_rdy_n => trn_rsrc_rdy_n ,
|
529 |
|
|
trn_rsrc_dsc_n => trn_rsrc_dsc_n ,
|
530 |
|
|
trn_rerrfwd_n => trn_rerrfwd_n ,
|
531 |
|
|
trn_rbar_hit_n => trn_rbar_hit_n ,
|
532 |
|
|
trn_rdst_rdy_n => trn_rdst_rdy_n ,
|
533 |
|
|
trn_rnp_ok_n => trn_rnp_ok_n ,
|
534 |
|
|
trn_recrc_err_n => open,
|
535 |
|
|
trn_fc_cpld => open,
|
536 |
|
|
trn_fc_cplh => open,
|
537 |
|
|
trn_fc_npd => open,
|
538 |
|
|
trn_fc_nph => open,
|
539 |
|
|
trn_fc_pd => open,
|
540 |
|
|
trn_fc_ph => open,
|
541 |
|
|
trn_fc_sel => "000" ,
|
542 |
|
|
cfg_do => cfg_do ,
|
543 |
|
|
cfg_rd_wr_done_n => cfg_rd_wr_done_n,
|
544 |
|
|
cfg_di => cfg_di ,
|
545 |
|
|
cfg_byte_en_n => cfg_byte_en_n ,
|
546 |
|
|
cfg_dwaddr => cfg_dwaddr ,
|
547 |
|
|
cfg_wr_en_n => cfg_wr_en_n ,
|
548 |
|
|
cfg_wr_rw1c_as_rw_n => '1',
|
549 |
|
|
cfg_rd_en_n => cfg_rd_en_n ,
|
550 |
|
|
|
551 |
|
|
cfg_err_cor_n => cfg_err_cor_n ,
|
552 |
|
|
cfg_err_ur_n => cfg_err_ur_n ,
|
553 |
|
|
cfg_err_ecrc_n => cfg_err_ecrc_n ,
|
554 |
|
|
cfg_err_cpl_timeout_n => cfg_err_cpl_timeout_n ,
|
555 |
|
|
cfg_err_cpl_abort_n => cfg_err_cpl_abort_n ,
|
556 |
|
|
cfg_err_cpl_unexpect_n => cfg_err_cpl_unexpect_n ,
|
557 |
|
|
cfg_err_posted_n => cfg_err_posted_n ,
|
558 |
|
|
cfg_err_locked_n => '1',
|
559 |
|
|
cfg_err_tlp_cpl_header => cfg_err_tlp_cpl_header ,
|
560 |
|
|
cfg_err_cpl_rdy_n => open,
|
561 |
|
|
cfg_interrupt_n => cfg_interrupt_n ,
|
562 |
|
|
cfg_interrupt_rdy_n => cfg_interrupt_rdy_n ,
|
563 |
|
|
cfg_interrupt_assert_n => '1' ,
|
564 |
|
|
cfg_interrupt_di => X"00" ,
|
565 |
|
|
cfg_interrupt_do => open,
|
566 |
|
|
cfg_interrupt_mmenable => open,
|
567 |
|
|
cfg_interrupt_msienable => open,
|
568 |
|
|
cfg_interrupt_msixenable => open,
|
569 |
|
|
cfg_interrupt_msixfm => open,
|
570 |
|
|
cfg_trn_pending_n => cfg_trn_pending_n ,
|
571 |
|
|
cfg_pm_send_pme_to_n => '1' ,
|
572 |
|
|
cfg_status => cfg_status ,
|
573 |
|
|
cfg_command => cfg_command ,
|
574 |
|
|
cfg_dstatus => cfg_dstatus ,
|
575 |
|
|
cfg_dcommand => cfg_dcommand ,
|
576 |
|
|
cfg_lstatus => cfg_lstatus ,
|
577 |
|
|
cfg_lcommand => cfg_lcommand ,
|
578 |
|
|
cfg_dcommand2 => open,
|
579 |
|
|
cfg_pcie_link_state_n => cfg_pcie_link_state_n ,
|
580 |
|
|
cfg_dsn => (others => '0') ,
|
581 |
|
|
cfg_pmcsr_pme_en => open,
|
582 |
|
|
cfg_pmcsr_pme_status => open,
|
583 |
|
|
cfg_pmcsr_powerstate => open,
|
584 |
|
|
cfg_msg_received => cfg_msg_received ,
|
585 |
|
|
cfg_msg_data => cfg_msg_data ,
|
586 |
|
|
cfg_msg_received_err_cor => cfg_msg_received_err_cor ,
|
587 |
|
|
cfg_msg_received_err_non_fatal => cfg_msg_received_err_non_fatal ,
|
588 |
|
|
cfg_msg_received_err_fatal => cfg_msg_received_err_fatal ,
|
589 |
|
|
cfg_msg_received_pme_to_ack => cfg_msg_received_pme_to_ack ,
|
590 |
|
|
cfg_msg_received_assert_inta => cfg_msg_received_assert_inta ,
|
591 |
|
|
cfg_msg_received_assert_intb => cfg_msg_received_assert_intb ,
|
592 |
|
|
cfg_msg_received_assert_intc => cfg_msg_received_assert_intc ,
|
593 |
|
|
cfg_msg_received_assert_intd => cfg_msg_received_assert_intd ,
|
594 |
|
|
cfg_msg_received_deassert_inta => cfg_msg_received_deassert_inta ,
|
595 |
|
|
cfg_msg_received_deassert_intb => cfg_msg_received_deassert_intb ,
|
596 |
|
|
cfg_msg_received_deassert_intc => cfg_msg_received_deassert_intc ,
|
597 |
|
|
cfg_msg_received_deassert_intd => cfg_msg_received_deassert_intd ,
|
598 |
|
|
cfg_ds_bus_number => X"00",
|
599 |
|
|
cfg_ds_device_number => "00000",
|
600 |
|
|
pl_initial_link_width => pl_initial_link_width ,
|
601 |
|
|
pl_lane_reversal_mode => pl_lane_reversal_mode ,
|
602 |
|
|
pl_link_gen2_capable => pl_link_gen2_capable ,
|
603 |
|
|
pl_link_partner_gen2_supported => pl_link_partner_gen2_supported ,
|
604 |
|
|
pl_link_upcfg_capable => pl_link_upcfg_capable ,
|
605 |
|
|
pl_ltssm_state => pl_ltssm_state ,
|
606 |
|
|
pl_sel_link_rate => pl_sel_link_rate ,
|
607 |
|
|
pl_sel_link_width => pl_sel_link_width ,
|
608 |
|
|
pl_directed_link_auton => pl_directed_link_auton ,
|
609 |
|
|
pl_directed_link_change => pl_directed_link_change ,
|
610 |
|
|
pl_directed_link_speed => pl_directed_link_speed ,
|
611 |
|
|
pl_directed_link_width => pl_directed_link_width ,
|
612 |
|
|
pl_upstream_prefer_deemph => pl_upstream_prefer_deemph ,
|
613 |
|
|
pl_transmit_hot_rst => '0',
|
614 |
|
|
pcie_drp_clk => '0',
|
615 |
|
|
pcie_drp_den => '0',
|
616 |
|
|
pcie_drp_dwe => '0',
|
617 |
|
|
pcie_drp_daddr => "000000000",
|
618 |
|
|
pcie_drp_di => X"0000",
|
619 |
|
|
pcie_drp_do => open,
|
620 |
|
|
pcie_drp_drdy => open,
|
621 |
|
|
sys_clk => sys_clk ,
|
622 |
|
|
sys_reset_n => sys_reset_n
|
623 |
|
|
|
624 |
|
|
);
|
625 |
|
|
|
626 |
|
|
CFG_APP : pci_exp_usrapp_cfg
|
627 |
|
|
port map (
|
628 |
|
|
cfg_do => cfg_do,
|
629 |
|
|
cfg_di => cfg_di,
|
630 |
|
|
cfg_byte_en_n => cfg_byte_en_n,
|
631 |
|
|
cfg_dwaddr => cfg_dwaddr,
|
632 |
|
|
cfg_wr_en_n => cfg_wr_en_n,
|
633 |
|
|
cfg_rd_en_n => cfg_rd_en_n,
|
634 |
|
|
cfg_rd_wr_done_n => cfg_rd_wr_done_n,
|
635 |
|
|
cfg_err_cor_n => cfg_err_cor_n,
|
636 |
|
|
cfg_err_ur_n => cfg_err_ur_n,
|
637 |
|
|
cfg_err_ecrc_n => cfg_err_ecrc_n,
|
638 |
|
|
cfg_err_cpl_timeout_n => cfg_err_cpl_timeout_n,
|
639 |
|
|
cfg_err_cpl_abort_n => cfg_err_cpl_abort_n,
|
640 |
|
|
cfg_err_cpl_unexpect_n => cfg_err_cpl_unexpect_n,
|
641 |
|
|
cfg_err_posted_n => cfg_err_posted_n,
|
642 |
|
|
cfg_err_tlp_cpl_header => cfg_err_tlp_cpl_header,
|
643 |
|
|
cfg_interrupt_n => cfg_interrupt_n,
|
644 |
|
|
cfg_interrupt_rdy_n => cfg_interrupt_rdy_n,
|
645 |
|
|
cfg_turnoff_ok_n => open,
|
646 |
|
|
cfg_to_turnoff_n => '1',
|
647 |
|
|
cfg_pm_wake_n => open,
|
648 |
|
|
cfg_bus_number => X"00",
|
649 |
|
|
cfg_device_number => "00000",
|
650 |
|
|
cfg_function_number => "000",
|
651 |
|
|
cfg_status => cfg_status,
|
652 |
|
|
cfg_command => cfg_command,
|
653 |
|
|
cfg_dstatus => cfg_dstatus,
|
654 |
|
|
cfg_dcommand => cfg_dcommand,
|
655 |
|
|
cfg_lstatus => cfg_lstatus,
|
656 |
|
|
cfg_lcommand => cfg_lcommand,
|
657 |
|
|
cfg_pcie_link_state_n => cfg_pcie_link_state_n,
|
658 |
|
|
cfg_trn_pending_n => cfg_trn_pending_n,
|
659 |
|
|
trn_clk => trn_clk,
|
660 |
|
|
trn_reset_n => trn_reset_n);
|
661 |
|
|
|
662 |
|
|
|
663 |
|
|
RX_APP : pci_exp_usrapp_rx_m2
|
664 |
|
|
port map (
|
665 |
|
|
trn_rdst_rdy_n => trn_rdst_rdy_n,
|
666 |
|
|
trn_rnp_ok_n => trn_rnp_ok_n,
|
667 |
|
|
trn_rd => trn_rd,
|
668 |
|
|
trn_rrem_n => trn_rrem_n_in,
|
669 |
|
|
trn_rsof_n => trn_rsof_n,
|
670 |
|
|
trn_reof_n => trn_reof_n,
|
671 |
|
|
trn_rsrc_rdy_n => trn_rsrc_rdy_n,
|
672 |
|
|
trn_rsrc_dsc_n => trn_rsrc_dsc_n,
|
673 |
|
|
trn_rerrfwd_n => trn_rerrfwd_n,
|
674 |
|
|
trn_rbar_hit_n => trn_rbar_hit_n,
|
675 |
|
|
trn_clk => trn_clk,
|
676 |
|
|
trn_reset_n => trn_reset_n,
|
677 |
|
|
trn_lnk_up_n => trn_lnk_up_n,
|
678 |
|
|
rx_tx_read_data => rx_tx_read_data,
|
679 |
|
|
rx_tx_read_data_valid => rx_tx_read_data_valid,
|
680 |
|
|
tx_rx_read_data_valid => tx_rx_read_data_valid);
|
681 |
|
|
|
682 |
|
|
TX_APP : pci_exp_usrapp_tx_m2
|
683 |
|
|
port map (
|
684 |
|
|
trn_td => trn_td,
|
685 |
|
|
trn_trem_n => trn_trem_n_out,
|
686 |
|
|
trn_tsof_n => trn_tsof_n,
|
687 |
|
|
trn_teof_n => trn_teof_n,
|
688 |
|
|
trn_terrfwd_n => trn_terrfwd_n,
|
689 |
|
|
trn_tsrc_rdy_n => trn_tsrc_rdy_n,
|
690 |
|
|
trn_tsrc_dsc_n => trn_tsrc_dsc_n,
|
691 |
|
|
trn_clk => trn_clk,
|
692 |
|
|
trn_reset_n => trn_reset_n,
|
693 |
|
|
trn_lnk_up_n => trn_lnk_up_n,
|
694 |
|
|
trn_tdst_rdy_n => trn_tdst_rdy_n,
|
695 |
|
|
trn_tdst_dsc_n => trn_tdst_dsc_n,
|
696 |
|
|
trn_tbuf_av => trn_tbuf_av,
|
697 |
|
|
speed_change_done_n => speed_change_done_n,
|
698 |
|
|
rx_tx_read_data => rx_tx_read_data,
|
699 |
|
|
rx_tx_read_data_valid => rx_tx_read_data_valid,
|
700 |
|
|
tx_rx_read_data_valid => tx_rx_read_data_valid,
|
701 |
|
|
|
702 |
|
|
cmd => cmd,
|
703 |
|
|
ret => ret
|
704 |
|
|
|
705 |
|
|
);
|
706 |
|
|
|
707 |
|
|
PL_APP : pci_exp_usrapp_pl
|
708 |
|
|
generic map (
|
709 |
|
|
LINK_CAP_MAX_LINK_SPEED => LINK_CAP_MAX_LINK_SPEED_int)
|
710 |
|
|
port map (
|
711 |
|
|
pl_initial_link_width => pl_initial_link_width,
|
712 |
|
|
pl_lane_reversal_mode => pl_lane_reversal_mode,
|
713 |
|
|
pl_link_gen2_capable => pl_link_gen2_capable,
|
714 |
|
|
pl_link_partner_gen2_supported => pl_link_partner_gen2_supported,
|
715 |
|
|
pl_link_upcfg_capable => pl_link_upcfg_capable,
|
716 |
|
|
pl_ltssm_state => pl_ltssm_state,
|
717 |
|
|
pl_received_hot_rst => '0',
|
718 |
|
|
pl_sel_link_rate => pl_sel_link_rate,
|
719 |
|
|
pl_sel_link_width => pl_sel_link_width,
|
720 |
|
|
pl_directed_link_auton => pl_directed_link_auton,
|
721 |
|
|
pl_directed_link_change => pl_directed_link_change,
|
722 |
|
|
pl_directed_link_speed => pl_directed_link_speed,
|
723 |
|
|
pl_directed_link_width => pl_directed_link_width,
|
724 |
|
|
pl_upstream_prefer_deemph => pl_upstream_prefer_deemph,
|
725 |
|
|
speed_change_done_n => speed_change_done_n,
|
726 |
|
|
trn_lnk_up_n => trn_lnk_up_n,
|
727 |
|
|
trn_clk => trn_clk,
|
728 |
|
|
trn_reset_n => trn_reset_n);
|
729 |
|
|
|
730 |
|
|
end rtl;
|