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[/] [pcie_ds_dma/] [trunk/] [core/] [wishbone/] [block_test_check/] [block_check_wb_burst_slave.v] - Blame information for rev 2

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1 2 dsmv 
//////////////////////////////////////////////////////////////////////////////////
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// Company:         ;)
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// Engineer:        Kuzmi4
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//
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// Create Date:     14:39:52 05/19/2010
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// Design Name:
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// Module Name:     block_check_wb_burst_slave
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// Project Name:    DS_DMA
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// Target Devices:  any
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// Tool versions:
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// Description:
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//
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//                  For now we have such restrictions for WB component:
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//                      1) no WB_RTY syupport
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//                      2) WB_ERR arize only at event detection and fall after it goes.
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//                      3) WB Transfer granularity - 64bit
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//                      4) (TBD)...
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//
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//                  ==> Design SUPPORT Master DELAY in Transfer !!!
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//
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// Revision:
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// Revision 0.01 - File Created
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//
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//////////////////////////////////////////////////////////////////////////////////
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`timescale 1ns / 1ps
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module block_check_wb_burst_slave
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(
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    //
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    // SYS_CON
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    input   i_clk,
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    input   i_rst,
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    //
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    // WB BURST SLAVE IF (WRITE-ONLY IF)
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    input       [11:0]  iv_wbs_burst_addr,
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    input       [63:0]  iv_wbs_burst_data,
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    input       [ 7:0]  iv_wbs_burst_sel,
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    input               i_wbs_burst_we,
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    input               i_wbs_burst_cyc,
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    input               i_wbs_burst_stb,
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    input       [ 2:0]  iv_wbs_burst_cti,
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    input       [ 1:0]  iv_wbs_burst_bte,
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    output              o_wbs_burst_ack,
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    output reg          o_wbs_burst_err,
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    output              o_wbs_burst_rty,
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    //
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    // TEST_CHECK IF (Output data with ENA)
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    output reg  [63:0]  ov_test_check_data,
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    output reg          o_test_check_data_ena,
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    //
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    // TEST_CHECK Controls (WBS_CFG)
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    input       [15:0]  iv_control
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);
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//////////////////////////////////////////////////////////////////////////////////
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    //
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    wire    s_wb_transfer_ok_0;
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    //wire    s_wb_transfer_master_hold;
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    // define WB stuff:
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    reg     [8:0]   sv_wbs_burst_counter;
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//////////////////////////////////////////////////////////////////////////////////
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    //
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    assign  s_wb_transfer_ok_0  =   (iv_wbs_burst_addr==0)                              & // START from INIT ADDR
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                                    i_wbs_burst_cyc & i_wbs_burst_stb & i_wbs_burst_we  & // WB Transfer strobes
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                                    iv_wbs_burst_sel==8'hFF                             & // WB_SEL point to 64bit transfer
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                                    iv_wbs_burst_bte==2'b00                             ; // WB Burst Transfer type check (Linear Burst)
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    /*assign  s_wb_transfer_master_hold   =   (iv_wbs_burst_addr==0)                              & // START from INIT ADDR
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                                            i_wbs_burst_cyc & !i_wbs_burst_stb & i_wbs_burst_we & // WB Transfer strobes (MASTER STALL case)
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                                            iv_wbs_burst_sel==8'hFF                             & // WB_SEL point to 64bit transfer
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                                            iv_wbs_burst_bte==2'b00                             ; // WB Burst Transfer type check (Linear Burst)*/
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    // WB stuff:
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    assign  o_wbs_burst_ack =   s_wb_transfer_ok_0;
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    assign  o_wbs_burst_rty =   0;  // for now no WB Retry func, only WB_ERR for now
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//////////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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always @ (posedge i_clk or posedge i_rst)
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begin   :   TEST_CHECK_DATA_OUT
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    //
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    o_test_check_data_ena   <= s_wb_transfer_ok_0;
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    ov_test_check_data      <= iv_wbs_burst_data;
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end
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//////////////////////////////////////////////////////////////////////////////////
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//
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// Create WB ERROR logic:
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//
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always @ (posedge i_clk or posedge i_rst)
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begin   :   WB_ERR
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    if (i_rst)
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        begin   :   RST
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            o_wbs_burst_err         <= 0;
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            sv_wbs_burst_counter    <= 0;
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        end
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    else
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        begin   :   WRK
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            // BURST counter
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            if (i_wbs_burst_cyc)
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                begin   :   TIME_TO_COUNT
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                    if (o_wbs_burst_ack) // count ENA
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                        sv_wbs_burst_counter <= sv_wbs_burst_counter + 1'b1;
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                end
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            else            // W8 for COUNT Time, CLR COUNTER
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                sv_wbs_burst_counter <= 0;
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            // ERR logic
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            if  (
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                    (sv_wbs_burst_counter == 511 & o_wbs_burst_ack & iv_wbs_burst_cti!=3'b111)  |   // check End-of-Burst
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                    (sv_wbs_burst_counter <  511 & o_wbs_burst_ack & iv_wbs_burst_cti!=3'b001)      // check Const-Addr-Burst
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                                                                                                    // ==> WB_BTE check at "s_wb_transfer_ok"
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                )
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                o_wbs_burst_err <= 1;
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            else
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                o_wbs_burst_err <= 0;
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        end
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end
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//////////////////////////////////////////////////////////////////////////////////
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endmodule

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