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[/] [pcie_ds_dma/] [trunk/] [core/] [wishbone/] [block_test_check/] [block_check_wb_config_slave.vhd] - Blame information for rev 2

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1 2 dsmv
----------------------------------------------------------------------------------
2
-- Company:         ;)
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-- Engineer:        Kuzmi4
4
-- 
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-- Create Date:     17:40:25 05/21/2010 
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-- Design Name:     
7
-- Module Name:     block_check_wb_config_slave - rtl 
8
-- Project Name:    DS_DMA
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-- Target Devices:  any
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-- Tool versions:   
11
-- Description:     
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--                  
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--                  For now we have such restrictions for WB component:
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--                      1) no WB_RTY support
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--                      2) WB_ERR arize only at event detection and fall after it goes.
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--                      3) Operate with Single 64bit WB Transfers. NO WB BURSTs.
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--                      4) (TBD)...
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--                  
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--                   WB_SLAVE MM (ONLY 256B range):
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--                  1) CONSTANTs:
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--                  ADDR=x00 - BLOCK_ID
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--                  ADDR=x08 - BLOCK_VER
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--                  ADDR=x10 - RSVD (CONSTANTs)
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--                  ADDR=x18 - RSVD (CONSTANTs)
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--                  ADDR=x20 - RSVD (CONSTANTs)
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--                  ADDR=x28 - RSVD (CONSTANTs)
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--                  ADDR=x30 - RSVD (CONSTANTs)
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--                  ADDR=x38 - RSVD (CONSTANTs)
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--                  2) COMMAND REGs:
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--                  ADDR=x40 - TEST_CHECK_CTRL
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--                  ADDR=x48 - TEST_CHECK_SIZE
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--                  ADDR=x50 - TEST_CHECK_ERR_ADDR
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--                  ADDR=x58 - TEST_CHECK_WBS_BURST_CTRL
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--                  ADDR=x60 - RSVD (COMMAND REGs)
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--                  ADDR=x68 - RSVD (COMMAND REGs)
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--                  ADDR=x70 - RSVD (COMMAND REGs)
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--                  ADDR=x78 - RSVD (COMMAND REGs)
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--                  3) STS REGs, etc:
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--                  ADDR=x80 - TEST_CHECK_BL_RD
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--                  ADDR=x88 - TEST_CHECK_BL_OK
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--                  ADDR=x90 - TEST_CHECK_BL_ERR
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--                  ADDR=x98 - TEST_CHECK_ERR
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--                  ADDR=xA0 - TEST_CHECK_ERR_DATA
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--                  ADDR=xA8 - RSVD (STS REGs, etc)
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--                  ....
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--                  ADDR=xFF - RSVD (STS REGs, etc)
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--                  
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--                  
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--
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-- Revision: 
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-- Revision 0.01 - File Created,
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--                  2do: for now ADD MemoryMap looks good, but maybe its quite diff from REAL SITUATION --> CHECK/FIX MM later!!!
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-- Revision 0.02 - upd WB_ERR func.
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-- Revision 0.03 - fix MM (8cell allign).
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--
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----------------------------------------------------------------------------------
57
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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60
package block_check_wb_config_slave_pkg is
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62
component block_check_wb_config_slave is
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generic
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(
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    BLOCK_ID   : in std_logic_vector( 15 downto 0 ):=x"0000"; -- идентификатор модуля
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    BLOCK_VER  : in std_logic_vector( 15 downto 0 ):=x"0000"  -- версия модуля
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);
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port
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(
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    --
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    -- SYS_CON
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    i_clk : in  STD_LOGIC;
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    i_rst : in  STD_LOGIC;
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    --
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    -- WB CFG SLAVE
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    iv_wbs_cfg_addr     :   in  std_logic_vector(  7 downto 0 );
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    iv_wbs_cfg_data     :   in  std_logic_vector( 63 downto 0 );
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    iv_wbs_cfg_sel      :   in  std_logic_vector(  7 downto 0 );    -- wor now, we NC this wires
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    i_wbs_cfg_we        :   in  std_logic;
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    i_wbs_cfg_cyc       :   in  std_logic;
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    i_wbs_cfg_stb       :   in  std_logic;
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    iv_wbs_cfg_cti      :   in  std_logic_vector(  2 downto 0 );
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    iv_wbs_cfg_bte      :   in  std_logic_vector(  1 downto 0 );
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85
    ov_wbs_cfg_data     :   out std_logic_vector( 63 downto 0 );
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    o_wbs_cfg_ack       :   out std_logic;
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    o_wbs_cfg_err       :   out std_logic;
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    o_wbs_cfg_rty       :   out std_logic;
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    --
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    -- CONTROL Outputs
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    ov_test_check_ctrl      :   out std_logic_vector( 15 downto 0 );
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    ov_test_check_size      :   out std_logic_vector( 15 downto 0 );
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    ov_test_check_err_adr   :   out std_logic_vector( 15 downto 0 );
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95
    ov_wb_burst_control     :   out std_logic_vector( 15 downto 0 );
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    --
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    -- STATUS Input
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    iv_test_check_bl_rd     :   in  std_logic_vector( 31 downto 0 );
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    iv_test_check_bl_ok     :   in  std_logic_vector( 31 downto 0 );
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    iv_test_check_bl_err    :   in  std_logic_vector( 31 downto 0 );
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    iv_test_check_error     :   in  std_logic_vector( 31 downto 0 );
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    iv_test_check_err_data  :   in  std_logic_vector( 15 downto 0 )
103
);
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end component block_check_wb_config_slave;
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106
end package block_check_wb_config_slave_pkg;
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----------------------------------------------------------------------------------
108
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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113
library work;
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use work.ctrl_ram16_v1_pkg.all;
115
use work.host_pkg.all;
116
 
117
entity block_check_wb_config_slave is
118
generic
119
(
120
    BLOCK_ID   : in std_logic_vector( 15 downto 0 ):=x"0000"; -- идентификатор модуля
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    BLOCK_VER  : in std_logic_vector( 15 downto 0 ):=x"0000"  -- версия модуля
122
);
123
port
124
(
125
    --
126
    -- SYS_CON
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    i_clk : in  STD_LOGIC;
128
    i_rst : in  STD_LOGIC;
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    --
130
    -- WB CFG SLAVE
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    iv_wbs_cfg_addr     :   in  std_logic_vector(  7 downto 0 );
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    iv_wbs_cfg_data     :   in  std_logic_vector( 63 downto 0 );
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    iv_wbs_cfg_sel      :   in  std_logic_vector(  7 downto 0 );    -- wor now, we NC this wires
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    i_wbs_cfg_we        :   in  std_logic;
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    i_wbs_cfg_cyc       :   in  std_logic;
136
    i_wbs_cfg_stb       :   in  std_logic;
137
    iv_wbs_cfg_cti      :   in  std_logic_vector(  2 downto 0 );
138
    iv_wbs_cfg_bte      :   in  std_logic_vector(  1 downto 0 );
139
 
140
    ov_wbs_cfg_data     :   out std_logic_vector( 63 downto 0 );
141
    o_wbs_cfg_ack       :   out std_logic;
142
    o_wbs_cfg_err       :   out std_logic;
143
    o_wbs_cfg_rty       :   out std_logic;
144
    --
145
    -- CONTROL Outputs
146
    ov_test_check_ctrl      :   out std_logic_vector( 15 downto 0 );
147
    ov_test_check_size      :   out std_logic_vector( 15 downto 0 );
148
    ov_test_check_err_adr   :   out std_logic_vector( 15 downto 0 );
149
 
150
    ov_wb_burst_control     :   out std_logic_vector( 15 downto 0 );
151
    --
152
    -- STATUS Input
153
    iv_test_check_bl_rd     :   in  std_logic_vector( 31 downto 0 );
154
    iv_test_check_bl_ok     :   in  std_logic_vector( 31 downto 0 );
155
    iv_test_check_bl_err    :   in  std_logic_vector( 31 downto 0 );
156
    iv_test_check_error     :   in  std_logic_vector( 31 downto 0 );
157
    iv_test_check_err_data  :   in  std_logic_vector( 15 downto 0 )
158
);
159
end block_check_wb_config_slave;
160
 
161
architecture rtl of block_check_wb_config_slave is
162
----------------------------------------------------------------------------------
163
--
164
-- Define CONSTANTs
165
constant    ct_bl_rom   :   bh_rom:=(
166
                                        0=> BLOCK_ID,   -- 
167
                                        1=> BLOCK_VER,  -- 
168
                                        2=> x"5504",    -- 2=> Device_ID,
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                                        3=> x"0210",    -- 3=> Revision,
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                                        4=> x"0104",    -- 4=> PLD_VER,  
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                                        5=> x"0000",
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                                        6=> x"0000",
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                                        7=> x"0000"
174
                                    );
175
--
176
-- Define BL_RAM stuff:
177
signal  sv_bl_ram_adr       :   std_logic_vector( 4 downto 0):= (others => '0');
178
signal  sv_bl_ram_data_in   :   std_logic_vector(15 downto 0):= (others => '0');
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signal  sv_bl_ram_data_out  :   std_logic_vector(15 downto 0):= (others => '0');
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signal  s_bl_ram_data_we    :   std_logic:= '0';
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--
182
-- DEFINE WB_FSM (required for build correct WB_ACK) stuff:
183
signal  sv_wbs_cfg_ack_counter  :   std_logic:='0';
184
--
185
-- Define additional WB signals:
186
signal  s_wbs_active_wr     :   std_logic;
187
signal  s_wbs_active_rd     :   std_logic;
188
signal  s_wbs_active        :   std_logic;
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signal  s_wbs_wr_ena        :   std_logic;
190
----------------------------------------------------------------------------------
191
begin
192
----------------------------------------------------------------------------------
193
--
194
-- WB ACTIVE/ENA flag (for RD/WR and for any WB activity)
195
--
196
s_wbs_active_wr <= '1' when (
197
                                i_wbs_cfg_cyc='1' and i_wbs_cfg_stb='1' and i_wbs_cfg_we='1' and    -- all strobes OK
198
                                (iv_wbs_cfg_cti="000") and (iv_wbs_cfg_bte="00")                    -- type of transfer OK
199
                            ) else '0';
200
 
201
s_wbs_active_rd <= '1' when (
202
                                i_wbs_cfg_cyc='1' and i_wbs_cfg_stb='1' and i_wbs_cfg_we='0' and
203
                                (iv_wbs_cfg_cti="000") and (iv_wbs_cfg_bte="00")
204
                            ) else '0';
205
 
206
s_wbs_active    <= '1' when (
207
                                i_wbs_cfg_cyc='1' and i_wbs_cfg_stb='1'                      and
208
                                (iv_wbs_cfg_cti="000") and (iv_wbs_cfg_bte="00")
209
                            ) else '0';
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211
s_wbs_wr_ena    <= '1' when (
212
                                s_wbs_active_wr='1'             and     -- have ACTIVE WR flag
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                                (sv_wbs_cfg_ack_counter='1')            -- present WB_ACK source
214
                            ) else '0';
215
----------------------------------------------------------------------------------
216
--
217
-- WB Write process
218
--
219
WB_WRITE    :   process (i_clk, i_rst)
220
    begin
221
        if (i_rst='1') then             -- RST
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            ov_test_check_ctrl      <= (others => '0');
223
            ov_test_check_size      <= (others => '0');
224
            ov_test_check_err_adr   <= (others => '0');
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            ov_wb_burst_control     <= (others => '0');
226
        elsif (rising_edge(i_clk)) then -- WRK
227
            if (s_wbs_wr_ena='1') then
228
                case(iv_wbs_cfg_addr(7 downto 0)) is
229
                    -- 
230
                    when x"40"  => ov_test_check_ctrl       <= iv_wbs_cfg_data( 15 downto 0);
231
                    when x"48"  => ov_test_check_size       <= iv_wbs_cfg_data( 15 downto 0);
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                    when x"50"  => ov_test_check_err_adr    <= iv_wbs_cfg_data( 15 downto 0);
233
                    -- 
234
                    when x"58"  => ov_wb_burst_control      <= iv_wbs_cfg_data( 15 downto 0);
235
                    when others => null;
236
                end case;
237
            end if;
238
        end if;
239
end process WB_WRITE;
240
----------------------------------------------------------------------------------
241
--
242
-- WB Read process
243
--
244
WB_READ     :   process (i_clk, i_rst)
245
    begin
246
        if (i_rst='1') then             -- RST
247
            ov_wbs_cfg_data <= (others => '0');
248
        elsif (rising_edge(i_clk)) then -- WRK
249
            if (s_wbs_active_rd='1') then
250
                case(iv_wbs_cfg_addr(7 downto 0)) is
251
                    -- STS MM region
252
                    when x"80"  => ov_wbs_cfg_data(31 downto 0) <= iv_test_check_bl_rd;
253
                    when x"88"  => ov_wbs_cfg_data(31 downto 0) <= iv_test_check_bl_ok;
254
                    when x"90"  => ov_wbs_cfg_data(31 downto 0) <= iv_test_check_bl_err;
255
                    when x"98"  => ov_wbs_cfg_data(31 downto 0) <= iv_test_check_error;
256
                    when x"A0"  => ov_wbs_cfg_data(15 downto 0) <= iv_test_check_err_data;
257
                    -- OTHER case -> BL_RAM MM region
258
                    when others =>  ov_wbs_cfg_data(15 downto 0) <= sv_bl_ram_data_out;
259
                end case;
260
            end if;
261
        end if;
262
end process WB_READ;
263
----------------------------------------------------------------------------------
264
--
265
-- WB ACK process
266
--
267
WB_ACK_CNT  :   process (i_clk, i_rst)
268
    begin
269
        if (i_rst='1') then             -- RST
270
            sv_wbs_cfg_ack_counter <= '0';
271
        elsif (rising_edge(i_clk)) then -- WRK:
272
            if (s_wbs_active='1') then  -- WB Transfer in progress
273
                --sv_wbs_cfg_ack_counter <= sv_wbs_cfg_ack_counter + '1';
274
                if (sv_wbs_cfg_ack_counter='0') then
275
                    sv_wbs_cfg_ack_counter <= '1';
276
                else
277
                    sv_wbs_cfg_ack_counter <= '0';
278
                end if;
279
            else                        -- no WB Transfer
280
                sv_wbs_cfg_ack_counter <= '0';
281
            end if;
282
        end if;
283
end process WB_ACK_CNT;
284
-- Define WB_ACK
285
o_wbs_cfg_ack <= '1' when   (
286
                                sv_wbs_cfg_ack_counter='1' and
287
                                i_wbs_cfg_cyc='1' and i_wbs_cfg_stb='1' -- add controls for avoid problems in anarranged transfers
288
                            ) else '0';
289
----------------------------------------------------------------------------------
290
--
291
-- Instaniate BL_RAM (contain CONSTANTs and RD values for COMMAND registers)
292
--
293
BL_RAM  :   ctrl_ram16_v1
294
generic map
295
(
296
    rom         => ct_bl_rom            -- значения констант
297
)
298
port map
299
(
300
    clk         => i_clk,               -- Тактовая частота
301
 
302
    adr         => sv_bl_ram_adr,       -- адрес 
303
    data_in     => sv_bl_ram_data_in,   -- вход данных
304
    data_out    => sv_bl_ram_data_out,  -- выход данных
305
 
306
    data_we     => s_bl_ram_data_we     -- 1 - запись данных
307
);
308
-- Define BL_RAM ADDR
309
sv_bl_ram_adr       <= iv_wbs_cfg_addr( 7 downto 3);    -- 8B granularity Transfers (cut [2:0] addr bits)
310
-- DEFINE BL_RAM DATA_IN
311
sv_bl_ram_data_in   <= iv_wbs_cfg_data(15 downto 0);    -- Cut only LS 16bit
312
-- DEFINE BL_RAM DATA_WRITE
313
s_bl_ram_data_we    <= s_wbs_wr_ena;                    -- WB_WE signal is OK
314
----------------------------------------------------------------------------------
315
--
316
-- MODULE OUTPUTs routing:
317
--
318
-- WB_ERR deal
319
o_wbs_cfg_err   <= '1' when (
320
                                i_wbs_cfg_cyc='1' and i_wbs_cfg_stb='1' and             -- all strobes OK
321
                                ( (iv_wbs_cfg_cti/="000") or (iv_wbs_cfg_bte/="00") )   -- BUT type of transfer is NOT OK
322
                            ) else '0';
323
-- WB_RTY deal
324
o_wbs_cfg_rty   <= '0'; -- nothing to report for now
325
----------------------------------------------------------------------------------
326
end rtl;
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