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-- Company: ;)
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-- Engineer: Kuzmi4
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--
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-- Create Date: 17:40:25 05/21/2010
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-- Design Name:
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-- Module Name: block_test_check_wb - rtl
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-- Project Name: DS_DMA
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-- Target Devices: any
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-- Tool versions: any
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-- Description:
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--
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-- Top-level module for TEST_CHECK_WB functionality
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-- (NB!!! --> module contain syb-modules with restrictions)
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Revision 0.02 - update BLOCK_ID/BLOCK_VER logic - now it's inner ID of component
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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package block_test_check_wb_pkg is
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component block_test_check_wb is
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port
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(
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--
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-- SYS_CON
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i_clk : in STD_LOGIC;
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i_rst : in STD_LOGIC;
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--
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-- WB CFG SLAVE IF
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iv_wbs_cfg_addr : in std_logic_vector( 7 downto 0 );
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iv_wbs_cfg_data : in std_logic_vector( 63 downto 0 );
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iv_wbs_cfg_sel : in std_logic_vector( 7 downto 0 );
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i_wbs_cfg_we : in std_logic;
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i_wbs_cfg_cyc : in std_logic;
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i_wbs_cfg_stb : in std_logic;
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iv_wbs_cfg_cti : in std_logic_vector( 2 downto 0 );
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iv_wbs_cfg_bte : in std_logic_vector( 1 downto 0 );
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ov_wbs_cfg_data : out std_logic_vector( 63 downto 0 );
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o_wbs_cfg_ack : out std_logic;
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o_wbs_cfg_err : out std_logic;
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o_wbs_cfg_rty : out std_logic;
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--
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-- WB BURST SLAVE IF (WRITE-ONLY IF)
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iv_wbs_burst_addr : in std_logic_vector( 11 downto 0 );
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iv_wbs_burst_data : in std_logic_vector( 63 downto 0 );
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iv_wbs_burst_sel : in std_logic_vector( 7 downto 0 );
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i_wbs_burst_we : in std_logic;
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i_wbs_burst_cyc : in std_logic;
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i_wbs_burst_stb : in std_logic;
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iv_wbs_burst_cti : in std_logic_vector( 2 downto 0 );
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iv_wbs_burst_bte : in std_logic_vector( 1 downto 0 );
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o_wbs_burst_ack : out std_logic;
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o_wbs_burst_err : out std_logic;
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o_wbs_burst_rty : out std_logic;
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--
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-- WB IRQ lines
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o_wbs_irq_0 : out std_logic;
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o_wbs_irq_dmar : out std_logic
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);
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end component block_test_check_wb;
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end package block_test_check_wb_pkg;
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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library work;
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use work.cl_test_check_pkg.all;
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use work.block_check_wb_config_slave_pkg.all;
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use work.block_check_wb_pkg.all;
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entity block_test_check_wb is
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port
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(
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--
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-- SYS_CON
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i_clk : in STD_LOGIC;
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i_rst : in STD_LOGIC;
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--
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-- WB CFG SLAVE IF
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iv_wbs_cfg_addr : in std_logic_vector( 7 downto 0 );
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iv_wbs_cfg_data : in std_logic_vector( 63 downto 0 );
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iv_wbs_cfg_sel : in std_logic_vector( 7 downto 0 );
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i_wbs_cfg_we : in std_logic;
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i_wbs_cfg_cyc : in std_logic;
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i_wbs_cfg_stb : in std_logic;
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iv_wbs_cfg_cti : in std_logic_vector( 2 downto 0 );
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iv_wbs_cfg_bte : in std_logic_vector( 1 downto 0 );
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ov_wbs_cfg_data : out std_logic_vector( 63 downto 0 );
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o_wbs_cfg_ack : out std_logic;
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o_wbs_cfg_err : out std_logic;
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o_wbs_cfg_rty : out std_logic;
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--
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-- WB BURST SLAVE IF (WRITE-ONLY IF)
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iv_wbs_burst_addr : in std_logic_vector( 11 downto 0 );
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iv_wbs_burst_data : in std_logic_vector( 63 downto 0 );
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iv_wbs_burst_sel : in std_logic_vector( 7 downto 0 );
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i_wbs_burst_we : in std_logic;
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i_wbs_burst_cyc : in std_logic;
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i_wbs_burst_stb : in std_logic;
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iv_wbs_burst_cti : in std_logic_vector( 2 downto 0 );
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iv_wbs_burst_bte : in std_logic_vector( 1 downto 0 );
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o_wbs_burst_ack : out std_logic;
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o_wbs_burst_err : out std_logic;
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o_wbs_burst_rty : out std_logic;
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--
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-- WB IRQ lines
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o_wbs_irq_0 : out std_logic;
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o_wbs_irq_dmar : out std_logic
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);
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end block_test_check_wb;
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architecture rtl of block_test_check_wb is
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----------------------------------------------------------------------------------
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--
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-- Define TEST_CHECK CTRL/STS stuff:
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signal sv_test_check_ctrl : std_logic_vector( 15 downto 0 );
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signal sv_test_check_size : std_logic_vector( 15 downto 0 );
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signal sv_test_check_bl_rd : std_logic_vector( 31 downto 0 );
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signal sv_test_check_bl_ok : std_logic_vector( 31 downto 0 );
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signal sv_test_check_bl_err : std_logic_vector( 31 downto 0 );
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signal sv_test_check_error : std_logic_vector( 31 downto 0 );
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signal sv_test_check_err_adr : std_logic_vector( 15 downto 0 );
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signal sv_test_check_err_data : std_logic_vector( 15 downto 0 );
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signal sv_wb_burst_control : std_logic_vector( 15 downto 0 );
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-- Define TEST_CHECK Data-In stuff:
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signal sv_test_check_data : std_logic_vector( 63 downto 0 );
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signal s_test_check_data_ena : std_logic;
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-- Define TEST_CHECK RST_n stuff:
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signal s_test_check_rst_n : std_logic;
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----------------------------------------------------------------------------------
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begin
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----------------------------------------------------------------------------------
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--
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-- Instaniate WB_CFG_SLAVE
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--
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WB_CFG_SLAVE : block_check_wb_config_slave
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generic map
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(
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BLOCK_ID => x"0001", -- идентификатор модуля
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BLOCK_VER => x"0100" -- версия модуля
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)
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port map
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(
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--
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-- SYS_CON
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i_clk => i_clk,
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i_rst => i_rst,
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--
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-- WB CFG SLAVE IF
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iv_wbs_cfg_addr => iv_wbs_cfg_addr,
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iv_wbs_cfg_data => iv_wbs_cfg_data,
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iv_wbs_cfg_sel => iv_wbs_cfg_sel,
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i_wbs_cfg_we => i_wbs_cfg_we,
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i_wbs_cfg_cyc => i_wbs_cfg_cyc,
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i_wbs_cfg_stb => i_wbs_cfg_stb,
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iv_wbs_cfg_cti => iv_wbs_cfg_cti,
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iv_wbs_cfg_bte => iv_wbs_cfg_bte,
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ov_wbs_cfg_data => ov_wbs_cfg_data,
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o_wbs_cfg_ack => o_wbs_cfg_ack,
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o_wbs_cfg_err => o_wbs_cfg_err,
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o_wbs_cfg_rty => o_wbs_cfg_rty,
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--
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-- CONTROL Outputs
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ov_test_check_ctrl => sv_test_check_ctrl,
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ov_test_check_size => sv_test_check_size,
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ov_test_check_err_adr => sv_test_check_err_adr,
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ov_wb_burst_control => sv_wb_burst_control,
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--
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-- STATUS Input
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iv_test_check_bl_rd => sv_test_check_bl_rd,
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iv_test_check_bl_ok => sv_test_check_bl_ok,
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iv_test_check_bl_err => sv_test_check_bl_err,
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iv_test_check_error => sv_test_check_error,
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iv_test_check_err_data => sv_test_check_err_data
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);
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----------------------------------------------------------------------------------
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--
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-- Instaniate TEST_CHECK
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--
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TEST_CHECK : cl_test_check
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port map
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(
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---- Global ----
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reset => s_test_check_rst_n, -- 0 - сброс
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clk => i_clk, -- тактовая частота
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---- DIO_OUT ----
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do_clk => i_clk, -- тактовая частота чтения из FIFO
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do_data => sv_test_check_data,
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do_data_en => s_test_check_data_ena, -- 1 - передача данных из dio_out
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---- Управление ----
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test_check_ctrl => sv_test_check_ctrl,
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test_check_size => sv_test_check_size, -- размер в блоках по 512x64 (4096 байт)
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test_check_bl_rd => sv_test_check_bl_rd,
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test_check_bl_ok => sv_test_check_bl_ok,
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test_check_bl_err => sv_test_check_bl_err,
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test_check_error => sv_test_check_error,
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test_check_err_adr => sv_test_check_err_adr,
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test_check_err_data => sv_test_check_err_data
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);
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----------------------------------------------------------------------------------
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--
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-- Instaniate WB_BURST_SLAVE (provide Input-Only Functionality)
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--
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WB_BURST_SLAVE : block_check_wb_burst_slave
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port map
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(
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--
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-- SYS_CON
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i_clk => i_clk,
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i_rst => i_rst,
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--
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-- WB BURST SLAVE IF (READ-ONLY IF)
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iv_wbs_burst_addr => iv_wbs_burst_addr,
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iv_wbs_burst_data => iv_wbs_burst_data,
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iv_wbs_burst_sel => iv_wbs_burst_sel,
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i_wbs_burst_we => i_wbs_burst_we,
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i_wbs_burst_cyc => i_wbs_burst_cyc,
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i_wbs_burst_stb => i_wbs_burst_stb,
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iv_wbs_burst_cti => iv_wbs_burst_cti,
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iv_wbs_burst_bte => iv_wbs_burst_bte,
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o_wbs_burst_ack => o_wbs_burst_ack,
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o_wbs_burst_err => o_wbs_burst_err,
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o_wbs_burst_rty => o_wbs_burst_rty,
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--
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-- TEST_CHECK IF (Output data with ENA)
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ov_test_check_data => sv_test_check_data,
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o_test_check_data_ena => s_test_check_data_ena,
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--
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-- TEST_CHECK Controls (WBS_CFG)
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iv_control => sv_wb_burst_control
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);
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----------------------------------------------------------------------------------
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--
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-- MODULE INNER wires routing:
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--
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-- define
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-- define TEST_CHECK.reset - it is RST_n signal
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s_test_check_rst_n <= not i_rst;
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----------------------------------------------------------------------------------
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--
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-- MODULE OUTPUTs routing:
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--
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-- DMAR WB IRQ deal
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o_wbs_irq_dmar <= sv_test_check_ctrl(5); -- TEST_CHECK_CTRL.START -> 1 - разрешение работы
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-- WB IRQ deal
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o_wbs_irq_0 <= '0'; -- No EVENTs for now
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----------------------------------------------------------------------------------
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end rtl;
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