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[/] [pcie_ds_dma/] [trunk/] [core/] [wishbone/] [block_test_check/] [cl_test_check.vhd] - Blame information for rev 2

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1 2 dsmv
-------------------------------------------------------------------------------
2
--
3
-- Title       : cl_test_check
4
-- Author      : Dmitry Smekhov
5
-- Company     : Instrumental Systems
6
-- E-mail      : dsmv@insys.ru
7
--
8
-- Version     : 1.0
9
--
10
-------------------------------------------------------------------------------
11
--
12
-- Description :        Óçåë ïðîâåðêè âõîäíîãî ïîòîêà
13
--                              
14
--              Òåñòîâàÿ ïîñëåäîâàòåëüíîñòü ïðåäñòàâëÿåò ñîáîé íàáîð áëîêîâ. 
15
--              Ðàçìåð áëîêà çàäà¸òñÿ êðàòíûì ñòðàíèöû ðàçìåðîì 4 êèëîáàéòà 
16
--              (512 ñëîâ ïî 64 áèòà)
17
--              Ïåðâîå 64-õ ðàçðÿäíîå ñëîâî â áëîêå ñîäåðæèò ñèãíàòóðó è ïîðÿäêîâûé íîìåð.       
18
--                  31..0  - ñèãíàòóðà 0xA5A50123
19
--                      63..32 - ïîðÿäêîâûé íîìåð áëîêà
20
--
21
--              Ñîäåðæèìîå áëîêà çàâèñèò îò åãî ïîðÿäêîâîãî íîìåðà â ïîñëåäîâàòåëüíîñòè.  
22
--
23
--              Ñîäåðæèìîå áëîêà:
24
--              0 - Áåãóùàÿ åäèíèöà ïî 64-ì ðàçðÿäàì
25
--              1 - Áåãóùèé íîëü ïî 64-ì ðàçðÿäàì
26
--              2 - Áåãóùàÿ åäèíèöà ñ èíâåðñèåé ïî 64-ì ðàçðÿäàì
27
---                     ׸òíûå íîìåðà ñëîâ - áåãóùàÿ åäèíèöà ïî 64-ì ðàçðÿäàì
28
--                      Íå÷¸òíûå íîìåðà - èíâåðñèÿ ïðåäûäóùåãî ñëîâà             
29
--              3 - Áåãóùàÿ åäèíèöà â áëîêå
30
--                      Íîìåð ñëîâà ñðàâíèâàåòñÿ ñ íîìåðîì áëîêà (ñðàâíèâàþòñÿ âîñåìü ìëàäøèé ðàçðÿäîâ)
31
--                      Ïðè ñîâïàäåíèè - â ñëîâî çàïèñûâàåòñÿ áåãóùàÿ 1.
32
--                      Îñòàëüíûå ñëîâà - çíà÷åíèå íîëü.
33
--              4 - Áåãóùèé íîëü ñ èíâåðñèåé ïî 64-ì ðàçðÿäàì
34
--                      ׸òíûå íîìåðà - áåãóùèé íîëü ïî 64-ì ðàçðÿäàì
35
--                      Íå÷¸òíûå íîìåðà - èíâåðñèÿ ïðåäûäóùåãî ñëîâà             
36
--              5 - Áåãóùèé íîëü à â áëîêå
37
--                      Íîìåð ñëîâà ñðàâíèâàåòñÿ ñ íîìåðîì áëîêà (ñðàâíèâàþòñÿ âîñåìü ìëàäøèé ðàçðÿäîâ)
38
--                      Ïðè ñîâïàäåíèè - â ñëîâî çàïèñûâàåòñÿ áåãóùèé 0.
39
--                      Îñòàëüíûå ñëîâà - çíà÷åíèå 0xFFFFFFFFFFFFFFFF.
40
--              6,7 - Ñ÷¸ò÷èê ïî 64-ì ðàçðÿäàì
41
--                      ׸òíûå íîìåðà - çíà÷åíèå ñ÷¸ò÷èêà
42
--                      Íå÷¸òíûå íîìåðà - èíâåðñèÿ ïðåäûäóùåãî ñëîâà
43
--              8,9 - Ïñåâäîñëó÷àéíàÿ ïîñëåäîâàòåëüíîñòü
44
--                      Ôîðìèðóåòñÿ Ì-ïîñëåäîâàòåëüíîñòü ïî 64 ðàçðÿäàì.
45
--                      Íà÷àëüíîå çíà÷åíèå - 1
46
--                      Ñëîâî ôîðìèðóåòñÿ ñäâèãîì íà îäèí ðàçðÿä âïðàâî.
47
--                       ìëàäøèé ðàçðÿä ñëîâà çàïèñûâàåòñÿ çíà÷åíèå x[63] xor x[62]
48
--                                                                                                                              
49
--
50
--              Äëÿ ðåæèìà ñ÷¸ò÷èêà è ïñåâäîñëó÷àéíîé ïîñëåäîâàòåëüíîñòè íà÷àëüíîå çíà÷åíèå
51
--              ôîðìèðóåòñÿ ïðè èíèöèàëèçàöèè òåñòîâîé ïîñëåäîâàòåëüíîñòè.
52
--              Äëÿ îñòàëüíûõ ðåæèìîâ - ïðè èíèöèàëèçàöèè ïðîâåðêè áëîêà
53
--
54
--
55
--              Ðåãèñòð test_check_ctrl
56
--                         
57
--                              0 - 1 ñáðîñ óçëà
58
--                              5 - 1 ñòàðò ïðè¸ìà äàííûõ
59
--                              7 - 1 ôèêñèðîâàííûé òèï áëîêà
60
--                              11..8 - íîìåð áëîêà ïðè test_check_ctrl[7]=1
61
--                              
62
 
63
-------------------------------------------------------------------------------
64
--
65
-- Version     1.0  
66
--
67
-------------------------------------------------------------------------------
68
 
69
 
70
 
71
 
72
library ieee;
73
use ieee.std_logic_1164.all;
74
 
75
package cl_test_check_pkg is
76
 
77
component cl_test_check is
78
        port(
79
 
80
                ---- Global ----
81
                reset           : in std_logic;         -- 0 - ñáðîñ
82
                clk                     : in std_logic;         -- òàêòîâàÿ ÷àñòîòà
83
 
84
                ---- DIO_OUT ----
85
                do_clk          : in  std_logic;        -- òàêòîâàÿ ÷àñòîòà ÷òåíèÿ èç FIFO
86
                do_data         : in  std_logic_vector( 63 downto 0 );
87
                do_data_en      : in  std_logic;        -- 1 - ïåðåäà÷à äàííûõ èç dio_out
88
 
89
 
90
                ---- Óïðàâëåíèå ----
91
                test_check_ctrl : in  std_logic_vector( 15 downto 0 );
92
                test_check_size : in  std_logic_vector( 15 downto 0 );    -- ðàçìåð â áëîêàõ ïî 512x64 (4096 áàéò)
93
                test_check_bl_rd        : out std_logic_vector( 31 downto 0 );
94
                test_check_bl_ok        : out std_logic_vector( 31 downto 0 );
95
                test_check_bl_err       : out std_logic_vector( 31 downto 0 );
96
                test_check_error        : out std_logic_vector( 31 downto 0 );
97
                test_check_err_adr      : in  std_logic_vector( 15 downto 0 );
98
                test_check_err_data: out std_logic_vector( 15 downto 0 )
99
 
100
        );
101
end component;
102
 
103
end package;
104
 
105
 
106
library ieee;
107
use ieee.std_logic_1164.all;
108
use ieee.std_logic_arith.all;
109
use ieee.std_logic_unsigned.all;
110
 
111
library unisim;
112
use unisim.vcomponents.all;
113
 
114
 
115
entity cl_test_check is
116
        port(
117
 
118
                ---- Global ----
119
                reset           : in std_logic;         -- 0 - ñáðîñ
120
                clk                     : in std_logic;         -- òàêòîâàÿ ÷àñòîòà
121
 
122
                ---- DIO_OUT ----
123
                do_clk          : in  std_logic;        -- òàêòîâàÿ ÷àñòîòà ÷òåíèÿ èç FIFO
124
                do_data         : in  std_logic_vector( 63 downto 0 );
125
                do_data_en      : in  std_logic;        -- 1 - ïåðåäà÷à äàííûõ èç dio_out
126
 
127
 
128
                ---- Óïðàâëåíèå ----
129
                test_check_ctrl : in  std_logic_vector( 15 downto 0 );
130
                test_check_size : in  std_logic_vector( 15 downto 0 );    -- ðàçìåð â áëîêàõ ïî 512x64 (4096 áàéò)
131
                test_check_bl_rd        : out std_logic_vector( 31 downto 0 );
132
                test_check_bl_ok        : out std_logic_vector( 31 downto 0 );
133
                test_check_bl_err       : out std_logic_vector( 31 downto 0 );
134
                test_check_error        : out std_logic_vector( 31 downto 0 );
135
                test_check_err_adr      : in  std_logic_vector( 15 downto 0 );
136
                test_check_err_data: out std_logic_vector( 15 downto 0 )
137
 
138
        );
139
end cl_test_check;
140
 
141
 
142
architecture cl_test_check of cl_test_check is
143
 
144
signal  block_rd                : std_logic_vector( 31 downto 0 );
145
signal  block_ok                : std_logic_vector( 31 downto 0 );
146
signal  block_err               : std_logic_vector( 31 downto 0 );
147
signal  total_err               : std_logic_vector( 31 downto 0 );
148
 
149
signal  data_expect             : std_logic_vector( 63 downto 0 );
150
 
151
signal  cnt1                    : std_logic_vector( 24 downto 0 );
152
signal  cnt1_z                  : std_logic;
153
signal  cnt1_eq                 : std_logic;
154
 
155
signal  rst                             : std_logic;
156
signal  data_en                 : std_logic;    -- 1 - ïðè¸ì ñëîâà äàííûõ  
157
signal  data_en_z               : std_logic;
158
signal  do_data_z               : std_logic_vector( 63 downto 0 );
159
 
160
signal  data_ex0                : std_logic_vector( 63 downto 0 );
161
signal  data_ex1                : std_logic_vector( 63 downto 0 );
162
signal  data_ex2                : std_logic_vector( 63 downto 0 );
163
signal  data_ex3                : std_logic_vector( 63 downto 0 );
164
signal  data_ex4                : std_logic_vector( 63 downto 0 );
165
signal  data_ex5                : std_logic_vector( 63 downto 0 );
166
 
167
 
168
signal  block_mode              : std_logic_vector( 3 downto 0 );
169
signal  word_error              : std_logic;
170
signal  flag_error              : std_logic;    -- 1 - ïðèçíàê îøèáêè ïðè ïðè¸ìà áëîêà
171
signal  flag_error_clr  : std_logic;    -- 1 - ñáðîñ flag_error
172
 
173
signal  data_error              : std_logic_vector( 191 downto 0 );
174
signal  data_error_wr   : std_logic;
175
signal  data_error_wr1  : std_logic;
176
signal  data_error_ovr  : std_logic;
177
signal  data_error_out  : std_logic_vector( 191 downto 0 );
178
signal  err_data                : std_logic_vector( 15 downto 0 );
179
 
180
signal  block_ok_en             : std_logic;
181
 
182
begin
183
 
184
pr_cnt1: process( do_clk ) begin
185
        if( rising_edge( do_clk ) ) then
186
                if( rst='0' or (cnt1_eq='1' and data_en='1') ) then
187
                        cnt1( 24 downto 0 )   <= (others=>'0') after 1 ns;
188
                elsif( data_en='1' ) then
189
                        cnt1 <= cnt1 + 1 after 1 ns;
190
                end if;
191
        end if;
192
end process;
193
 
194
pr_cnt1_z: process( do_clk ) begin
195
        if( rising_edge( do_clk ) ) then
196
 
197
                if( rst='0' ) then
198
                        cnt1_z <= '1' after 1 ns;
199
                        cnt1_eq <= '0' after 1 ns;
200
                elsif( data_en='1' ) then
201
 
202
                        if( cnt1_eq='1' ) then
203
                                cnt1_z <= '1' after 1 ns;
204
                        else
205
                                cnt1_z <= '0' after 1 ns;
206
                        end if;
207
 
208
                        if( cnt1( 24 downto 9 )=test_check_size-1 and cnt1( 8 downto 0 )="111111110" ) then
209
                                cnt1_eq <= '1' after 1 ns;
210
                        else
211
                                cnt1_eq <= '0' after 1 ns;
212
                        end if;
213
                end if;
214
 
215
        end if;
216
end process;
217
 
218
 
219
 
220
data_en <= do_data_en;
221
 
222
rst <= reset and not test_check_ctrl(0);
223
 
224
pr_block_mode: process( do_clk ) begin
225
        if( rising_edge( do_clk ) ) then
226
                if( rst='0' ) then
227
                        block_mode <= "0000" after 1 ns;
228
                elsif( test_check_ctrl(7)='1' ) then
229
                        block_mode <= test_check_ctrl( 11 downto 8 ) after 1 ns;
230
                elsif( data_en='1' and cnt1_eq='1' ) then
231
                                if( block_mode="1001" ) then
232
                                        block_mode <= "0000" after 1 ns;
233
                                else
234
                                        block_mode <= block_mode + 1 after 1 ns;
235
                                end if;
236
                end if;
237
        end if;
238
end process;
239
 
240
pr_block_rd: process( do_clk ) begin
241
        if( rising_edge( do_clk ) ) then
242
                if( rst='0' ) then
243
                        block_rd <= (others=>'0') after 1 ns;
244
                elsif( data_en='1' and cnt1_eq='1' ) then
245
                        block_rd <= block_rd + 1 after 1 ns;
246
                end if;
247
        end if;
248
end process;
249
 
250
 
251
pr_data_expect: process( do_clk ) begin
252
        if( rising_edge( do_clk ) ) then
253
          if( rst='0' ) then
254
                  data_ex4 <= (others=>'0') after 1 ns;
255
                  data_ex5 <= (0=>'1', others=>'0') after 1 ns;
256
                  data_ex0 <= x"0000000000000001" after 1 ns;
257
          elsif( data_en='1' ) then
258
                if( cnt1_z='1' ) then
259
                        data_expect( 31 downto 0 ) <= x"A5A50123" after 1 ns;
260
                        data_expect( 63 downto 32 ) <= block_rd after 1 ns;
261
                        case( block_mode( 3 downto 0 ) ) is
262
                          when "0000" => -- Áåãóùàÿ 1 ïî 64-ì ðàçðÿäàì
263
                                data_ex0 <= x"0000000000000001" after 1 ns;
264
                          when "0001" => -- Áåãóùèé 0 ïî 64-ì ðàçðÿäàì
265
                                data_ex0 <= not x"0000000000000001" after 1 ns;
266
                          when "0010" => -- Áåãóùàÿ 1 ñ èíâåðñèåé  ïî 64-ì ðàçðÿäàì
267
                                data_ex1 <= x"0000000000000001" after 1 ns;
268
                          when "0011" => -- Áåãóùèé 0 ñ èíâåðñèåé  ïî 64-ì ðàçðÿäàì
269
                                data_ex1 <= not x"0000000000000001" after 1 ns;
270
                          when "0100" => -- Áåãóùàÿ 1 â áëîêå 0
271
                                data_ex2 <= x"0000000000000001" after 1 ns;
272
                                data_ex3 <= (others=>'0');
273
                          when "0101" => -- Áåãóùèé 0 â áëîêå 1
274
                                data_ex2 <= not x"0000000000000001" after 1 ns;
275
                                data_ex3 <= (others=>'1') after 1 ns;
276
 
277
                          when others=> null;
278
                        end case;
279
                else
280
                        case( block_mode( 3 downto 0 ) )is
281
                          when "0000" | "0001" =>
282
                                data_expect <= data_ex0 after 1 ns;
283
                                data_ex0( 63 downto 1 ) <= data_ex0( 62 downto 0 ) after  1 ns;
284
                                data_ex0( 0 ) <= data_ex0( 63 ) after 1 ns;
285
 
286
                          when "0010" | "0011" => -- Áåãóùèé 0 ñ èíâåðñèåé  ïî 32-ì ðàçðÿäàì
287
--                        when "0011" => -- Áåãóùèé 0 ñ èíâåðñèåé  ïî 64-ì ðàçðÿäàì
288
                                if( cnt1(0)='0' ) then
289
                                        data_expect <= data_ex1 after 1 ns;
290
                                else
291
                                        data_expect <= not data_ex1 after 1 ns;
292
                                        data_ex1( 63 downto 1 ) <= data_ex1( 62 downto 0 ) after  1 ns;
293
                                        data_ex1( 0 ) <= data_ex1( 63 ) after 1 ns;
294
                                end if;
295
                          when "0100" | "0101" => -- Áåãóùèé 0 â áëîêå 1
296
--                        when "0111" => -- Áåãóùèé 1 â áëîêå 0
297
                                if( cnt1( 7 downto 0 )=block_rd( 7 downto 0 ) )then
298
                                        data_expect <= data_ex2 after 1 ns;
299
                                        data_ex2( 63 downto 1 ) <= data_ex2( 62 downto 0 ) after  1 ns;
300
                                        data_ex2( 0 ) <= data_ex2( 63 ) after 1 ns;
301
                                else
302
                                        data_expect <= data_ex3 after 1 ns;
303
                                end if;
304
 
305
                          when "0110" | "0111" => -- Ñ÷¸ò÷èê 
306
                            if( cnt1(0)='0' ) then
307
                                        data_expect <= data_ex4 after 1 ns;
308
                                else
309
                                        data_expect <= not data_ex4 after 1 ns;
310
--                                      data_ex4 <= data_ex4 + x"0000000000000001";
311
                                        data_ex4(31 downto 0) <= data_ex4(31 downto 0) + 1;
312
                                        if (data_ex4(31 downto 0)=x"FFFFFFFF") then
313
                                                data_ex4(63 downto 32) <= data_ex4(63 downto 32) + 1;
314
                                        end if;
315
                                end if;
316
 
317
                          when "1000" | "1001" => -- Ïñåâäîñëó÷àéíàÿ ïîñëåäîâàòåëüíîñòü          
318
                                        data_expect <= data_ex5 after 1 ns;
319
                                        data_ex5( 63 downto 1 ) <= data_ex5( 62 downto 0 ) after 1 ns;
320
                                        --data_ex5( 0 ) <= data_ex5( 63 ) xor data_ex5(62) after 1 ns;
321
                                        data_ex5( 0 ) <= data_ex5( 63 ) xor data_ex5(62) xor data_ex5(60) xor data_ex5(59) after 1 ns;
322
                          when others=> null;
323
                        end case;
324
                end if;
325
          end if;
326
        end if;
327
end process;
328
 
329
 
330
 
331
do_data_z <= do_data after 1 ns when rising_edge( do_clk );
332
data_en_z <= data_en after 1 ns when rising_edge( do_clk );
333
 
334
word_error <= '1' when do_data_z /= data_expect else '0';
335
 
336
pr_total_err: process( do_clk ) begin
337
        if( rising_edge( do_clk ) ) then
338
                if( rst='0' ) then
339
                        total_err <= (others=>'0') after 1 ns;
340
                elsif( data_en_z='1' and word_error='1' and total_err/=x"FFFFFFFF" ) then
341
                        total_err <= total_err + 1 after 1 ns;
342
                end if;
343
        end if;
344
end process;
345
 
346
pr_flag_error_clr: process( do_clk ) begin
347
        if( rising_edge( do_clk ) ) then
348
                if( rst='0' ) then
349
                        flag_error_clr <= '0' after 1 ns;
350
                elsif(  cnt1_z='1' and data_en='1' ) then
351
                        flag_error_clr <= '1' after 1 ns;
352
                else
353
                        flag_error_clr <= '0' after 1 ns;
354
                end if;
355
        end if;
356
end process;
357
 
358
 
359
pr_flag_error: process( do_clk ) begin
360
        if( rising_edge( do_clk ) ) then
361
                if( rst='0' ) then
362
                        flag_error <= '0' after 1 ns;
363
                elsif( data_en_z='1' and word_error='1' ) then
364
                        flag_error <= '1' after 1 ns;
365
                elsif( flag_error_clr='1' ) then
366
                        flag_error <= '0' after 1 ns;
367
                end if;
368
        end if;
369
end process;
370
 
371
 
372
data_error_wr <= data_en_z and word_error;
373
 
374
data_error( 63 downto 0 ) <= do_data_z;
375
data_error( 127 downto 64 ) <= data_expect;
376
data_error( 152 downto 128 ) <= cnt1 after 1 ns when rising_edge( do_clk );
377
data_error( 159 downto 153 ) <= (others=>'0');
378
data_error( 191 downto 160 ) <= block_rd after 1 ns when rising_edge( do_clk );
379
 
380
pr_data_error_ovr: process( do_clk ) begin
381
        if( rising_edge( do_clk ) ) then
382
                if( rst='0' ) then
383
                        data_error_ovr <= '0' after 1 ns;
384
                elsif( data_error_wr='1' and total_err( 3 downto 0 )="1111" ) then
385
                        data_error_ovr <= '1' after 1 ns;
386
                end if;
387
        end if;
388
end process;
389
 
390
data_error_wr1 <= data_error_wr and not data_error_ovr;
391
 
392
pr_block_ok: process( do_clk ) begin
393
        if( rising_edge( do_clk ) ) then
394
                if( rst='0' ) then
395
                        block_ok <= (others=>'0') after 1 ns;
396
                        block_err <= (others=>'0' ) after 1 ns;
397
                elsif( block_ok_en='1' ) then
398
                        if( flag_error_clr='1' and flag_error='0' ) then
399
                                block_ok <= block_ok + 1 after 1 ns;
400
                        end if;
401
                        if( flag_error_clr='1' and flag_error='1' ) then
402
                                block_err <= block_err + 1 after 1 ns;
403
                        end if;
404
                end if;
405
        end if;
406
end process;
407
 
408
pr_block_ok_en: process( clk ) begin
409
        if( rising_edge( clk ) ) then
410
                if( rst='0' ) then
411
                        block_ok_en <= '0' after 1 ns;
412
                elsif( cnt1_eq='1' ) then
413
                        block_ok_en <= '1' after 1 ns;
414
                end if;
415
        end if;
416
end process;
417
 
418
 
419
gen_data_error: for ii in 0 to 191 generate
420
 
421
ram0:   ram16x1d
422
                port map(
423
                        we      => data_error_wr1,
424
                        d       => data_error( ii ),
425
                        wclk => do_clk,
426
                        a0      => total_err( 0 ),
427
                        a1      => total_err( 1 ),
428
                        a2      => total_err( 2 ),
429
                        a3      => total_err( 3 ),
430
                        --spo   => data_out( 0 ),
431
                        dpra0 => test_check_err_adr( 4 ),
432
                        dpra1 => test_check_err_adr( 5 ),
433
                        dpra2 => test_check_err_adr( 6 ),
434
                        dpra3 => test_check_err_adr( 7 ),
435
                        dpo       => data_error_out( ii )
436
                );
437
 
438
end generate;
439
 
440
err_data <=                     data_error_out( 15 downto 0 )   when test_check_err_adr( 3 downto 0 )="0000" else
441
                                                data_error_out( 31 downto 16 )   when test_check_err_adr( 3 downto 0 )="0001" else
442
                                                data_error_out( 47 downto 32 )   when test_check_err_adr( 3 downto 0 )="0010" else
443
                                                data_error_out( 63 downto 48 )   when test_check_err_adr( 3 downto 0 )="0011" else
444
                                                data_error_out( 79 downto 64 )   when test_check_err_adr( 3 downto 0 )="0100" else
445
                                                data_error_out( 95 downto 80 )   when test_check_err_adr( 3 downto 0 )="0101" else
446
                                                data_error_out( 111 downto 96 )  when test_check_err_adr( 3 downto 0 )="0110" else
447
                                                data_error_out( 127 downto 112 ) when test_check_err_adr( 3 downto 0 )="0111" else
448
                                                data_error_out( 143 downto 128 ) when test_check_err_adr( 3 downto 0 )="1000" else
449
                                                data_error_out( 159 downto 144 ) when test_check_err_adr( 3 downto 0 )="1001" else
450
                                                data_error_out( 175 downto 160 ) when test_check_err_adr( 3 downto 0 )="1010" else
451
                                                data_error_out( 191 downto 176 ) when test_check_err_adr( 3 downto 0 )="1011" else
452
                                                (others=>'-');
453
 
454
 
455
test_check_err_data <= err_data after 1 ns when rising_edge( clk );
456
 
457
 
458
test_check_bl_rd        <= block_rd;
459
test_check_bl_ok        <= block_ok;
460
test_check_bl_err       <= block_err;
461
test_check_error        <= total_err;
462
 
463
 
464
end cl_test_check;
465
 
466
 

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