URL https://opencores.org/ocsvn/pcie_ds_dma/pcie_ds_dma/trunk

Subversion Repositories pcie_ds_dma

[/] [pcie_ds_dma/] [trunk/] [core/] [wishbone/] [block_test_generate/] [block_generate_wb_burst_slave.v] - Blame information for rev 2

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//////////////////////////////////////////////////////////////////////////////////
// Company:         ;)
// Engineer:        Kuzmi4
// 
// Create Date:     14:39:52 05/19/2010 
// Design Name:     
// Module Name:     block_generate_wb_burst_slave 
// Project Name:    DS_DMA
// Target Devices:  any
// Tool versions:   
// Description:     
//                  
//                  For now we have such restrictions for WB component:
//                      1) no WB_RTY syupport
//                      2) WB_ERR arize only at event detection and fall after it goes.
//                      3) WB Transfers muts be without STB->LOW (NO Master DELAY in Transfer) --> !!! (because counted on standard FIFO IF)
//                      4) (TBD)...
//                  
//
// Revision: 
// Revision 0.01 - File Created, 
//                      2do: provide "Master DELAY in Transfer" functionality (STB->LOW when CYC==HIGH) (looks like FW FIFO can provide such func)
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
 
module block_generate_wb_burst_slave
(
    //
    // SYS_CON
    input   i_clk,
    input   i_rst,
    //
    // WB BURST SLAVE IF (READ-ONLY IF)
    input       [11:0]  iv_wbs_burst_addr,
    input       [ 7:0]  iv_wbs_burst_sel,
    input               i_wbs_burst_we,
    input               i_wbs_burst_cyc,
    input               i_wbs_burst_stb,
    input       [ 2:0]  iv_wbs_burst_cti,
    input       [ 1:0]  iv_wbs_burst_bte,
 
    output reg  [63:0]  ov_wbs_burst_data,
    output reg          o_wbs_burst_ack,
    output reg          o_wbs_burst_err,
    output              o_wbs_burst_rty,
    //
    // TEST_GEN_FIFO IF
    input       [63:0]  iv_test_gen_fifo_data,
    output              o_test_gen_fifo_rd,
    input               i_test_gen_fifo_full,       // unused for now
    input               i_test_gen_fifo_empty,
    input               i_test_gen_fifo_prog_full   // unused for now
);
//////////////////////////////////////////////////////////////////////////////////
//
localparam  lp_INIT_STATE   =   0;
localparam  lp_WRK_STATE    =   1;
//////////////////////////////////////////////////////////////////////////////////
    // 
    wire            s_wb_transfer_ok_0;
    // define WB stuff:
    reg     [8:0]   sv_wbs_burst_counter;
    reg     [0:0]   sv_wbs_fsm;
//////////////////////////////////////////////////////////////////////////////////
    // 
    assign  s_wb_transfer_ok_0  =   (iv_wbs_burst_addr==0)                              & // START from INIT ADDR
                                    i_wbs_burst_cyc & i_wbs_burst_stb & !i_wbs_burst_we & // WB Transfer strobes
                                    iv_wbs_burst_sel==8'hFF                             & // WB_SEL point to 64bit transfer 
                                    iv_wbs_burst_bte==2'b00                             ; // WB Burst Transfer type check (Linear Burst)
    // TEST_GEN_FIFO IF deal:
    assign  o_test_gen_fifo_rd   =   s_wb_transfer_ok_0 & !i_test_gen_fifo_empty & (sv_wbs_burst_counter < 510);
    // WB stuff deal:
    assign  o_wbs_burst_rty =   0;  // for now no WB retry func, only WB_ERR for now
//////////////////////////////////////////////////////////////////////////////////
//
// Create WB DATA_OUT logic:
//
always @ (posedge i_clk or posedge i_rst)
begin   :   WB_DATA_OUT
    if (i_rst)
        begin   :   RST
            ov_wbs_burst_data   <= 0;
            o_wbs_burst_ack     <= 0;
            sv_wbs_fsm          <= lp_INIT_STATE;
        end
    else
        begin   :   WRK
            //
            o_wbs_burst_ack     <=0;
            // 
            case(sv_wbs_fsm)
                lp_INIT_STATE   :   begin
                                        if (o_test_gen_fifo_rd/*s_wb_transfer_ok_1*/)
                                            sv_wbs_fsm <= lp_WRK_STATE;
                                    end
                lp_WRK_STATE    :   begin
                                        // 
                                        ov_wbs_burst_data   <=  (i_test_gen_fifo_empty)? 0 : iv_test_gen_fifo_data;
                                        //
                                        o_wbs_burst_ack     <=  (
                                                                    iv_wbs_burst_cti==3'b111    |   // End-of-Burst
                                                                    !s_wb_transfer_ok_0             // No Transfer
                                                                )?  1'b0                    :       // ...
                                                                    !i_test_gen_fifo_empty  ;       // FIFO EMPTY control here
                                        // 
                                        if (i_test_gen_fifo_empty | !s_wb_transfer_ok_0)
                                            sv_wbs_fsm <= lp_INIT_STATE;
 
                                    end
            endcase
        end
end
//////////////////////////////////////////////////////////////////////////////////
//
// Create WB ERROR logic:
//
always @ (posedge i_clk or posedge i_rst)
begin   :   WB_ERR
    if (i_rst)
        begin   :   RST
            o_wbs_burst_err         <= 0;
            sv_wbs_burst_counter    <= 0;
        end
    else
        begin   :   WRK
            // BURST counter
            if (i_wbs_burst_cyc)
                begin   :   TIME_TO_COUNT
                    if (o_wbs_burst_ack) // count ENA
                        sv_wbs_burst_counter <= sv_wbs_burst_counter + 1'b1;
                end
            else            // W8 for COUNT Time, CLR COUNTER 
                sv_wbs_burst_counter <= 0;
            // ERR logic
            if  (
                    (sv_wbs_burst_counter == 511 & o_wbs_burst_ack & iv_wbs_burst_cti!=3'b111)  |   // check End-of-Burst
                    (sv_wbs_burst_counter <  511 & o_wbs_burst_ack & iv_wbs_burst_cti!=3'b001)  |   // check Const-Addr-Burst
                    (sv_wbs_burst_counter!=0 & i_wbs_burst_cyc & !i_wbs_burst_stb)                  // check delays in MASTER transfer --> !!!
                                                                                                    // ==> WB_BTE check at "s_wb_transfer_ok"
                )
                o_wbs_burst_err <= 1;
            else
                o_wbs_burst_err <= 0;
        end
end
//////////////////////////////////////////////////////////////////////////////////
endmodule

Line No.	Rev	Author	Line
1	2	dsmv	`//////////////////////////////////////////////////////////////////////////////////`
2			`// Company: ;)`
3			`// Engineer: Kuzmi4`
4			`//`
5			`// Create Date: 14:39:52 05/19/2010`
6			`// Design Name:`
7			`// Module Name: block_generate_wb_burst_slave`
8			`// Project Name: DS_DMA`
9			`// Target Devices: any`
10			`// Tool versions:`
11			`// Description:`
12			`//`
13			`// For now we have such restrictions for WB component:`
14			`// 1) no WB_RTY syupport`
15			`// 2) WB_ERR arize only at event detection and fall after it goes.`
16			`// 3) WB Transfers muts be without STB->LOW (NO Master DELAY in Transfer) --> !!! (because counted on standard FIFO IF)`
17			`// 4) (TBD)...`
18			`//`
19			`//`
20			`// Revision:`
21			`// Revision 0.01 - File Created,`
22			`// 2do: provide "Master DELAY in Transfer" functionality (STB->LOW when CYC==HIGH) (looks like FW FIFO can provide such func)`
23			`//`
24			`//////////////////////////////////////////////////////////////////////////////////`
25			`timescale 1ns / 1ps
26
27			`module block_generate_wb_burst_slave`
28			`(`
29			`//`
30			`// SYS_CON`
31			`input i_clk,`
32			`input i_rst,`
33			`//`
34			`// WB BURST SLAVE IF (READ-ONLY IF)`
35			`input [11:0] iv_wbs_burst_addr,`
36			`input [ 7:0] iv_wbs_burst_sel,`
37			`input i_wbs_burst_we,`
38			`input i_wbs_burst_cyc,`
39			`input i_wbs_burst_stb,`
40			`input [ 2:0] iv_wbs_burst_cti,`
41			`input [ 1:0] iv_wbs_burst_bte,`
42
43			`output reg [63:0] ov_wbs_burst_data,`
44			`output reg o_wbs_burst_ack,`
45			`output reg o_wbs_burst_err,`
46			`output o_wbs_burst_rty,`
47			`//`
48			`// TEST_GEN_FIFO IF`
49			`input [63:0] iv_test_gen_fifo_data,`
50			`output o_test_gen_fifo_rd,`
51			`input i_test_gen_fifo_full, // unused for now`
52			`input i_test_gen_fifo_empty,`
53			`input i_test_gen_fifo_prog_full // unused for now`
54			`);`
55			`//////////////////////////////////////////////////////////////////////////////////`
56			`//`
57			`localparam lp_INIT_STATE = 0;`
58			`localparam lp_WRK_STATE = 1;`
59			`//////////////////////////////////////////////////////////////////////////////////`
60			`//`
61			`wire s_wb_transfer_ok_0;`
62			`// define WB stuff:`
63			`reg [8:0] sv_wbs_burst_counter;`
64			`reg [0:0] sv_wbs_fsm;`
65			`//////////////////////////////////////////////////////////////////////////////////`
66			`//`
67			`assign s_wb_transfer_ok_0 = (iv_wbs_burst_addr==0) & // START from INIT ADDR`
68			`i_wbs_burst_cyc & i_wbs_burst_stb & !i_wbs_burst_we & // WB Transfer strobes`
69			`iv_wbs_burst_sel==8'hFF & // WB_SEL point to 64bit transfer`
70			`iv_wbs_burst_bte==2'b00 ; // WB Burst Transfer type check (Linear Burst)`
71			`// TEST_GEN_FIFO IF deal:`
72			`assign o_test_gen_fifo_rd = s_wb_transfer_ok_0 & !i_test_gen_fifo_empty & (sv_wbs_burst_counter < 510);`
73			`// WB stuff deal:`
74			`assign o_wbs_burst_rty = 0; // for now no WB retry func, only WB_ERR for now`
75			`//////////////////////////////////////////////////////////////////////////////////`
76			`//`
77			`// Create WB DATA_OUT logic:`
78			`//`
79			`always @ (posedge i_clk or posedge i_rst)`
80			`begin : WB_DATA_OUT`
81			`if (i_rst)`
82			`begin : RST`
83			`ov_wbs_burst_data <= 0;`
84			`o_wbs_burst_ack <= 0;`
85			`sv_wbs_fsm <= lp_INIT_STATE;`
86			`end`
87			`else`
88			`begin : WRK`
89			`//`
90			`o_wbs_burst_ack <=0;`
91			`//`
92			`case(sv_wbs_fsm)`
93			`lp_INIT_STATE : begin`
94			`if (o_test_gen_fifo_rd/s_wb_transfer_ok_1/)`
95			`sv_wbs_fsm <= lp_WRK_STATE;`
96			`end`
97			`lp_WRK_STATE : begin`
98			`//`
99			`ov_wbs_burst_data <= (i_test_gen_fifo_empty)? 0 : iv_test_gen_fifo_data;`
100			`//`
101			`o_wbs_burst_ack <= (`
102			`iv_wbs_burst_cti==3'b111 \| // End-of-Burst`
103			`!s_wb_transfer_ok_0 // No Transfer`
104			`)? 1'b0 : // ...`
105			`!i_test_gen_fifo_empty ; // FIFO EMPTY control here`
106			`//`
107			`if (i_test_gen_fifo_empty \| !s_wb_transfer_ok_0)`
108			`sv_wbs_fsm <= lp_INIT_STATE;`
109
110			`end`
111			`endcase`
112			`end`
113			`end`
114			`//////////////////////////////////////////////////////////////////////////////////`
115			`//`
116			`// Create WB ERROR logic:`
117			`//`
118			`always @ (posedge i_clk or posedge i_rst)`
119			`begin : WB_ERR`
120			`if (i_rst)`
121			`begin : RST`
122			`o_wbs_burst_err <= 0;`
123			`sv_wbs_burst_counter <= 0;`
124			`end`
125			`else`
126			`begin : WRK`
127			`// BURST counter`
128			`if (i_wbs_burst_cyc)`
129			`begin : TIME_TO_COUNT`
130			`if (o_wbs_burst_ack) // count ENA`
131			`sv_wbs_burst_counter <= sv_wbs_burst_counter + 1'b1;`
132			`end`
133			`else // W8 for COUNT Time, CLR COUNTER`
134			`sv_wbs_burst_counter <= 0;`
135			`// ERR logic`
136			`if (`
137			`(sv_wbs_burst_counter == 511 & o_wbs_burst_ack & iv_wbs_burst_cti!=3'b111) \| // check End-of-Burst`
138			`(sv_wbs_burst_counter < 511 & o_wbs_burst_ack & iv_wbs_burst_cti!=3'b001) \| // check Const-Addr-Burst`
139			`(sv_wbs_burst_counter!=0 & i_wbs_burst_cyc & !i_wbs_burst_stb) // check delays in MASTER transfer --> !!!`
140			`// ==> WB_BTE check at "s_wb_transfer_ok"`
141			`)`
142			`o_wbs_burst_err <= 1;`
143			`else`
144			`o_wbs_burst_err <= 0;`
145			`end`
146			`end`
147			`//////////////////////////////////////////////////////////////////////////////////`
148			`endmodule`

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Subversion Repositories pcie_ds_dma

[/] [pcie_ds_dma/] [trunk/] [core/] [wishbone/] [block_test_generate/] [block_generate_wb_burst_slave.v] - Blame information for rev 2