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-- Company: ;)
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-- Engineer: Kuzmi4
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--
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-- Create Date: 17:40:25 05/21/2010
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-- Design Name:
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-- Module Name: block_generate_wb_config_slave - rtl
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-- Project Name: DS_DMA
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-- Target Devices: any
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-- Tool versions:
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-- Description:
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--
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-- For now we have such restrictions for WB component:
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-- 1) no WB_RTY support
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-- 2) WB_ERR arize only at event detection and fall after it goes.
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-- 3) Operate with Single 64bit WB Transfers. NO WB BURSTs.
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-- 4) (TBD)...
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--
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-- WB_SLAVE MM (ONLY 256B range):
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-- 1) CONSTANTs:
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-- ADDR=x00 - BLOCK_ID
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-- ADDR=x08 - BLOCK_VER
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-- ADDR=x10 - RSVD (CONSTANTs)
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-- ADDR=x18 - RSVD (CONSTANTs)
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-- ADDR=x20 - RSVD (CONSTANTs)
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-- ADDR=x28 - RSVD (CONSTANTs)
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-- ADDR=x30 - RSVD (CONSTANTs)
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-- ADDR=x38 - RSVD (CONSTANTs)
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-- 2) COMMAND REGs:
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-- ADDR=x40 - TEST_GEN_CTRL
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-- ADDR=x48 - TEST_GEN_SIZE
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-- ADDR=x50 - TEST_GEN_CNT1
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-- ADDR=x58 - TEST_GEN_CNT2
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-- ADDR=x60 - RSVD (COMMAND REGs)
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-- ADDR=x68 - RSVD (COMMAND REGs)
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-- ADDR=x70 - RSVD (COMMAND REGs)
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-- ADDR=x78 - RSVD (COMMAND REGs)
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-- 3) STS REGs, etc:
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-- ADDR=x80 - TEST_GEN_BL_WR
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-- ADDR=x88 - RSVD (STS REGs, etc)
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-- ....
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-- ADDR=xFF - RSVD (STS REGs, etc)
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--
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--
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--
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-- Revision:
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-- Revision 0.01 - File Created,
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-- 2do: for now ADD MemoryMap looks good, but maybe its quite diff from REAL SITUATION --> CHECK/FIX MM later!!!
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-- Revision 0.02 - upd WB_ERR func.
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-- Revision 0.03 - fix MM (8cell allign).
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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package block_generate_wb_config_slave_pkg is
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component block_generate_wb_config_slave is
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generic
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(
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BLOCK_ID : in std_logic_vector( 15 downto 0 ):=x"0000"; -- идентификатор модуля
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BLOCK_VER : in std_logic_vector( 15 downto 0 ):=x"0000" -- версия модуля
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);
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port
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(
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--
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-- SYS_CON
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i_clk : in STD_LOGIC;
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i_rst : in STD_LOGIC;
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--
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-- WB CFG SLAVE
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iv_wbs_cfg_addr : in std_logic_vector( 7 downto 0 );
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iv_wbs_cfg_data : in std_logic_vector( 63 downto 0 );
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iv_wbs_cfg_sel : in std_logic_vector( 7 downto 0 ); -- wor now, we NC this wires
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i_wbs_cfg_we : in std_logic;
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i_wbs_cfg_cyc : in std_logic;
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i_wbs_cfg_stb : in std_logic;
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iv_wbs_cfg_cti : in std_logic_vector( 2 downto 0 );
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iv_wbs_cfg_bte : in std_logic_vector( 1 downto 0 );
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ov_wbs_cfg_data : out std_logic_vector( 63 downto 0 );
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o_wbs_cfg_ack : out std_logic;
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o_wbs_cfg_err : out std_logic;
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o_wbs_cfg_rty : out std_logic;
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--
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-- CONTROL Outputs
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ov_test_gen_ctrl : out std_logic_vector( 15 downto 0 );
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ov_test_gen_size : out std_logic_vector( 15 downto 0 );
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ov_test_gen_cnt1 : out std_logic_vector( 15 downto 0 );
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ov_test_gen_cnt2 : out std_logic_vector( 15 downto 0 );
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--
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-- STATUS Input
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iv_test_gen_bl_wr : in std_logic_vector( 31 downto 0 )
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);
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end component block_generate_wb_config_slave;
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end package block_generate_wb_config_slave_pkg;
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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library work;
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use work.ctrl_ram16_v1_pkg.all;
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use work.host_pkg.all;
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entity block_generate_wb_config_slave is
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generic
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(
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BLOCK_ID : in std_logic_vector( 15 downto 0 ):=x"0000"; -- идентификатор модуля
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BLOCK_VER : in std_logic_vector( 15 downto 0 ):=x"0000" -- версия модуля
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);
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port
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(
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--
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-- SYS_CON
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i_clk : in STD_LOGIC;
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i_rst : in STD_LOGIC;
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--
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-- WB CFG SLAVE
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iv_wbs_cfg_addr : in std_logic_vector( 7 downto 0 );
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iv_wbs_cfg_data : in std_logic_vector( 63 downto 0 );
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iv_wbs_cfg_sel : in std_logic_vector( 7 downto 0 ); -- wor now, we NC this wires
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i_wbs_cfg_we : in std_logic;
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i_wbs_cfg_cyc : in std_logic;
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i_wbs_cfg_stb : in std_logic;
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iv_wbs_cfg_cti : in std_logic_vector( 2 downto 0 );
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iv_wbs_cfg_bte : in std_logic_vector( 1 downto 0 );
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ov_wbs_cfg_data : out std_logic_vector( 63 downto 0 );
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o_wbs_cfg_ack : out std_logic;
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o_wbs_cfg_err : out std_logic;
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o_wbs_cfg_rty : out std_logic;
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--
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-- CONTROL Outputs
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ov_test_gen_ctrl : out std_logic_vector( 15 downto 0 );
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ov_test_gen_size : out std_logic_vector( 15 downto 0 );
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ov_test_gen_cnt1 : out std_logic_vector( 15 downto 0 );
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ov_test_gen_cnt2 : out std_logic_vector( 15 downto 0 );
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--
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-- STATUS Input
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iv_test_gen_bl_wr : in std_logic_vector( 31 downto 0 )
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);
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end block_generate_wb_config_slave;
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architecture rtl of block_generate_wb_config_slave is
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----------------------------------------------------------------------------------
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--
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-- Define CONSTANTs
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constant ct_bl_rom : bh_rom:=(
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0=> BLOCK_ID, --
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1=> BLOCK_VER, --
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2=> x"5504", -- 2=> Device_ID,
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3=> x"0210", -- 3=> Revision,
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4=> x"0104", -- 4=> PLD_VER,
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5=> x"0000",
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6=> x"0000",
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7=> x"0000"
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);
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--
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-- Define BL_RAM stuff:
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signal sv_bl_ram_adr : std_logic_vector( 4 downto 0):= (others => '0');
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signal sv_bl_ram_data_in : std_logic_vector(15 downto 0):= (others => '0');
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signal sv_bl_ram_data_out : std_logic_vector(15 downto 0):= (others => '0');
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signal s_bl_ram_data_we : std_logic:= '0';
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--
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-- DEFINE WB_FSM (required for build correct WB_ACK) stuff:
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signal sv_wbs_cfg_ack_counter : std_logic:='0';
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--
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-- Define additional WB signals:
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signal s_wbs_active_wr : std_logic;
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signal s_wbs_active_rd : std_logic;
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signal s_wbs_active : std_logic;
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signal s_wbs_wr_ena : std_logic;
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----------------------------------------------------------------------------------
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begin
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----------------------------------------------------------------------------------
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--
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-- WB ACTIVE/ENA flag (for RD/WR and for any WB activity)
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--
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s_wbs_active_wr <= '1' when (
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i_wbs_cfg_cyc='1' and i_wbs_cfg_stb='1' and i_wbs_cfg_we='1' and -- all strobes OK
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(iv_wbs_cfg_cti="000") and (iv_wbs_cfg_bte="00") -- type of transfer OK
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) else '0';
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s_wbs_active_rd <= '1' when (
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i_wbs_cfg_cyc='1' and i_wbs_cfg_stb='1' and i_wbs_cfg_we='0' and
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(iv_wbs_cfg_cti="000") and (iv_wbs_cfg_bte="00")
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) else '0';
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s_wbs_active <= '1' when (
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i_wbs_cfg_cyc='1' and i_wbs_cfg_stb='1' and
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(iv_wbs_cfg_cti="000") and (iv_wbs_cfg_bte="00")
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) else '0';
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s_wbs_wr_ena <= '1' when (
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s_wbs_active_wr='1' and -- have ACTIVE WR flag
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(sv_wbs_cfg_ack_counter='1') -- present WB_ACK source
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) else '0';
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----------------------------------------------------------------------------------
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--
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-- WB Write process
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--
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WB_WRITE : process (i_clk, i_rst)
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begin
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if (i_rst='1') then -- RST
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ov_test_gen_ctrl <= (others => '0');
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ov_test_gen_size <= (others => '0');
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ov_test_gen_cnt1 <= (others => '0');
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ov_test_gen_cnt2 <= (others => '0');
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elsif (rising_edge(i_clk)) then -- WRK
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if (s_wbs_wr_ena='1') then
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case(iv_wbs_cfg_addr(7 downto 0)) is
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when x"40" => ov_test_gen_ctrl <= iv_wbs_cfg_data( 15 downto 0);
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when x"48" => ov_test_gen_size <= iv_wbs_cfg_data( 15 downto 0);
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when x"50" => ov_test_gen_cnt1 <= iv_wbs_cfg_data( 15 downto 0);
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when x"58" => ov_test_gen_cnt2 <= iv_wbs_cfg_data( 15 downto 0);
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when others => null;
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end case;
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end if;
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end if;
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end process WB_WRITE;
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----------------------------------------------------------------------------------
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--
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-- WB Read process
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--
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WB_READ : process (i_clk, i_rst)
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begin
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if (i_rst='1') then -- RST
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ov_wbs_cfg_data <= (others => '0');
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elsif (rising_edge(i_clk)) then -- WRK
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if (s_wbs_active_rd='1') then
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case(iv_wbs_cfg_addr(7 downto 0)) is
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-- STS MM region
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when x"80" => ov_wbs_cfg_data(31 downto 0) <= iv_test_gen_bl_wr;
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-- BL_RAM MM region
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when others => ov_wbs_cfg_data(15 downto 0) <= sv_bl_ram_data_out;
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end case;
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end if;
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end if;
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end process WB_READ;
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----------------------------------------------------------------------------------
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--
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-- WB ACK process
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--
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WB_ACK_CNT : process (i_clk, i_rst)
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begin
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if (i_rst='1') then -- RST
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sv_wbs_cfg_ack_counter <= '0';
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elsif (rising_edge(i_clk)) then -- WRK:
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if (s_wbs_active='1') then -- WB Transfer in progress
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--sv_wbs_cfg_ack_counter <= sv_wbs_cfg_ack_counter + '1';
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if (sv_wbs_cfg_ack_counter='0') then
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sv_wbs_cfg_ack_counter <= '1';
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else
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sv_wbs_cfg_ack_counter <= '0';
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end if;
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else -- no WB Transfer
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sv_wbs_cfg_ack_counter <= '0';
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end if;
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end if;
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end process WB_ACK_CNT;
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-- Define WB_ACK
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o_wbs_cfg_ack <= '1' when (
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sv_wbs_cfg_ack_counter='1' and
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i_wbs_cfg_cyc='1' and i_wbs_cfg_stb='1' -- add controls for avoid problems in anarranged transfers
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) else '0';
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----------------------------------------------------------------------------------
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--
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-- Instaniate BL_RAM (contain CONSTANTs and RD values for COMMAND registers)
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--
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BL_RAM : ctrl_ram16_v1
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generic map
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(
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rom => ct_bl_rom -- значения констант
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)
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port map
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(
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clk => i_clk, -- Тактовая частота
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adr => sv_bl_ram_adr, -- адрес
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data_in => sv_bl_ram_data_in, -- вход данных
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data_out => sv_bl_ram_data_out, -- выход данных
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data_we => s_bl_ram_data_we -- 1 - запись данных
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);
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-- Define BL_RAM ADDR
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sv_bl_ram_adr <= iv_wbs_cfg_addr( 7 downto 3); -- 8B granularity Transfers (cut [2:0] addr bits)
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-- DEFINE BL_RAM DATA_IN
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sv_bl_ram_data_in <= iv_wbs_cfg_data(15 downto 0); -- Cut only LS 16bit
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-- DEFINE BL_RAM DATA_WRITE
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s_bl_ram_data_we <= s_wbs_wr_ena; -- WB_WE signal is OK
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----------------------------------------------------------------------------------
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--
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-- MODULE OUTPUTs routing:
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--
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-- WB_ERR deal
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o_wbs_cfg_err <= '1' when (
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i_wbs_cfg_cyc='1' and i_wbs_cfg_stb='1' and -- all strobes OK
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( (iv_wbs_cfg_cti/="000") or (iv_wbs_cfg_bte/="00") ) -- BUT type of transfer is NOT OK
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) else '0';
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-- WB_RTY deal
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o_wbs_cfg_rty <= '0'; -- nothing to report for now
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----------------------------------------------------------------------------------
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end rtl;
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