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----------------------------------------------------------------------------------
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-- Company: ;)
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-- Engineer: Kuzmi4
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--
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-- Create Date: 17:40:25 05/21/2010
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-- Design Name:
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-- Module Name: block_test_generate_wb - rtl
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-- Project Name: DS_DMA
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-- Target Devices: (XC6LX45T - FIFO)
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-- Tool versions: Xilinx
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-- Description:
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--
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-- Top-level module for TEST_GEN_WB functionality
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-- (NB!!! --> module contain syb-modules with restrictions)
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Revision 0.02 - update BLOCK_ID/BLOCK_VER logic - now it's inner ID of component
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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package block_test_generate_wb_pkg is
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component block_test_generate_wb is
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port
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(
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--
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-- SYS_CON
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i_clk : in STD_LOGIC;
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i_rst : in STD_LOGIC;
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--
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-- WB CFG SLAVE IF
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iv_wbs_cfg_addr : in std_logic_vector( 7 downto 0 );
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iv_wbs_cfg_data : in std_logic_vector( 63 downto 0 );
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iv_wbs_cfg_sel : in std_logic_vector( 7 downto 0 );
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i_wbs_cfg_we : in std_logic;
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i_wbs_cfg_cyc : in std_logic;
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i_wbs_cfg_stb : in std_logic;
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iv_wbs_cfg_cti : in std_logic_vector( 2 downto 0 );
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iv_wbs_cfg_bte : in std_logic_vector( 1 downto 0 );
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ov_wbs_cfg_data : out std_logic_vector( 63 downto 0 );
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o_wbs_cfg_ack : out std_logic;
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o_wbs_cfg_err : out std_logic;
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o_wbs_cfg_rty : out std_logic;
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--
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-- WB BURST SLAVE IF (READ-ONLY IF)
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iv_wbs_burst_addr : in std_logic_vector( 11 downto 0 );
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iv_wbs_burst_sel : in std_logic_vector( 7 downto 0 );
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i_wbs_burst_we : in std_logic;
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i_wbs_burst_cyc : in std_logic;
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i_wbs_burst_stb : in std_logic;
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iv_wbs_burst_cti : in std_logic_vector( 2 downto 0 );
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iv_wbs_burst_bte : in std_logic_vector( 1 downto 0 );
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ov_wbs_burst_data : out std_logic_vector( 63 downto 0 );
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o_wbs_burst_ack : out std_logic;
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o_wbs_burst_err : out std_logic;
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o_wbs_burst_rty : out std_logic;
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--
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-- WB IRQ lines
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o_wbs_irq_0 : out std_logic;
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o_wbs_irq_dmar : out std_logic
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);
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end component block_test_generate_wb;
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end package block_test_generate_wb_pkg;
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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library work;
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use work.cl_test_generate_pkg.all;
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use work.block_generate_wb_config_slave_pkg.all;
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use work.block_generate_wb_pkg.all;
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entity block_test_generate_wb is
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port
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(
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--
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-- SYS_CON
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i_clk : in STD_LOGIC;
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i_rst : in STD_LOGIC;
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--
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-- WB CFG SLAVE IF
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iv_wbs_cfg_addr : in std_logic_vector( 7 downto 0 );
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iv_wbs_cfg_data : in std_logic_vector( 63 downto 0 );
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iv_wbs_cfg_sel : in std_logic_vector( 7 downto 0 );
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i_wbs_cfg_we : in std_logic;
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i_wbs_cfg_cyc : in std_logic;
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i_wbs_cfg_stb : in std_logic;
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iv_wbs_cfg_cti : in std_logic_vector( 2 downto 0 );
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iv_wbs_cfg_bte : in std_logic_vector( 1 downto 0 );
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ov_wbs_cfg_data : out std_logic_vector( 63 downto 0 );
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o_wbs_cfg_ack : out std_logic;
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o_wbs_cfg_err : out std_logic;
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o_wbs_cfg_rty : out std_logic;
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--
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-- WB BURST SLAVE IF (READ-ONLY IF)
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iv_wbs_burst_addr : in std_logic_vector( 11 downto 0 );
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iv_wbs_burst_sel : in std_logic_vector( 7 downto 0 );
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i_wbs_burst_we : in std_logic;
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i_wbs_burst_cyc : in std_logic;
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i_wbs_burst_stb : in std_logic;
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iv_wbs_burst_cti : in std_logic_vector( 2 downto 0 );
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iv_wbs_burst_bte : in std_logic_vector( 1 downto 0 );
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ov_wbs_burst_data : out std_logic_vector( 63 downto 0 );
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o_wbs_burst_ack : out std_logic;
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o_wbs_burst_err : out std_logic;
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o_wbs_burst_rty : out std_logic;
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--
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-- WB IRQ lines
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o_wbs_irq_0 : out std_logic;
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o_wbs_irq_dmar : out std_logic
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);
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end block_test_generate_wb;
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architecture rtl of block_test_generate_wb is
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----------------------------------------------------------------------------------
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--
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-- Define TEST_GEN CTRL/STS stuff:
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signal sv_test_gen_ctrl : std_logic_vector(15 downto 0);
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signal sv_test_gen_size : std_logic_vector(15 downto 0);
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signal sv_test_gen_cnt1 : std_logic_vector(15 downto 0);
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signal sv_test_gen_cnt2 : std_logic_vector(15 downto 0);
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signal sv_test_gen_bl_wr : std_logic_vector(31 downto 0);
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--
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-- Define TEST_GEN DATA_OUT IF stuff:
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signal sv_di_data : std_logic_vector(63 downto 0);
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signal s_di_data_we : std_logic;
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signal s_di_flag_paf : std_logic;
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signal s_di_fifo_rst : std_logic;
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signal s_di_start : std_logic;
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--
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-- Define WB_BURST_SLAVE/TEST_GEN_FIFO communication stuff:
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signal sv_test_gen_fifo_data : std_logic_vector(63 downto 0);
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signal s_test_gen_fifo_rd : std_logic;
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signal s_test_gen_fifo_full : std_logic;
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signal s_test_gen_fifo_empty : std_logic;
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dsmv |
signal s_test_gen_fifo_prog_full : std_logic;
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signal iv_test_gen_status : std_logic_vector( 31 downto 0 );
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signal rstp : std_logic;
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signal dmar : std_logic;
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2 |
dsmv |
----------------------------------------------------------------------------------
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begin
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----------------------------------------------------------------------------------
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--
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-- Instaniate WB_CFG_SLAVE
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--
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WB_CFG_SLAVE : block_generate_wb_config_slave
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generic map
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(
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18 |
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BLOCK_ID => x"001B", -- идентификатор модуля
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2 |
dsmv |
BLOCK_VER => x"0100" -- версия модуля
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)
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port map
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(
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--
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-- SYS_CON
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i_clk => i_clk,
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i_rst => i_rst,
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--
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-- WB CFG SLAVE IF
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iv_wbs_cfg_addr => iv_wbs_cfg_addr,
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iv_wbs_cfg_data => iv_wbs_cfg_data,
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iv_wbs_cfg_sel => iv_wbs_cfg_sel,
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i_wbs_cfg_we => i_wbs_cfg_we,
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i_wbs_cfg_cyc => i_wbs_cfg_cyc,
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i_wbs_cfg_stb => i_wbs_cfg_stb,
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iv_wbs_cfg_cti => iv_wbs_cfg_cti,
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iv_wbs_cfg_bte => iv_wbs_cfg_bte,
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ov_wbs_cfg_data => ov_wbs_cfg_data,
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o_wbs_cfg_ack => o_wbs_cfg_ack,
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o_wbs_cfg_err => o_wbs_cfg_err,
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o_wbs_cfg_rty => o_wbs_cfg_rty,
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--
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-- CONTROL Outputs
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ov_test_gen_ctrl => sv_test_gen_ctrl,
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ov_test_gen_size => sv_test_gen_size,
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ov_test_gen_cnt1 => sv_test_gen_cnt1,
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ov_test_gen_cnt2 => sv_test_gen_cnt2,
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--
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dsmv |
-- STATUS Input
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iv_test_gen_status => iv_test_gen_status,
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dsmv |
iv_test_gen_bl_wr => sv_test_gen_bl_wr
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);
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----------------------------------------------------------------------------------
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--
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-- Instaniate TEST_GEN
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--
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TEST_GEN : cl_test_generate
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port map
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(
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---- Global ----
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reset => s_di_fifo_rst, -- 0 - сброс
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clk => i_clk, -- тактовая частота
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---- DIO_IN ----
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di_clk => i_clk, -- тактовая частота записи в FIFO
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di_data => sv_di_data, -- данные
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di_data_we => s_di_data_we, -- 1 - запись данных
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di_flag_paf => s_di_flag_paf, -- 1 - есть место для записи
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di_fifo_rst => s_di_fifo_rst, -- 0 - сброс FIFO
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di_start => s_di_start, -- 1 - разрешение работы (MODE0[5])
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---- Управление ----
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test_gen_ctrl => sv_test_gen_ctrl, -- Регистр управления
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test_gen_size => sv_test_gen_size, -- размер в блоках по 512x64 (4096 байт)
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test_gen_bl_wr => sv_test_gen_bl_wr, -- Число записанных блоков [31:0]
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test_gen_cnt1 => sv_test_gen_cnt1, -- Счётчик разрешения работы
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test_gen_cnt2 => sv_test_gen_cnt2 -- Счётчик запрещения работы
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);
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----------------------------------------------------------------------------------
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--
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-- Instaniate TEST_GEN_FIFO
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-- ==> Volume==(512+512)x64bit
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--
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TEST_GEN_FIFO : ctrl_fifo1024x64_st_v1
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PORT MAP
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(
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--
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-- SYS_CON
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clk => i_clk,
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29 |
dsmv |
rst => rstp,
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2 |
dsmv |
--
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-- DATA_IN
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din => sv_di_data,
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wr_en => s_di_data_we,
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--
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-- DATA_OUT
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dout => sv_test_gen_fifo_data,
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rd_en => s_test_gen_fifo_rd,
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--
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-- FLAGs
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full => s_test_gen_fifo_full,
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empty => s_test_gen_fifo_empty,
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prog_full => s_test_gen_fifo_prog_full -- Level==512
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);
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----------------------------------------------------------------------------------
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--
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-- Instaniate WB_BURST_SLAVE (provide Output-Only Functionality)
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--
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WB_BURST_SLAVE : block_generate_wb_burst_slave
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port map
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(
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--
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-- SYS_CON
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i_clk => i_clk,
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i_rst => i_rst,
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--
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-- WB BURST SLAVE IF (READ-ONLY IF)
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iv_wbs_burst_addr => iv_wbs_burst_addr,
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iv_wbs_burst_sel => iv_wbs_burst_sel,
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i_wbs_burst_we => i_wbs_burst_we,
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i_wbs_burst_cyc => i_wbs_burst_cyc,
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i_wbs_burst_stb => i_wbs_burst_stb,
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iv_wbs_burst_cti => iv_wbs_burst_cti,
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iv_wbs_burst_bte => iv_wbs_burst_bte,
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ov_wbs_burst_data => ov_wbs_burst_data,
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o_wbs_burst_ack => o_wbs_burst_ack,
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o_wbs_burst_err => o_wbs_burst_err,
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o_wbs_burst_rty => o_wbs_burst_rty,
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269 |
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--
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270 |
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-- TEST_GEN_FIFO IF
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iv_test_gen_fifo_data => sv_test_gen_fifo_data,
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o_test_gen_fifo_rd => s_test_gen_fifo_rd,
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i_test_gen_fifo_full => s_test_gen_fifo_full,
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i_test_gen_fifo_empty => s_test_gen_fifo_empty,
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i_test_gen_fifo_prog_full => s_test_gen_fifo_prog_full
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);
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278 |
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----------------------------------------------------------------------------------
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279 |
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--
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280 |
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-- MODULE INNER wires routing:
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281 |
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--
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282 |
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-- define TEST_GEN.di_flag_paf like TEST_GEN_FIFO.prog_full
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283 |
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s_di_flag_paf <= not s_test_gen_fifo_prog_full;
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284 |
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-- define TEST_GEN.di_start like TEST_GEN.sv_test_gen_ctrl[1] ( 1-> RSVD )
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285 |
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s_di_start <= sv_test_gen_ctrl(5);
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286 |
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-- define TEST_GEN.di_fifo_rst - it is RST_n signal
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287 |
29 |
dsmv |
s_di_fifo_rst <= not rstp;
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288 |
2 |
dsmv |
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289 |
29 |
dsmv |
rstp <= i_rst or sv_test_gen_ctrl(0) after 1 ns when rising_edge( i_clk );
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290 |
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iv_test_gen_status(0) <= '1';
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iv_test_gen_status(1) <= '0';
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iv_test_gen_status(2) <= s_test_gen_fifo_empty;
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iv_test_gen_status(3) <= s_test_gen_fifo_prog_full;
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iv_test_gen_status(4) <= s_test_gen_fifo_full;
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iv_test_gen_status(5) <= '0';
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297 |
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iv_test_gen_status(6) <= '0';
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298 |
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iv_test_gen_status(7) <= '0';
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299 |
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iv_test_gen_status(8) <= sv_test_gen_ctrl(5);
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iv_test_gen_status(9) <= dmar;
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301 |
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iv_test_gen_status(10) <= rstp;
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iv_test_gen_status(11) <= '0';
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303 |
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iv_test_gen_status(12) <= '0';
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304 |
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iv_test_gen_status(13) <= '0';
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305 |
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iv_test_gen_status(14) <= '0';
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306 |
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iv_test_gen_status(15) <= '0';
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307 |
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308 |
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iv_test_gen_status( 31 downto 16 ) <= (others=>'0');
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309 |
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310 |
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311 |
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|
312 |
2 |
dsmv |
----------------------------------------------------------------------------------
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313 |
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--
|
314 |
|
|
-- MODULE OUTPUTs routing:
|
315 |
|
|
--
|
316 |
29 |
dsmv |
-- DMAR WB IRQ deal
|
317 |
|
|
dmar <= s_test_gen_fifo_prog_full or sv_test_gen_ctrl(14); -- (DS: 512 слов заполнили - взевели dmar)
|
318 |
|
|
o_wbs_irq_dmar <= dmar;
|
319 |
2 |
dsmv |
-- WB IRQ deal
|
320 |
|
|
o_wbs_irq_0 <= '0'; -- No EVENTs for now
|
321 |
|
|
----------------------------------------------------------------------------------
|
322 |
|
|
end rtl;
|
323 |
|
|
|